Memory system and control method

Abstract

This provides a memory system useful for identifying the type of individual data. [Solution] According to the embodiment, the memory system includes a controller configured to write data and history information to one of a plurality of blocks. When the controller copies first data, which is valid data stored in the source block, to the destination block, it reads the first data and first history information, which is history information corresponding to the first data, from the source block, and writes the first data and second history information based on the value of the first history information to the destination block.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory system and a control method for controlling a non-volatile memory.

Background Art

[0002] A memory system including a non-volatile memory and a controller is known.

[0003] In such a memory system, different types of data are handled, such as data with a high rewrite frequency and data with a low rewrite frequency. Data with a high rewrite frequency is referred to as hot data, and data with a low rewrite frequency is referred to as cold data.

[0004] When hot data and cold data are mixed in the same block of the non-volatile memory, a decrease in the efficiency of garbage collection of the non-volatile memory is caused.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0006] A problem to be solved by one embodiment of the present invention is to provide a memory system and a control method useful for identifying the type of each data.

Means for Solving the Problems

[0007] The memory system according to the embodiment comprises a non-volatile memory including a plurality of blocks, and a controller configured to write data and history information corresponding to the data to one of the plurality of blocks. The value of the history information is a value based on the number of times the data has been copied from the block in which the data is stored to another block. When the controller copies first data, which is valid data stored in the source block of the plurality of blocks, to the destination block of the plurality of blocks, it reads the first data and first history information, which is history information corresponding to the first data, from the source block. The controller writes the read first data and second history information, which is the value of the read first history information as the history information corresponding to the first data, to the destination block. [Brief explanation of the drawing]

[0008] [Figure 1] A block diagram showing an example configuration of an information processing device including a memory system according to the embodiment. [Figure 2] A block diagram showing an example configuration of non-volatile memory included in the memory system according to the embodiment. [Figure 3] A circuit diagram showing an example configuration of a non-volatile memory cell array. [Figure 4] Block diagrams showing example configurations for the sense amplifier and data register of non-volatile memory. [Figure 5] A block diagram showing an example configuration of each of the multiple blocks contained in non-volatile memory. [Figure 6] A diagram illustrating the process of writing data and history information to the data area and the remaining area, respectively. [Figure 7] A diagram illustrating the process of reading data and history information from the data area and the remaining area, respectively. [Figure 8]A diagram illustrating the process of writing four cluster data points to the data area and four history information points to the remaining area. [Figure 9] This diagram illustrates the process of reading four cluster data from the data area and then reading four history pieces of information corresponding to each of the four cluster data from the remaining area. [Figure 10] A diagram illustrating the process of generating free blocks through garbage collection (GC). [Figure 11] This diagram illustrates how garbage collection (GC) copies hot and cold data to the same destination block. [Figure 12] A flowchart illustrating the procedure for host write operations performed in a memory system according to an embodiment. [Figure 13] A flowchart illustrating the GC procedure performed in the memory system according to the embodiment. [Figure 14] A flowchart illustrating the procedure for a refresh operation performed in the memory system according to the embodiment. [Figure 15] This diagram illustrates the process of writing a value obtained by adding a first value to the history information value read from the source block during garbage collection (GC) to the target block. [Figure 16] This diagram illustrates the process of writing a value obtained by adding a second value to the history information value read from the block targeted for forced refresh to another block. [Figure 17] This diagram illustrates the process of writing a value obtained by adding a first value to the history information value read from a block that is normally refreshed, to another block. [Figure 18] A diagram illustrating the process of assigning a single representative historical value to several clustered data points. [Modes for carrying out the invention]

[0009] The embodiments will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of an information processing apparatus including a memory system according to an embodiment. The information processing apparatus includes a memory system 1 and a host device 2.

[0010] The memory system 1 is a semiconductor storage device such as a UFS (universal flash storage) or an SSD (solid state drive). The memory system 1 is connected to an external host device 2 and executes data writing processing and data reading processing for the non-volatile memory included in the memory system 1 based on requests from the host device 2. The memory system 1 includes a non-volatile memory 10, a volatile memory 20, and a memory controller 30.

[0011] The non-volatile memory 10 is a non-volatile semiconductor memory. The non-volatile memory 10 is, for example, a NAND flash memory. The non-volatile memory 10 includes a plurality of blocks. Each of the plurality of blocks is a unit of data erasure operation. Each of the plurality of blocks includes a plurality of pages. Each of the plurality of pages is a unit of each of the data writing operation and the data reading operation.

[0012] The non-volatile memory 10 includes, for example, a plurality of chips 10-0 to 10-N (N is an integer of 1 or more) each including a plurality of memory cells. Each of the chips 10-0 to 10-N is, for example, a NAND flash memory chip. Each of the chips 10-0 to 10-N may be a three-dimensional NAND flash memory or a two-dimensional NAND flash memory. Hereinafter, the non-volatile memory 10 is referred to as a NAND flash memory 10.

[0013] The volatile memory 20 is a volatile semiconductor memory. For example, the volatile memory 20 is a DRAM (Dynamic Random Access Memory). The memory area of ​​the volatile memory 20 is used to store firmware for managing the NAND flash memory 10, and various management information used in the memory system 1. In the following description, the volatile memory 20 will be referred to as a DRAM 20.

[0014] An example of management information is the logical-physical address translation table 21. The logical-physical address translation table 21 is a table for holding mapping information. The mapping information is information that shows the correspondence between logical addresses contained in the logical address space of the memory system 1 and physical addresses of the NAND flash memory 10 in units of a predetermined management size.

[0015] A logical address is an address used by the host device 2 to access memory system 1. In other words, memory system 1 has a logical address space with a size corresponding to the capacity of memory system 1, and individual logical addresses within the logical address space are used by the host device 2 to specify the logical address to write to or the logical address to read from within the logical address space. For example, a logical block address (LBA) is used as a logical address.

[0016] The physical address is an address used to identify a storage location (physical storage location) within the NAND flash memory 10.

[0017] A cluster can be used as the predetermined management size. In this case, the mapping information manages the correspondence between each logical address and each physical address on a cluster basis. A cluster may have a size of, for example, 4KB.

[0018] The memory controller 30 is a controller with a circuit, and is implemented as an LSI such as a system-on-a-chip (SoC). Hereinafter, the memory controller 30 will be referred to as controller 30.

[0019] The controller 30 is electrically connected to the NAND flash memory 10 and the DRAM 20, respectively. A Toggle NAND flash interface or an Open NAND Flash Interface (ONFI) can be used as the physical interface connecting the controller 30 and the NAND flash memory 10.

[0020] The controller 30 executes a data write operation based on a write request received from the host device 2. The data write operation is the process of writing data to the NAND flash memory 10. The data write operation includes, for example, the process of obtaining the write data associated with the received write request from the memory of the host device 2, the process of determining the storage location in the NAND flash memory 10 where the write data should be written, the process of instructing the NAND flash memory 10 to perform a data write operation by sending a write command set (command, address, and data) to the NAND flash memory 10, and the process of updating the logical-physical address translation table 21 to map the physical address indicating the storage location where the write data was written to the logical address of the write destination specified by the write request.

[0021] Furthermore, the controller 30 executes a data read operation based on a read request received from the host device 2. The data read operation is the process of reading data from the NAND flash memory 10. The data read operation includes the process of referring to the logical-physical address translation table 21 to identify the physical address to which the logical address specified by the read request is mapped, the process of sending a read command set (command and address) to the NAND flash memory 10 to cause the NAND flash memory 10 to execute a data read operation, and the process of transferring the data read from the NAND flash memory 10 to the memory of the host device 2.

[0022] Next, we will explain the internal configuration of the controller 30.

[0023] The controller 30 includes a processor (CPU) 31, a buffer memory 32, a host interface circuit 33, an error correction circuit 34, a NAND interface circuit 35, a DRAM interface circuit 36, and a history information management unit 37.

[0024] The processor 31 loads the firmware stored in the NAND flash memory 10 or a ROM (Read-only memory) (not shown) into the DRAM 20. Based on this firmware, the processor 31 performs various processes as described below.

[0025] The processor 31, acting as the flash translation layer (FTL), manages the data stored in the NAND flash memory 10 and manages multiple blocks contained within the NAND flash memory 10.

[0026] The management of data stored in the NAND flash memory 10 includes the management of mapping information. The processor 31 uses a logic-physical conversion table 21 to manage the correspondence between each logical address and each physical address in the NAND flash memory 10. The logic-physical conversion table 21 may be loaded from the NAND flash memory 10 to the DRAM 20 when the memory system 1 is powered on. The physical address corresponding to a given logical address indicates the storage location (physical storage location) in the NAND flash memory 10 where the data corresponding to that logical address is written.

[0027] Writing data to each of the multiple pages contained in a block is only possible once per program / erase cycle of that block. Therefore, the processor 31 writes the update data corresponding to a certain logical address to a different physical memory location, rather than to the physical memory location where the previous data corresponding to that logical address is stored. The processor 31 then updates the logic-physical translation table 21 so that the physical address indicating this different physical memory location is mapped to this logical address. This update of the logic-physical translation table 21 invalidates the previous data.

[0028] In the following, data stored in a physical memory location indicated by a physical address mapped to a logical address is referred to as "active data." Active data is the most recent data corresponding to a logical address, that is, data that may be read later by host device 2. Conversely, data stored in a physical memory location indicated by a physical address not mapped to any logical address is referred to as "invalid data." Invalid data is data that can no longer be read by host device 2.

[0029] The management of blocks contained in the NAND flash memory 10 includes, for example, garbage collection (GC) and refresh operations.

[0030] GC (Garbage Collection) is an operation that reduces the number of blocks containing a mix of valid and invalid data, thereby increasing the number of free blocks. Free blocks are blocks that do not store valid data; that is, blocks that can be freely used for writing data after a data erasure operation has been performed on them. Free blocks are also called unused blocks.

[0031] As data is written to the NAND flash memory 10, the number of written blocks increases, while the number of free blocks decreases. Written blocks are blocks filled with data, including at least valid data. In addition, within each written block, the number of invalid data increases due to the writing of update data to the NAND flash memory 10. Therefore, for example, when the condition that the number of remaining free blocks falls below a predetermined number is met, the processor 31 performs garbage collection (GC) of the NAND flash memory 10 so that some written blocks can be reused for writing data.

[0032] In garbage collection (GC), the processor 31 selects a block from among the already written blocks as the source block (also called the source block for GC). The block to be GC is a block that contains a mixture of valid and invalid data. For example, the processor 31 decides on a block with a lower percentage of valid data among the blocks containing a mixture of valid and invalid data as the block to be GC. Then, the processor 31 copies the valid data stored in the block to be GC to the destination block (also called the destination block for GC). In other words, the processor 31 reads the valid data from the block to be GC and writes the read valid data to the destination block.

[0033] When valid data is copied from the GC target block (source block) to the destination block, the processor 31 updates the logical-physical translation table 21 so that the physical address mapped to the logical address corresponding to this valid data changes from the physical address of the source physical storage location to the physical address of the destination physical storage location. As a result, the valid data in the source block that has been copied to the destination block becomes invalid data. Once all valid data in the source block has been copied to the destination block, all data in the source block becomes invalid data. Therefore, this source block is released as a free block.

[0034] Furthermore, whether each piece of data stored in a block targeted by garbage collection (GC) is valid data may be determined using bitmap data containing multiple bits indicating whether each piece of data stored in the GC target block is valid or invalid. Alternatively, when calculating whether data stored at a certain physical storage location within a block targeted by GC is valid data, the physical address mapped to the logical address corresponding to this data may be obtained from the logical-physical address translation table 21. In this case, whether the data stored at this physical storage location is valid data can be determined based on whether the obtained physical address matches the physical address of this physical storage location.

[0035] A refresh operation is an operation that rewrites each of the valid data stored in the target block to another block. There are two types of refresh operations: Type 1 refresh, also known as a forced refresh, and Type 2 refresh, also known as a normal refresh.

[0036] A forced refresh is a refresh operation that rewrites each piece of data (valid data) stored in a block that has been written to it for a period of time exceeding a threshold, to another block. In other words, in memory system 1, an operation is performed to rewrite data written to a block of NAND flash memory 10 to another block within a certain period of time. For this reason, blocks that have been written to them for a period of time exceeding a threshold are selected as targets for forced refresh, and each piece of valid data in the selected block is rewritten to another block.

[0037] A normal refresh is a refresh operation that rewrites each of the data (valid data) stored in a block containing a predetermined number of error bits in the read data (for example, a block that still contains a predetermined number of error bits in the read data even after the execution of a read voltage adjustment operation called "Vth tracking") to another block.

[0038] The buffer memory 32 is a memory used to temporarily store read data read from the NAND flash memory 10 and write data received from the host device 2. The buffer memory 32 is, for example, SRAM (Static Random Access Memory).

[0039] The host interface circuit 33 is connected to the host device 2 via a bus and is responsible for communication between the controller 30 and the host device 2. The bus is, for example, a bus compliant with SAS (Serial attached SCSI (small computer system interface)), SATA (Serial ATA (advanced technology attachment)), or PCIe (Peripheral component interconnect express)).

[0040] The error correction circuit 34 is a circuit for protecting data to be written to the NAND flash memory 10 (user data) with error correction codes (ECC). The error correction circuit 34 encodes the user data to be written to the NAND flash memory 10 and generates a codeword that includes the user data and the ECC. The error correction circuit 34 also decodes the codeword (user data and ECC) read from the NAND flash memory 10 to detect and correct errors contained in the user data. For example, hard-bit decoding and soft-bit decoding can be used as methods for error detection and correction. For example, BCH (Bose Chaudhuri Hocquenghem) codes or RS (Reed Solomon) codes can be used as codes for hard-bit decoding. For example, LDPC (Low Density Parity Check) codes can be used as codes for soft-bit decoding.

[0041] The NAND interface circuit 35 is connected to the NAND flash memory 10 via the memory bus and performs communication with the NAND flash memory 10. The NAND interface circuit 35 controls the transfer of data, commands, and addresses between the controller 30 and the NAND flash memory 10.

[0042] The DRAM interface circuit 36 ​​is connected to the DRAM 20 and performs communication between the controller 30 and the DRAM 20.

[0043] The history information management unit 37 performs processes such as determining the type of individual data (hot data or cold data) based on the history information value corresponding to each data. The history information value corresponding to a given data is a value based on the number of times this data has been copied from the block in which it is stored to another block. This operation of copying data from one block to another can be performed by garbage collection (GC). Therefore, the history information value corresponding to a given data is used as information representing the number of times this data has become data subject to GC (GC count).

[0044] The historical information corresponding to a given data is used to determine whether that data is hot data or cold data. Here, hot data is the data corresponding to each LBA that is frequently written to by host device 2. Cold data is the data corresponding to each LBA that is not frequently written to by host device 2. In other words, data that is frequently rewritten is hot data, and data that is not frequently rewritten is cold data.

[0045] When hot data and cold data are mixed in the same block in roughly equal proportions (for example, when about half the block size is hot data and the remaining half is cold data), the efficiency of garbage collection can be significantly reduced.

[0046] However, the LBAs (or LBA ranges) that are frequently written to and those that are not are not predetermined. When observing logs related to long-term host writes, it may be observed that frequently written LBAs and less frequently written LBAs may swap places with each other.

[0047] Furthermore, the information provided by the host device 2 during data writing typically does not include information indicating the type of data being written. Therefore, it is difficult for the memory system 1 to determine whether the data being written is hot data or cold data based on the information provided by the host device 2 during data writing (such as the destination LBA and the data being written).

[0048] Therefore, in this embodiment, the controller 30 performs a process of writing the data and the history information corresponding to this data to one of the multiple blocks of the NAND flash memory 10, that is, one destination block, in order to identify the type of individual data (hot data / cold data) written to the NAND flash memory 10. Then, when copying certain valid data stored in the source block of these multiple blocks to the destination block of these multiple blocks, the controller 30 reads both the valid data and the history information corresponding to this valid data from the source block. The controller 30 writes the valid data read from the source block to the destination block, and also writes a value larger than the value of the history information read from the source block as new history information corresponding to the valid data read from the source block to the destination block.

[0049] The operation of copying valid data from one block to another can be performed by garbage collection (GC) or by a refresh operation.

[0050] Generally, the longer data remains valid, the more often it is selected for garbage collection (GC) (or refresh operations). Therefore, cold data is more likely to be selected for GC (or refresh operations) than hot data.

[0051] Therefore, by writing both the data and history information to the destination block, and by increasing the value of the history information each time a data copy operation is performed, it becomes possible to effectively use the value of the history information to distinguish between hot data and cold data.

[0052] More specifically, if the value of the history information written to a block along with a given data is above a threshold, the data can be determined to be cold data; if the value of the history information is below the threshold, the data can be determined to be hot data.

[0053] Next, we will explain the configuration of the NAND flash memory 10.

[0054] Figure 2 is a block diagram showing an example configuration of the NAND flash memory 10.

[0055] Figure 2 shows the configuration of chip 10-0 as an example. Note that chips 10-1 to 10-N have the same configuration as chip 10-0, so their explanation is omitted. As shown in Figure 2, chip 10-0 includes an input / output circuit 111, a register set 112, a logic controller 113, a sequencer 114, a ready / busy control circuit 115, a voltage generation circuit 116, a memory cell array 117, a row decoder 118, a sense amplifier 119, a data register 120, and a column decoder 121.

[0056] The input / output circuit 111 is a circuit that transmits and receives input / output signals I / O1 to I / O8, for example, 8 bits wide, with the controller 30. The input / output signals I / O are used for transmitting and receiving data DAT, transmitting status STS, receiving address ADD, and receiving command CMD. The input / output circuit 111 also transmits and receives data DAT with the data register 120.

[0057] Register set 112 includes a status register 112A, an address register 112B, and a command register 112C. The status register 112A, address register 112B, and command register 112C are registers that store the status STS, address ADD, and command CMD, respectively.

[0058] The status STS is updated, for example, based on the operating status of the sequencer 14. The status STS is also transferred from the status register 112A to the input / output circuit 111 based on instructions from the controller 30, and output to the controller 30. The address ADD is transferred from the input / output circuit 11 to the address register 112B. The address ADD may include, for example, the chip address, block address, page address, column address, etc. The command CMD is transferred from the input / output circuit 111 to the command register 112C. The command CMD includes instructions related to various operations of the chip 10-0.

[0059] The logic controller 113 controls the input / output circuit 111 and the sequencer 114, respectively, based on the control signals received from the controller 30. Examples of such control signals include the chip enable signal CEn, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, the read enable signal REn, and the write protect signal WPn.

[0060] The chip enable signal CEn is a signal to enable chip 10-0. The command latch enable signal CLE is a signal to notify the input / output circuit 111 that the received input / output signal I / O is a command CMD. The address latch enable signal ALE is a signal to notify the input / output circuit 111 that the received input / output signal I / O is an address ADD. The write enable signal WEn is a signal to command the input / output circuit 111 to input input / output signal I / O. The read enable signal REn is a signal to command the input / output circuit 111 to output input / output signal I / O. The write protect signal WPn is a signal to put chip 10-0 into a protected state when the power is turned on or off.

[0061] The sequencer 114 controls the operation of the entire chip 10-0. For example, the sequencer 114 performs data read operations, data write operations, data erase operations, etc., based on the command CMD stored in the command register 12C and the address ADD stored in the address register 12B.

[0062] The ready / busy control circuit 115 generates a ready / busy signal RBn based on the operating state of the sequencer 14. The ready / busy signal RBn is a signal to notify the controller 30 whether the chip 10-0 is in a ready state or a busy state. In this specification, "ready state" indicates that the chip 10-0 is in a state where it can accept commands from the controller 30, and "busy state" indicates that the chip 10-0 is not in a state where it can accept commands from the controller.

[0063] The voltage generation circuit 116 generates the voltages used in data read operations, data write operations, data erase operations, etc. The voltage generation circuit 116 then supplies the generated voltages to the memory cell array 117, the row decoder 118, and the sense amplifier 119.

[0064] The memory cell array 117 includes multiple blocks BLK0 to BLKn (where n is an integer greater than or equal to 2). A block BLK is a collection of memory cell transistors capable of storing data non-volatilely and is used as a unit for data erasure operations. Each memory cell transistor is associated with one bit line BL and one word line WL.

[0065] The row decoder 118 selects one block BLK from multiple block BLKs based on the block address. The row decoder 118 then supplies the voltage supplied from the voltage generation circuit 16 to the word line WL within the selected block BLK.

[0066] In a data read operation, the sense amplifier 119 reads data from the memory cell array 117 and transfers the read data to the data register 120. In a data write operation, the sense amplifier 119 applies a predetermined voltage to the bit line BL based on the data stored in the data register 120.

[0067] The data register 120 is a register that temporarily stores data DAT. The data register 120 is connected to the sense amplifier 119. The data register 120 includes multiple latch circuits. Each latch circuit temporarily stores write data or read data.

[0068] The column decoder 121 is a circuit that decodes the column address. The column decoder 121 receives the column address from the address register 112B. Based on the result of decoding the column address, the column decoder 121 selects the latch circuit of the data register 120.

[0069] Next, the configuration of the memory cell array 117 will be described.

[0070] Figure 3 is a circuit diagram showing an example configuration of a memory cell array 117 included in the NAND flash memory 10. Figure 3 shows the configuration of one block BLK of the memory cell array 117.

[0071] As shown in Figure 3, block BLK includes, for example, four string units SU0 to SU3. Note that the configurations of string units SU2 and SU3 are shown in a simplified manner in Figure 3.

[0072] Each string unit SU includes multiple NAND strings NS, each associated with a bit line BL0 to BLm (where m is an integer greater than or equal to 1). The NAND strings NS include, for example, memory cell transistors MT0 to MT15, as well as selection transistors ST1 and ST2.

[0073] The memory cell transistor MT includes a control gate and a charge storage layer, and stores data nonvolatilically. The selection transistors ST1 and ST2 are used to select the string unit SU during various operations.

[0074] In each NAND string NS, memory cell transistors MT0 to MT15 are connected in series. A selection transistor ST1 is connected between one end of the series-connected memory cell transistors MT0 to MT15 and the associated bit line BL. The drain of selection transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT15. The source line SL is connected to the source of selection transistor ST2.

[0075] In the same block BLK, the gates of each of the multiple selection transistors ST1 included in string units SU0 to SU3 are commonly connected to selection gate lines SGD0 to SGD3, respectively. The control gates of each of the multiple memory cell transistors MT0 to MT15 are commonly connected to word lines WL0 to WL15, respectively. The gates of each of the multiple selection transistors ST2 are commonly connected to the selection gate line SGS.

[0076] Bit lines BL0 to BLm are shared among multiple block blocks (BLK). The same bit line BL is connected to the same NAND string NS corresponding to the same column address. Each of the word lines W L0 to WL15 is provided for each block block. Source lines SL are shared, for example, among multiple block blocks.

[0077] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU is called a cell unit CU, and corresponds to a page, which is the unit of data writing and data reading operations, respectively. For example, the storage capacity of a cell unit CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data". A cell unit CU may have a storage capacity of 2 pages of data or more, depending on the number of bits of data stored by the memory cell transistors MT.

[0078] The circuit configuration of the memory cell array 117 described above is merely an example and is not limited thereto. For example, the number of string units SU included in each block BLK can be designed to any number. The number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can each be designed to any number.

[0079] Next, the configuration of the sense amplifier 119 and the data register 120 will be described.

[0080] Figure 4 is a block diagram showing example configurations of the sense amplifier 119 and data register 120 of the NAND flash memory 10.

[0081] The sense amplifier 119 includes multiple sense amplifier units SAU. Each of the multiple sense amplifier units SAU is connected to multiple bit lines BL0 to BLn, respectively.

[0082] The data register 120 includes multiple latch circuits XDL. Each of the multiple latch circuits XDL is connected to a multiple sense amplifier unit SAU. The multiple latch circuits XDL are used for sending and receiving data with the controller 30. In a data read operation, data read from a block BLK in the memory cell array 117 is stored in the multiple latch circuits XDL. In a data write operation, data received from the controller 30 (write data) is stored in the multiple latch circuits XDL.

[0083] The sense amplifier unit SAU includes a sense circuit SA, an arithmetic unit OP, and latch circuits SDL, ADL, BDL, CDL, and TDL. The sense circuit SA, and the latch circuits SDL, ADL, BDL, CDL, and TDL are commonly connected to the corresponding latch circuit XDL via the bus LBUS. In other words, the latch circuit XDL, the sense circuit SA, and the latch circuits SDL, ADL, BDL, CDL, and TDL are connected to each other via the bus LBUS so that they can send and receive data. The number of latch circuits included in the sense amplifier unit SAU may be designed based on the number of data bits that one memory cell transistor MT can store.

[0084] During data read operations, the sense circuit SA senses the data read onto the corresponding bit line BL and determines whether the read data is "0" or "1". During data write operations, the sense circuit SA applies a voltage to the bit line BL based on the data to be written.

[0085] The arithmetic unit OP performs various logical operations using data stored in the latch circuits XDL, SDL, ADL, BDL, CDL, and TDL.

[0086] The latch circuits SDL, ADL, BDL, CDL, and TDL temporarily store read or written data. For example, in a data read operation, the read data is stored in one of the latch circuits SDL, ADL, BDL, CDL, and TDL. Similarly, in a data write operation, the written data from latch circuit XDL is stored in one of the latch circuits SDL, ADL, BDL, CDL, and TDL.

[0087] The latch circuit XDL is used as a cache for data input and output between the sense amplifier unit SAU and the input / output circuit 111. More specifically, write data received from the controller 30 is transmitted via the latch circuit XDL to the latch circuits SDL, ADL, BDL, CDL, or TDL. Similarly, data read from a block BLK in the memory cell array 117 is temporarily held in the latch circuits SDL, ADL, BDL, CDL, or TDL, and then transmitted to the controller 30 via the latch circuit XDL.

[0088] Next, we will explain the configuration of each block BLK.

[0089] Figure 5 is a block diagram showing examples of the configurations of each of the multiple block BLKs included in the NAND flash memory 10.

[0090] The NAND flash memory 10 supports a function (also called the surplus area writing function) that, when writing data to a destination block, allows it to write arbitrary information other than the data to the surplus area of ​​the destination block. Furthermore, the NAND flash memory 10 also supports a function (also called the surplus area reading function) that, when reading data from a target block, allows it to read information stored in the surplus area of ​​that target block.

[0091] In other words, as shown in Figure 5, each of the multiple block BLKs contains multiple pages, and each of the multiple pages contains a data area that is permitted to be accessed from outside the NAND flash memory 10, and a surplus area that is an area other than the data area.

[0092] The data area is an area that can be accessed by writing and reading using standard write and read commands, respectively, and is also called the user access area.

[0093] On the other hand, the surplus area is an area where access is prohibited until a specific procedure for accessing this surplus area is performed on the NAND flash memory 10, and is also called the user-access-restricted area.

[0094] Data transfer between the page, which includes the data area and the surplus area, and the controller 30 is performed via XDL. In Figure 5, a collection of multiple latch circuit XDLs is shown as a single XDL. The data area of ​​the XDL is the area corresponding to the data area of ​​each page. The surplus area of ​​the XDL is the area corresponding to the surplus area of ​​each page.

[0095] In this embodiment, the controller 30 writes data to the data area of ​​one of the multiple pages in the block BLK (the destination page), and writes history information (information representing the number of GC cycles) corresponding to this data to the surplus area of ​​the destination page using a specific procedure.

[0096] In this case, the data received from the controller 30 (for example, a codeword including user data and ECC) is temporarily stored in the XDL data area. The history information received from the controller 30 is also temporarily stored in the XDL surplus area. Then, the data stored in the XDL data area is written to the data area of ​​the destination page, and the history information stored in the XDL surplus area is written to the surplus area of ​​this destination page.

[0097] Figure 6 illustrates the process of writing data and history information to the data area and the surplus area, respectively.

[0098] Here, we assume the use of the Set Feature command as a specific procedure for gaining write access to surplus areas.

[0099] The controller 30 instructs the NAND flash memory 10 to write history information H to the surplus area by sending a set feature command set (set feature command CMD, address (XXh), and data (history information H)) to the NAND flash memory 10. Here, the combination of set feature command CMD and address (XXh) is used to specify the surplus area write function, which is one of several functions supported by the NAND flash memory 10. In the NAND flash memory 10, the history information H received from the controller 30 is temporarily stored in the surplus area of ​​the XDL.

[0100] Next, the controller 30 instructs the NAND flash memory 10 to write data to the data area by sending a write command set (command 80H, address, data, and command 10H) to the NAND flash memory 10. Here, the address following command 80H includes an address specifying the destination block and an address specifying the destination page within this destination block. In the NAND flash memory 10, the data received from the controller 30 (e.g., user data and ECC) is temporarily stored in the XDL data area.

[0101] After receiving a set feature command set from the controller 30, and then receiving a write command set from the controller 30, the NAND flash memory 10 writes the data stored in the data area of ​​the XDL and the history information H stored in the surplus area of ​​the XDL to the data area and surplus area included in the write destination page within the write destination block, respectively.

[0102] In this way, the data is written to the data area in the destination page specified by the write command set that follows the set feature command set, and the history information H is written to the surplus area in this destination page specified by the write command set.

[0103] Next, we will explain the process for retrieving data and historical information.

[0104] Figure 7 illustrates the operation for reading data and history information from the data area and the surplus area, respectively.

[0105] Here, we assume that the GET Feature command is used as a specific procedure for read access to the surplus area.

[0106] First, the controller 30 instructs the NAND flash memory 10 to read data from the data area by sending a read command set (command 00H, address, and command 30H) to the NAND flash memory 10. Here, the address following command 00H includes an address specifying the block to be read and an address specifying the page to be read within the block. The address following command 00H may further include an address within the page to be read.

[0107] Next, the controller 30 instructs the NAND flash memory 10 to read the history information H stored in the surplus area by sending a get-feature command set (get-feature command CMD and address (YYh)) to the NAND flash memory 10. Here, the combination of get-feature command CMD and address (YYh) is used to specify the surplus area read function, which is one of several functions supported by the NAND flash memory 10.

[0108] After receiving a read command set from the controller 30, and then a get feature command set from the controller 30, the NAND flash memory 10 reads data and history information H from the data area and surplus area of ​​the page to be read within the block to be read specified by the read command set. The read data and the read history information H are output to the controller 30 via XDL.

[0109] Figure 8 illustrates the process of writing four cluster data points to the data area and four history information points to the remaining area.

[0110] The page size, or the size of the data area for each page, is, for example, 16KB + α. The α portion of the capacity is used, for example, for storing ECC corresponding to 16KB of data. If one cluster is 4KB and the page size is 16KB + α, then four cluster data and four ECCs corresponding to these four cluster data can be written to the data area. Each cluster data is 4KB in size. In this case, four cluster data can be written to the data area of ​​a page, and four history information entries corresponding to each of the four cluster data can be written to the remaining area of ​​this page.

[0111] First, the controller 30 instructs the NAND flash memory 10 to write history information H1, history information H2, history information H3, and history information H4 to the surplus area by sending a set feature command set (set feature command CMD, address (XXh), and data (history information H1, history information H2, history information H3, history information H4)) to the NAND flash memory 10. In the NAND flash memory 10, the history information H1 to H4 received from the controller 30 is temporarily stored in the surplus area of ​​the XDL.

[0112] Next, the controller 30 instructs the NAND flash memory 10 to write data (in this case, cluster data D1, cluster data D2, cluster data D3, and cluster data D4) to the data area by sending a write command set (command 80H, address, data, and command 10H) to the NAND flash memory 10. In the NAND flash memory 10, cluster data D1, cluster data D2, cluster data D3, and cluster data D4 received from the controller 30 are temporarily stored in the data area of ​​the XDL.

[0113] After receiving a set feature command set from the controller 30, and then receiving a write command set from the controller 30, the NAND flash memory 10 writes the data stored in the data area of ​​the XDL (cluster data D1, cluster data D2, cluster data D3, cluster data D4) and the history information stored in the surplus area of ​​the XDL (history information H1, history information H2, history information H3, history information H4) to the data area and surplus area included in the write destination page within the write destination block, respectively.

[0114] Figure 9 illustrates the process of reading four cluster data from the data area and four history information entries corresponding to each of the four cluster data from the remaining area.

[0115] First, the controller 30 instructs the NAND flash memory 10 to read data from the data area by sending a read command set (command 00H, address, and command 30H) to the NAND flash memory 10.

[0116] Next, the controller 30 instructs the NAND flash memory 10 to read the history information stored in the surplus area by sending a get feature command set (get feature command CMD and address (YYh)) to the NAND flash memory 10.

[0117] After receiving a read command set from the controller 30, and then receiving a get feature command set from the controller 30, the NAND flash memory 10 reads the data (cluster data D1, cluster data D2, cluster data D3, cluster data D4) stored in the data area of ​​the page to be read within the read target block specified by the read command set, and the history information (history information H1, history information H2, history information H3, history information H4) stored in the surplus area of ​​this page to be read. The read data (cluster data D1, cluster data D2, cluster data D3, cluster data D4) and the read history information (history information H1, history information H2, history information H3, history information H4) are output to the controller 30 via XDL.

[0118] Thus, in this embodiment, the history information corresponding to each data is written to the surplus area, not to the data area used for writing the data (data and ECC). It is also possible to use a configuration in which both the data and the corresponding history information are written to the data area. However, in this case, since a part of the data area is used for storing the history information, the size of the data area available for writing data is reduced by the size of the history information. By writing the history information to the surplus area, it is possible to record the number of GC cycles for each data without reducing the size of the data area available for writing data.

[0119] Next, I will explain garbage collection (GC).

[0120] Figure 10 is a diagram illustrating the process by which garbage collection (GC) generates free blocks.

[0121] Figure 10 assumes that each block BLK is composed of a set of eight clusters. Each small, horizontal rectangle within each block BLK represents one cluster.

[0122] Each cluster is in one of the following states: a state where valid data (valid cluster data) is stored, a state where invalid data (invalid cluster data) is stored due to the writing of update data, or an erased state where data has not yet been written after a block data erase operation has been performed.

[0123] The top of Figure 10 shows the state of the NAND flash memory 10 before garbage collection (GC). The bottom of Figure 10 shows the state of the NAND flash memory after GC. The middle section of Figure 10 shows how each active cluster data is copied by GC.

[0124] Before garbage collection, the number of unused blocks (free blocks) falls below a certain threshold. In the upper part of Figure 10, the blank unused block frame represents a situation where, although some free blocks actually remain, the number of remaining free blocks is small.

[0125] Furthermore, before garbage collection, there are many written blocks. Among these written blocks, there are, for example, blocks where all the stored data is valid data, as well as several blocks where valid and invalid data are mixed.

[0126] When performing garbage collection (GC), the controller 30, for example, prioritizes selecting blocks with a lower effective data rate from among the written blocks as the blocks to be GC'd (GC source blocks).

[0127] The controller 30 then allocates the free block as the copy destination block BLK (GC destination block) and copies only the valid cluster data from the GC source block to the GC destination block.

[0128] When valid cluster data is copied from a source block to a destination block, the controller 30 updates the logical-physical address translation table 21 so that the physical address of the destination storage location of this valid cluster data is mapped to the logical address corresponding to this valid cluster data. As a result, the valid cluster data in the source block that was copied to the destination block is invalidated.

[0129] Once all valid cluster data has been copied to the GC target block by the GC, the source block is reused as an unused block (free block) for writing data after a data erasure operation is performed on that source block.

[0130] Each GC target block is filled with 8 valid cluster data points by the garbage collector. Each GC target block filled with 8 valid cluster data points is managed as a written block.

[0131] The lower part of Figure 10, which shows the situation after garbage collection, illustrates an example where each of the written blocks is filled with 8 valid cluster data.

[0132] Figure 11 shows how hot data and cold data are copied to the same GC destination block (copy destination block) by garbage collection (GC).

[0133] Individual active cluster data can be either hot data or cold data. Therefore, when garbage collection (GC) is performed using the procedure described in Figure 10, as shown at the bottom of Figure 11, hot active cluster data and cold active cluster data may be mixed in the same GC target block. In Figure 11, the small, horizontal white squares labeled "(Hot)" or "(Cold)" represent active data (active cluster data). Here, "(Hot)" represents data that potentially has the properties of hot data, and "(Cold)" represents data that potentially has the properties of cold data. Normally, it is not possible to determine whether individual data is hot or cold data. Therefore, in Figure 11, the potential properties of individual data are expressed by enclosing "Hot" and "Cold" in parentheses, as in "(Hot)" and "(Cold)". Thus, normally, it is not possible to distinguish between hot and cold data, so hot and cold data are mixed in the same block. In that case, GC efficiency decreases.

[0134] Of the eight active cluster data copied to the GC target block, each active cluster data that is hot data may be immediately invalidated by the writing of update data.

[0135] For example, in the GC target block BLK at the bottom right of Figure 11, four of the eight copied valid cluster data are hot data, and the remaining four are cold data.

[0136] Therefore, when each hot data (i.e., (Hot)) in this GC target block BLK is invalidated, the effective data rate of this GC target block BLK decreases. Consequently, this GC target block BLK becomes more likely to be selected as a block for GC. When this GC target block BLK is selected as a block for GC, the four effective cluster data, which are cold data (i.e., (Cold)), are copied again to another block.

[0137] Therefore, in each individual block, it is desirable that more of the data within the block is cold data, or that more of the data within the block is hot data.

[0138] If almost all the data within a block is hot data, the effective data rate of that block will be low. When all the data is invalidated by writing updated data, the block can be made a free block without performing garbage collection on it. Also, even if some of the hot data within the block remains effective data, the block can be made a free block with only a small amount of data copying, improving GC efficiency.

[0139] On the other hand, if almost all the data within a block is cold data, the effective data rate of this block remains high. Therefore, this block does not require garbage collection (GC). As a result, the cold data within this block will not be copied by GC.

[0140] In this embodiment, the controller 30 performs the following processing to enable a simple determination of whether each data item targeted for GC is cold data or hot data, using the number of times it has been selected for GC, and to improve GC efficiency by avoiding the mixing of cold data and hot data within the same block as much as possible.

[0141] (1) Writing data When writing data to a block, the controller 30 writes history information (GC count) to that block.

[0142] (1-1) Host Light A host write is a data writing process that is performed based on a write request received from host device 2. When a host write is performed, that is, when the data associated with the write request received from host device 2 is written to the destination block, the controller 30 writes an initial value (e.g., 0) of the history information (GC count) to the destination block.

[0143] (1-2)GC When GC copies valid data from the source block to the destination block, the controller 30 writes a value to the destination block that is obtained by adding a first value (for example, 1) to the value of the previous history information (GC count) corresponding to this valid data. Note that the value of each history information is limited to a certain upper limit. Therefore, if the value of the previous history information (GC count) has reached the upper limit, the controller 30 writes the same value as the previous history information (GC count) to the destination block.

[0144] (1-3) Refresh operation (1-3-1) Forced refresh operation When a forced refresh operation copies valid data from the target block to another block, the controller 30 writes a value to the other block that is the sum of the previous history information (GC count) value corresponding to this valid data and a second value. The second value is the same as the first value, or a value greater than the first value. Each valid data in the target block of the forced refresh operation is data that has been held as valid data in that block for a long time. Therefore, the GC count for each of these valid data tends to be kept at a relatively small value. For this reason, in order to make each valid data in the target block of the forced refresh operation more likely to be treated as cold data, it is preferable to add a second value greater than the first value to the previous history information (GC count) value.

[0145] (1-3-2) Normal refresh operation When valid data is copied from the target block to another block during a normal refresh operation, the controller 30 writes to this other block a value obtained by adding a first value (for example, 1) to the value of the previous history information (number of GC operations) corresponding to this valid data, similar to the case of GC.

[0146] (2) Switching to the GC target block When performing garbage collection (GC), the controller 30 switches the block to be used as the GC destination block between the GC destination block allocated for cold data and the GC destination block allocated for hot data, based on whether the value of the history information (GC count) read from the GC source block is equal to or greater than a threshold. By switching the block to be used as the GC destination block in this way, cold data and hot data can be written to different blocks, respectively. As a result, it is possible to avoid mixing cold data and hot data within the same block, thereby improving GC efficiency.

[0147] Next, we will explain the procedure for hosting a light.

[0148] Figure 12 is a flowchart showing the procedure for a host write operation performed in memory system 1.

[0149] In response to receiving a write request from host device 2, controller 30 writes the data associated with the write request and the corresponding history information (GC count) to the destination block (step S101). In this case, controller 30 writes the data to the data area of ​​the destination page within the destination block and writes the initial value of the history information (GC count) to the surplus area of ​​the destination page. The writing of the initial value of the history information (GC count) to the surplus area is performed using the set feature command.

[0150] Next, I will explain the garbage collection procedure.

[0151] Figure 13 is a flowchart showing the garbage collection (GC) procedure performed in memory system 1.

[0152] When performing garbage collection (GC), the controller 30 selects blocks with a lower effective data rate as the target blocks for GC (GC source blocks). The controller 30 reads both the effective data stored in the GC source block and the history information H corresponding to this effective data from the GC source block (step S111). In step S111, the effective data is read from the data area of ​​a page within the GC source block, and the history information H is read from the surplus area of ​​this page. The reading of the history information H from the surplus area is performed using the get feature command.

[0153] The controller 30 determines whether the value of the read history information H is greater than or equal to a threshold (step S112).

[0154] If the value of the read history information H is greater than or equal to a threshold (Yes in step S112), the controller 30 selects the first block as the GC destination block (step S113). The first block is the block allocated for collecting cold data and is referred to as the cold data write destination block or the cold data GC destination block.

[0155] If the value of the read history information H is smaller than the threshold (No in step S112), the controller 30 selects a second block different from the first block as the GC destination block (step S114). The second block is a block allocated for collecting hot data and is referred to as the hot data write destination block or the hot data GC destination block.

[0156] The controller 30 writes the read valid data to the data area of ​​the GC destination block (GC destination block for cold data or GC destination block for hot data) and writes (H+a) to the surplus area of ​​the GC destination block (GC destination block for cold data or GC destination block for hot data) (step S115).

[0157] More specifically, if the value of the read history information H is greater than or equal to a threshold, the controller 30 writes the read valid data to the data area of ​​one of the multiple pages contained in the cold data GC destination block, and writes (H+a) to the surplus area of ​​that page. If the value of the read history information H is less than a threshold, the controller 30 writes the read valid data to the data area of ​​one of the multiple pages contained in the hot data GC destination block, and writes (H+a) to the surplus area of ​​that page.

[0158] Here, in (H+a), "H" is the value of the read history information H, and "a" in (H+a) is, for example, 1, so (H+a) is the value obtained by adding, for example, 1 to "H". Writing (H+a) to the surplus area is performed using the set feature command.

[0159] In S115, the controller 30 may determine whether the value of the read history information H has reached the upper limit. In this case, if the value of the read history information H has reached the upper limit, the controller 30 writes the same value as the read history information H, i.e., "H", to the surplus area. If the value of the read history information H has not yet reached the upper limit, it writes (H+a) to the surplus area. The upper limit is a value determined based on the size of the history information, and this upper limit is a value greater than the threshold used in S112. Therefore, by limiting the value of the history information to the upper limit, it is possible to switch the GC destination block to which the data should be copied between the GC destination block for cold data and the GC destination block for hot data without unnecessarily increasing the value of the history information.

[0160] Next, we will explain the procedure for the refresh operation.

[0161] Figure 14 is a flowchart showing the procedure for the refresh operation performed in memory system 1.

[0162] When performing a forced refresh or a normal refresh, the controller 30 selects the blocks to be refreshed. In a forced refresh, the blocks to be refreshed are those for which a threshold period has elapsed since data was written. In a normal refresh, the blocks to be refreshed are those for which the read data still contains a predetermined number of error bits even after the read voltage adjustment operation has been performed.

[0163] The controller 30 reads both the valid data stored in the block to be refreshed and the history information H corresponding to this valid data from the block to be refreshed (step S121). In step S121, the valid data is read from the data area of ​​the page in the block to be refreshed, and the history information H is read from the surplus area of ​​this page. The reading of the history information H from the surplus area is performed using the get feature command.

[0164] The controller 30 determines whether the refresh operation currently being performed is a forced refresh or a normal refresh (step S122).

[0165] If the controller determines that the currently executing refresh operation is a forced refresh (Yes in step S122), the controller 30 writes the read valid data to the data area of ​​another block (the copy destination block for refresh) and writes (H+b) to the surplus area of ​​the copy destination block for refresh (step S123). More specifically, the controller 30 writes the read valid data to the data area of ​​one of the multiple pages contained in the copy destination block for refresh and writes (H+b) to the surplus area of ​​this page. In (H+b), "H" is the value of the read history information H, and "b" is a value greater than or equal to "a". In order to make it easier for data that is subject to forced refresh to be classified as cold data, it is preferable that "b" be set to a value greater than "a".

[0166] On the other hand, if the controller determines that the currently executing refresh operation is a forced refresh (No in step S122), the controller 30 writes the read valid data to the data area of ​​the refresh destination block and writes (H+a) to the surplus area of ​​the refresh destination block (step S124).

[0167] In both S123 and S124, the values ​​of the history information are limited to the upper limit, just as in the case of GC.

[0168] Next, an example of garbage collection (GC) in this embodiment will be described.

[0169] Figure 15 illustrates the operation of writing a value obtained by adding a first value to the history information value read from the source block during garbage collection (GC) to the target block. The first value corresponds to the aforementioned "a".

[0170] In Figure 15, blocks BLK1 to BLK6 are written blocks. Also, in Figure 15, as in Figure 10, it is assumed that each block BLK contains a set of 8 clusters. The small horizontal rectangles within each block BLK represent one cluster. The small horizontal white rectangles labeled "(Hot)" or "(Cold)" represent valid data (valid cluster data). In other words, of the 8 cluster data in each block, each valid cluster data is represented by "deemed Hot" or "deemed Cold". Here, "deemed Hot" indicates that this cluster data is treated as hot data in this embodiment. Also, "deemed Cold" indicates that this cluster data is treated as cold data in this embodiment. Furthermore, the number next to "deemed Hot" or "deemed Cold" in each valid cluster data represents the value of the history information stored in the surplus area. Here, the threshold is 10. Each cluster data with a corresponding history information value of less than 10 is represented as "presumably Hot," and each cluster data with a corresponding history information value of 10 or more is represented as "presumably Cold." In this case, the first value is 1. Cluster data designated as "presumably Hot" may actually be hot data, but it may also be cold data that is stored in a block with a lot of valid data, resulting in fewer garbage collection attempts and consequently a small history information value. Since such cluster data exists, "presumably Hot" does not necessarily mean that it is actually hot data that is frequently rewritten. However, since such cluster data is less likely to be selected for garbage collection in the first place, in the garbage collection of this embodiment, the possibility of such cluster data and other cluster data that is actually hot data being written to the same destination block is low.

[0171] Of blocks BLK1 to BLK6, block BLK3 has the lowest effective data rate. Therefore, controller 30 selects block BLK3 as the block to be GC'd (the block from which GC will be performed).

[0172] In block BLK3, both the first and third cluster data are valid data.

[0173] The controller 30 reads the first cluster data and the first history information corresponding to the first cluster data from block BLK3. The value of the first history information corresponding to the first cluster data is 3. Therefore, the first cluster data is determined to be considered Hot, and the controller 30 selects the write destination block allocated for hot data as the GC destination block. In Figure 15, block BLK11 is the write destination block allocated for hot data. The controller 30 then writes the read first cluster data to the first cluster of block BLK11, and writes a value of 4, obtained by adding 1 to the read first history information, to block BLK11 as new history information corresponding to the read first cluster data.

[0174] Controller 30 reads the third cluster data and the third history information corresponding to the third cluster data from block BLK3. The value of the third history information corresponding to the third cluster data is 2. Therefore, the third cluster data is determined to be presumably Hot, and controller 30 selects block BLK11 as the GC target block. Then, controller 30 writes the read third cluster data to the second cluster of block BLK11, and writes a value of 3 (the read third history information plus 1) to block BLK11 as new history information corresponding to the read third history information.

[0175] The blocks with the next lowest effective data rate after block BLK3 are block BLK4 and block BLK6. Here, we assume that block BLK6 is selected as the block to be garbage collected (the block from which garbage collection will be performed).

[0176] In block BLK6, the first, fourth, fifth, and seventh cluster data are all valid data.

[0177] The controller 30 reads the first cluster data and the first history information corresponding to the first cluster data from block BLK6. The value of the first history information corresponding to the first cluster data is 14. Therefore, the first cluster data is determined to be deemed cold, and the controller 30 selects the write destination block allocated for cold data as the GC destination block. In Figure 15, block BLK12 is the write destination block allocated for cold data. The controller 30 then writes the read first cluster data to the first cluster of block BLK12, and writes a value of 15, obtained by adding 1 to the read first history information, to block BLK12 as new history information corresponding to the read first cluster data.

[0178] Similarly, the remaining three valid cluster data in block BLK6 are determined to be deemed Cold. Therefore, the remaining three valid cluster data in block BLK6 and three new history entries, each with a value of 15, are written to block BLK12.

[0179] Next, block BLK4 is selected as the source block. The four valid cluster data in block BLK4 are determined to be considered Cold. Then, the four valid cluster data from block BLK4 and four new history information entries (14, 14, 14, 13) are written to block BLK12.

[0180] Next, block BLK5 is selected as the source block. The five valid cluster data in block BLK5 are determined to be considered Hot. Then, the five valid cluster data in block BLK5 and five new history information entries (3,3,4,4,2) are written to block BLK11. At this stage, seven valid cluster data entries have been written to block BLK11, so the number of remaining available clusters in block BLK11 is 1. The first cluster data in block BLK2 is valid data, and the value of the first history information entry corresponding to this first cluster data is 3. Therefore, the first cluster data in block BLK2 is data that is determined to be considered Hot. Consequently, the first cluster data in block BLK2 and one new history information entry (4) may be written to block BLK11.

[0181] Next, an example of a forced refresh in this embodiment will be described.

[0182] Figure 16 illustrates the operation of writing a value obtained by adding a second value to the history information value read from the block targeted for forced refresh to another block. The second value corresponds to the aforementioned "b".

[0183] In Figure 16, the small, horizontal white squares labeled "(Hot)" or "(Cold)" represent valid data (valid cluster data). Figure 16 also assumes that block BLK1 is selected as the block to be forcibly refreshed. Block BLK1 is a block where data has been written for more than a threshold period. Here, it is assumed that each of the eight cluster data points in block BLK1 is valid data, and that the corresponding history information value for each of these eight cluster data points is 1. Furthermore, the second value is 5.

[0184] The controller 30 reads eight cluster data and eight history information entries corresponding to each of these eight cluster data from block BLK1. The controller 30 then writes each of these eight cluster data to a write destination block for forced refresh (in this case, block BLK21), and also writes a value of 6, obtained by adding 5 to the value of each history information entry, to block BLK21 as new history information corresponding to each of the eight cluster data.

[0185] Next, an example of a normal refresh in this embodiment will be described.

[0186] Figure 17 illustrates the operation of writing a value obtained by adding a first value to the history information value read from the block that is normally refreshed, to another block.

[0187] In Figure 17, the small, horizontal white squares labeled "(Hot)" or "(Cold)" represent valid data (valid cluster data). Figure 17 also assumes that block BLK1 is selected as the block to be refreshed. Here, it is assumed that each of the eight cluster data points in block BLK1 is valid data, and that the corresponding history information value for each of these eight cluster data points is 1. In this case, the first value is 1.

[0188] The controller 30 reads eight cluster data and eight history information entries corresponding to each of these eight cluster data from block BLK1. The controller 30 then writes each of these eight cluster data to the normal refresh write destination block (in this case, block BLK31), and also writes a value of 6, obtained by adding 1 to the value of each history information entry, to block BLK31 as new history information corresponding to each of the eight cluster data.

[0189] The above explanation described the case where one history entry is assigned to each cluster of data. This configuration allows for strict control over the number of garbage collection (GC) operations for each individual cluster of data.

[0190] However, one configuration may be used in which a single representative historical value is assigned to several clusters of data.

[0191] Figure 18 illustrates the process of assigning a single representative historical value to several clustered data points.

[0192] Figure 18 assumes a scenario where data for four clusters is written to the data area of ​​each page, and one representative history value is written to the remaining area of ​​each page.

[0193] In block BLK100, four cluster data entries are written to each data area of ​​pages P1 to P3, and one representative history value is written to the remaining area of ​​each page P1 to P3. As the representative history value, for example, the minimum value of the four history pieces of information corresponding to each of the four cluster data entries can be used. This means that the number of garbage collections (GCs) of the data with the highest update frequency among the four cluster data entries stored on the same page becomes the representative history value, making it less likely that the data with the highest update frequency among the four cluster data entries stored on the same page will be classified as cold data. A detailed explanation follows below.

[0194] On page P1 of block BLK100, only cluster data A is valid, while the other three cluster data are already invalid. The representative historical value for the four cluster data on page P1 is 3.

[0195] On page P2 of block BLK100, only cluster data B is valid; the other three cluster data are already invalid. The representative historical value for the four cluster data on page P2 is 5.

[0196] On page P3 of block BLK100, cluster data C and cluster data D are both valid data, while the other two cluster data are already invalid. The representative historical value for the four cluster data on page P3 is 4.

[0197] In other words, the historical information value for cluster data A is 3, the historical information value for cluster data B is 5, the historical information value for cluster data C is 4, and the historical information value for cluster data D is 4.

[0198] Here, we assume that cluster data A, cluster data B, cluster data C, and cluster data D from block BLK100 are copied to page P1 of block BLK200 by the garbage collector (GC).

[0199] Controller 30 selects block BLK100, the block to be GC, as the source block. Controller 30 reads cluster data A and representative history value 3 from page P1 of block BLK100, cluster data B and representative history value 5 from page P2 of block BLK100, and cluster data C, cluster data D, and representative history value 4 from page P3 of block BLK100. The minimum value among the representative history values ​​corresponding to cluster data A, cluster data B, cluster data C, and cluster data D is 3. Therefore, Controller 30 writes cluster data A, cluster data B, cluster data C, and cluster data D to the data area of ​​page P1 of block BLK200, and writes 4, which is the minimum value 3 plus 1, to the surplus area of ​​page P1 of block BLK200 as the representative history value for cluster data A, cluster data B, cluster data C, and cluster data D.

[0200] As described above, according to this embodiment, the controller 30 writes data and history information corresponding to this data to one of the multiple block BLKs of the NAND flash memory 10. When copying valid data stored in the source block of the multiple block BLKs to the destination block of the multiple block BLKs, the controller 30 reads both the valid data and the history information corresponding to this valid data from the source block. The controller 30 then writes the read valid data to the destination block and writes a new history information corresponding to this valid data to the destination block that is larger than the value of the read history information. Generally, the longer the period that data is kept as valid data, the more times this data is selected as data to be GC (or refresh operation) performed. For this reason, cold data is more likely to be selected as data to be GC (or refresh operation) than hot data. Therefore, by writing both the data and history information to the block, and by increasing the value of the history information of the copied valid data each time a data copy operation is performed, it becomes possible to effectively use the value of the history information to distinguish between hot data and cold data.

[0201] Note that the value of each history information is limited to an upper limit. Therefore, if the value of the read history information (first history information) does not reach the upper limit, a value greater than the value of the first history information is written to the destination block as new history information (second history information). If the value of the first history information reaches the upper limit, the same value as the value of the first history information is written to the destination block as new history information (second history information). In other words, new history information (second history information) based on the value of the read history information (first history information) is written to the destination block.

[0202] Furthermore, when performing garbage collection (GC) on the NAND flash memory 10, the controller 30 selects the block to be GC'd as the source block and determines whether the value of the history information read from the source block is above a threshold. If the controller 30 determines that the value of the history information read from the source block is above a threshold, it selects the first block BLK among the multiple block BLKs of the NAND flash memory 10 as the destination block. If the controller 30 determines that the value of the history information read from the source block is below a threshold, it selects a second block, different from the first block, as the destination block. This prevents hot data and cold data from mixing within the same block, thereby improving the efficiency of GC.

[0203] Furthermore, the controller 30 writes history information corresponding to individual data to a surplus area, rather than to the data area used for writing the data. By writing history information to the surplus area in this way, it becomes possible to efficiently record the history information of individual data without reducing the size of the data area available for writing data.

[0204] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0205] 1…Memory system 2…Host device 10…Non-volatile memory 30…Memory controller 31… Processor 37…History Information Management Department

Claims

1. Non-volatile memory containing multiple blocks, The system comprises a controller configured to write data and corresponding history information to one of the aforementioned plurality of blocks, wherein the value of the history information is a value based on the number of times the data has been copied from the block in which the data is stored to another block. The aforementioned controller, When copying the first data, which is valid data stored in the source block among the aforementioned multiple blocks, to the destination block among the aforementioned multiple blocks, The first data and the first history information, which is history information corresponding to the first data, are read from the source block. The system is configured to write the first data read out and the second history information, which is based on the value of the first history information read out as history information corresponding to the first data, to the copy destination block. Memory system.

2. The aforementioned controller, Determine whether the value of the first history information read out is equal to or greater than a threshold, In response to determining that the value of the first history information is equal to or greater than the threshold, the first block among the plurality of blocks is selected as the copy destination block. In response to determining that the value of the first history information is less than the threshold, the system is further configured to select a second block from among the plurality of blocks, which is different from the first block, as the copy destination block. The memory system according to claim 1.

3. The aforementioned controller, The system is further configured to generate the second history information by adding a first value to the value of the first history information read out. The memory system according to claim 2.

4. The aforementioned controller, The system is configured to select blocks from which data has been written for a period of time or longer as the source block for copying. The memory system according to claim 3.

5. The aforementioned controller, When selecting a block as the source block after a threshold period has elapsed since data was written, the system is further configured to generate a second history information by adding a second value greater than the first value to the value of the first history information that was read out. The memory system according to claim 4.

6. The aforementioned controller, Determine whether the value of the first history information read out has reached the upper limit. In response to the determination that the value of the first history information has reached the upper limit, the second history information will be set to the same value as the first history information. The system is further configured such that, in response to determining that the value of the first history information has not reached the upper limit, a value greater than the value of the first history information is set as the second history information. The memory system according to claim 1.

7. Each of the aforementioned blocks includes multiple pages, Each of the aforementioned pages includes a data area that is permitted to be accessed from outside the non-volatile memory and a surplus area which is an area other than the data area, wherein access to the surplus area is prohibited until a specific procedure for accessing the surplus area is performed on the non-volatile memory. The controller is configured to write data to the data area of ​​one of the multiple pages contained in one of the multiple blocks, and to write history information corresponding to the data to the surplus area of ​​the one page using the specific procedure. The aforementioned controller, When copying the first data stored in the source block to the destination block, The first data is read from the data area of ​​the first page of the source block, and the first history information is read from the surplus area of ​​the first page of the source block using the specific procedure. The system is further configured to write the first data to the data area of ​​the second page of the destination block, and to write the second history information to the surplus area of ​​the second page of the destination block using the specific procedure described above. The memory system according to claim 1, 2, 3, 4, or 6.

8. A memory system that can be connected to a host, Non-volatile memory containing multiple blocks, The system comprises a controller configured to write data and corresponding history information to one of the aforementioned plurality of blocks, wherein the value of the history information is a value based on the number of times the data has been copied from the block in which the data is stored to another block. The aforementioned controller, Upon receiving a write request from the host, the data associated with the write request and the initial value of the history information corresponding to the data are written to the destination block among the plurality of blocks. When performing garbage collection, When selecting a block containing the first block and the second block as the source block for the garbage collection, The first data, which is valid data included in the first block, and the first history information, which is history information corresponding to the first data, are read from the first block. The second data, which is valid data contained in the second block, and the second history information, which is history information corresponding to the second data, are read from the second block. Determine whether the value of the first history information read out is equal to or greater than a threshold, In response to determining that the value of the first history information is equal to or greater than the threshold, a third block among the plurality of blocks is selected as the copy destination block, and the read first data and the third history information, which is the value obtained by adding the first value to the value of the read first history information as the history information corresponding to the first data, are written to the third block. In response to determining that the value of the first history information is less than the threshold, a fourth block from the plurality of blocks, different from the third block, is selected as the copy destination block, and the read first data and the third history information are written to the fourth block. Determine whether the value of the second history information read out is equal to or greater than the threshold, In response to determining that the value of the second history information is equal to or greater than the threshold, the third block is selected as the copy destination block, and the read second data and the fourth history information, which is the value obtained by adding the first value to the value of the read second history information as the history information corresponding to the second data, are written to the third block. In response to determining that the value of the second history information is less than the threshold, the fourth block is selected as the copy destination block, and the read second data and the fourth history information are written to the fourth block. It is structured in such a way. Memory system.

9. Each of the aforementioned blocks includes multiple pages, Each of the aforementioned pages includes a data area that is permitted to be accessed from outside the non-volatile memory and a surplus area which is an area other than the data area, wherein access to the surplus area is prohibited until a specific procedure for accessing the surplus area is performed on the non-volatile memory. The controller is configured to write data to the data area of ​​one of the multiple pages contained in one of the multiple blocks, and to write history information corresponding to the data to the surplus area of ​​the one page. The aforementioned controller, When performing the aforementioned garbage collection, The first data is read from the data area of ​​the first page of the first block, and the first history information is read from the surplus area of ​​the first page of the first block using the specific procedure. The system is further configured to write the first data to the data area of ​​the second page of the destination block, and to write the third history information to the surplus area of ​​the second page of the destination block using the specific procedure described above. The memory system according to claim 8.

10. The aforementioned controller, The system is configured to select blocks from which data has been written for a period of time or longer as the source block for copying. The memory system according to claim 8.

11. The aforementioned controller, When selecting a block as the source block after a threshold period has elapsed since the data was written, The system is further configured to read a fifth history information, which is the history information of the source block, from the source block, generate a sixth history information by adding a second value greater than the first value to the value of the read fifth history information, and write the sixth history information to the destination block. The memory system according to claim 10.

12. A method for controlling non-volatile memory containing multiple blocks, Data and history information corresponding to the data are written to one of the aforementioned plurality of blocks, and the value of the history information is a value based on the number of times the data has been copied from the block in which the data is stored to another block. When copying the first data, which is valid data stored in the source block among the plurality of blocks, to the destination block among the plurality of blocks, The first data and the first history information, which is history information corresponding to the first data, are read from the source block. The first data read out and the second history information, which corresponds to the first data and has a value greater than the value of the first history information read out, are written to the destination block. method.

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