Semiconductor memory

Abstract

Reduce the size of each memory cell. [Solution] In a semiconductor memory device, a third conductive film extends within the first semiconductor film in a third direction. The third direction intersects the first and second directions. A fourth conductive film is spaced apart from the third conductive film in a first direction. The fourth conductive film extends within the first semiconductor film in a third direction. A fifth conductive film extends within the first semiconductor film in a third direction between the third and fourth conductive films. A reference potential is applied to the fifth conductive film. A first memory cell is provided at a position where the first conductive film faces the first semiconductor film via a first insulating film. A second memory cell is provided at a position where the second conductive film faces the first semiconductor film via a second insulating film.

Description

[Technical Field]

[0001] This embodiment relates to a semiconductor memory device. [Background technology]

[0002] In semiconductor memory devices having multiple memory cells, the multiple memory cells are sometimes configured to be arranged in a three-dimensional manner. In semiconductor memory devices, reducing the size of the memory cells is desirable in order to achieve high integration of multiple memory cells. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-013907 [Patent Document 2] U.S. Patent No. 11404431 [Patent Document 3] U.S. Patent Application Publication No. 2023 / 0077181 [Patent Document 4] U.S. Patent No. 11610909 [Non-patent literature]

[0004] [Non-Patent Document 1] Symp. VLSI Technol. 2018, P.117 [Non-Patent Document 2] HT Lue et al., Dig. Tech. Pap. - Symp. VLSI Technol. 2018, 177, (2018). [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] One embodiment aims to provide a semiconductor memory device that can reduce the size of each memory cell. [Means for solving the problem]

[0006] According to one embodiment, a semiconductor memory device is provided having a first conductive film, a second conductive film, a first semiconductor film, a first insulating film, a second insulating film, a third conductive film, a fourth conductive film, and a fifth conductive film. The first conductive film extends in a first direction. The second conductive film is spaced apart from the first conductive film in a second direction. The second direction intersects the first direction. The second conductive film extends in a first direction. The first semiconductor film is disposed between the first conductive film and the second conductive film. The first semiconductor film extends in a first direction and a second direction. The first insulating film is disposed between the first conductive film and the first semiconductor film. The first insulating film extends in a first direction. The second insulating film is disposed between the second conductive film and the first semiconductor film. The second insulating film extends in a first direction. The third conductive film extends within the first semiconductor film in a third direction. This third direction intersects with the first and second directions. The fourth conductive film is spaced apart from the third conductive film in the first direction. The fourth conductive film extends within the first semiconductor film in the third direction. The fifth conductive film extends within the first semiconductor film in the third direction between the third and fourth conductive films. A reference potential is applied to the fifth conductive film. A first memory cell is provided at a position where the first conductive film faces the first semiconductor film via a first insulating film. A second memory cell is provided at a position where the second conductive film faces the first semiconductor film via a second insulating film. [Brief explanation of the drawing]

[0007] [Figure 1] A perspective view showing the configuration of a semiconductor memory device according to the first embodiment. [Figure 2] A block diagram showing the configuration of a semiconductor memory device according to the first embodiment. [Figure 3] A circuit diagram showing the configuration of a semiconductor memory device according to the first embodiment. [Figure 4] A plan view showing the configuration of the memory cell array in the first embodiment. [Figure 5] A cross-sectional view showing the configuration of the memory cell array in the first embodiment. [Figure 6]Cross-sectional view showing the configuration of the memory cell array in the first embodiment. [Figure 7] Cross-sectional view showing the manufacturing method of the semiconductor memory device according to the first embodiment. [Figure 8] Planar view showing the manufacturing method of the semiconductor memory device according to the first embodiment. [Figure 9] Planar view showing the manufacturing method of the semiconductor memory device according to the first embodiment. [Figure 10] Perspective view showing the configuration of the semiconductor memory device according to the second embodiment. [Figure 11] Circuit diagram showing the configuration of the semiconductor memory device according to the second embodiment. [Figure 12] Planar view showing the configuration of the memory cell array in the second embodiment. [Figure 13] Cross-sectional view showing the configuration of the memory cell array in the second embodiment. [Figure 14] Planar view showing the manufacturing method of the semiconductor memory device according to the second embodiment. [Figure 15] Perspective view showing the configuration of the semiconductor memory device according to the third embodiment. [Figure 16] Circuit diagram showing the configuration of the semiconductor memory device according to the third embodiment. [Figure 17] Planar view showing the configuration of the memory cell in the third embodiment. <​​​​​​​​​​​​​​​​​​​​​The semiconductor memory device according to the embodiment will be described in detail below with reference to the attached drawings. However, the present invention is not limited to these embodiments.

[0009] (First embodiment) The semiconductor memory device according to the first embodiment has a plurality of memory cells, which are arranged in a three-dimensional array, and measures are taken to reduce the size of each memory cell.

[0010] The semiconductor memory device 1 may be configured as shown in Figure 1. Figure 1 is a perspective view showing the configuration of the semiconductor memory device 1.

[0011] The semiconductor memory device 1 is a three-dimensional memory, for example, a ferroelectric memory. The semiconductor memory device 1 includes a substrate SB, a memory cell array 2, a plurality of conductive films (a plurality of first conductive films, a plurality of second conductive films) WL, a plurality of conductive films (a plurality of third conductive films) BL, a plurality of conductive films (a plurality of fifth conductive films) BC, and a plurality of conductive films (a plurality of fourth conductive films) SL. Hereinafter, the direction perpendicular to the surface of the substrate SB will be defined as the Z direction, and the two mutually orthogonal directions in the plane perpendicular to the Z direction will be defined as the X direction and the Y direction.

[0012] Multiple conductive films WL are stacked on the +Z side of the substrate SB, spaced apart in the Z direction. Multiple layers of insulating layer IF2 and conductive films WL may be arranged alternately. Multiple conductive films WL are arranged in the X direction. Each conductive film WL extends in a plate-like manner in the XY direction. Each conductive film WL has its longitudinal direction in the Y direction. The conductive films WL may be formed from a material mainly composed of metal, such as tungsten (W). The substrate SB may be formed from a material mainly composed of semiconductor, such as silicon. The insulating layer IF2 may be formed from an insulator, such as silicon oxide.

[0013] In the example shown in Figure 1, the conductive film WL is divided and insulated in the Y direction by the slit IF3. The slit IF3 can be formed from an insulator such as silicon oxide. The slit IF3 is located on the +Z side of the substrate SB and extends in both the Y and Z directions.

[0014] The memory cell array 2 has a plurality of semiconductor films SF and a plurality of insulating films FE.

[0015] Multiple semiconductor films SF are stacked on the +Z side of the substrate SB, spaced apart in the Z direction. Multiple layers of insulating layer IF2 and semiconductor films SF may be arranged alternately. Multiple semiconductor films SF are arranged in the XYZ direction.

[0016] Multiple semiconductor films SF adjacent in the Y direction between multiple conductive films WL are electrically isolated by an insulating film IF1. Multiple semiconductor films SF adjacent in the X direction across multiple word lines WL are electrically isolated by a slit IF3. Slit IF3 can be formed from a material mainly composed of an insulator (e.g., silicon oxide). Multiple semiconductor films SF adjacent in the Z direction are electrically isolated by an insulating layer IF2.

[0017] Each semiconductor film SF extends in a plate-like manner in the XY direction. Each semiconductor film SF can be formed from a semiconductor film whose main component is a semiconductor (e.g., silicon).

[0018] Multiple insulating films FE are stacked on the +Z side of the substrate SB, spaced apart in the Z direction. Multiple layers of insulating layer IF2 and insulating films FE may be arranged alternately. Multiple insulating films FE are arranged in the X direction. In the X direction, each insulating film FE is positioned between the conductive film WL and the semiconductor film SF. Each insulating film FE extends linearly in the Y direction. Each insulating film FE may be formed of an insulator. Each insulating film FE may contain a ferroelectric material.

[0019] Each insulating film FE may be formed from a material primarily composed of hafnium oxide (HfO). Each insulating film FE may further be formed from a material containing at least one element selected from the group including silicon (Si), scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), zirconium (Zr), aluminum (Al), strontium (Sr), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

[0020] Multiple conductive films BL are arranged in the XY direction on the +Z side of the substrate SB. The XY arrangement of the multiple conductive films BL corresponds to the XY arrangement of the multiple semiconductor films SF. Each conductive film BL corresponds to multiple semiconductor films SF aligned in the Z direction. Each conductive film BL extends in the Z direction, penetrating the corresponding multiple semiconductor films SF, and reaches the semiconductor film SF on the -Z side. Each conductive film BL does not reach the substrate SB. Each conductive film BL extends in the Z direction within the semiconductor films SF. Each conductive film BL can be formed from a material mainly composed of metal, such as tungsten (W).

[0021] Multiple conductive films SL are arranged in the XY direction on the +Z side of the substrate SB. The XY arrangement of the multiple conductive films SL corresponds to the XY arrangement of multiple semiconductor films SF, and corresponds to the XY arrangement of multiple conductive films BL. Each conductive film SL corresponds to multiple semiconductor films SF arranged in the Z direction. Each conductive film SL extends in the Z direction, penetrating the corresponding multiple semiconductor films SF at a position spaced apart from the conductive film BL in the Y direction, and reaching the semiconductor film SF on the -Z side. Each conductive film SL does not reach the substrate SB. Each conductive film SL extends in the Z direction within the semiconductor film SF. Each conductive film SL can be formed from a material mainly composed of metal, such as tungsten (W).

[0022] Multiple conductive films BC are arranged in the XY direction on the +Z side of the substrate SB. The XY arrangement of the multiple conductive films BC corresponds to the XY arrangement of multiple semiconductor films SF, the XY arrangement of multiple conductive films BL, and the XY arrangement of multiple conductive films SL. Each conductive film BC corresponds to multiple semiconductor films SF arranged in the Z direction. Each conductive film BC extends in the Z direction, penetrating the corresponding multiple semiconductor films SF at a position between conductive films BL and SL, and reaching the substrate SB. Each conductive film BC extends in the Z direction within the semiconductor films SF. Each conductive film BC can be formed from a material mainly composed of metal, such as tungsten (W).

[0023] In the semiconductor memory device 1, a laminate SST is constructed in which a conductive film WL, an insulating film FE, a semiconductor film SF, and an insulating layer IF2 are alternately stacked. The laminate SST is located on the +Z side of the substrate SB via an interlayer insulating film 81. The interlayer insulating film 81 can be formed from an insulator such as silicon oxide.

[0024] In a stacked SST, the conductive film WL functions as a word line. The conductive film BL functions as a bit line. The conductive film BC functions as a body contact line. The conductive film SL functions as a source line. The semiconductor film SF functions as a channel region. Multiple semiconductor films SF are arranged in the XYZ directions, and in the X direction, the insulating film FE and conductive film WL are adjacent to each other in order, forming a three-dimensional array of memory cells (memory cell array). The conductive films BL, BC, and SL each penetrate the stacked SST.

[0025] In other words, in the semiconductor memory device 1, the portion of the semiconductor film SF facing the conductive film WL via the insulating film FE functions as a memory cell MT, and a memory cell array 2 is formed in which multiple memory cells MT are arranged three-dimensionally. In the semiconductor memory device 1, the storage capacity can be increased by increasing the number of layers of conductive film WL in the stacked structure SST, without using finer patterning techniques.

[0026] Furthermore, on the +Z side of the conductive film BL, selection transistors BT1 and BT2 may be provided, respectively, for selectively supplying a selectable potential to the conductive film BL. Selection transistors BT1 and BT2 are driven via selection gate lines SG1 and SG2, respectively, connected to their gates. On the +Z side of the conductive film SL, selection transistors ST1 and ST2 may be provided, respectively, for selectively supplying a selectable potential to the conductive film SL. Selection transistors ST1 and ST2 are driven via selection gate lines SG1 and SG2, respectively, connected to their gates. For simplification, the selection transistors BT1, BT2, ST1, and ST2 are not shown in Figure 1.

[0027] Figure 2 is a block diagram showing the schematic configuration of the semiconductor memory device 1. As shown in Figure 2, the semiconductor memory device 1 has a memory cell array 2, peripheral circuits 100, and an interface 200. The peripheral circuits 100 include a WL drive circuit 110, an SG1 drive circuit 120, an SG2 drive circuit 130, an SL drive circuit 140, and a sense amplifier circuit 150.

[0028] The WL drive circuit 110 is a circuit that controls the voltage applied to the conductive film WL, and the SG1 drive circuit 120 is a circuit that controls the voltage applied to the selected gate line SG1. The SG2 drive circuit 130 is a circuit that controls the voltage applied to the selected gate line SG2, and the SL drive circuit 140 is a circuit that controls the voltage applied to the conductive film SL. The sense amplifier circuit 150 is a circuit that controls the voltage applied to the conductive film BL, and is also a circuit that determines the data read out according to the signal from the selected memory cell.

[0029] The peripheral circuit 100 controls the operation of the semiconductor memory device 1 based on instructions input from an external source (for example, the memory controller of the memory system to which the semiconductor memory device 1 is applied) via the interface 200.

[0030] Next, the circuit configuration of memory cell array 2 will be explained using Figure 3. Figure 3 is a three-dimensional diagram showing the circuit configuration of memory cell array 2.

[0031] In memory cell array 2, multiple memory cells MT are connected by a NOR-type circuit. Both random and serial access are possible for these multiple memory cells MT.

[0032] In Figure 3, the memory cell array 2 is provided with, for example, 2k+n+1 word lines WL_1 to WL_2k+n+1 (where k and n are integers greater than or equal to 2). The memory cell array 2 is also provided with m bit lines BL_1 to BL_m (where m is an integer greater than or equal to 2), m source lines SL_1 to SL_m, and m body contact lines BC_1 to BC_m.

[0033] The memory cell array 2 can be divided into m drive units DU_1 to DU_m. Each drive unit DU contains 2n memory cells MT that share a bit line BL, a source line SL, and a body contact line BC. Each of the 2n memory cells MT contains two sets of n memory cells MT aligned in the Z direction. By arranging the drive units DU in the XY direction, a three-dimensional array of multiple memory cells MT is formed.

[0034] In the drive unit DU, n memory cells MT aligned in the Z direction are connected in parallel between the bit line BL and the source line SL, forming a NOR-type memory cell group MG. Similarly, two memory cells MT aligned in the X direction are connected in parallel between the bit line BL and the source line SL. In other words, each drive unit DU is configured such that two memory cell groups aligned in the X direction share the bit line BL, the source line SL, and the body contact line BC.

[0035] The word lines WL are located on both sides of the drive unit DU in the X direction and connect across the drive units DU aligned in the Y direction. The word lines WL are connected to the gates of multiple memory cells MT aligned in the Y direction.

[0036] Furthermore, if selection transistors BT1 and BT2 are provided on the +Z side of the bit line BL, the drains of selection transistors BT1 and BT2 are connected to the bit line BL, and the sources are connected to the global bit line, respectively. Selection transistors BT1 and BT2 are driven via selection gate lines SG1 and SG2, which are connected to their gates, respectively.

[0037] When selection transistors ST1 and ST2 are provided on the +Z side of source line SL, the drains of selection transistors ST1 and ST2 are connected to source line SL, and the sources of selection transistors ST1 and ST2 are connected to the global source line, respectively. Selection transistors ST1 and ST2 are driven via selection gate lines SG1 and SG2, which are connected to their gates, respectively.

[0038] Next, the detailed configuration of the memory cell array 2 will be explained using Figures 4 to 6. Figure 4 is an XY plan view showing the configuration of the memory cell array 2, and is an enlarged XY plan view corresponding to part A in Figure 1. Figure 5 is an XZ cross-sectional view showing the configuration of the memory cell array 2, and shows the cross-section corresponding to the cross-section of Figure 4 cut along the BB line. Figure 6 is an XZ cross-sectional view showing the configuration of the memory cell array 2, and shows the cross-section corresponding to the cross-section of Figure 4 cut along the CC line.

[0039] As shown in Figure 4, in the memory cell array 2, adjacent memory cells MT_1 and MT_2 in the X direction form a back-to-back structure. Adjacent memory cells MT_1 and MT_2 in the X direction share a common semiconductor film SF and also share conductive films BL, BC, and SL, respectively. The -X side portion of the semiconductor film SF functions as the channel region CH of memory cell MT_1, and the +X side portion of the semiconductor film SF functions as the channel region CH of memory cell MT_2. The channel regions CH of memory cell MT_1 and MT_2 face each other in the X direction with conductive films BL, BC, and SL in between. Conductive films BL, BC, and SL are spaced apart in the Y direction. Conductive film BC is positioned between conductive films BL and SL in the Y direction.

[0040] As shown in Figures 5 and 6, in the memory cell array 2, adjacent memory cells MT_1 and MT_3 in the Z direction do not share a common semiconductor film SF, but they do share conductive films BL, BC, and SL, respectively. The channel region CH of memory cell MT_1 and the channel region CH of memory cell MT_3 face each other in the Z direction via an insulating layer IF2. The channel region CH of memory cell MT_1 covers the -X side surfaces of conductive films BL, BC, and SL. The channel region CH of memory cell MT_3 covers the -X side surfaces of conductive films BL, BC, and SL at a Z position -Z side from the channel region CH of memory cell MT_1.

[0041] Adjacent memory cells MT_2 and MT_4 in the Z direction do not share a common semiconductor film SF, but they do share conductive films BL, BC, and SL, respectively. The channel region CH of memory cell MT_2 and the channel region CH of memory cell MT_4 are separated in the Z direction via an insulating layer IF2. The channel region CH of memory cell MT_2 covers the +X side surfaces of conductive films BL, BC, and SL. The channel region CH of memory cell MT_4 covers the +X side surfaces of conductive films BL, BC, and SL at a Z position -Z side from the channel region CH of memory cell MT_2.

[0042] In this structure, conductive films BL, BC, and SL function as bit lines, body contact lines, and source lines, respectively. Conductive films BL and SL are supplied with a potential corresponding to the operation of the memory cell MT.

[0043] At this time, a fixed potential is supplied to the conductive film BC, which suppresses electric field interference between adjacent memory cells MT_1 and MT_2 in the X direction. As a result, adjacent memory cells MT_1 and MT_2 in the X direction can share the conductive films BL, BC, and SL, while bringing their respective channel regions CH closer together, thereby reducing the cell size of each memory cell MT.

[0044] Furthermore, since a fixed potential is supplied to the conductive film BC, potential fluctuations in the channel region CH can be suppressed. As a result, threshold fluctuations due to substrate stray effect in the channel region CH can be suppressed in each memory cell MT, and the influence of noise during reading can be reduced.

[0045] For example, when a write operation of "1" is performed to the selected memory cell MT_1, a select potential of "1" (e.g., -2.5V) is applied to the conductive film WL of the selected memory cell MT_1, and a non-select potential (e.g., 0V) is applied to the conductive film WL of the non-selected memory cells MT_2 to MT_4. The global bit line and global source line are controlled to a select potential of "1" (e.g., 2.5V), and the potential of the substrate SB is controlled to the potential when "1" is written (e.g., 2.5V). The select potentials of the global bit line and global source line are supplied to the conductive film BL and conductive film SL, respectively, via the selection transistor, and the potential of the substrate SB is supplied to the conductive film BC.

[0046] In response, the channel region CH of the selected memory cell MT_1 becomes a selection potential (e.g., 2.5V), and in the selected memory cell MT_1, an electric field (e.g., 5V) exceeding the threshold for the conductive film WL to be positive relative to the channel region CH is applied to the insulating film FE, causing a write operation to the memory cell MT that shifts Vth in the negative direction. A "1" can be written to the memory cell MT. If the memory cell MT is easily self-polarized, it can retain the "1". This allows for the proper writing of a "1" to the selected memory cell MT_1.

[0047] At this time, a fixed potential is supplied to the conductive film BC, so electric field interference between adjacent memory cells MT_1 and MT_2 in the X direction can be suppressed, and potential fluctuations in the channel region CH can be suppressed. Between adjacent memory cells MT_1 and MT_3 in the Z direction, electric field interference can be suppressed by the interposition of the insulating layer IF2. This suppresses erroneous writing to non-selected memory cells MT_2 to MT_4.

[0048] Alternatively, when a "0" write operation is performed to the selected memory cell MT_1, a "0" selection potential (e.g., 2.5V) is applied to the conductive film WL of the selected memory cell MT_1, and a non-selection potential (e.g., 0V) is applied to the conductive film WL of the non-selected memory cells MT_2 to MT_4. The global bit line and global source line are controlled to a "0" selection potential (e.g., -2.5V), and the potential of the substrate SB is controlled to the potential when "0" is written (e.g., -2.5V). The selection potentials of the global bit line and global source line are supplied to the conductive film BL and conductive film SL via the selection transistor, respectively, and the potential of the substrate SB is supplied to the conductive film BC.

[0049] In response, the channel region CH of the selected memory cell MT_1 becomes a select potential (e.g., -2.5V), and in the selected memory cell MT_1, an electric field (e.g., -5V) exceeding the threshold at which the conductive film WL becomes negative relative to the channel region CH is applied to the insulating film FE, causing a write operation to the memory cell MT that shifts Vth in the positive direction. A "0" can be written to the memory cell MT. If the memory cell MT is easily self-polarized, it can retain the "0". This allows for the proper writing of a "0" to the selected memory cell MT_1.

[0050] At this time, a fixed potential is supplied to the conductive film BC, so electric field interference between adjacent memory cells MT_1 and MT_2 in the X direction can be suppressed, and potential fluctuations in the channel region CH can be suppressed. Between adjacent memory cells MT_1 and MT_3 in the Z direction, electric field interference can be suppressed by the interposition of the insulating layer IF2. This suppresses erroneous writing to non-selected memory cells MT_2 to MT_4.

[0051] Alternatively, when a read operation is performed on the selected memory cell MT_1, the read selection potential (e.g., 1.5V) is applied to the conductive film WL of the selected memory cell MT_1, and the non-selection potential (e.g., 0V) is applied to the conductive film WL of the non-selected memory cells MT_2 to MT_4. The global bit line is controlled to the read selection potential (e.g., 0.5V), the global source line is controlled to the read selection potential (e.g., 0V), and the potential of the substrate SB is controlled to the read potential (e.g., 0V). The selection potentials of the global bit line and global source line are supplied to the conductive film BL and conductive film SL, respectively, via the selection transistor, and the potential of the substrate SB is supplied to the conductive film BC.

[0052] If "1" is written to the selected memory cell MT_1, cell current flows from the conductive film BL to the conductive film SL in the channel region CH of the selected memory cell MT_1, causing the potential of the conductive film BL to decrease. The sense amplifier circuit 150 detects "1" in response to the decrease in the potential of the conductive film BL. As a result, "1" is read from the selected memory cell MT_1. Alternatively, if "0" is written to the selected memory cell MT_1, almost no cell current flows from the conductive film BL to the conductive film SL in the channel region CH of the selected memory cell MT_1, and the potential of the conductive film BL is maintained. The sense amplifier circuit 150 detects "0" in response to the maintenance of the potential of the conductive film BL. As a result, "0" is read from the selected memory cell MT_1.

[0053] At this time, a fixed potential is supplied to the conductive film BC, so electric field interference between adjacent memory cells MT_1 and MT_2 in the X direction can be suppressed. Between adjacent memory cells MT_1 and MT_3 in the Z direction, electric field interference can be suppressed by the presence of the insulating layer IF2. This suppresses erroneous reads from non-selected memory cells MT_2 to MT_4.

[0054] Furthermore, since a fixed potential is supplied to the conductive film BC, potential fluctuations in the channel region CH can be suppressed. This reduces the influence of noise on the read signal from the selected memory cell MT_1.

[0055] As shown in Figures 5 and 6, a barrier metal may be placed at the interface between the conductive film WL, the insulating layer IF2, and the insulating film FE. The barrier metal may consist of two layers, varimetal BM1 and BM2, in order from the conductive film WL side. Varimetal BM1 may be formed from a material mainly composed of a metal with barrier properties, such as titanium. Varimetal BM2 may be formed from a material mainly composed of a metal nitride with barrier properties, such as titanium nitride.

[0056] Next, the manufacturing method of the semiconductor memory device 1 will be explained using Figures 7 to 9. Figures 7(a) to 7(e) are cross-sectional views showing the manufacturing method of the semiconductor memory device 1. Figures 8(a) to 8(c) and 9(a) to 9(c) are plan views showing the manufacturing method of the semiconductor memory device 1. Figures 8(a) to 8(c) and 9(a) to 9(c) correspond to the XY cross-sections obtained when Figure 7(e) is cut along the DD line, respectively.

[0057] In the process shown in Figure 7(a), a transistor is formed on the substrate SB (see Figure 1), and contact plugs, wiring films, via plugs, etc. are formed on the substrate SB, and an interlayer insulating film 81 is formed around them. This forms the peripheral circuit 100 (see Figure 2). Subsequently, the interlayer insulating film is deposited on the +Z side of the substrate SB. The interlayer insulating film 81 (see Figure 1) can be formed from a material mainly composed of an insulator (e.g., a semiconductor oxide such as silicon oxide). An insulating layer IF2 and a semiconductor film SFab are alternately deposited multiple times on the +Z side of the interlayer insulating film 81 to form a laminate SSTA. The insulating layer IF2 can be formed from a material mainly composed of a semiconductor oxide (e.g., silicon oxide). The semiconductor film SFab can be formed from a material mainly composed of a semiconductor (e.g., silicon). The thickness of the insulating layer IF2 and the thickness of the semiconductor film SFab may be approximately equal or different. For example, the thickness of the insulating layer IF2 may be 30 nm, and the thickness of the semiconductor film SFab may be 20 nm.

[0058] A resist pattern with an opening at the formation position of the slit IF3 (see Figure 1) is formed on the uppermost insulating layer IF2 of each laminated SSTa. Anisotropic etching, such as RIE (Reactive Ion Etching), is performed using the resist pattern as a mask to form grooves TR that extend in the Y direction and penetrate the laminated SSTa in the Z direction, reaching the interlayer insulating film 81.

[0059] In the process shown in Figure 7(b), a semiconductor film recess treatment is performed to etch and recede the side surface of the semiconductor film SFab exposed in the groove TR. This semiconductor film recess treatment forms a recess TRa on the inner surface of the groove TR. The recess TRa is formed so as to be recessed in the direction away from the X-direction center plane CP of the groove TR relative to the inner surface of the groove TR at the Z position of the semiconductor film SFab in the laminate SSTa. For example, the inner surface of the groove TR is wet-etched using an etchant with a high etching selectivity ratio for the semiconductor film SFab relative to the insulating layer IF2. Alternatively, the inner surface of the groove TR is dry-etched under isotropic etching conditions using a processing gas with a high etching selectivity ratio for the semiconductor film SFab relative to the insulating layer IF2. This allows the side surface of the semiconductor film SFb exposed in the groove TR to be etched and receded, forming a recess TRa on the inner surface of the groove TR. The recess width (amount of recess) of the recess TRa relative to the inner surface of the groove TR can be adjusted by the etching time. The width of the recess TRa in the Z direction is approximately equal to the thickness of the semiconductor film SFb. The semiconductor film SFb has a striped shape when viewed in the XY plane.

[0060] In the process shown in Figure 7(c), an insulating film FEa is deposited on the side and bottom surfaces of the groove TR. The insulating film FEa is deposited in an amorphous state. At this time, the insulating film FEa is embedded in the recess TRa. The insulating film FEa can be formed from a material mainly composed of ferroelectric material. The insulating film FEa can be formed from a material in an amorphous state.

[0061] The insulating film FEa can be formed from a material primarily composed of hafnium oxide (HfO), for example. The insulating film FEa may further be formed from a material containing at least one element selected from the group including silicon (Si), scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), zirconium (Zr), aluminum (Al), strontium (Sr), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

[0062] A resist pattern with an opening at the formation position of the slit IF3 (see Figure 1) is formed on the uppermost insulating layer IF2 of each laminate SSTb. Anisotropic etching, such as RIE (Reactive Ion Etching), is performed using the resist pattern as a mask. This removes the insulating film FEa in the groove TR while leaving the portion embedded in the recess TRa of the insulating film FEa.

[0063] An insulating film recess treatment is performed to etch and recede the side surface of the insulating film FEa exposed in the groove TR. This insulating film recess treatment forms a recess TRb on the inner surface of the groove TR. The recess TRb is formed so as to be recessed in the Z position of the insulating film FEb in the laminate SSTb, away from the X-direction center plane CP of the groove TR relative to the inner surface of the groove TR. For example, the inner surface of the groove TR is wet-etched using an etchant with a high etching selectivity ratio of insulating film FEb to insulating layer IF2. Alternatively, the inner surface of the groove TR is dry-etched under isotropic etching conditions using a processing gas with a high etching selectivity ratio of insulating film FEb to insulating layer IF2. This allows the side surface of the insulating film FEb exposed in the groove TR to be etched and receded, forming a recess TRb on the inner surface of the groove TR. The recess width (amount of recess) of the recess TRb relative to the inner surface of the groove TR can be adjusted by the etching time. The width of the recess TRb in the Z direction is approximately equal to the thickness of the semiconductor film SFb.

[0064] The laminated SSTb is heat-treated. As a result, the amorphous insulating film FEb crystallizes and becomes polycrystalline. Simultaneously, the crystallinity of the semiconductor film SFb is improved.

[0065] In the process shown in Figure 7(d), barrier metal BM2, barrier metal BM1, and conductive film WL are sequentially embedded in groove TR and recess TRb. Barrier metal BM2 may be formed from a material mainly composed of a metal nitride with barrier properties, such as titanium nitride. Barrier metal BM1 may be formed from a material mainly composed of a metal with barrier properties, such as titanium. Conductive film WL may be formed from a material mainly composed of a metal, such as tungsten (W).

[0066] A resist pattern with an opening for the formation of slit IF3 (see Figure 1) is formed on the uppermost insulating layer IF2 of each laminate SSTb. Anisotropic etching, such as RIE (Reactive Ion Etching), is performed using the resist pattern as a mask. This removes the barrier metal BM2, barrier metal BM1, and conductive film WL from the groove TR, while leaving the portions embedded in the recess TRb of each barrier metal BM2, barrier metal BM1, and conductive film WL.

[0067] In the process shown in Figure 7(e), the slit IF3 is embedded in the groove TR. The slit IF3 can be formed from an insulator such as silicon oxide.

[0068] In the process shown in Figure 8(a), a resist pattern with openings for the formation of the insulating film IF1 (see Figure 1) is formed on the uppermost insulating layer IF2 of each laminate SSTb. Anisotropic etching, such as RIE (Reactive Ion Etching), is performed using the resist pattern as a mask. This forms a groove TR2 that extends in the X direction at a position that divides the semiconductor film SFb and the insulating films FEb on both sides in the X direction in the Y direction, and penetrates the laminate SSTb in the Z direction to reach the interlayer insulating film 81. At this time, the groove TR2 is formed such that portions of the conductive film WL remain connected in the Y direction on both sides in the X direction. As a result, the semiconductor film SFb is divided into multiple semiconductor films SF aligned in the Y direction, and the insulating film FEb is divided into multiple insulating films FE aligned in the Y direction.

[0069] In the process shown in Figure 8(b), an insulating film IF1 is embedded in the groove TR2. The insulating film IF1 can be formed from an insulator such as silicon oxide.

[0070] In the process shown in Figure 8(c), a resist pattern with openings for the formation of the conductive film BC (see Figure 1) is formed on the uppermost insulating layer IF2 of each laminate SSTb. Anisotropic etching, such as RIE (Reactive Ion Etching), is performed using the resist pattern as a mask. This creates a hole CH that penetrates the laminate SSTc in the Z direction and reaches the substrate SB near the center of the semiconductor film SF in the XY direction. At this time, the hole CH is formed such that portions of the semiconductor film SF remain connected in the Y direction on both sides in the X direction.

[0071] In the process shown in Figure 9(a), a conductive film BC is embedded in the hole CH. The conductive film BC can be formed from a material mainly composed of metal, such as tungsten (W). This creates a conductive film BC that penetrates the semiconductor film SF, extends in the Z direction, and reaches the substrate SB.

[0072] In the process shown in Figure 9(b), resist patterns with openings for the formation positions of conductive films SL and BL (see Figure 1) are formed on the uppermost insulating layer IF2 of each laminate SSTc. Anisotropic etching, such as RIE (Reactive Ion Etching), is performed using the resist patterns as a mask. This forms holes SH, which penetrate the laminate SSTd in the Z direction and reach the semiconductor film SF on the -Z side, between the center and +Y side of the semiconductor film SF in the XY direction, and holes BH, which penetrate the laminate SSTd in the Z direction and reach the semiconductor film SF on the -Z side, between the center and -Y side of the semiconductor film SF in the XY direction. At this time, holes SH are formed such that portions of the semiconductor film SF remain connected in the Y direction on both sides in the X direction, and are separated in the Y direction from the insulating film IF1 and conductive film BC, respectively. Holes BH are formed such that portions of the semiconductor film SF remain connected in the Y direction on both sides in the X direction, and are separated in the Y direction from the insulating film IF1 and conductive film BC, respectively.

[0073] In the process shown in Figure 9(c), a conductive film SL is embedded in hole SH and a conductive film BL is embedded in hole BH. The conductive film SL can be formed from a material mainly composed of metal, such as tungsten (W). The conductive film BL can be formed from a material mainly composed of metal, such as tungsten (W). This creates a conductive film SL that penetrates the semiconductor film SF and extends in the Z direction to the semiconductor film SF on the -Z side, and a conductive film BL that penetrates the semiconductor film SF and extends in the Z direction to the semiconductor film SF on the -Z side.

[0074] Thus, the semiconductor memory device 1 shown in Figures 1 to 6 can be manufactured using the manufacturing method shown in Figures 7 to 9.

[0075] As described above, in the first embodiment, in the memory cell array 2 of the semiconductor memory device 1, adjacent memory cells MT in the X direction form a back-to-back structure with a common semiconductor film SF, and share conductive films BL, BC, and SL, respectively. Conductive film BC is positioned between conductive films BL and SL and extends in the Z direction to reach the substrate SB. As a result, a fixed potential can be supplied to the channel region CH via conductive film BC, so that the channel regions CH of adjacent memory cells MT_1 and MT_2 in the X direction can be brought closer to each other while suppressing electric field interference. As a result, the cell size of each memory cell MT can be reduced in the semiconductor memory device 1.

[0076] Furthermore, in the first embodiment, a fixed potential can be supplied to the channel region CH of each memory cell MT via the conductive film BC in the semiconductor memory device 1, thereby suppressing potential fluctuations in the channel region CH. As a result, threshold fluctuations due to substrate stray effect in the channel region CH of each memory cell MT can be suppressed, and the influence of noise during reading can be suppressed.

[0077] (Second embodiment) Next, a semiconductor memory device 101 according to the second embodiment will be described. The following description will focus on the differences from the first embodiment.

[0078] In the first embodiment, a structure is exemplified in which a conductive film BC is introduced as a body contact line between adjacent memory cells in the X direction within the memory cell array, while in the second embodiment, a structure is exemplified in which an air gap AG is introduced between adjacent memory cells in the X direction within the memory cell array.

[0079] The semiconductor memory device 101 may be configured as shown in Figure 10. Figure 10 is a perspective view showing the configuration of the semiconductor memory device 101.

[0080] The semiconductor memory device 101 has a memory cell array 102 instead of the memory cell array 2 (see Figure 1), further has an air gap AG, and omits multiple conductive films BC.

[0081] The memory cell array 102 has multiple semiconductor films SF1 and multiple semiconductor films SF2 instead of multiple semiconductor films SF (see Figure 1). Semiconductor films SF1 and SF2 are obtained by dividing semiconductor film SF in the X direction. An air gap AG is interposed between semiconductor films SF1 and SF2 in the X direction. Conductive films SL and BL are separated in the Y direction via the air gap AG. The X width of the air gap AG is smaller than the X width of conductive film SL and smaller than the X width of conductive film BL.

[0082] The difference between the crystal orientation of semiconductor film SF1 and semiconductor film SF2 is 5 degrees or less. For example, the difference between the orientation of the (100) plane of semiconductor film SF1 and the orientation of the (100) plane of semiconductor film SF2 is 5 degrees or less. As a result, semiconductor films SF1 and SF2 have nearly identical crystal orientations and can be considered to have crystallinity relatively close to that of a single crystal.

[0083] The air gaps AG are arranged in the XY direction on the +Z side of the substrate SB. The XY arrangement of multiple air gaps AG corresponds to the XY arrangement of multiple semiconductor films SF1, multiple semiconductor films SF2, multiple conductive films BL, and multiple conductive films SL. Each air gap AG corresponds to multiple semiconductor films SF1 and multiple semiconductor films SF2 aligned in the Z direction. Each air gap AG extends in the Z direction between the corresponding semiconductor films SF1 and SF2, reaching the semiconductor film SF on the -Z side.

[0084] In the semiconductor memory device 101, the portion of the semiconductor film SF1 or semiconductor film SF2 facing the conductive film WL via an insulating film FE functions as a memory cell MT, and a memory cell array 102 is formed in which a plurality of memory cells MT are arranged three-dimensionally.

[0085] The circuit configuration of the memory cell array 102 is the same as that of the memory cell array 2 (see Figure 3), but with the body contact lines BC_1 to BC_m omitted, as shown in Figure 11. Figure 11 is a three-dimensional diagram showing the circuit configuration of the memory cell array 102. Each drive unit DU is configured to share bit line BL and source line SL with two memory cell groups aligned in the X direction. The circuit configuration of the memory cell array 102 is basically the same as that of the memory cell array 2 in all other respects.

[0086] In the memory cell array 102, an air gap AG is introduced between adjacent memory cells MT in the X direction, as shown in Figures 12 and 13. Figure 12 is an XY plan view showing the configuration of the memory cell array 102, and is an enlarged XY plan view corresponding to portion D of Figure 10. Figure 13 is an XZ cross-sectional view showing the configuration of the memory cell array 102, and shows a cross-section corresponding to the cross-section of Figure 12 cut along the EE line.

[0087] As shown in Figure 12, in the memory cell array 102, adjacent memory cells MT_1 and MT_2 in the X direction form a back-to-back structure, similar to the first embodiment. However, it differs from the first embodiment in that the back-to-back memory cells MT_1 and MT_2 are electrically isolated by an air gap AG.

[0088] Adjacent memory cells MT_1 and MT_2 in the X direction share conductive films BL and SL, respectively. Semiconductor film SF1 functions as the channel region CH of memory cell MT_1, and semiconductor film SF2 functions as the channel region CH of memory cell MT_2. The channel regions CH of memory cell MT_1 and MT_2 face each other in the X direction, separated by conductive films BL, SL, and an air gap AG. Conductive films BL and SL are separated in the Y direction via the air gap AG.

[0089] As shown in Figures 12 and 13, in the memory cell array 102, adjacent memory cells MT_1 and MT_3 in the Z direction share conductive film BL and conductive film SL, respectively. The channel region CH of memory cell MT_1 and the channel region CH of memory cell MT_3 face each other in the Z direction via the insulating layer IF2. The channel region CH of memory cell MT_1 covers the -X side surfaces of conductive film BL and conductive film SL. The channel region CH of memory cell MT_3 covers the -X side surfaces of conductive film BL and conductive film SL at a Z position -Z side from the channel region CH of memory cell MT_1.

[0090] Adjacent memory cells MT_2 and MT_4 in the Z direction share conductive film BL and conductive film SL, respectively. The channel region CH of memory cell MT_2 and the channel region CH of memory cell MT_4 are separated in the Z direction via the insulating layer IF2. The channel region CH of memory cell MT_2 covers the +X side surfaces of conductive film BL and conductive film SL. The channel region CH of memory cell MT_4 covers the +X side surfaces of conductive film BL and conductive film SL at a Z position -Z side from the channel region CH of memory cell MT_2.

[0091] In this structure, conductive film BL and conductive film SL function as bit lines and source lines, respectively. Conductive film BL and conductive film SL are supplied with a potential corresponding to the operation of memory cell MT.

[0092] In this case, an air gap AG with a dielectric constant lower than that of the insulating film is interposed between the channel regions CH of adjacent memory cells MT_1 and MT_2 in the X direction. Therefore, parasitic coupling capacitance can be suppressed compared to the case where an insulating film is present. This suppresses electric field interference between the channel regions CH of adjacent memory cells MT_1 and MT_2 in the X direction. As a result, the channel regions CH of adjacent memory cells MT_1 and MT_2 can be brought closer to each other while sharing conductive films BL and SL, thus reducing the cell size of each memory cell MT.

[0093] The method for manufacturing the semiconductor memory device 101 differs from the first embodiment in the following respects, as shown in Figure 14. Figures 14(a) to 14(c) are plan views showing the method for manufacturing the semiconductor memory device 101. Figures 14(a) to 14(c) correspond to the XY cross-sections obtained by cutting Figure 7(e) along the DD line, respectively.

[0094] After the steps shown in Figures 7(a) to 8(b) are carried out in the same manner as in the first embodiment, the step shown in Figure 14(a) is performed.

[0095] In the process shown in Figure 14(a), resist patterns with openings for the formation positions of conductive films SL and BL (see Figure 1) are formed on the uppermost insulating layer IF2 of each laminate SSTb. Anisotropic etching, such as RIE (Reactive Ion Etching), is performed using the resist patterns as a mask. This forms holes SH, which penetrate the laminate SSTe in the Z direction and reach the semiconductor film SF on the -Z side, between the center and +Y side of the semiconductor film SF in the XY direction, and holes BH, which penetrate the laminate SSTe in the Z direction and reach the semiconductor film SF on the -Z side, between the center and -Y side of the semiconductor film SF in the XY direction. At this time, holes SH are formed such that portions of the semiconductor film SF remain connected in the Y direction on both sides in the X direction, and are separated in the Y direction from the insulating film IF1 and conductive film BC, respectively. Holes BH are formed such that portions of the semiconductor film SF remain connected in the Y direction on both sides in the X direction, and are separated in the Y direction from the insulating film IF1 and conductive film BC, respectively.

[0096] In the process shown in Figure 14(b), a conductive film SL is embedded in hole SH and a conductive film BL is embedded in hole BH. The conductive film SL can be formed from a material mainly composed of metal, such as tungsten (W). The conductive film BL can be formed from a material mainly composed of metal, such as tungsten (W). This creates a conductive film SL that penetrates the semiconductor film SF and extends in the Z direction to the semiconductor film SF on the -Z side, and a conductive film BL that penetrates the semiconductor film SF and extends in the Z direction to the semiconductor film SF on the -Z side.

[0097] In the process shown in Figure 14(c), a resist pattern with an opening for the formation of an air gap AG (see Figure 1) is formed on the uppermost insulating layer IF2 of each laminate SSTe. Anisotropic etching, such as RIE (Reactive Ion Etching), is performed using the resist pattern as a mask. This forms an air gap AG structure that penetrates the laminate SST100 in the Z direction near the center of the semiconductor film SF in the XY direction and reaches the substrate SB. At this time, the air gap AG is formed by dividing the semiconductor film SF into two in the X direction, forming semiconductor film SF1 and semiconductor film SF2. Furthermore, since the air gap AG does not require insulator filling, its X width can be easily narrowed.

[0098] As described above, in the second embodiment, in the memory cell array 102 of the semiconductor memory device 101, adjacent memory cells MT in the X direction form a back-to-back structure facing each other via an air gap AG, and share conductive films BL and SL, respectively. The air gap AG is positioned between the conductive films BL and SL and extends in the Z direction to reach the substrate SB. As a result, the air gap AG provides electrical isolation, allowing the channel regions CH of adjacent memory cells MT_1 and MT_2 in the X direction to be brought closer together while suppressing electric field interference. Consequently, the cell size of each memory cell MT can be reduced in the semiconductor memory device 101.

[0099] (Third embodiment) Next, a semiconductor memory device 201 according to the third embodiment will be described. The following description will focus on the differences from the first and second embodiments.

[0100] In the first and second embodiments, examples are given of structural improvements between adjacent memory cells in the X direction within a memory cell array, while in the third embodiment, examples are given of structural improvements within a memory cell itself.

[0101] The semiconductor memory device 201 may be configured as shown in Figure 15. Figure 15 is a perspective view showing the configuration of the semiconductor memory device 201.

[0102] The semiconductor memory device 201 has a memory cell array 202 instead of the memory cell array 2 (see Figure 1), and the conductive film BC is omitted.

[0103] The memory cell array 202 has multiple semiconductor films SF1 and multiple semiconductor films SF2 instead of multiple semiconductor films SF (see Figure 1). Semiconductor films SF1 and SF2 are obtained by dividing the semiconductor film SF in the X direction via an insulating film IF201. Conductive films SL and BL are provided by multiple semiconductor films SF1 and multiple semiconductor films SF2, respectively.

[0104] The conductive film SL provided on semiconductor film SF1 and the conductive film SL provided on semiconductor film SF2 are separated in the X direction via the insulating film IF2. The conductive film BL provided on semiconductor film SF1 and the conductive film BL provided on semiconductor film SF2 are separated in the X direction via the insulating film IF2.

[0105] The conductive film SL and conductive film BL provided on the semiconductor film SF1 are separated in the Y direction via the insulating film IF2. The conductive film SL and conductive film BL provided on the semiconductor film SF2 are separated in the Y direction via the insulating film IF2.

[0106] In the semiconductor memory device 201, the portion of the semiconductor film SF1 or semiconductor film SF2 facing the conductive film WL via an insulating film FE functions as a memory cell MT, and a memory cell array 202 is formed in which a plurality of memory cells MT are arranged in three dimensions.

[0107] In the memory cell array 202, each memory cell MT differs from the first and second embodiments in that impurities are doped into the regions on both ends in the Y direction of the channel region CH (see Figure 19). This ensures that the ON-state cell current can be secured in the regions on both ends in the Y direction of the channel region CH, even when the conductive film SL and conductive film BL are brought close together in both semiconductor films SF1 and SF2. As a result, the degradation of the ON / OFF characteristics of the memory cell MT can be suppressed, and the cell size of the memory cell MT can be reduced while ensuring the ON-state cell current.

[0108] As shown in Figure 16, the circuit configuration of the memory cell array 202 is the same as that of the memory cell array 2 (see Figure 3), but with the body contact lines BC_1 to BC_m omitted, and the bit line BL and source line SL divided into two in the X direction. Figure 16 is a three-dimensional diagram showing the circuit configuration of the memory cell array 202.

[0109] Bit line BL_1 is divided into two bit lines BL_1a and BL_1b, which are aligned in the X direction. Source line SL_1 is divided into two source lines SL_1a and SL_1b, which are aligned in the X direction. Bit line BL_2 is divided into two bit lines BL_2a and BL_2b, which are aligned in the X direction. Source line SL_2 is divided into two source lines SL_2a and SL_2b, which are aligned in the X direction. Bit line BL_m is divided into two bit lines BL_ma and BL_mb, which are aligned in the X direction. Source line SL_m is divided into two source lines SL_ma and SL_mb, which are aligned in the X direction.

[0110] As the bit line BL and source line SL are divided into two in the X direction, each drive unit DU is also divided into two in the X direction.

[0111] Drive unit DU_1 is divided into two drive units DU_1a and DU_1b, which are aligned in the X direction. Drive unit DU_2 is divided into two drive units DU_2a and DU_2b, which are aligned in the X direction. Drive unit DU_m is divided into two drive units DU_ma and DU_mb, which are aligned in the X direction.

[0112] The circuit configuration of memory cell array 202 is, in all other respects, basically the same as that of memory cell array 2.

[0113] Each memory cell MT can be configured as shown in Figure 17. Figure 17 is a plan view showing the configuration of the memory cell MT. It is an enlarged XY plan view corresponding to portion F of Figure 15. Figure 17 illustrates the configuration of a memory cell MT including a semiconductor film SF1, but the configuration of a memory cell MT including a semiconductor film SF2 can be obtained by deforming the configuration of the memory cell MT including semiconductor film SF1 symmetrically with respect to the Y axis, and is otherwise the same.

[0114] In the memory cell MT shown in Figure 17, the semiconductor film SF1, which functions as the channel region CH, has regions RG1, RG2, and RG3. Region RG1 is located between the conductive films WL and BL. Region RG2 is located between the conductive films WL and SL. Region RG3 is located between regions RG1 and RG2.

[0115] Regions RG1 and RG2 each contain an impurity of the first conductivity type at a concentration C1. Region RG1 may contain the impurity of the first conductivity type at a concentration C1 throughout its entire region, or it may contain the impurity of the first conductivity type at a concentration C1 only in the -Y side portion. Region RG2 may contain the impurity of the first conductivity type at a concentration C1 throughout its entire region, or it may contain the impurity of the first conductivity type at a concentration C1 only in the +Y side portion. The concentration C1 can be experimentally determined in advance as an impurity concentration that can realize the ON-time cell current required for the memory cell MT, depending on the processing dimensions of the semiconductor film SF1. The concentration C1 is 1.0 × 10⁻⁶ 18 cm -3 The above is also acceptable. If the first conductivity type is N-type, the impurities of the first conductivity type may be N-type impurities such as phosphorus and arsenic.

[0116] Region RG3 contains a second-type impurity at a concentration C2. Region RG3 may contain the second-type impurity at a concentration C2 throughout its entire region, or it may contain the second-type impurity at a concentration C2 only in the +X side portion. Concentration C2 is lower than concentration C1. Concentration C2 can be experimentally determined in advance as an impurity concentration that keeps the leakage between conductive films BL and SL within an acceptable range, depending on the processing dimensions of the semiconductor film SF1. Concentration C2 is 5.0 × 10⁻⁶ 17 cm -3The above 1.0 × 10 18 cm -3 It may be less than [a certain value]. The second conductivity type is the opposite conductivity type of the first conductivity type. If the second conductivity type is P-type, the impurities of the second conductivity type may be P-type impurities such as boron and aluminum.

[0117] The configuration shown in Figure 17 is represented by an equivalent circuit as shown in Figure 18. Figure 18 is a plan view showing the equivalent circuit of the memory cell MT.

[0118] As shown in Figures 17 and 18, when the memory cell MT is ON, the semiconductor film SF1 has a resistance R corresponding to the channel in the -X side portion. CH It functions as follows: the portion corresponding to region RG1 functions as the resistance R1 between the channel and the conductive film BL, and the portion corresponding to region RG2 functions as the resistance R2 between the channel and the conductive film SL.

[0119] Here, regions RG1 and RG2 each contain a first-conductivity impurity at a concentration C1, and since concentration C1 is higher than concentration C2, resistances R1 and R2 can be reduced, and as shown in Figure 19, the cell current Ion when the memory cell MT is ON can be secured. Figure 19 is a plan view showing the electron density distribution when the memory cell MT is ON, and it is shown that the difference in density is small and the electron density is high in the -Y side portion of region RG1 and the +Y side portion of region RG2. In other words, it is shown that the cell current Ion can be secured in the -Y side portion of region RG1 and the +Y side portion of region RG2.

[0120] For example, Figure 20 shows the on / off characteristics of a memory cell MT, with the vertical axis representing the drain current of the memory cell MT and the horizontal axis representing the gate voltage. Figure 20 illustrates the case in which the memory cell MT turns on when the gate voltage changes from a negative value to a positive value. In Figure 20, the third embodiment is shown by a solid line, the case where regions RG1 and RG2 do not contain impurities is shown by a dashed line, and the case where region RG3 does not contain impurities is shown by a dotted line.

[0121] When the regions RG1 and RG2 do not contain impurities, the resistance R1 between the channel and the conductive film BL and the resistance R2 between the channel and the conductive film SL tend to be high resistances. As shown by the dashed line in FIG. 20, the on-cell current Ion3 is relatively small.

[0122] On the other hand, when the regions RG1 and RG2 each contain impurities of the first conductivity type at a concentration C1, and the concentration C1 is higher than the concentration C2, the resistances R1 and R2 can be reduced to low resistances. As shown by the solid line in FIG. 20, a relatively large on-cell current Ion1 can be ensured.

[0123] Also, in a state where the memory cell MT is on, in the semiconductor film SF1, the portion corresponding to the region RG3 functions as the resistance R3 between the conductive film BL and the conductive film SL.

[0124] Here, when the region RG3 contains impurities of the second conductivity type at a concentration C2, and the concentration C2 is lower than the concentration C1, the resistance R3 can be increased to a high resistance. As shown in FIG. 19, the leakage between the conductive film BL and the conductive film SL when the memory cell MT is on can be reduced. In FIG. 19, it is shown that there is a large difference in shading and a low electron density in the portion between the conductive film BL and the conductive film SL. That is, it is shown that the leakage between the conductive film BL and the conductive film SL can be reduced.

[0125] For example, when the region RG3 does not contain impurities, the portion between the conductive film BL and the conductive film SL tends to leak. As shown by the dotted line in FIG. 20, the subthreshold swing value S S2 when the memory cell MT is on is relatively large.

[0126] On the other hand, when the region RG3 contains impurities of the second conductivity type at a concentration C2, and the concentration C2 is lower than the concentration C1, the resistance R3 can be increased to a high resistance, and the leakage between the conductive film BL and the conductive film SL can be suppressed. Therefore, as shown by the solid line in FIG. 20, the subthreshold swing value S S1 when the memory cell MT is on can be suppressed to be relatively small.

[0127] As a result, even when the conductive film SL and conductive film BL are brought close together in the semiconductor film SF1, the degradation of the on / off characteristics of the memory cell MT can be suppressed, and the on current can be secured.

[0128] Next, the method for manufacturing the semiconductor memory device 201 differs from the first embodiment in the following respects, as shown in Figures 21 and 22. Figures 21(a) to 22(c) are plan views showing the method for manufacturing the semiconductor memory device 201. Figures 21(a) to 22(c) correspond to the XY cross-sections obtained by cutting Figure 7(e) along the DD line, respectively.

[0129] In the process shown in Figure 7(a), the semiconductor film SFa can be formed from a material mainly composed of a semiconductor (e.g., silicon) containing a second-type conductivity impurity at a concentration C2. The second-type conductivity impurity may be a P-type impurity such as boron or aluminum. The concentration C2 is 5.0 × 10⁻⁶ 17 cm -3 The above 1.0 × 10 18 cm -3 It may be less than [value]. Otherwise, the process shown in Figure 7(a) is carried out in the same manner as in the first embodiment.

[0130] After the process shown in Figure 7(b) is carried out in the same manner as in the first embodiment, in the process shown in Figure 7(c), a sacrificial film FEc is deposited on the side and bottom surfaces of the groove TR instead of the insulating film FEa. The sacrificial film FEc can be formed from any insulator that can ensure an etching selectivity ratio for both the sacrificial film WLa and the semiconductor film SFa. The sacrificial film FEc may also be formed from a semiconductor oxynitride such as silicon oxynitride.

[0131] A resist pattern with an opening at the formation position of the slit IF3 (see Figure 1) is formed on the uppermost insulating layer IF2 of each laminate SSTb. Anisotropic etching, such as RIE (Reactive Ion Etching), is performed using the resist pattern as a mask. This removes the sacrificial film FEc in the groove TR while leaving the portion embedded in the recess TRa of the sacrificial film FEc.

[0132] An insulating film recess treatment is performed to etch and recede the side surface of the sacrificial film FEc exposed in the groove TR. This insulating film recess treatment forms a recess TRb on the inner surface of the groove TR. The recess TRb is formed so as to be recessed in the direction away from the X-direction center plane CP of the groove TR relative to the inner surface of the groove TR at the Z position of the sacrificial film FEd in the laminate SSTb. For example, the inner surface of the groove TR is wet-etched using an etchant with a high etching selectivity ratio of the sacrificial film FEd to the insulating layer IF2. Alternatively, the inner surface of the groove TR is dry-etched under isotropic etching conditions using a processing gas with a high etching selectivity ratio of the insulating film FEb to the insulating layer IF2. This allows the side surface of the sacrificial film FEd exposed in the groove TR to be etched and receded, forming a recess TRb on the inner surface of the groove TR. The recess width (amount of recess) of the recess TRb relative to the inner surface of the groove TR can be adjusted by the etching time. The width of the recess TRb in the Z direction is approximately equal to the thickness of the semiconductor film SFb.

[0133] In the process shown in Figure 7(d), a sacrificial film WLa is embedded in the groove TR and recess TRb instead of the barrier metal BM2, barrier metal BM1, and conductive film WL. The sacrificial film WLa can be formed from any insulator that can ensure an etching selectivity ratio for both the sacrificial film FEc and the insulating layer IF2. The sacrificial film WLa may also be formed from a semiconductor nitride such as silicon nitride.

[0134] A resist pattern with an opening at the formation position of the slit IF3 (see Figure 1) is formed on the uppermost insulating layer IF2 of each laminate SSTb. Anisotropic etching, such as RIE (Reactive Ion Etching), is performed using the resist pattern as a mask. This removes the sacrificial film WLa in the groove TR while leaving the portion embedded in the recess TRb of the sacrificial film WLa.

[0135] Subsequently, the process shown in Figure 21(a) is carried out.

[0136] In the process shown in Figure 21(a), a resist pattern is formed on the uppermost insulating layer IF2 of each laminate SSTb, with openings at the formation positions of the portions of the insulating film IF201 between semiconductor films SF1 and SF2 (see Figure 15). Anisotropic etching, such as RIE (Reactive Ion Etching), is performed using the resist pattern as a mask. This creates a hole IH between the center and the +Y side edge of the semiconductor film SFa in the XY direction, penetrating the laminate SSTe in the Z direction and reaching the semiconductor film SFa on the -Z side. At this time, the hole IH is formed such that portions of the semiconductor film SFa remain connected in the Y direction on both sides in the X direction.

[0137] In the process shown in Figure 21(b), an insulating film IF201a is embedded in the hole IH. The insulating film IF201a can be formed from an insulator such as silicon oxide. This creates an insulating film IF201a that penetrates the semiconductor film SFa and extends in the Z direction, reaching the semiconductor film SFa on the -Z side.

[0138] In the process shown in Figure 21(c), a resist pattern is formed on the uppermost insulating layer IF2 of each laminate SSTe, with openings at the formation positions of both ends of the insulating film IF201 in the Y direction (see Figure 15). Anisotropic etching, such as RIE (Reactive Ion Etching), is performed using the resist pattern as a mask. This creates a groove TR3 that extends in the X direction at a position that divides the semiconductor film SFa and the sacrificial films FEd on both sides in the X direction, and penetrates the laminate SSTf in the Z direction, reaching the interlayer insulating film 81. At this time, the groove TR3 is formed such that portions of the sacrificial film WLa remain connected in the Y direction on both sides in the X direction. As a result, the semiconductor film SFb is divided into multiple semiconductor films SF1 and SF2 aligned in the X direction with the insulating film IF201a in between, and the sacrificial film FEd is divided into multiple sacrificial films FEe aligned in the Y direction with the groove TR3 in between.

[0139] A resist pattern with openings at the formation positions of regions RG1 and RG2 (see Figure 17), indicated by dotted lines, is formed on the uppermost insulating layer IF2 of each laminate SSTe. Doping with impurities is performed using the resist pattern as a mask by ion implantation or the like. As a result, the regions indicated by dotted lines are doped with a first-type conductivity impurity at a concentration C1. The first-type conductivity impurity may be an N-type impurity such as phosphorus or arsenic. The concentration C1 is 1.0 × 10⁻⁶ 18 cm -3 That's fine too.

[0140] In the process shown in Figure 22(a), isotropic etching, such as wet etching, is performed through groove TR3 to remove the sacrificial film FEd. The insulating film FE is then embedded in the void formed by the removal of the sacrificial film FEd. The insulating film FE can be formed from a material mainly composed of ferroelectrics. The insulating film FE can also be formed from an amorphous material.

[0141] The insulating film FE can be formed from a material primarily composed of hafnium oxide (HfO), for example. The insulating film FEf may further be formed from a material containing at least one element selected from the group including silicon (Si), scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), zirconium (Zr), aluminum (Al), strontium (Sr), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

[0142] The laminate SSTf is heat-treated. As a result, the amorphous insulating film FE crystallizes and becomes polycrystalline. Simultaneously, the crystallinity of the semiconductor films SF1 and SF2 is improved.

[0143] An insulating film IF201 is embedded in the groove TR3. The insulating film IF201 can be formed from an insulator such as silicon oxide.

[0144] Isotropic etching, such as wet etching, is performed through the groove TR to remove the sacrificial film WLa. The conductive film WL is then embedded in the void formed by the removal of the sacrificial film WLa. The conductive film WL can be formed from a material primarily composed of metal, such as tungsten (W).

[0145] In the process shown in Figure 22(b), the slit IF3 is embedded in the groove TR. The slit IF3 can be formed from an insulator such as silicon oxide.

[0146] A resist pattern with openings for the formation positions of conductive films SL and BL (see Figure 15) is formed on the uppermost insulating layer IF2 of each laminate SSTf. Anisotropic etching, such as RIE (Reactive Ion Etching), is performed using the resist pattern as a mask. This creates holes SH at the +X and +Y ends of semiconductor film SF1 or the -X and +Y ends of semiconductor film SF2, penetrating the laminate SSTg in the Z direction and reaching the semiconductor film SF1 or semiconductor film SF2 on the far -Z side, and holes BH at the +X and +Y ends of semiconductor film SF1 or semiconductor film SF2, penetrating the laminate SSTg in the Z direction and reaching the semiconductor film SF1 or semiconductor film SF2 on the far -Z side. At this time, holes SH are formed such that a portion of semiconductor film SF1 or semiconductor film SF2 remains connected in the Y direction on its -X or +X side. Hole BH is formed such that a portion of semiconductor film SF1 or semiconductor film SF2 remains connected in the Y direction on its -X or +X side.

[0147] In the process shown in Figure 22(c), a conductive film SL is embedded in hole SH and a conductive film BL is embedded in hole BH. The conductive film SL can be formed from a material mainly composed of metal, such as tungsten (W). The conductive film BL can be formed from a material mainly composed of metal, such as tungsten (W). This results in the formation of a conductive film SL that extends in the Z direction through semiconductor film SF1 or semiconductor film SF2 and reaches the semiconductor film SF1 or semiconductor film SF2 on the -Z side, and a conductive film BL that extends in the Z direction through semiconductor film SF1 or semiconductor film SF2 and reaches the semiconductor film SF1 or semiconductor film SF2 on the -Z side.

[0148] As described above, in the third embodiment, in each memory cell MT of the memory cell array 202, regions RG1 and RG2 on both ends in the Y direction of the semiconductor film SF1 or SR2 each contain an impurity of the first conductivity type at a concentration C1. This makes it possible to reduce the equivalent resistance of regions RG1 and RG2, and to secure a relatively large on-time cell current Ion1. In addition, in each memory cell MT, region RG3 in the center in the Y direction contains an impurity of the second conductivity type at a concentration C2. The concentration C2 is lower than the concentration C1. Region RG3 is interposed between the conductive film SL and the conductive film BL. This makes it possible to increase the equivalent resistance of region RG3, and to reduce leakage between the conductive film BL and the conductive film SL. As a result, even if the conductive film SL and the conductive film BL are brought close together in the semiconductor film SF1, the degradation of the on / off characteristics of the memory cell MT can be suppressed, and the on-current can be secured. As a result, the cell size of each memory cell MT can be reduced in the semiconductor memory device 201.

[0149] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0150] 1,101,201 Semiconductor memory device, 2,102,202 Memory cell array, BC,BL,SL,WL Conductive film, FE Insulating film, MT Memory cell, SF,SF1,SF2 Semiconductor film.

Claims

1. A first conductive film extending in a first direction, A second conductive film is spaced apart from the first conductive film in a second direction intersecting the first direction and extending in the first direction, A first semiconductor film is disposed between the first conductive film and the second conductive film, and extends in the first direction and the second direction, A first insulating film is disposed between the first conductive film and the first semiconductor film and extends in the first direction, Displaced between the second conductive film and the first semiconductor film, a second insulating film extending in the first direction, A third conductive film extending within the first semiconductor film in a third direction intersecting the first and second directions, A fourth conductive film is spaced apart from the third conductive film in the first direction and extends within the first semiconductor film in the third direction, A fifth conductive film extends within the first semiconductor film in the third direction between the third conductive film and the fourth conductive film, to which a reference potential is applied, Equipped with, A first memory cell is provided at a position where the first semiconductor film faces the first conductive film via the first insulating film. A second memory cell is provided at a position where the first semiconductor film faces the second conductive film via the second insulating film. Semiconductor memory device.

2. The first insulating film and the second insulating film each contain a ferroelectric material. The semiconductor memory device according to claim 1.

3. Further equipped with a circuit board, The fifth conductive film extends in the third direction and reaches the substrate. The third conductive film and the fourth conductive film do not reach the substrate, respectively. The semiconductor memory device according to claim 1.

4. The fifth conductive film is subjected to a first fixed potential when data is written to at least one of the first memory cell and the second memory cell, and a second fixed potential when data is read from at least one of the first memory cell and the second memory cell. The semiconductor memory device according to claim 1.

5. A first conductive film extending in a first direction, A second conductive film is spaced apart from the first conductive film in a second direction intersecting the first direction and extending in the first direction, A first semiconductor film is disposed between the first conductive film and the second conductive film and extends in the first direction, A second semiconductor film is disposed between the first semiconductor film and the second conductive film and extends in the first direction, A first insulating film is disposed between the first conductive film and the first semiconductor film and extends in the first direction, Displaced between the second conductive film and the second semiconductor film, a second insulating film extending in the first direction, A third conductive film extends between the first semiconductor film and the second semiconductor film in a third direction intersecting the first and second directions, and is connected to the first semiconductor film and the second semiconductor film, respectively. A fourth conductive film is spaced apart from the third conductive film in the first direction via an air gap, extends between the first semiconductor film and the second semiconductor film in the third direction, and is connected to the first semiconductor film and the second semiconductor film, respectively. Equipped with, A first memory cell is provided at a position where the first semiconductor film faces the first conductive film via the first insulating film. A second memory cell is provided at a position where the second semiconductor film faces the second conductive film via the second insulating film. Semiconductor memory device.

6. The first insulating film and the second insulating film each contain a ferroelectric material. The semiconductor memory device according to claim 5.

7. The difference between the crystal orientation of the first semiconductor film and the crystal orientation of the second semiconductor film is 5 degrees or less. The semiconductor memory device according to claim 5.

8. The width of the air gap in the second direction is smaller than the width of the third conductive film in the second direction and smaller than the width of the fourth conductive film in the second direction. The semiconductor memory device according to claim 5.

9. A first conductive film extending in a first direction, A first semiconductor film extending in the first direction and in a second direction intersecting the first direction, A first insulating film is disposed between the first conductive film and the first semiconductor film and extends in the first direction, A third conductive film extending in a third direction intersecting the first and second directions and connected to the first semiconductor film, A fourth conductive film is spaced apart from the third conductive film in the first direction, extends in the third direction, and is connected to the first semiconductor film, Equipped with, A first memory cell is provided at a position where the first semiconductor film faces the first conductive film via the first insulating film. The first semiconductor film is A first region disposed between the first conductive film and the third conductive film, A second region disposed between the first conductive film and the fourth conductive film, A third region is located between the first region and the second region, Includes, The first region and the second region each contain impurities of the first conductivity type. Semiconductor memory device.

10. The third region contains impurities of the second conductivity type. The semiconductor memory device according to claim 9.

11. The first region and the second region each contain the first conductivity type of impurity at a concentration of a first concentration or higher. The third region contains the second conductivity type of impurity at a concentration less than the first concentration. The semiconductor memory device according to claim 10.

12. The third region contains the second conductivity type impurity at a concentration equal to or greater than the second concentration and less than the first concentration. The semiconductor memory device according to claim 11.

13. The first insulating film includes a ferroelectric material. The semiconductor memory device according to claim 9.

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