Semiconductor memory device and method for manufacturing a semiconductor memory device

Abstract

To improve the operating characteristics of memory cells. [Solution] The semiconductor memory device of the embodiment comprises a laminate in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one layer at a time, and a pillar extending within the laminate in the stacking direction of the laminate, wherein the pillar has a first semiconductor layer extending within the laminate in the stacking direction, and a second semiconductor layer extending within the laminate in the stacking direction and containing more crystal grain boundaries than the first semiconductor layer, and contains an additive having a peak concentration at the interface between the first semiconductor layer and the second semiconductor layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device and a method of manufacturing the semiconductor memory device.

Background Art

[0002] In a three-dimensional non-volatile memory, a plurality of memory cells each having a channel layer on a side surface of a pillar extending in a height direction are arranged along the height direction of the pillar. In the three-dimensional non-volatile memory, improvement in operation characteristics of the memory cells is desired.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to provide a semiconductor memory device and a method of manufacturing the semiconductor memory device that can improve operation characteristics of memory cells.

Means for Solving the Problems

[0005] The semiconductor memory device of the embodiment comprises a laminate in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one layer at a time, and a pillar extending within the laminate in the stacking direction of the laminate, wherein the pillar has a first semiconductor layer extending within the laminate in the stacking direction, and a second semiconductor layer extending within the laminate in the stacking direction and containing more crystal grain boundaries than the first semiconductor layer, and contains an additive having a peak concentration at the interface between the first semiconductor layer and the second semiconductor layer. [Brief explanation of the drawing]

[0006] [Figure 1] A diagram showing a schematic configuration example of a semiconductor memory device according to an embodiment. [Figure 2] A cross-sectional view showing an example of the configuration of a semiconductor memory device according to the embodiment. [Figure 3] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 4] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 5] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 6] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 7] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 8] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 9] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 10] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 11] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 12] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 13] Partial enlarged cross-sectional view of a pillar included in a semiconductor memory device according to a modified example of an embodiment. [Figure 14] Diagram illustrating a part of the procedure of a method of manufacturing a semiconductor memory device according to a modified example of an embodiment. [Embodiments of the Invention]

[0007] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited by the following embodiments. Also, the constituent elements in the following embodiments include those that can be easily assumed by those skilled in the art or those that are substantially the same.

[0008] [Embodiment] Hereinafter, embodiments will be described in detail with reference to the drawings.

[0009] [Configuration Example of Semiconductor Memory Device] FIG. 1 is a diagram showing a schematic configuration example of a semiconductor memory device 1 according to an embodiment. More specifically, FIG. 1(a) is a cross-sectional view of the semiconductor memory device 1 along the X direction, and FIG. 1(b) is a schematic plan view showing the layout of the semiconductor memory device 1.

[0010] However, in FIG. 1(a), hatching is omitted for ease of viewing the drawing. Also, in FIG. 1(a), components that do not necessarily exist in the same cross-section are shown, and some upper-layer wirings and the like are omitted.

[0011] Also, in this specification, both the X direction and the Y direction are directions along the plane of the word line WL, and the X direction and the Y direction are orthogonal to each other. Also, the electrical extraction direction of the word line WL may be referred to as the first direction, and this first direction is a direction along the X direction. Also, the direction intersecting the first direction may be referred to as the second direction, and this second direction is a direction along the Y direction. However, since the semiconductor memory device 1 may include manufacturing errors, the first direction and the second direction are not necessarily orthogonal.

[0012] As shown in FIG. 1(a), the semiconductor memory device 1 includes a semiconductor substrate SB provided with an electrode film EL, a source line SL, one or more select gate lines SGS, a plurality of word lines WL, one or more select gate lines SGD, and a peripheral circuit CBA in this order from the lower side of the paper surface.

[0013] On the electrode film EL, a source line SL is disposed via an insulating layer 60. A plurality of plugs PG are disposed in the insulating layer 60, and electrical conduction is maintained between the source line SL and the electrode film EL via the plugs PG. Although not shown, electrode pads for supplying power and signals to the semiconductor memory device 1 from the outside are provided in the same layer as the electrode film EL. On the source line SL, a select gate line SGS, a plurality of word lines WL, and a select gate line SGD are laminated in this order.

[0014] As shown in FIGS. 1(a) and 1(b), a memory region MR is disposed at the central portion in the X direction of the plurality of word lines WL and the like, and staircase regions SR are disposed at both ends in the X direction of the plurality of word lines WL and the like, respectively. These memory regions MR and staircase regions SR are divided into a plurality of regions by a plurality of plate-like contacts LI extending in the direction along the X direction through the plurality of word lines WL and the like.

[0015] Note that a region including the memory region MR and the staircase region SR is called a block region BLK and is disposed between plate-like contacts LI adjacent to each other in the Y direction. As will be described later, a plurality of memory cells that hold data non-volatilely are included in the memory region MR, and the above-described block region BLK is an erasure unit for these data.

[0016] Also, a plurality of separation layers SHE extending in the direction along the X direction through the select gate line SGD are disposed between plate-like contacts LI adjacent to each other in the Y direction. The plurality of separation layers SHE extend in the direction along the X direction over the entire memory region MR and reach a part of the staircase regions SR at both ends in the X direction.

[0017] In the memory region MR, multiple pillars PL are arranged that penetrate the word line WL and the selection gate lines SGD and SGS in the stacking direction. The lower end of the pillar PL reaches the source line SL. Multiple memory cells are formed at the intersections of the pillar PL and the word line WL. Thus, the semiconductor memory device 1 is configured as a three-dimensional non-volatile memory, for example, in which memory cells are arranged three-dimensionally in the memory region MR.

[0018] In the stepped region SR, multiple word lines WL and selection gate lines SGD and SGS are processed and terminated in a stepped manner. As we move away from the memory region MR in the X direction, the multiple word lines WL and selection gate lines SGD and SGS that make up the terrace section move from the upper layer to the lower layer, causing the height of the terrace section to decrease towards the source line SL.

[0019] In this specification, the direction in which the terrace surfaces of multiple word lines WL and selected gate lines SGD and SGS face is defined as the upper side of the semiconductor memory device 1.

[0020] The aforementioned isolation layer SHE extends from the memory region MR to the stepped portion of the step region SR where the selected gate line SGD is processed in a step-like manner. As a result, within a single block region BLK, the selected gate line SGD is separated into multiple regions. In other words, the isolation layer SHE penetrates the portion above multiple word lines WL, thereby dividing these upper portions into multiple patterns of selected gate line SGD.

[0021] Each terrace section of a layer, composed of multiple word lines WL and selection gate lines SGD and SGS, has contact CCs connected to the word lines WL and selection gate lines SGD and SGS of each layer. One contact CC is connected to each layer of the word lines WL and selection gate lines SGS. For the selection gate lines SGD, one contact CC is connected to each section separated by the isolation layer SHE per layer.

[0022] Here, within a single block region BLK, multiple contacts CC are positioned on one side of the staircase region SR on both sides in the X direction. Also, looking at one side in the X direction, for example, multiple contacts CC are positioned every two block regions BLK.

[0023] In other words, in the example shown in Figure 1(b), in the block region BLK at the very top of the page, multiple contact CCs are located in the stair region SR on the left side of the page, among the stair regions SR at both ends in the X direction. Furthermore, in the block region BLK one level below and two levels below the above block region BLK, multiple contact CCs are located in the stair region SR on the right side of the page, among the stair regions SR at both ends in the X direction. Moreover, in the block region BLK at the very bottom of the page, multiple contact CCs are again located in the stair region SR on the left side of the page.

[0024] Therefore, as shown in Figure 1(a), the respective contact CCs of the stair region SR at both ends in the X direction belong to different block regions BLK and are not actually located in the same cross-section.

[0025] These contact CCs allow individual stacked word lines WLs to be drawn out. More specifically, these contact CCs apply write voltages and read voltages to memory cells included in the memory region MR at the center of multiple word lines WLs, via word lines WLs located at the same height as the memory cells.

[0026] Multiple word lines WL, selection gate lines SGD, SGS, pillar PL, and contact CC are covered by an insulating layer 50. The insulating layer 50 also extends around these components, including the multiple word lines WL, etc.

[0027] The semiconductor substrate SB above the insulating layer 50 covering the above configuration is, for example, a silicon substrate. Peripheral circuits CBA, including transistors TR and wiring, are arranged on the surface of the semiconductor substrate SB. Various voltages applied to the memory cell from the contacts CC are controlled by the peripheral circuits CBA that are electrically connected to these contacts CC. In this way, the peripheral circuits CBA control the electrical operation of the memory cell.

[0028] The peripheral circuit CBA is covered with an insulating layer 40, and by joining this insulating layer 40 with an insulating layer 50 that covers multiple word lines WL, etc., a semiconductor memory device 1 is formed that includes multiple word lines WL, selection gate lines SGD, SGS, pillar PL, contact CC, etc., and the peripheral circuit CBA.

[0029] Next, a detailed example of the configuration of the semiconductor memory device 1 will be described using Figure 2. Figure 2 is a cross-sectional view showing an example of the configuration of the semiconductor memory device 1 according to the embodiment.

[0030] More specifically, Figure 2(a) is a cross-sectional view along the Y direction in the memory region MR of the semiconductor memory device 1. In Figure 2(a), the structure below the insulating layer 60 and above the insulating layer 53, which will be described later, is omitted.

[0031] Figure 2(b) is an enlarged cross-sectional view of pillar PL at the height of the selected gate lines SGD and SGS. Figure 2(c) is an enlarged cross-sectional view of pillar PL at the height of the word line WL.

[0032] As shown in Figure 2(a), the source wire SL has a multilayer structure in which, for example, a lower source wire DSLa, an intermediate source wire BSL, and an upper source wire DSLb are stacked in this order on an insulating layer 60. The lower source wire DSLa, the intermediate source wire BSL, and the upper source wire DSLb are, for example, polysilicon layers. Of these, at least the intermediate source wire BSL may be a conductive polysilicon layer in which impurities have been diffused.

[0033] The source wire SL is connected to the peripheral circuit CBA via the electrode film EL through a through-contact (not shown) that extends from the electrode film EL to the peripheral circuit CBA, within the aforementioned insulating layer 50 on the outside of the laminate LM.

[0034] A laminate LM is placed on the source line SL. The laminate LM comprises laminates LMa and LMb, in which multiple word lines WL and multiple insulating layers OL are alternately stacked one layer at a time.

[0035] The LMa laminate is positioned above the source line SL. Below the bottommost word line WL of the LMa laminate, multiple selectable gate lines SGS0 and SGS1 are arranged in this order from the top of the LMa laminate, via an insulating layer OL. The LMb laminate is positioned on top of the LMa laminate. Above the topmost word line WL of the LMB laminate, multiple selectable gate lines SGD0 and SGD1 are arranged in this order from the top of the LMB laminate, via an insulating layer OL.

[0036] However, the number of layers of these word lines WL and selective gate lines SGD,SGS in the laminate LM is arbitrary. The word lines WL and selective gate lines SGD,SGS are, for example, tungsten layers or molybdenum layers. The insulating layer OL is, for example, a silicon oxide layer.

[0037] The upper surface of the laminate LM is covered in this order by insulating layers 52 and 53. Insulating layers 52 and 53 each constitute a part of the insulating layer 50 in Figure 1.

[0038] As described above, the laminate LM is divided in the Y direction by multiple plate-like contacts LI. That is, each plate-like contact LI is aligned with the others in the Y direction and extends in a direction along the stacking direction and the X direction of the laminate LM.

[0039] Thus, the plate-shaped contact LI extends continuously within the laminate LM from one end in the X direction to the other end. Furthermore, the plate-shaped contact LI penetrates the laminate LM and the upper source line DSLb, and reaches the intermediate source line BSL in the memory region MR.

[0040] Furthermore, the plate-shaped contact LI may have a tapered shape in which its width in the Y direction decreases from the upper end to the lower end, for example. Alternatively, the plate-shaped contact LI may have a bowing shape in which its width in the Y direction is maximum at a predetermined position between the upper end and the lower end.

[0041] Each plate-shaped contact LI includes an insulating layer 54 and a conductive layer 24. The insulating layer 54 is, for example, a silicon oxide layer. The conductive layer 24 is, for example, a tungsten layer or a conductive polysilicon layer.

[0042] The insulating layer 54 covers the side walls of the plate-shaped contact LI that face each other in the Y direction. The conductive layer 24 is filled further inside the insulating layer 54 that covers the side walls of the plate-shaped contact LI and is electrically connected to the source wire SL, including the intermediate source wire BSL.

[0043] However, instead of the plate-shaped contact LI, a plate-shaped member filled with an insulating layer may penetrate the laminate LM and extend in a direction along the X direction, thereby dividing the laminate LM in the Y direction.

[0044] Between adjacent plate-shaped contacts LI in the Y direction, multiple isolation layers SHE are arranged, extending in the direction along the X direction and penetrating the upper portion of the laminate LMb. These isolation layers SHE are insulating layers 56 such as silicon oxide layers that penetrate the selection gate lines SGD0 and SGD1 and reach the insulating layer OL directly below the selection gate line SGD1.

[0045] In other words, these separation layers SHE, which penetrate the upper portion of the laminated LMb, extend in the X direction between the plate-shaped contacts LI, dividing the upper portion of the laminated LMb into the aforementioned selected gate lines SGD0 and SGD1.

[0046] In the memory region MR, multiple pillars PL are distributed and arranged, penetrating the stacked structure LM, the upper source line DSLb, and the intermediate source line BSL, and reaching the lower source line DSLa.

[0047] Multiple pillars PL are arranged, for example, in a staggered pattern when viewed from the stacking direction of the laminate LM. Each pillar PL has a cross-sectional shape in the direction along the layering direction of the laminate LM, i.e., along the XY plane, such as a circular, elliptical, or oval shape.

[0048] Furthermore, the pillar PL has a tapered shape in the portion that penetrates the laminate LMa and the portion that penetrates the laminate LMb, where the diameter and cross-sectional area decrease from the upper layer side to the lower layer side. Alternatively, the pillar PL has a bowing shape in the portion that penetrates the laminate LMa and the portion that penetrates the laminate LMb, where the diameter and cross-sectional area are maximized at a predetermined position between the upper and lower layers, for example.

[0049] Each of the multiple pillar PLs has a memory layer ME extending in the stacking direction within the laminate LM, a channel layer CN extending in the stacking direction within the laminate LM inside the memory layer ME, a cap layer CP covering the upper surface of the channel layer CN, and a core layer CR which serves as the core material of the pillar PL.

[0050] The channel layer CN is in direct contact with the intermediate source line BSL at the depth of the intermediate source line BSL. That is, the memory layer ME is located on the side of the pillar PL, excluding the depth of the intermediate source line BSL. The memory layer ME is also located on the bottom surface of the pillar PL, which reaches the depth of the lower source line DSLa.

[0051] As a result, the channel layer CN is in contact with the intermediate source line BSL on its side, and further, is electrically connected to the entire source line SL via the intermediate source line BSL.

[0052] The cap layer CP is positioned at the upper end of the pillar PL so as to cover at least the upper end of the channel layer CN and is connected to the channel layer CN. Furthermore, the cap layer CP is connected to the bit wire BL located in the insulating layer 53 via a plug CH located in the uppermost insulating layer OL, 52 of the laminate LM. The bit wire BL extends above the laminate LM in a direction along the Y direction so as to intersect with the drawing direction of the word wire WL.

[0053] As shown in Figures 2(b) and 2(c), the memory layer ME has a laminated structure including a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN, in that order from the outer periphery of the pillar PL. The block insulating layer BK and tunnel insulating layer TN of the memory layer ME, as well as the core layer CR, are, for example, silicon oxide layers. The charge storage layer CT is, for example, a silicon nitride layer.

[0054] The channel layer CN is composed of semiconductor layers CN1, CN2, and CN3, in order from the memory layer ME side.

[0055] The semiconductor layer CN1 is a highly crystalline semiconductor layer, such as a single-crystal silicon layer. The semiconductor layer CN3 has more grain boundaries than semiconductor layer CN1, such as a polycrystalline silicon layer, i.e., a polysilicon layer. However, semiconductor layer CN3 may also contain a portion of an amorphous semiconductor layer, i.e., an amorphous silicon layer.

[0056] The semiconductor layer CN2 is a semiconductor layer such as a silicon layer containing at least one of the following additives: carbon, nitrogen, oxygen, or fluorine. The concentration of the additive in the semiconductor layer CN2 is, for example, 2 × 10⁻⁶. 21 atoms / cm 3 A larger value is preferable. Furthermore, the additive in semiconductor layer CN2 may partially diffuse into at least one of semiconductor layers CN1 and CN3, so that at least one of semiconductor layers CN1 and CN3 may contain a lower concentration of the additive than semiconductor layer CN2.

[0057] With this configuration, the channel layer CN as a whole contains an additive that has a peak concentration at the interface between semiconductor layer CN1 and semiconductor layer CN3.

[0058] The cap layer CP, like the semiconductor layer CN3, is a semiconductor layer such as polysilicon or a mixture of amorphous silicon. Furthermore, the cap layer CP may contain N-type impurities such as arsenic or phosphorus. Since the cap layer CP is, for example, a polycrystalline layer, it allows impurities to diffuse more easily than a single-crystal layer. The diffusion of N-type impurities in the cap layer CP reduces the contact resistance between the cap layer CP and the plug CH.

[0059] As shown in Figure 2(c), with the above configuration, memory cells MC are formed in the portions of the pillar PL side surface that face each word line WL. Data is written to and read from the memory cells MC by applying a predetermined voltage from the word line WL.

[0060] As shown in Figure 2(b), selection gate STD is formed on the side of pillar PL where it faces selection gate lines SGD0 and SGD1. Additionally, selection gate STS is formed on the side of pillar PL where it faces selection gate lines SGS0 and SGS1, which are lower than the word line WL.

[0061] By applying predetermined voltages to the selection gate lines SGD and SGS, respectively, the selection gates STD and STS can be turned on or off, thereby selecting or deselecting the memory cell MC of the pillar PL to which the selection gates STD and STS belong.

[0062] (Method of manufacturing semiconductor memory devices) Next, the manufacturing method of the semiconductor memory device 1 according to the embodiment will be described using Figures 3 to 12. Figures 3 to 12 are diagrams illustrating, in order, some of the steps of the manufacturing method of the semiconductor memory device 1 according to the embodiment. Note that Figures 3 to 12, except for Figure 7, show cross-sections along the Y direction of the region that will later become the memory area MR. Figure 7 is a partially enlarged cross-sectional view of the pillar PL during manufacturing.

[0063] As shown in Figure 3(a), the lower source line DSLa, the intermediate sacrificial layer SCN, and the upper source line DSLb are formed on the support substrate SS in this order.

[0064] As the support substrate SS, a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, or a conductive substrate can be used. The insulating layer 60 described above (see Figure 2(a), etc.) may be formed on the upper surface of the support substrate SS. The intermediate sacrificial layer SCN is, for example, a silicon nitride layer, which is later replaced with a polysilicon layer or the like to become the intermediate source line BSL.

[0065] On the upper source line DSLb, a laminate LMsa is formed by alternately stacking multiple insulating layers NL and multiple insulating layers OL, one layer at a time. The insulating layer NL is, for example, a silicon nitride layer and functions as a sacrificial layer that will later be replaced by a conductive material to become the word line WL or the selected gate line SGS.

[0066] Although not shown in the diagram, in a portion of the laminated LMsa, the insulating layer NL and insulating layer OL are processed in a stepped manner. This processing can be achieved by repeatedly slimming the mask pattern of the photoresist layer, etc., and etching the insulating layer NL and insulating layer OL of the laminated LMsa.

[0067] Specifically, a mask pattern is formed on the upper surface of the laminated LMsa, and the insulating layer NL and insulating layer OL in the exposed areas are etched away one layer at a time. Then, the edges of the mask pattern are receded by treatment with oxygen plasma or the like, exposing the upper surface of the laminated LMsa, and the insulating layer NL and insulating layer OL are etched away one layer at a time again. By repeating this process multiple times, a laminated LMsa with a stepped shape at both ends in the X direction is formed.

[0068] Subsequently, the stepped shape at both ends in the X direction is covered with a portion of the insulating layer 50 (see Figure 1(a)) described above.

[0069] As shown in Figure 3(b), the laminate LMsa forms multiple memory holes MHa extending in the stacking direction. These multiple memory holes MHa penetrate the laminate LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa. These memory holes MHa later become the substructure of the pillar PL.

[0070] As shown in Figure 3(c), these memory holes MHa are filled with a sacrificial layer 26, such as an amorphous silicon layer or a CVD-carbon layer. This forms a pillar PLc in which multiple memory holes MHa are filled with the sacrificial layer 26.

[0071] As shown in Figure 4(a), the laminate LMsa is covered, and a laminate LMsb is formed by alternately stacking multiple insulating layers NL and multiple insulating layers OL one layer at a time. The insulating layers NL of the laminate LMsb function as sacrificial layers that are later replaced by conductive layers to become word lines WL or selected gate lines SGD.

[0072] Although not shown in the diagram, a portion of the laminate LMsb is processed in a stepwise manner, altering the insulating layer NL and insulating layer OL. This processing can be achieved by repeatedly performing the same steps as the processing for the laminate LMsa described above: slimming the mask pattern of the photoresist layer, etc., and etching the insulating layer NL and insulating layer OL of the laminate LMsb.

[0073] At this time, the uppermost step of the stair section formed on the laminated LMsa and the lowermost step of the stair section formed on the laminated LMsb are brought into close proximity to form a stair shape that extends continuously from the lower layer of the laminated LMsa to the upper layer of the laminated LMsb. As a result, the laminated LMsa and LMsb are formed with a stair region SR having a stair shape extending from the laminated LMsa to the laminated LMsb, with the stair region SR formed at both ends in the X direction.

[0074] Subsequently, the stepped shape at both ends in the X direction is further covered with a portion of the insulating layer 50 (see Figure 1(a)) described above.

[0075] As shown in Figure 4(b), multiple memory holes MHb are formed that penetrate the laminate LMsb and connect to multiple pillars PLc that have already been formed within the laminate LMsa. The memory holes MHb are the parts that will later become the upper structure of the pillars PL.

[0076] As shown in Figure 5(a), the sacrificial layer 26 is removed from the pillar PLc at the bottom of the memory hole MHb. As a result, multiple memory holes MHa open at the bottom of multiple memory holes MHb, and multiple memory holes MH are formed that penetrate the laminate LMsb, LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa.

[0077] Furthermore, if the sacrificial layer 26 filled inside the pillar PLc is a CVD-carbon layer or the like, the sacrificial layer 26 can be removed from these pillar PLc all at once when the mask pattern used to form the memory holes MHb in Figure 4(b) above is removed by ashing using oxygen plasma or the like.

[0078] As shown in Figure 5(b), a memory layer ME is formed on the side wall of the memory hole MH and on the bottom surface where the lower source line DSLa is exposed, in the order of block insulating layer BK, charge storage layer CT, and tunnel insulating layer TN (see Figures 2(b) and 2(c)), starting from the side wall side of the memory hole MH. The memory layer ME is also formed on the top surface of the laminate LMsb.

[0079] As shown in Figure 6(a), a metal layer MS is formed on the memory layer ME that covers the bottom surface of the memory hole MH. The metal layer MS is a layer containing, for example, at least one of nickel, palladium, or aluminum.

[0080] As shown in Figure 6(b), the channel layer CNb and the core layer CR are formed in this order within the memory hole MH. This results in the formation of the channel layer CNb on the memory layer ME covering the sides and bottom of the memory hole MH, and on the metal layer MS, while the core layer CR fills the center of the memory hole MH. The channel layer CNb and the core layer CR are also formed in this order on the upper surface of the laminate LMsb via the memory layer ME.

[0081] Note that the channel layer CNb is a semiconductor layer that will later become the channel layer CN. At this point, the entire channel layer CNb is an amorphous semiconductor layer, such as an amorphous silicon layer.

[0082] In the above process, the channel layer CNb is formed by adding at least one of carbon, nitrogen, oxygen, or fluorine along the way, so that it has a peak concentration at a predetermined position within the channel layer CNb.

[0083] As shown in Figure 7(a), the channel layer CNb has a structure in which semiconductor layer CN2 is interposed within semiconductor layer CN4, which later becomes semiconductor layers CN1 and CN3, respectively, through the addition of carbon, nitrogen, oxygen, fluorine, etc. Furthermore, the formation of the channel layer CNb covering the metal layer MS on the memory layer MEb causes the metal layer MS to be silicided.

[0084] As shown in Figure 7(b), the core layer CR formed on the upper surface of the laminate LMsb is etched back and removed, and the core layer CR inside the memory hole MH is receded to form a recess DN at the upper end of the memory hole MH.

[0085] As shown in Figure 7(c), a cap layer CPa is formed in the recess DN at the upper end of the memory hole MH. The cap layer CPa is an amorphous semiconductor layer, such as an amorphous silicon layer, which later becomes the cap layer CP. The cap layer CPa is also formed on the upper surface of the laminate LMsb via the memory layer ME and the semiconductor layers CN4, CN2, and CN4.

[0086] Furthermore, when forming the cap layer CPa, as described above, N-type impurities such as arsenic or phosphorus may be added to the cap layer CPa.

[0087] As shown in Figure 7(d), the entire support substrate SS is annealed at a low temperature. Low-temperature annealing is a heat treatment at a temperature at which crystallization of the semiconductor layer CN4 does not occur. However, the metal-containing layer NS, which is provided at the lower end of the memory hole MH and in which the metal layer MS has been silicided, promotes the crystallization of the semiconductor layer CN4. In other words, the metal-containing layer NS functions as a catalyst for the crystallization of the semiconductor layer CN4.

[0088] Therefore, the above annealing process initiates crystallization of the semiconductor layer CN4, which is located closer to the memory layer ME than the semiconductor layer CN2 and is in direct contact with the metal-containing layer NS. This process of crystallizing the semiconductor layer CN4 using an annealing process with a metal-containing layer NS, etc., is also called metal-assisted annealing.

[0089] Some of the metal-containing layer NS, which acted as a catalyst for the crystallization of semiconductor layer CN4, are broken down into fine metal fragments NSf, which then diffuse into semiconductor layer CN4. The portion of semiconductor layer CN4 into which the metal fragments NSf have entered transforms into the aforementioned semiconductor layer CN1, which is, for example, a single-crystal silicon layer.

[0090] On the other hand, semiconductor layer CN2 containing high concentrations of at least one of the additives, such as carbon, nitrogen, oxygen, or fluorine, inhibits the crystallization of semiconductor layer CN4 during metal-assisted annealing. Therefore, crystallization that begins in semiconductor layer CN4 near the memory layer ME at the lower end of memory hole MH does not proceed in semiconductor layer CN4 near the core layer CR on the inside of semiconductor layer CN4.

[0091] As shown in Figure 7(e), crystallization that begins in the semiconductor layer CN4 at the lower end of the memory hole MH continues to progress upward within the semiconductor layer CN4 outside of semiconductor layer CN2. Furthermore, the metal-containing layer NS formed at the bottom surface of the memory hole MH diffuses into the semiconductor layer CN4 as metal fragments NSf, as described above, and disappears at a predetermined stage of the metal-assisted annealing process.

[0092] As shown in Figure 7(f), when crystallization progresses to the upper end of the memory hole MH, the entire semiconductor layer CN4 outside of semiconductor layer CN2 becomes semiconductor layer CN1, such as a single-crystal silicon layer. The metal fragment NSf that has penetrated to the upper end of semiconductor layer CN4 segregates at the upper end of the crystallized semiconductor layer CN1.

[0093] On the other hand, semiconductor layer CN4 inside semiconductor layer CN2 is blocked by semiconductor layer CN2 and does not undergo crystallization by metal assistance. However, due to annealing at low temperatures, the entire layer transforms into semiconductor layer CN3, such as a polysilicon layer, at the end of the annealing process. However, as mentioned above, amorphous silicon layers may be mixed in a portion of semiconductor layer CN3.

[0094] Furthermore, in the manufacturing process of the semiconductor memory device 1 of this embodiment, annealing treatments targeting various layers formed thereafter may be repeatedly performed. Therefore, in the semiconductor layer CN3, polycrystallization may gradually progress not only through the annealing treatment performed during the formation of the semiconductor layer CN1 by metal assistance, but also through subsequent annealing treatments.

[0095] Similarly, the cap layer CPa at the upper end of the memory hole MH is also transformed by the annealing treatment into a polysilicon layer, or a polysilicon layer with a partially amorphous silicon layer. Furthermore, if the cap layer CPa contains N-type impurities, the annealing treatment causes the N-type impurities to diffuse more uniformly into the polycrystalline cap layer CP, and also activates the N-type impurities.

[0096] Furthermore, the additives in semiconductor layer CN2 may partially diffuse into semiconductor layers CN1, CN3, etc., through the annealing process described above.

[0097] As a result, a channel layer CN having semiconductor layers CN1, CN2, and CN3 is formed. Furthermore, a cap layer CP is formed at the upper end of the channel layer CN.

[0098] As shown in Figure 7(g), a gettering layer GT, such as an amorphous silicon layer, is formed on the upper surface of the channel layer CN.

[0099] As shown in Figure 7(h), annealing causes the metal fragment NSf that was segregated at the upper end of the channel layer CN to move into the gettering layer GT. This makes it possible to remove most of the metal fragment NSf in the channel layer CN.

[0100] As shown in Figure 7(i), the gettering layer GT is then removed.

[0101] As a result, a channel layer CN is formed in which a semiconductor layer CN1 with few grain boundaries and a semiconductor layer CN3 with many grain boundaries are interposed by a semiconductor layer CN2 to which an additive is added.

[0102] Furthermore, in annealing using metal assistance, crystallization is more easily promoted when the layer to be crystallized is thicker. Therefore, the channel layer CNb described above may be formed thicker than the channel layer CN that will ultimately be present in the pillar PL, and crystallization may be carried out.

[0103] If the channel layer CNb is formed thickly, a portion of the channel layer CNb can be crystallized, the core layer CR can be temporarily removed, and the channel layer CN exposed in the memory hole MH can be slimmed down to the desired thickness. After that, the core layer CR can be formed again in the memory hole MH.

[0104] As shown in Figure 8(a), the cap layer CP, channel layer CN, and memory layer ME on the upper surface of the laminated LMsb are removed by CMP or the like, along with a portion of the insulating layer OL on the top layer of the laminated LMsb.

[0105] As shown in Figure 8(b), the insulating layer OL on the top layer of the laminated LMsb, which has been thinned by CMP or the like, is stacked again. This forms a pillar PL in which the cap layer CP is embedded in the insulating layer OL on the top layer. However, at this point, the memory layer ME covers the entire side wall of the pillar PL, and no part of the side of the channel layer CN is exposed from the memory layer ME.

[0106] As shown in Figure 9(a), a slit ST is formed that penetrates the laminates LMsb, LMsa and the upper source wire DSLb, reaching the intermediate sacrificial layer SCN. An insulating layer 54s is also formed on the side walls of the slit ST facing in the Y direction. The slit ST also extends along the X direction within the laminates LMsa and LMsb.

[0107] As shown in Figure 9(b), a removal solution for the intermediate sacrificial layer SCN, such as thermal phosphoric acid, is introduced through the slit ST, whose sidewalls are protected by the insulating layer 54s, to remove the intermediate sacrificial layer SCN sandwiched between the lower source wire DSLa and the upper source wire DSLb.

[0108] As a result, a gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb. In addition, a portion of the memory layer ME on the outer periphery of the pillar PL is exposed within the gap layer GPs. At this time, since the sidewall of the slit ST is protected by the insulating layer 54s, the removal of the insulating layer NL within the laminates LMsa and LMsb is suppressed.

[0109] As shown in Figure 10(a), chemical solutions are introduced into the gap layer GPs through the slit ST as needed, sequentially removing the block insulating layer BK, charge storage layer CT, and tunnel insulating layer TN (see Figures 2(b) and 2(c)) of the memory layer ME exposed within the gap layer GPs. As a result, the memory layer ME is removed from a portion of the side wall of the pillar PL, and a portion of the inner channel layer CN is exposed within the gap layer GPs.

[0110] As shown in Figure 10(b), a raw material gas, such as amorphous silicon, is injected through the slit ST, whose sidewalls are protected by an insulating layer 54s, to fill the gap layer GPs with amorphous silicon or the like. The support substrate SS is then heat-treated to polycrystallize the amorphous silicon filled in the gap layer GPs, forming an intermediate source wire BSL containing polysilicon or the like.

[0111] As a result, a portion of the channel layer CN of the pillar PL is connected to the source line SL on the side via the intermediate source line BSL.

[0112] As shown in Figure 11(a), the insulating layer 54s on the side wall of the slit ST is removed.

[0113] As shown in Figure 11(b), a solution for removing the insulating layer NL, such as thermal phosphoric acid, is introduced into the interior of the laminates LMsa and LMsb from the slit ST from which the insulating layer 54s has been removed, thereby removing the insulating layer NL of the laminates LMsa and LMsb. This forms laminates LMga and LMgb having multiple gap layers GP from which the insulating layer NL between insulating layers OL has been removed.

[0114] Laminates LMga and LMgb, which contain multiple gap layers GP, have a fragile structure. Multiple pillars PL support these fragile laminates LMga and LMgb. This prevents the insulating layer OL remaining in the laminate from bending, and prevents the laminate LMga and LMgb from deforming or collapsing.

[0115] As shown in Figure 12(a), a conductive material raw material gas, such as tungsten or molybdenum, is injected into the interior of the laminates LMga and LMgb through the slit ST, and the gap layer GP of the laminates LMga and LMgb is filled with the conductive material to form multiple word lines WL, etc. This forms a laminate LM containing laminates LMa and LMb, in which multiple word lines WL, etc. and multiple insulating layers OL are alternately stacked one layer at a time.

[0116] As described above, the process of forming the intermediate source line BSL from the intermediate sacrificial layer SCN, and the process of forming the word line WL from the insulating layer NL, are also called replacement processes.

[0117] As shown in Figure 12(b), a conductive layer 24 is filled into the slit ST via an insulating layer 54 to form a plate-shaped contact LI. In addition, a groove is formed that penetrates one or more conductive layers, including the uppermost conductive layer of the laminate LMb, and an insulating layer 56 is filled into the groove to form a separation layer SHE that divides these conductive layers into a pattern of selected gate lines SGD.

[0118] Subsequently, although not shown in the diagram, multiple contacts CC are formed from the upper side of the staircase area SR, reaching the word lines WL and selection gate lines SGD and SGS that constitute each step of the staircase structure of the staircase area SR.

[0119] Furthermore, after forming an insulating layer 52 that covers the laminate LM, plugs CH are formed that penetrate the uppermost insulating layer OL and insulating layer 52 of the laminate LM and are connected to the cap layer CP at the upper end of the pillar PL. In addition, an insulating layer 53 is formed that covers the insulating layer 52, and bit wires BL are formed in the insulating layer 53 to which the individual plugs CH are connected.

[0120] Furthermore, the plug CH and bit wire BL may be formed collectively by using methods such as the dual damascene method.

[0121] Furthermore, peripheral circuits CBA are formed on a semiconductor substrate SB, which is separate from the support substrate SS on which the laminated structure LM is formed, and covered with an insulating layer 40. Contacts, vias, wiring, etc. are formed in the insulating layer 40 to bring the peripheral circuits CBA to the surface of the insulating layer 40, and these are connected to electrode pads etc. formed on the upper surface of the insulating layer 40.

[0122] Next, the support substrate SS and the semiconductor substrate SB are bonded together by their respective insulating layers 50 and 40, and the electrode pads in the insulating layers 50 and 40 are connected. After that, the support substrate SS is removed to expose the source wire SL, and the electrode film EL is connected via the insulating layer 60 on which the plug PG is formed.

[0123] The semiconductor memory device 1 of the embodiment is manufactured as described above.

[0124] (Overview) In semiconductor memory devices such as 3D non-volatile memory, there is a technique to monocrystallineize the channel layer of the pillars. This improves carrier mobility in the channel layer and reduces noise because traps are not generated by grain boundaries. On the other hand, impurities such as arsenic do not easily diffuse into the monocrystalline channel layer, and the threshold of the memory cell is lower compared to a polycrystalline channel layer. Furthermore, if the monocrystallineization of the channel layer is incomplete and polycrystalline material is included in some parts, it leads to a decrease in the reliability of memory cells located in the regions where polycrystalline material is mixed.

[0125] According to the semiconductor memory device 1 of the embodiment, the pillar PL has a semiconductor layer CN1 extending within the laminate LM in the stacking direction of the laminate LM, and a semiconductor layer CN3 extending within the laminate LM in the stacking direction of the laminate LM and containing more crystal grain boundaries than semiconductor layer CN1, and includes an additive having a peak concentration at the interface between semiconductor layer CN1 and semiconductor layer CN3.

[0126] Thus, by using a two-layer structure for the pillar PL, consisting of a semiconductor layer CN1 with few grain boundaries and a semiconductor layer CN3 with many grain boundaries, it is possible to achieve both improved carrier mobility and noise reduction in the channel layer, and the construction of a Molysel MC with easily adjustable thresholds. This improves the operating characteristics of the memory cell MC, such as write and read characteristics.

[0127] Furthermore, by creating a structure that includes an additive having a peak concentration at the interface between semiconductor layer CN1 and semiconductor layer CN3, it is possible to suppress the progression of crystallization in semiconductor layer CN3 when a portion of the channel layer CNb (see Figure 7, etc.) is crystallized to form semiconductor layer CN1.

[0128] In the semiconductor memory device 1 of this embodiment, the cap layer CP contains N-type impurities. This reduces the contact resistance between the cap layer CP and the plug CH. Furthermore, since the cap layer CP is made of, for example, a polycrystalline layer, the impurities can be easily diffused. Also, when diffusing impurities into the channel layer CN, since the channel layer CN consists of semiconductor layer CN1 and semiconductor layer CN3, it is possible to easily diffuse the impurities into the channel layer CN at least through semiconductor layer CN3, which includes a polysilicon layer.

[0129] According to the semiconductor memory device 1 of the embodiment, the peak concentration of the additive is 2 × 10⁻⁶ 21 atoms / cm 3 This is larger. As a result, the semiconductor layer CN2, which has a peak concentration of the additive in the channel layer CN, can function effectively as a barrier to inhibit the crystallization of a portion of the channel layer CNb.

[0130] According to the semiconductor memory device 1 of the embodiment, the additive is at least one of carbon, nitrogen, oxygen, or fluorine. By including these elements as additives, the semiconductor layer CN2 can function sufficiently as a barrier that inhibits the crystallization of a portion of the channel layer CNb.

[0131] In the semiconductor memory device 1 of this embodiment, semiconductor layer CN1 is a single-crystal layer, and semiconductor layer CN3 is a polycrystalline layer. This further improves the writing characteristics of the memory cell MC. Furthermore, since the pillar PL has a two-layer structure of semiconductor layer CN1 and semiconductor layer CN3, the threshold of the memory cell MC can be easily adjusted even when polycrystalline material is mixed in semiconductor layer CN1, compared to the case where the entire channel layer CNb is crystallized. Therefore, the reliability of individual memory cells MC can be further improved.

[0132] (modified version) In the above embodiment, in the channel layer CN of the pillar PL, the semiconductor layer CN1 with fewer grain boundaries is placed on the memory layer ME side, and the semiconductor layer CN3 with many grain boundaries is placed on the core layer CR side via the semiconductor layer CN2 to which the additive is added. However, the arrangement of semiconductor layers CN1 and CN3 may be reversed.

[0133] A modified semiconductor memory device of the embodiment will be described below with reference to Figures 13 and 14. In the modified semiconductor memory device, the arrangement of semiconductor layers CN1 and CN3 in the channel layer CNr differs from that of the embodiment described above.

[0134] In the following drawings, components similar to those in the embodiments described above are denoted by the same reference numerals, and their descriptions may be omitted.

[0135] Figure 13 is a partially enlarged cross-sectional view of a pillar PLr in a semiconductor memory device according to a modified embodiment. As shown in Figures 13(a) and 13(b), the modified semiconductor memory device includes a pillar PLr having a channel layer CNr.

[0136] The channel layer CNr comprises semiconductor layers CN1, CN2, and CN3, similar to the channel layer CN in the above-described embodiment. However, in the channel layer CNr, semiconductor layer CN1 is located on the core layer CR side, and semiconductor layer CN3 is located on the memory layer ME side, sandwiching semiconductor layer CN2. Such a channel layer CNr can be formed, for example, as shown in Figure 14 below.

[0137] Figure 14 illustrates a part of the procedure for manufacturing a semiconductor memory device according to a modified embodiment. More specifically, Figure 14 corresponds to Figure 7 of the above-described embodiment, and shows the process of forming the channel layer CNr of the pillar PLr in the modified semiconductor memory device, as shown in a partially enlarged cross-sectional view of the pillar PLr in the process of formation.

[0138] In the modified semiconductor memory device manufacturing method, the pillar PLr being formed has a memory layer ME, a semiconductor layer CN4, a semiconductor layer CN2, a semiconductor layer CN4, and a core layer CR formed in order from the outer periphery of the pillar PLr, and a cap layer CPa is formed at the upper end of the pillar PLr.

[0139] As shown in Figure 14(a), a metal-containing layer NS is formed on the upper end of the pillar PLr during its formation, and the entire support substrate SS is annealed at a low temperature.

[0140] As a result, metal-assisted crystallization is initiated in the cap layer CPa that is in direct contact with the metal-containing layer NS, and in the semiconductor layer CN4 covered by the cap layer CPa on the inside of the semiconductor layer CN2. Some of the metal-containing layer NS that acted as a catalyst for the crystallization of the semiconductor layer CN4 are each broken down into fine metal fragments NSf and diffused into the semiconductor layer CN4.

[0141] In this case, the semiconductor layer CN4 outside the semiconductor layer CN2 is shielded from the metal-containing layer NS by the semiconductor layer CN2 and is not subject to crystallization.

[0142] As shown in Figure 14(b), crystallization that begins in the cap layer CPa at the upper end of the pillar PLr during formation continues downward within the semiconductor layer CN4 inside the semiconductor layer CN2. Furthermore, the metal-containing layer NS formed at the upper end of the pillar PLr during formation diffuses into the semiconductor layer CN4 as metal fragments NSf, as described above, and disappears at a predetermined stage of the metal-assisted annealing process.

[0143] As shown in Figure 14(c), when crystallization progresses to the lower end of the pillar PLr in the process of formation, the entire semiconductor layer CN4 inside semiconductor layer CN2 becomes semiconductor layer CN1, such as a single-crystal silicon layer. The metal fragment NSf that has penetrated to the lower end of semiconductor layer CN4 segregates at the lower end of the crystallized semiconductor layer CN1.

[0144] On the other hand, semiconductor layer CN4 outside semiconductor layer CN2 is blocked by semiconductor layer CN2 and does not undergo metal-assisted crystallization. However, due to annealing at low temperatures, the entire layer transforms into semiconductor layer CN3, such as a polysilicon layer, at the end of the annealing process. However, as mentioned above, amorphous silicon layers may be mixed in a portion of semiconductor layer CN3. Also, as mentioned above, polycrystallization of semiconductor layer CN3 may continue to progress through subsequent annealing processes.

[0145] Subsequently, similar to the embodiment described above, a getter layer is formed on the upper end of the pillar PLr during formation, and the metal fragment NSf segregated at the lower end of the pillar PLr is removed.

[0146] Based on the above, the modified pillar PLr is formed.

[0147] The modified semiconductor memory device provides the same effects as the embodiment described above.

[0148] In the above-described embodiment, the metal-containing layer NS is pre-formed at the lower end of the memory hole MH, and the semiconductor layer CN4 outside the semiconductor layer CN2 is subjected to metal-assisted annealing. However, the metal-assisted annealing method for the semiconductor layer CN4 in the above-described embodiment is not limited to the above method.

[0149] As an example, as in the embodiment described above, when crystallizing the semiconductor layer CN4 outside the semiconductor layer CN2, for example, the metal-containing layer NS formed at the upper end of the memory hole MH may be used instead of the metal-containing layer NS at the lower end of the memory hole MH, as in the modified example described above.

[0150] In this case, a semiconductor layer CN2 can be interposed in the semiconductor layer CN4 between the memory layer ME and the core layer CR, and a semiconductor layer CN2 can also be formed on the upper end of the semiconductor layer CN4 on the core layer CR side, which is not subject to crystallization. This makes it possible to suppress the crystallization of the semiconductor layer CN4 on the core layer CR side while performing crystallization of the semiconductor layer CN4 on the memory layer ME side by metal assistance.

[0151] Furthermore, in the embodiments and modifications described above, the semiconductor memory device 1 is provided with a stacked LM having a 2-tier structure in which two stacked structures LMa and LMb are stacked vertically. However, the configuration of the stacked structure is not limited to 2 tiers; it may be 1 tier or 3 tiers or more.

[0152] Furthermore, in the embodiments and modifications described above, the pillars PL and PLr are connected to the source line SL on the sides of the channel layers CN and CNr, but this is not limited to this configuration. For example, the pillars may be configured such that the memory layer on the bottom surface of the pillar is removed and the source line is connected at the lower end of the channel layer.

[0153] Furthermore, in the embodiments and modifications described above, the peripheral circuit CBA is positioned above the laminate LM. However, the peripheral circuit may be positioned below the laminate, or on the same layer as the laminate. When the peripheral circuit is positioned below the laminate, the laminate can be formed directly above the semiconductor substrate on which the peripheral circuit is formed. Also, when the peripheral circuit is positioned on the same layer as the laminate, the laminate can be formed at a different location on the semiconductor substrate from where the peripheral circuit is formed.

[0154] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0155] 1... Semiconductor memory device, CN... Channel layer, CN1, CN2, CN3... Semiconductor layer, LM, LMa, LMb, LMga, LMgb, LMsa, LMsb... Stack, MC... Memory cell, MR... Memory region, NL, OL... Insulating layer, PL... Pillar, SR... Stair region, SGD, SGS... Selected gate line, WL... Word line.

Claims

1. A laminate in which multiple conductive layers and multiple insulating layers are stacked alternately, The laminate comprises pillars extending within the laminate in the stacking direction, The aforementioned pillar is A first semiconductor layer extending within the laminate in the aforementioned stacking direction, The laminate has a second semiconductor layer that extends within the laminate in the stacking direction and contains more grain boundaries than the first semiconductor layer, The present invention includes an additive having a peak concentration at the interface between the first semiconductor layer and the second semiconductor layer. Semiconductor memory device.

2. The aforementioned pillar is It has a memory layer on the outer periphery, The first semiconductor layer is Displaced between the memory layer and the second semiconductor layer, The semiconductor memory device according to claim 1.

3. The aforementioned pillar is It has a memory layer on the outer periphery, The aforementioned second semiconductor layer is Displaced between the memory layer and the first semiconductor layer, The semiconductor memory device according to claim 1.

4. The peak concentration of the aforementioned additive is 2 × 10 ２１ atoms / cm ３ Larger, The semiconductor memory device according to claim 1.

5. The aforementioned additive is at least one of carbon, nitrogen, oxygen, or fluorine. The semiconductor memory device according to claim 1.

6. The first semiconductor layer is a single crystal layer. The second semiconductor layer is a polycrystalline layer. The semiconductor memory device according to claim 1.

7. A laminate is formed in which multiple first insulating layers and multiple second insulating layers are stacked alternately, one layer at a time. A hole is formed in the laminate that extends within the laminate in the stacking direction of the laminate. First and second semiconductor layers extending in the stacking direction of the laminate are formed within the hole. The formation of the first and second semiconductor layers is as follows: Additives are added to the interface between the first semiconductor layer and the second semiconductor layer to form amorphous first and second semiconductor layers, This includes crystallizing the amorphous first semiconductor layer by annealing using metal assist to form a crystalline first semiconductor layer. A method for manufacturing semiconductor memory devices.

8. The crystallization of the first semiconductor layer is The additive, which is unevenly distributed at the interface between the first semiconductor layer and the second semiconductor layer, inhibits the crystallization of the second semiconductor layer. The method for manufacturing a semiconductor memory device according to claim 7.

9. The formation of the first and second semiconductor layers is as follows: The annealing process using the metal assist is used to crystallize the amorphous first semiconductor layer into a single crystal. The method for manufacturing a semiconductor memory device according to claim 7.

10. During the annealing process using the metal assist, the annealing process can be performed on the second semiconductor layer without using the metal assist, or By performing another annealing treatment after the annealing treatment using the aforementioned metal assist, This includes forming a polycrystalline second semiconductor layer by polycrystallizing the amorphous second semiconductor layer. The method for manufacturing a semiconductor memory device according to claim 7.

Images