Semiconductor memory device and method for manufacturing the same

Abstract

The present invention provides a semiconductor memory device having suitable characteristics and a method for manufacturing the same. [Solution] The semiconductor memory device comprises a plurality of first conductive layers aligned in a first direction and extending in a second direction intersecting the first direction, and in a third direction intersecting the first and second directions, and a memory structure including a first semiconductor layer extending in the first direction and facing the plurality of first conductive layers, and a gate insulating layer provided between the first semiconductor layer and the plurality of first conductive layers. The first semiconductor layer comprises single-crystal silicon and impurities. The impurities include a first metal element capable of forming silicides and a second metal element constituting a metal material with a coefficient of thermal expansion greater than that of the silicon material.

Description

[Technical Field]

[0001] This embodiment relates to a semiconductor memory device and a method for manufacturing the same. [Background technology]

[0002] A semiconductor memory device is known that comprises a substrate, a plurality of conductive layers stacked in a direction intersecting the surface of the substrate, semiconductor layers facing these plurality of conductive layers, and a gate insulating layer provided between the conductive layers and the semiconductor layers. The gate insulating layer includes a memory section capable of storing data, such as an insulating charge storage layer or a conductive charge storage layer such as a floating gate. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2020 / 0388688 [Overview of the project] [Problems that the invention aims to solve]

[0004] The present invention provides a semiconductor memory device having suitable characteristics and a method for manufacturing the same. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a plurality of first conductive layers aligned in a first direction and extending in a second direction intersecting the first direction, and in a third direction intersecting the first and second directions; a memory structure including a first semiconductor layer extending in the first direction and facing the plurality of first conductive layers, and a gate insulating layer provided between the first semiconductor layer and the plurality of first conductive layers. The first semiconductor layer includes single-crystal silicon and impurities. The impurities include a first metallic element capable of forming silicides and a second metallic element constituting a metallic material with a coefficient of thermal expansion greater than that of the silicon material. [Brief explanation of the drawing]

[0006] [Figure 1] It is a schematic circuit diagram showing the configuration of the memory die MD according to the first embodiment. [Figure 2] It is a schematic perspective view showing the configuration of the same memory die MD. [Figure 3] It is a schematic bottom view showing the configuration of the chip CM. [Figure 4] It is a schematic bottom view showing a part of the configuration of the chip CM. [Figure 5] It is a schematic cross-sectional view showing a part of the configuration of the memory die MD. [Figure 6] It is a schematic cross-sectional view showing a part of the configuration of FIG. 5. [Figure 7] It is a schematic cross-sectional view for explaining the manufacturing method of the semiconductor memory device according to the first embodiment. [Figure 8] It is a schematic cross-sectional view for explaining the same manufacturing method. [Figure 9] It is a schematic cross-sectional view for explaining the same manufacturing method. [Figure 10] It is a schematic cross-sectional view for explaining the same manufacturing method. [Figure 11] It is a schematic cross-sectional view for explaining the same manufacturing method. [Figure 12] It is a schematic cross-sectional view for explaining the same manufacturing method. [Figure 13] It is a schematic cross-sectional view for explaining the same manufacturing method. [Figure 14] It is a graph for explaining the same manufacturing method. [Figure 15] It is a schematic cross-sectional view for explaining the same manufacturing method. [Figure 16] It is a schematic cross-sectional view for explaining the same manufacturing method. [Figure 17] It is a schematic cross-sectional view for explaining the same manufacturing method. [Figure 18] It is a schematic cross-sectional view for explaining the same manufacturing method. [Figure 19] It is a schematic cross-sectional view for explaining the same manufacturing method. [Figure 20] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 21] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 22] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 23] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 24] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 25] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 26] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 27] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 28] This is a schematic cross-sectional view illustrating the manufacturing method. [Modes for carrying out the invention]

[0007] Next, a semiconductor memory device and a method for manufacturing the same according to the embodiments will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. Furthermore, the following drawings are schematic, and some components may be omitted for illustrative purposes. Also, parts common to multiple embodiments are denoted by the same reference numerals, and their descriptions may be omitted.

[0008] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die, or to a memory system including a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). It may also refer to a configuration including a host computer, such as a smartphone, tablet device, or personal computer.

[0009] Furthermore, in this specification, when we say that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or it may be connected to the second configuration via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0010] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0011] Furthermore, in this specification, the direction intersecting a predetermined surface may be referred to as the first direction, the direction along this predetermined surface as the second direction, and the direction along this predetermined surface that intersects the second direction as the third direction. These first, second, and third directions may or may not correspond to any of the Z, Y, and X directions.

[0012] Furthermore, in this specification, expressions such as "top" and "bottom" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "top," and the direction approaching the substrate along the Z direction is called "bottom." Also, when referring to the bottom surface or bottom end of a configuration, it means the surface or end of that configuration that is on the substrate side, and when referring to the top surface or top end, it means the surface or end of that configuration that is on the opposite side from the substrate. In addition, surfaces that intersect with the X direction or Y direction are called sides, etc.

[0013] Furthermore, in this specification, when we refer to the "width," "length," or "thickness" of a component, member, etc., in a predetermined direction, it may mean the width, length, or thickness of a cross-section observed by SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy), etc.

[0014] [First Embodiment] [Circuit Configuration] Figure 1 is an equivalent circuit diagram schematically showing the configuration of a semiconductor memory device according to the first embodiment.

[0015] The semiconductor memory device according to this embodiment comprises a memory cell array MCA and a peripheral circuit PC that controls the memory cell array MCA.

[0016] The memory cell array MCA comprises multiple memory blocks MB. Each of these memory blocks MB comprises multiple string units SU. Each of these string units SU comprises multiple memory units MU. One end of each of these memory units MU is connected to a peripheral circuit PC via a bit line BL. The other end of each of these memory units MU is connected to the peripheral circuit PC via a common source line SL.

[0017] The memory unit MU comprises one or more drain selection transistors STD, multiple memory cells MC, and one or more source selection transistors STS, all connected in series between the bit line BL and the source line SL. Hereinafter, the drain selection transistors STD and STS may simply be referred to as selection transistors (STD, STS), etc.

[0018] A memory cell MC is a field-effect transistor (memory transistor) comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film contains a memory portion capable of storing data. This memory portion is a charge storage film, such as a silicon nitride (SiN) film or a floating gate. The threshold voltage of the memory cell MC changes according to the amount of charge in the charge storage film. A word line WL is connected to the gate electrode of each of the multiple memory cell MCs contained in a single memory unit MU. These word lines WL are commonly connected to memory cells MS at the same location in the series direction of all memory units MU within a single memory block MB.

[0019] The selection transistors (STD, STS) are field-effect transistors including a semiconductor layer that functions as a channel region, a gate insulating film, and a gate electrode. In this example, it is shown that one memory unit MU includes two drain selection transistors STD and two source selection transistors STS, but the number of selection transistors STD, STS in one memory unit MU may be one each, or three or more may be provided. Selection gates lines (SGD, SGS) are respectively connected to the gate electrodes of the selection transistors (STD, STS).

[0020] The drain selection gate line SGD is provided separately for each string unit SU and is commonly connected to all the drain selection transistors STD in one string unit SU. In FIG. 1, the drain selection gate lines SGD connected to the respective string units SU are denoted as drain selection gate lines SGD1, SGD2, …, SGDn-1, SGDn.

[0021] The source selection gate line SGS is commonly connected to all the source selection transistors STS in one memory block MB.

[0022] [Structure of Memory Die MD] FIG. 2 is a schematic exploded perspective view showing a configuration example of the semiconductor memory device according to the present embodiment. The semiconductor memory device according to the present embodiment includes a memory die MD. The memory die MD includes a chip C including a memory cell array MCA M and a chip C including a peripheral circuit PC P and includes them.

[0023] On the upper surface of the chip C M a plurality of bonding pad electrodes P X are provided. Also, on the lower surface of the chip C M a plurality of first bonding electrodes P I1 are provided. Also, on the upper surface of the chip C P a plurality of second bonding electrodes P I2 are provided. Hereinafter, the chip C MRegarding this, multiple first bonded electrodes P I1 The surface on which the bonding pad electrodes P are provided is called the surface, and multiple bonding pad electrodes P X The side on which this is provided is called the back side. Also, chip C P Regarding this, multiple second adhesive electrodes P I2 The surface on which the chip is provided is called the front surface, and the surface opposite the front surface is called the back surface. In the illustrated example, chip C P The surface is chip C P It is located above the back surface, and chip C M The back side is chip C M It is positioned above the surface.

[0024] Chip C M and chip C P This is chip C M Surface and chip C P Multiple first bonding electrodes P are arranged so as to face the surface of the first bonding electrode P. I1 This is a plurality of second bonded electrodes P I2 Multiple second bonding electrodes P are provided, corresponding to each of them. I2 It is positioned in a location where it can be bonded. First bonding electrode P I1 and the second bonded electrode P I2 This refers to chip C M and chip C P It functions as a bonding electrode for bonding and electrically connecting two materials. Bonding pad electrode P X These function as electrodes for electrically connecting the memory die MD to a controller die (not shown) or the like.

[0025] In the example shown in Figure 2, chip C M The corners a1, a2, a3, and a4 are, respectively, chip C P These correspond to corners b1, b2, b3, and b4.

[0026] Figure 3 shows chip C MThis is a schematic bottom view showing the configuration. Figure 4 is a schematic bottom view showing an enlarged view of the configuration of the part indicated by A in Figure 3. Figure 4 also shows plan views of the structure in Figure 5, cut along the CC' line and DD' line respectively, arranged in the direction of the arrows, in the X direction. Figure 5 is a schematic cross-sectional view of the memory die MD, cut along the BB' line shown in Figure 4, viewed from the direction of the arrow. Figure 6 is a schematic cross-sectional view showing an enlarged view of the configuration of the part indicated by E in Figure 5.

[0027] [Chip C M [Structure] Chip C M For example, as shown in Figure 3, there are four memory cell array regions R aligned in the X and Y directions. MCA and memory cell array region R MCA The outer periphery region R of the memory cell array is provided along the outer edge. MCAE and multiple bonding pad electrodes P X Multiple bonding pad electrode regions R corresponding to each other PX And, Chip C M Edge seal region R provided along the outer edge E It is equipped with the following.

[0028] Memory cell array region R MCA It has multiple memory blocks MB aligned in the Y direction. Between adjacent memory blocks MB in the Y direction, interblock structures ST extending in the X and Z directions are arranged, respectively, as shown in Figures 4 and 5. Memory cell array region R MCA It comprises a plurality of memory block BLKs and a conductive layer 112 provided on the upper surface of a plurality of inter-block structures STs. A wiring layer 160 is provided below these plurality of memory block BLKs. A wiring layer 170 is provided above the conductive layer 112.

[0029] As shown in Figure 5, the memory block MB comprises a plurality of conductive layers 110 arranged in the Z direction and a plurality of memory structures 100 extending in the Z direction.

[0030] The multiple conductive layers 110 are each substantially plate-shaped conductive layers stretched in the X direction. The conductive layers 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layers 110 may also include polycrystalline silicon containing, for example, N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). An insulating layer 101 such as silicon oxide (SiO2) is provided between the multiple conductive layers 110 arranged in the Z direction.

[0031] Of the multiple conductive layers 110, one or more conductive layers 110 located at the top function as gate electrodes for the source selection gate line SGS and the multiple source selection transistors STS (Figure 1) connected thereto. Hereinafter, such conductive layers 110 may be referred to as conductive layer 110 (SGS).

[0032] Of the multiple conductive layers 110, one or more conductive layers 110 located at the bottom layer function as gate electrodes for the drain selection gate wire SGD and the multiple drain selection transistors STD (Figure 1) connected thereto. Hereinafter, such conductive layers 110 may be referred to as conductive layer 110 (SGD).

[0033] Among the multiple conductive layers 110, the multiple conductive layers 110 arranged between conductive layer 110(SGS) and conductive layer 110(SGD) function as gate electrodes for the word line WL and the multiple memory cells MC (Figure 1) connected thereto. Hereinafter, such conductive layers 110 may be referred to as conductive layer 110(WL).

[0034] The memory structure 100 comprises a semiconductor layer 120 extending in the Z direction, and a gate insulating film 130 provided between a plurality of conductive layers 110 and the semiconductor layer 120. One or more source selection transistors STS (Figure 1) are configured at a position facing the conductive layer 110 (SGS) of the memory structure 100. One or more drain selection transistors STD (Figure 1) are configured at a position facing the conductive layer 110 (SGD) of the memory structure 100. A plurality of memory cells MC (Figure 1) are configured at a position facing the conductive layer 110 (WL) of the memory structure 100.

[0035] The memory structure 100 is arranged in a predetermined pattern in the X and Y directions, as shown in Figure 4, for example. The semiconductor layer 120 in the memory structure 100 functions, for example, as a channel region for multiple memory cells. The semiconductor layer 120 is, for example, a semiconductor layer made of single-crystal silicon (Si). The semiconductor layer 120 may also contain impurities, which will be described later. The semiconductor layer 120 has a substantially bottomed cylindrical shape, as shown in Figure 5, for example, and an insulating layer 125 made of silicon oxide or the like is provided in the central part. The outer surface of the semiconductor layer 120 faces the conductive layer 110. A gate insulating film 130 is provided between the semiconductor layer 120 and the conductive layer 110.

[0036] A conductive layer 112 made of polycrystalline silicon (Si) or the like is provided on top of the uppermost insulating layer 101. An impurity region containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B) is provided at the upper end of the semiconductor layer 120. The upper end of the semiconductor layer 120 is covered by a gate insulating film 130. A portion of the gate insulating film 130 is removed, exposing a part of the side surface of the upper end of the semiconductor layer 120, which is electrically connected to the conductive layer 112.

[0037] An impurity region containing N-type impurities such as phosphorus (P) is provided at the lower end of the semiconductor layer 120. This impurity region covers the lower end of the insulating layer 125. This impurity region is also electrically connected to the bit line BL. The bit line BL is connected to the first bonding electrode P described above. I1 via chip C P It is electrically connected to the internal components.

[0038] The gate insulating film 130 has a substantially cylindrical shape that covers the outer circumferential surface of the semiconductor layer 120. The gate insulating film 130 comprises a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 laminated between the semiconductor layer 120 and the conductive layer 110, as shown in Figure 6, for example. The tunnel insulating film 131 and the block insulating film 133 are insulating films such as silicon oxide (SiO2). The charge storage film 132 is a charge-storing film such as silicon nitride (Si3N4). The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and are stretched in the Z direction along the outer circumferential surface of the semiconductor layer 120.

[0039] Figure 6 shows an example in which the gate insulating film 130 includes a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may also include a floating gate such as polycrystalline silicon containing N-type or P-type impurities.

[0040] The interblock structure ST extends in the X and Z directions, as shown in Figures 4 and 5, for example, and divides the multiple conductive layers 110 and multiple insulating layers 101 in the Y direction for each memory block MB. The interblock structure ST comprises, for example, a conductive layer 141 extending in the X and Z directions, and an insulating layer 142 made of silicon oxide (SiO2) or the like provided on the Y-direction side of the conductive layer 141. The conductive layer 141 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 141 functions, for example, as part of the source line. The upper end of the conductive layer 141 is located above the upper surface of the uppermost insulating layer 101. The upper end of the conductive layer 141 is also electrically connected to the conductive layer 112.

[0041] The conductive layer 112 may contain, for example, polycrystalline silicon containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). The conductive layer 112 functions, for example, as part of the source wire. The conductive layer 112 is in contact with the upper surface of the insulating layer 101, the upper end of the semiconductor layer 120, and the upper end of the conductive layer 141.

[0042] The conductive layer 110 (SGD) is divided in the Y direction for each string unit SU by the inter-string unit insulating layer SHE. Therefore, the conductive layer 110 (SGD) has a smaller width in the Y direction than the other conductive layers 110 (SGS) and 110 (WL). Each conductive layer 110 (SGD) is electrically independent for each string unit SU.

[0043] In this example, five inter-string unit insulating layers SHE are provided between the inter-block structures ST, as shown in Figure 4. The central inter-string unit insulating layer SHE in the Y direction is provided so as to overlap with a row of dummy memory structures 100 aligned in the X direction at the center of the memory block MB in the Y direction. The other inter-string unit insulating layers SHE are provided between rows of memory structures 100 aligned in the X direction that are adjacent in the Y direction, so as to be in contact with these rows of memory structures 100.

[0044] [Chip C P [Structure] Chip C P As shown in Figure 5, for example, the device comprises a substrate 200 and a plurality of transistors Tr provided on the surface of the substrate 200. These plurality of transistors Tr are connected to the second bonding electrode P described above. I2 via chip C M It is connected to the internal configuration and functions as a peripheral circuit PC used to control the memory cell array MCA. For example, in a read operation, this peripheral circuit PC supplies voltage to the current path including the bit line BL, semiconductor layer 120, conductive layer 110, conductive layer 112, and conductive layer 141, and determines the data recorded in the memory cell depending on whether or not current is flowing.

[0045] When reading (or writing) data to a memory cell MC, the peripheral circuit PC applies a drive voltage to the conductive layer 110 (SGD) corresponding to the string unit SU to be accessed, turning on only the drain selection transistor STD of the selected string unit SU. Furthermore, when reading (or writing) data to a memory cell MC, the peripheral circuit PC applies a drive voltage to one of the conductive layers 110 (SGS) containing the selected string unit SU, turning off the source selection transistor STS connected to the other conductive layer (SGS). This causes memory cells MC not involved in the read operation to be in a floating state.

[0046] [Manufacturing method] Next, the manufacturing method of the memory die MD will be described with reference to Figures 7 to 28. Figures 7 to 28 are diagrams illustrating the manufacturing method. Figures 7 to 12 and 16 to 20 show cross-sections corresponding to parts of Figure 5, and Figures 21 to 28 show cross-sections corresponding to Figure 5. Figures 13 and 15 are schematic cross-sectional views illustrating the operation of this manufacturing method. Figure 14 is a graph illustrating the operation of this manufacturing method.

[0047] In manufacturing the memory die MD according to this embodiment, an insulating layer 102 made of silicon oxide (SiO2) or the like is formed on a substrate 300, for example, as shown in Figure 7. This step is carried out by a method such as CVD (Chemical Vapor Deposition). Next, a conductive layer 112A made of silicon, a sacrificial layer 103A made of silicon oxide (SiO2), a sacrificial layer 103B made of silicon nitride (SiN), a sacrificial layer 103C made of silicon oxide (SiO2), and a conductive layer 112B made of silicon are formed on the insulating layer 102. The conductive layers 112A and 112B may contain polycrystalline silicon containing, for example, N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). Next, multiple insulating layers 101 made of silicon oxide (SiO2) and multiple sacrificial layers 110A made of silicon nitride (SiN) are alternately formed on the conductive layer 112B. These steps are carried out by a method such as CVD. Next, a cover insulating layer 104 is formed on the uppermost insulating layer 101. This process is carried out, for example, by methods such as CVD.

[0048] Next, as shown in Figure 8, for example, a mask (not shown) is used to form multiple memory holes 100A at positions corresponding to the memory structure 100. The memory holes 100A extend in the Z direction, penetrating multiple insulating layers 101, multiple sacrificial layers 110A, conductive layer 112B, and sacrificial layers 103C, 103B, and 103A, reaching partway through the conductive layer 112A. This process is carried out by a method such as RIE (Reactive Ion Etching).

[0049] Next, as shown in Figure 9, for example, a gate insulating film 130 (tunnel insulating film 131, charge storage film 132, and block insulating film 133), a semiconductor layer 120A, and an insulating layer 125A are formed on the upper surface of the cover insulating layer 104 and the inner circumferential surface of the memory hole 100A. The semiconductor layer 120A includes, for example, amorphous silicon (a-Si). The insulating layer 125A includes, for example, silicon oxide (SiO2). The semiconductor layer 120A and the insulating layer 125A are formed by, for example, CVD. Alternatively, prior to forming the gate insulating film 130 on the inner circumferential surface of the memory hole 100A, an insulating layer of silicon oxide (SiO2) or the like may be formed on the portions of the conductive layer 112A and conductive layer 112B that are exposed to the memory hole 100A, for example, by thermal oxidation.

[0050] Next, as shown in Figure 10, for example, a sacrificial core 126 is generated inside the insulating layer 125A formed in the memory hole 100A. The sacrificial core 126 includes a metallic material or a metallic compound material having a larger coefficient of thermal expansion than silicon (Si). For example, the sacrificial core 126 includes a metallic material containing at least one metallic element from zinc (Pb), indium (In), silver (Ag), gold (Au), cobalt (Co), zirconium (Zr), aluminum (Al), titanium (Ti), yttrium (Y), and copper (Cu), or at least one metallic compound material from ZrO2, Al2O3, TiC, TiNi, Y2O3, and AlN.

[0051] Next, as shown in Figure 11, for example, the upper surfaces of the sacrificial core 126 and the insulating layer 125A are removed down to the midpoint of the cover insulating layer 104. This step is performed by methods such as wet etching or RIE.

[0052] Next, as shown in Figure 12, for example, a semiconductor layer 122 is formed on the semiconductor layer 120A and the sacrificial core 126. The semiconductor layer 122 includes, for example, amorphous silicon (a-Si). A metal layer 111 is then formed on the semiconductor layer 122. The metal layer 111 includes at least one of a metal element capable of forming silicides with silicon, such as nickel, palladium, and cobalt. An example in which the metal layer 111 is nickel will be described below. The semiconductor layer 122 and the metal layer 111 are formed by, for example, a method such as CVD.

[0053] Next, the semiconductor layer 120A is crystallized using the MILC method (Metal Induced Lateral Crystallization). Specifically, chip C M Next, crystallization annealing is performed at 400-800°C for an extended period. This causes nickel atoms contained in the metal layer 111 to diffuse into the amorphous silicon of the semiconductor layer 122, and nickel disilicide (NiSi2) crystals to grow in the semiconductor layer 122. As the crystallization annealing continues, these crystals move within the semiconductor layer 122, promoting the diffusion of Ni and the crystallization of silicon, until they reach the semiconductor layer 120A, and then move further within the semiconductor layer 120A from one end to the other in the Z direction.

[0054] Figure 13 is a diagram illustrating the details of the MILC method described above, and is a schematic cross-sectional view of the semiconductor layer 120A in an enlarged view. As shown in Figure 13(a), at the interface S1 between the amorphous silicon semiconductor layer 120A and the silicide layer 123, nickel atoms Ni in the silicide layer 123 diffuse into the semiconductor layer 120A, forming the silicide layer 123 at the locations where they diffuse. Meanwhile, within the silicide layer 123, vacancies V corresponding to the nickel atoms Ni that diffused into the semiconductor layer 120A are generated at S2. These vacancies V diffuse through the silicide layer 123 and reach the interface S3 between the silicide layer 123 and the semiconductor layer 120. At interface S3, the vacancies V aggregate, and silicon crystals grow. Then, as shown in Figures 13(a), (b), and (c), as the silicide layer 123 moves from one end to the other of the semiconductor layer 120A, the amorphous silicon semiconductor layer 120A crystallizes, forming a semiconductor layer 120 made of single-crystal silicon. It should be noted that, here, "single-crystal silicon" does not mean that it is limited to perfectly "single-crystal silicon," but also includes "crystallized silicon" that is close to single-crystal silicon but has a larger maximum grain width than "polysilicon."

[0055] The crystallization process using the MILC method described above requires prolonged heating. However, longer crystallization annealing times make amorphous silicon more likely to convert to polysilicon. Polysilicon has a higher resistance than single-crystal silicon, leading to an increase in cell current.

[0056] To accelerate the crystallization rate by the MILC method, it is effective to (1) facilitate the formation of vacancies V, (2) promote the diffusion of vacancies V, and (3) facilitate the disappearance of vacancies V. According to the inventors' findings, applying a tensile stress in the crystallization progression method (Z direction) to the semiconductor layer 120A is effective in accelerating the above (1) to (3).

[0057] Figure 14 is a graph showing the relationship between the stress applied to the semiconductor layer 120A in the direction of crystallization (Z direction) and the change in energy required for Ni atoms to move. As is clear from Figure 14, at all locations, including the NiSi2 / a-Si interface S1, the bulk NiSi2 layer S2, and the c-Si / NiSi2 interface S3, the greater the applied tensile stress, the easier it is for Ni atoms to move.

[0058] Therefore, in this embodiment, a metallic material or metallic compound material with a higher coefficient of thermal expansion than silicon is used as the sacrificial core 126. Figure 15 is a schematic cross-sectional view showing an enlarged portion of the semiconductor layer 120 and sacrificial core 126 during the crystallization annealing process. As shown in Figure 15, during crystallization annealing, the sacrificial core 126 expands in the direction of crystallization (Z direction), and as a result, tensile stress is applied to the semiconductor layers 120 and 120A in the direction of crystallization (Z direction). This promotes the progression of crystallization, and a single-crystal semiconductor layer 120 is produced. The insulating layer 125A functions as a shielding layer to prevent the reaction between the metallic elements contained in the sacrificial core 126 and the semiconductor layers 120 and 120A during crystallization annealing.

[0059] After the crystallization annealing by the MILC method is completed, an adsorption layer 124 made of amorphous silicon is formed on the crystallized semiconductor layer 122, as shown in Figure 16. This step is carried out by a method such as CVD.

[0060] Next, a heat treatment is performed. This adsorbs any nickel atoms remaining in the semiconductor layer 120 by the adsorption layer 124. After the heat treatment, a small amount of the first metal element (e.g., nickel) capable of forming silicides may remain in the semiconductor layer 120 as an impurity, which was not adsorbed during the adsorption treatment. In addition, a small amount of the second metal element contained in the sacrificial core 126 that has moved into the semiconductor layer 120 beyond the insulating layer 125A may remain in the semiconductor layer 120. Note that the content of the second metal is smaller than the content of the second metal.

[0061] Next, as shown in Figure 17, the adsorption layer 124, semiconductor layer 122, sacrificial core 126, and insulating layer 125A are removed. This step is carried out by methods such as RIE or wet etching.

[0062] Next, as shown in Figure 18, the semiconductor layer 120 is slimmed. This reduces the thickness of the semiconductor layer 120. This process is carried out by methods such as wet etching.

[0063] Next, as shown in Figure 19, an insulating layer 125 is formed in the center of the semiconductor layer 120. This forms the memory structure 100B. This process is carried out by methods such as CVD.

[0064] Next, as shown in Figure 20, for example, a portion of the insulating layer 125, semiconductor layer 120, and gate insulating film 130 is removed to expose the cover insulating layer 104 located at the top. Furthermore, the upper ends of the semiconductor layer 120 and insulating layer 125 are excavated below the upper surface of the cover insulating layer 104. This process is carried out, for example, by a method such as RIE.

[0065] Next, as shown in Figure 21, for example, a semiconductor layer 121 is formed on the upper end of the semiconductor layer 120 and the insulating layer 125. The semiconductor layer 121 contains amorphous silicon containing, for example, N-type impurities such as phosphorus (P). This step is carried out by, for example, a method such as CVD. Next, a part of the semiconductor layer 121 is removed by, for example, a method such as RIE to expose the cover insulating layer 104. Next, an insulating layer 105 is formed on the cover insulating layer 104 and the semiconductor layer 121. This step is carried out by, for example, a method such as CVD.

[0066] Next, a groove STA is formed at the position where the interblock structure ST is formed, as shown in Figure 22, for example. The groove STA extends in the Z and X directions, dividing the cover insulating layer 104, insulating layer 101, sacrificial layer 110A, conductive layer 112B, sacrificial layer 103C, and sacrificial layer 103B in the Y direction, exposing the upper surface of the sacrificial layer 103A. This step is performed, for example, by a method such as RIE. Next, a protective film 140B, such as silicon nitride, is formed on the Y-direction side surface of the groove STA. This step is performed, for example, by forming an insulating film such as silicon nitride on the Y-direction side surface and bottom surface of the groove STA by a method such as CVD, and then removing the portion of this insulating film that covers the bottom surface of the groove STA by a method such as RIE.

[0067] Next, as shown in Figure 23, for example, a portion of the sacrificial layers 103A, 103B, 103C and the gate insulating film 130 is removed, exposing a portion of the semiconductor layer 120. This step is performed, for example, by a method such as wet etching.

[0068] Next, as shown in Figure 24, for example, a semiconductor layer is formed in the area where the sacrificial layers 103A, 103B, 103C and a portion of the gate insulating film 130 have been removed, and a conductive layer 112 is formed with the newly formed semiconductor layer and conductive layers 112A, 112B. The semiconductor layer formed in the groove STA is then removed. This process is carried out by methods such as epitaxial growth and RIE.

[0069] Next, as shown in Figure 25, for example, the protective film 140B is removed, and the sacrificial layer 110A is removed via the groove STA. This step is performed by a method such as wet etching. As a result, a hollow structure is formed which includes a plurality of insulating layers 101 arranged in the Z direction and a memory structure 100B that supports these insulating layers 101.

[0070] Next, a conductive layer 110 is formed in the hollow portion, for example, as shown in Figure 26. This step is performed by a method such as CVD. Next, an insulating layer 142 constituting the interblock structure ST is formed in the groove STA. Next, a conductive layer 141 is formed in the center of the insulating layer 142 in the Y direction, and a contact 161 is formed. These steps are performed by a method such as CVD and RIE. The insulating layer 142 extends from the insulating layer 105 to the conductive layer 112. The conductive layer 141 penetrates the insulating layer 105, and its lower end is electrically connected to the conductive layer 112. The contact 161 penetrates the insulating layer 105 and is electrically connected to the semiconductor layer 121 of the memory structure 100B.

[0071] Next, as shown in Figure 27, for example, a resist is formed on the insulating layer 105, and a mask 106 is formed by a photoetching method. Using the mask 106, grooves SHEA are formed that divide the insulating layer 105, the cover insulating layer 104, the insulating layer 101, and the conductive layer 110 (SGD) in the Y direction. This step is performed by a method such as RIE.

[0072] Next, as shown in Figure 28, for example, an insulating layer SHE is formed in the groove SHEA between string units. Then, another insulating layer 105 is laminated on top of the insulating layer 105. Next, the insulating layer 105 is etched in a predetermined pattern to form the contact 162 and the bit line BL that are connected to the contact 161.

[0073] Subsequently, an insulating layer 105 is laminated on the bit line BL, and then the wiring layer 160 shown in Figure 5 is formed, resulting in chip C M It is manufactured.

[0074] [effect] According to this embodiment, tensile stress can be applied to the semiconductor layer 120A by utilizing the thermal expansion of the sacrificial core 126 during the MILC process, thereby improving the crystallization rate of the semiconductor layer 120A. This makes it possible to provide a semiconductor memory device with suitable characteristics, having a semiconductor layer that is well crystallized as a channel.

[0075] [others] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0076] 110...conductive layer, 112...conductive layer, 120...semiconductor layer, 125...insulating layer, 125A...sacrificial core, 130...gate insulating film.

Claims

1. A plurality of first conductive layers are arranged in a first direction and extend in a second direction intersecting the first direction, and in a third direction intersecting the first and second directions, The memory structure includes a first semiconductor layer extending in the first direction and facing the plurality of first conductive layers, and a gate insulating layer provided between the first semiconductor layer and the plurality of first conductive layers, The first semiconductor layer is It contains single-crystal silicon and impurities. The aforementioned impurities are A first metallic element capable of forming a silicide, The second metallic element that constitutes a metallic material with a coefficient of thermal expansion greater than that of silicon, including Semiconductor memory device.

2. The first metallic element includes at least one of nickel, palladium, and cobalt. The semiconductor memory device according to claim 1.

3. The first metallic element is nickel. The semiconductor memory device according to claim 2.

4. The second metallic element includes at least one of zinc, indium, silver, gold, cobalt, zirconium, aluminum, titanium, yttrium, and copper. The semiconductor memory device according to claim 1.

5. The first insulating layer and the first sacrificial layer are alternately stacked in the first direction. Memory holes extending in the first direction are formed in the first insulating layer and the first sacrificial layer. A second insulating layer is formed inside the memory hole. A first semiconductor layer containing amorphous silicon is formed inside the second insulating film of the memory hole. A metal layer containing a first metal element capable of forming a silicide is formed at one end of the first semiconductor layer in the first direction. A first heat treatment is performed to convert the amorphous silicon of the first semiconductor layer into a single crystal. In a method for manufacturing semiconductor memory devices, After forming the first semiconductor layer and before forming the metal layer, a third insulating layer is formed inside the first semiconductor layer. A pseudo-core containing a second metal element having a higher coefficient of linear thermal expansion than the first semiconductor layer is formed inside the third insulating layer. After the first heat treatment, Remove the simulated core and the third insulating layer, A fourth insulating layer is formed inside the first semiconductor layer. A method for manufacturing semiconductor memory devices.

6. After the first heat treatment, a second semiconductor layer is formed on one end of the first semiconductor layer in the first direction. A second heat treatment is performed to adsorb the first metal element onto the second semiconductor layer. A method for manufacturing a semiconductor memory device according to claim 5.

7. After removing the simulated core and the third insulating layer, and before forming the fourth insulating layer, the first semiconductor layer is subjected to a slimming process. A method for manufacturing a semiconductor memory device according to claim 5.

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