Communication method, controller and chip

Abstract

One embodiment aims to provide a communication method, controller, and chip that can efficiently transfer data. [Solution] According to one embodiment, a communication method is provided. The communication method includes transmitting a first packet, which includes identification information of a first chip and a specification of a first size, from a controller to a first bus. The communication method includes making first data of a first size transferable from the first chip to a second bus in response to the first packet being received by the first chip. The communication method includes releasing the second bus after the transfer of the first data is complete.

Description

Technical Field

[0001] This embodiment relates to a communication method, a controller, and a chip.

Background Art

[0002] In a system where a plurality of chips are connected to a controller, upon receiving a packet from the controller to a chip, data transfer is performed from the chip to a data bus. At this time, it is desired that the data transfer be performed efficiently.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to provide a communication method, a controller, and a chip that can perform data transfer efficiently.

Means for Solving the Problems

[0005] According to one embodiment, a communication method is provided. The communication method includes transmitting, from a controller to a first bus, a first packet including identification information of a first chip and a specification of a first size. The communication method includes enabling transfer of first data of the first size from the first chip to a second bus in response to the first packet being received by the first chip. The communication method includes releasing the second bus after completion of the transfer of the first data. [Brief explanation of the drawing]

[0006] [Figure 1] A diagram showing the schematic configuration of a memory system to which the communication method according to the first embodiment is applied. [Figure 2] A diagram showing the configuration of the memory system in the first embodiment. [Figure 3] A diagram showing a communication method according to the first embodiment. [Figure 4] A diagram showing a communication method according to the first embodiment. [Figure 5] A diagram showing the schematic configuration of the memory system in a modified example of the first embodiment. [Figure 6] A diagram showing the configuration of a memory system in a modified example of the first embodiment. [Figure 7] A diagram showing a communication method according to the second embodiment. [Figure 8] A diagram illustrating a communication method according to the third embodiment. [Figure 9] A diagram illustrating a communication method according to the third embodiment. [Figure 10] A diagram showing a communication method according to the fourth embodiment. [Figure 11] A diagram showing a communication method according to the fifth embodiment. [Figure 12] A diagram showing a communication method according to the sixth embodiment. [Figure 13] A diagram showing a communication method according to the seventh embodiment. [Figure 14] A diagram showing a communication method according to the seventh embodiment. [Figure 15] A diagram showing the communication method in the eighth embodiment. [Figure 16] A diagram showing a communication method according to the eighth embodiment. [Figure 17] A diagram showing a communication method according to the eighth embodiment. [Figure 18] A diagram showing the configuration of a memory system according to a modified example of the eighth embodiment. [Modes for carrying out the invention]

[0007] Referring to the accompanying drawings below, the memory system according to the embodiments will be described in detail. Note that the present invention is not limited by these embodiments.

[0008] (First Embodiment) The communication method according to the first embodiment is used for accessing one or more chips out of a plurality of chips from a controller in a memory system, and a device for efficiently accessing the chips is provided.

[0009] The communication method may be applied to the memory system 1 as shown in FIG. 1. FIG. 1 is a diagram showing a schematic configuration of the memory system 1 to which the communication method is applied.

[0010] The memory system 1 includes a controller 2 and memory chips 3_LUN0, 3_LUN1, 3_LUN2, 3_LUN3. The controller 2 and the plurality of memory chips 3_LUN0 to 3_LUN3 are communicably connected to each other via a channel CH. The controller 2 and the plurality of memory chips 3_LUN0 to 3_LUN3 may communicate according to the SCA protocol.

[0011] The channel CH is configured based on a predetermined standard. When each memory chip 3 is a NAND type flash memory, the predetermined standard is, for example, the toggle DDR standard. The predetermined standard may support the SCA protocol in the toggle DDR standard.

[0012] The channel CH includes a plurality of signal lines. The channel CH may include a command address bus CA_bus, a clock line CA_CLK, a data bus DQ_bus, a read enable line RE￣ / RE, and a data strobe signal DQS￣ / DQS.

[0013] The command address bus CA_bus is used to transmit packets containing commands and addresses. The clock line CA_CLK is used to transmit the clock for packet capture. The data bus DQ_bus is used to transmit data. The read enable line RE￣ / RE is used to transmit the read enable signal RE￣ / RE, which is a timing signal for data capture. The read enable signal RE￣ / RE is a pair of differential signals.

[0014] In the memory system 1, the controller 2 has a transmitting unit 21, a receiving unit 22, a control unit 23, a packet issuing unit 24, and a channel interface 25, as shown in Figure 2. Figure 2 is a diagram showing the configuration of the memory system 1. Each memory chip 3 has a receiving unit 31, a transmitting unit 32, a packet decoder 33, a control unit 34, a memory cell array 35, and a channel interface 36.

[0015] The channel interface 25 of controller 2 is connected to channel CH. The channel interface 25 performs interface operations for channel CH.

[0016] The packet issuing unit 24 issues packet PK1, which includes the identification information and size specification of the memory chip 3. The packet issuing unit 24 may also issue a "Pre-defined Trans Num" packet as packet PK1. The "Pre-defined Trans Num" packet is not a packet in the SCA protocol, but it may be newly defined and pre-configured in the packet issuing unit 24.

[0017] A "Pre-defined Trans Num" packet can be issued to release the data bus DQ_bus after transferring data of a specified size at the destination, depending on the size specified. Once issued, this packet is continuously applied at the destination. A "Pre-defined Trans Num" packet can also be issued to terminate this continuous application at the destination by specifying a size of zero.

[0018] The packet issuing unit 24 may issue an SCE (Select Chip Enable) packet containing identification information for the memory chip 3 and an instruction to start the transfer. The SCE packet is defined in the SCA protocol.

[0019] When packet PK1 is issued by packet issuing unit 24, control unit 23 waits until it is time to send packet PK1. When it is time to send packet PK1, control unit 23 supplies packet PK1 to transmission unit 21.

[0020] The transmitting unit 21 sends packet PK1 to the command address bus CA_bus. This allows the controller 2 to notify the memory chip 3 in advance of the size (e.g., the number of bytes to be transferred).

[0021] The channel interface 36 of the memory chip 3 is connected to channel CH. The channel interface 36 performs interface operations for channel CH.

[0022] The receiving unit 31 checks the identification information of the memory chip 3 contained in packet PK1. If the identification information of the memory chip 3 contained in packet PK1 matches its own identification information, the receiving unit 31 receives packet PK1 via the command address bus CA_bus.

[0023] The control unit 34 waits until packet PK1 is received, and when packet PK1 is received by the receiving unit 31, it passes packet PK1 to the packet decoder 33.

[0024] The packet decoder 33 decodes packet PK1 and extracts the size specification from packet PK1. The packet decoder 33 may also decode a "Pre-defined Trans Num" packet and extract the size specification from the "Pre-defined Trans Num" packet. The "Pre-defined Trans Num" packet is not a packet in the SCA protocol, but it may be newly defined and pre-configured in the packet decoder 33. The packet decoder 33 passes the size specification as the decoding result to the control unit 34.

[0025] The control unit 34 reads data DT of the specified size from the memory cell array 35, passes the read data to the transmission unit 32, and notifies the transmission unit 32 of the size specification.

[0026] The transmitting unit 32 sends data DT of the specified size to the data bus DQ_bus.

[0027] The receiving unit 22 receives data DT via the data bus DQ_bus.

[0028] The transmitting unit 32 releases the data bus DQ_bus after completing the transmission of data DT of the specified size.

[0029] In other words, memory chip 3 automatically releases the data bus DQ_bus once a predetermined number of transfers are completed. This eliminates the need to issue an SCT (Select Chip Terminate) packet, which is recommended as a transfer completion notification in the SCA protocol, thus suppressing the degradation of transfer performance that would otherwise occur during the SCT issuance time.

[0030] Next, the communication method will be explained using Figures 3 and 4. Figures 3 and 4 are diagrams illustrating the communication method, respectively. In Figures 3 and 4, the horizontal axis represents time. Figures 3(a) and 4(a) show the sequence of packets transferred on the command address bus CA_bus, respectively. Figures 3(b) and 4(b) show the sequence of data transferred on the data bus DQ_bus, respectively.

[0031] At timing t1, a "Pre-defined Trans Num LUN0" packet PK1 containing the identification information "LUN0" and the size specification DS1 for memory chip 3_LUN0 is sent from controller 2 to the command address bus CA_bus. Subsequently, the "Pre-defined Trans Num LUN0" packet PK1 is received by memory chip 3_LUN0.

[0032] At timing t2, a "DQ Related LUN0" packet PK11 containing the identification information "LUN0" for memory chip 3_LUN0 and a transfer instruction is sent from controller 2 to the command address bus CA_bus. Subsequently, the "DQ Related LUN0" packet PK11 is received by memory chip 3_LUN0. Note that the "DQ Related LUN0" packet is defined in the SCA protocol as a general term for data transfer commands using the DQ Bus.

[0033] At timing t3, SCE packet PK12, containing the identification information "LUN0" for memory chip 3_LUN0 and an instruction to start the transfer, is sent from controller 2 to the command address bus CA_bus. Subsequently, SCE packet PK12 is received by memory chip 3_LUN0.

[0034] At timing t4, data DT1 of size DS1, specified in packet PK1, begins to be sent from memory chip 3_LUN0 to data bus DQ_bus.

[0035] Simultaneously, a "Pre-defined Trans Num LUN1" packet PK2, containing the identification information "LUN1" and the size specification DS2 for memory chip 3_LUN1, is sent from controller 2 to the command address bus CA_bus. Subsequently, the "Pre-defined Trans Num LUN1" packet PK2 is received by memory chip 3_LUN1.

[0036] At timing t5, the "DQ Related LUN1" packet PK13, which contains the identification information "LUN1" for memory chip 3_LUN1 and a transfer instruction, is sent from controller 2 to the command address bus CA_bus. Subsequently, the "DQ Related LUN1" packet PK13 is received by memory chip 3_LUN1.

[0037] At timing t6, the size of data DT1 reaches DS1, and the transmission of data DT1 from memory chip 3_LUN0 to command address bus CA_bus is completed.

[0038] At timing t7, upon completion of the transmission of data DT1, the data bus DQ_bus is released by memory chip 3_LUN0. This makes the other memory chips 3_LUN1 to 3_LUN3 able to use the data bus DQ_bus.

[0039] Accordingly, SCE packet PK14, containing the identification information "LUN1" for memory chip 3_LUN1 and an instruction to start the transfer, is sent from controller 2 to the command address bus CA_bus. Subsequently, SCE packet PK14 is received by memory chip 3_LUN1.

[0040] At timing t8, data DT2 of size DS2, specified in packet PK2, begins to be sent from memory chip 3_LUN1 to data bus DQ_bus.

[0041] At timing t9, the controller 2 sends a "DQ Related LUN0" packet PK15 containing the identification information "LUN0" for memory chip 3_LUN0 and a transfer instruction to the command address bus CA_bus. Subsequently, the "DQ Related LUN0" packet PK15 is received by memory chip 3_LUN0.

[0042] At timing t10, the size of data DT2 reaches DS2, and the transmission of data DT2 from memory chip 3_LUN1 to data bus DQ_bus is completed.

[0043] At timing t11, upon completion of the transmission of data DT2, the data bus DQ_bus is released by memory chip 3_LUN1. This makes the other memory chips 3_LUN0, 3_LUN2, and 3_LUN3 able to use the data bus DQ_bus.

[0044] At timing t12, SCE packet PK16, containing the identification information "LUN0" for memory chip 3_LUN0 and an instruction to start the transfer, is sent from controller 2 to the command address bus CA_bus. Subsequently, SCE packet PK16 is received by memory chip 3_LUN0.

[0045] At timing t13, data DT3 of size DS1, specified in packet PK1, begins to be sent from memory chip 3_LUN0 to data bus DQ_bus.

[0046] At timing t14, the "DQ Related LUN1" packet PK17, which contains the identification information "LUN1" for memory chip 3_LUN1 and a transfer instruction, is sent from controller 2 to the command address bus CA_bus. Subsequently, the "DQ Related LUN0" packet PK17 is received by memory chip 3_LUN1.

[0047] At timing t15, the size of data DT3 reaches DS1, and the transmission of data DT3 from memory chip 3_LUN0 to command address bus CA_bus is completed.

[0048] At timing t16, upon completion of the transmission of data DT3, the data bus DQ_bus is released by memory chip 3_LUN0. This makes the other memory chips 3_LUN1 to 3_LUN3 able to use the data bus DQ_bus.

[0049] Accordingly, SCE packet PK18, containing the identification information "LUN1" for memory chip 3_LUN1 and an instruction to start the transfer, is sent from controller 2 to the command address bus CA_bus. Subsequently, SCE packet PK18 is received by memory chip 3_LUN1.

[0050] At timing t17, data DT2 of size DS2, specified in packet PK2, begins to be sent from memory chip 3_LUN1 to data bus DQ_bus.

[0051] At timing t18, the size of data DT4 reaches DS2, and the transmission of data DT4 from memory chip 3_LUN1 to command address bus CA_bus is completed.

[0052] At timing t19, upon completion of the transmission of data DT4, the data bus DQ_bus is released by memory chip 3_LUN1. This makes the data bus DQ_bus available to the other memory chips 3_LUN0, 3_LUN2, and 3_LUN3.

[0053] At timing t20, the "Pre-defined Trans Num LUN0 size0" packet PK3, which includes the identification information "LUN0" and size "0" for memory chip 3_LUN0, is sent from controller 2 to the command address bus CA_bus. Subsequently, the "Pre-defined Trans Num LUN0 size0" packet PK3 is received by memory chip 3_LUN0. This terminates the continued application of the "Pre-defined Trans Num LUN0" packet PK1 in memory chip 3_LUN0.

[0054] At timing t21, a "Pre-defined Trans Num LUN1 size0" packet PK3a, containing the identification information "LUN1" and size "0" for memory chip 3_LUN1, is sent from controller 2 to the command address bus CA_bus. Subsequently, the "Pre-defined Trans Num LUN1 size0" packet PK3a is received by memory chip 3_LUN1. This terminates the continued application of the "Pre-defined Trans Num LUN1" packet PK2 in memory chip 3_LUN1.

[0055] As described above, in the first embodiment, in the communication method, the controller 2 can issue and transmit packet PK1, which includes the identification information and size specification of the memory chip 3, and the memory chip 3 can receive and recognize it. This allows the memory chip 3, which has sent data of the specified size to the data bus, to release the data bus after transmission is complete. In other words, the memory chip 3 that receives packet PK1 can release the data bus without sending or receiving an SCT packet, which is recommended as a transfer completion notification in the SCA protocol, thus suppressing the degradation of transfer performance due to the time it takes to issue an SCT. That is, data transfer from the memory chip 3 to the data bus can be performed efficiently.

[0056] The packet PK, which includes the identification information and size specification of the memory chip 3, may consist of one packet or multiple packets. In the first embodiment, an example is given where the packet PK, which includes the identification information and size specification of the memory chip 3, consists of one packet.

[0057] Alternatively, as a modification of the first embodiment, the memory system 1i may further include an interface chip 4i, as shown in Figure 5. Figure 5 is a diagram showing a schematic configuration of the memory system 1i according to a modification of the first embodiment.

[0058] In the memory system 1i, the interface chip 4i is connected between the controller 2 and the multiple memory chips 3_LUN0 to 3_LUN3. The interface chip 4i is connected to the controller 2 via channel CH1 and to each of the multiple memory chips 3_LUN0 to 3_LUN3 via channel CH2.

[0059] Each channel CH1 and CH2 is configured according to a predetermined standard. If each memory chip 3 is a NAND flash memory, the predetermined standard is, for example, the toggle DDR standard. The predetermined standard may also support the SCA protocol in the toggle DDR standard.

[0060] Each channel CH1 and CH2 contains multiple signal lines. Each channel CH1 and CH2 may also contain a command address bus CA_bus, a clock line CA_CLK, a data bus DQ_bus, and a read enable line RE_ / RE.

[0061] This configuration reduces the external load on each memory chip 3 and enables faster data transfer between the controller 2 and the memory chips 3.

[0062] As shown in Figure 6, the interface chip 4i includes a receiving unit 41, a transmitting unit 42, a transmitting unit 43, a receiving unit 44, a control unit 45, a channel interface 46, and a channel interface 47. Figure 6 shows the configuration of a memory system 1i according to a modified example of the first embodiment.

[0063] The channel interface 46 is connected to channel CH1. The channel interface 46 performs interface operations for channel CH1.

[0064] Channel interface 47 is connected to channel CH2. Channel interface 47 performs interface operations for channel CH2.

[0065] The receiving unit 41 receives the packet PK via the command address bus CA_bus.

[0066] When the packet PK is received by the receiving unit 41, the control unit 45 supplies the packet PK to the transmitting unit 43.

[0067] The transmitting unit 43 transfers the packet PK to the memory chip 3 via the command address bus CA_bus.

[0068] The receiving unit 44 receives data DT via the data bus DQ_bus.

[0069] When the data DT is received by the receiving unit 44, the control unit 45 supplies the data DT to the transmitting unit 42.

[0070] The transmitting unit 42 transfers the data DT to the controller 2 via the data bus DQ_bus.

[0071] The interface chip 4i transfers packets and data directly between the controller 2 and the memory chip 3. The communication method used in the memory system 1i is the same as the communication method shown in Figures 3 and 4.

[0072] In such a memory system 1i, the controller 2 can issue and transmit a packet PK1 containing the identification information and size specification of the memory chip 3, which the memory chip 3 can receive and recognize. This allows the memory chip 3, after sending data of the specified size to the data bus, to release the data bus after the transmission is complete.

[0073] (Second embodiment) Next, we will describe the memory system 1 according to the second embodiment. The following description will focus on the differences from the first embodiment.

[0074] The first embodiment illustrates the sending and receiving of packets, including the specification of size, and the data transfer using those packets, while the second embodiment illustrates the cancellation of data transfer using those packets.

[0075] The packet issuing unit 24 of the controller 2 shown in Figure 2 may issue an SCT (Select Chip Terminate) packet PK21 containing the identification information "LUN0" for the memory chip 3_LUN0 and an instruction to terminate the transfer if it wants to interrupt the data transfer by packet PK1, which includes a size specification. The SCT packet is defined in the SCA protocol.

[0076] When the SCT packet PK21 is issued by the packet issuing unit 24, the control unit 23 waits until it is time to send the packet PK21. When it is time to send the SCT packet PK21, the control unit 23 supplies the SCT packet PK21 to the transmitting unit 21.

[0077] The transmitting unit 21 sends SCT packet PK21 to the command address bus CA_bus. This allows the controller 2 to have the data transfer by packet PK1, which includes the size specification, interrupted by the memory chip 3 midway through.

[0078] The receiving unit 31 of the memory chip 3 checks the identification information of the memory chip 3 contained in the SCT packet PK21. If the identification information of the memory chip 3 contained in the SCT packet PK21 matches its own identification information, the receiving unit 31 receives the SCT packet PK21 via the command address bus CA_bus.

[0079] The control unit 34 waits until packet PK21 is received, and when packet PK21 is received by the receiving unit 31, it passes packet PK21 to the packet decoder 33.

[0080] The packet decoder 33 decodes packet PK21, extracts a transmission completion instruction from packet PK1, and passes it to the transmission unit 32 via the control unit 34.

[0081] In response to the instruction to complete the transfer, the transmitting unit 32 stops the transmission of data DT to the data bus DQ_bus midway through.

[0082] The communication method differs from the first embodiment in the following respects, as shown in Figure 7. Figure 7 is a diagram illustrating the communication method according to the second embodiment. In Figure 7, the horizontal axis represents time. Figure 7(a) shows the sequence of packets transferred on the command address bus CA_bus. Figure 7(b) shows the sequence of data transferred on the data bus DQ_bus.

[0083] At timings t1 to t5, the same operations as in the first embodiment are performed, and then at timing t31, an SCT packet PK21 containing the identification information "LUN0" for memory chip 3_LUN0 and an instruction to complete the transfer is sent from controller 2 to the command address bus CA_bus. Subsequently, the SCT packet PK21 is received by memory chip 3_LUN0.

[0084] In response, the transmission of data DT1 from memory chip 3_LUN0 to data bus DQ_bus is interrupted midway.

[0085] At timing t32, the data bus DQ_bus is released by memory chip 3_LUN0. This makes the other memory chips 3_LUN1 to 3_LUN3 able to use the data bus DQ_bus.

[0086] At timing t7, SCE packet PK14, containing the identification information "LUN1" for memory chip 3_LUN1 and an instruction to start the transfer, is sent from controller 2 to the command address bus CA_bus. Subsequently, SCE packet PK14 is received by memory chip 3_LUN1.

[0087] Subsequently, from timing t8 onward, the same operation as in the first embodiment is performed.

[0088] As described above, in the second embodiment, in the communication method, the controller 2 can issue and transmit a packet PK21 containing the identification information of the memory chip 3 and an instruction to terminate the transfer, and the memory chip 3 can receive and recognize it. This makes it possible to interrupt the transfer of data of a specified size midway and cause the memory chip 3 to release the data bus.

[0089] (Third embodiment) Next, a description of the memory system 1 according to the third embodiment will be given. The following description will focus on the differences from the first and second embodiments.

[0090] In the first and second embodiments, the transmission and reception of packets including identification information and size specification of memory chip 3 are illustrated, while in the third embodiment, the transmission and reception of packets including specification of all memory chips and size specification are illustrated.

[0091] The packet issuing unit 24 of the controller 2 shown in Figure 2 may issue packet PK4 which includes the specification of all memory chips and the specification of size DS1. The packet issuing unit 24 may also issue a "Pre-defined Trans Num ALL LUN" packet as packet PK4 which includes the specification of all memory chips and the specification of size DS1. The "Pre-defined Trans Num ALL LUN" packet is a packet that is not in the SCA protocol, but it may be newly defined and pre-configured in the packet issuing unit 24.

[0092] When packet PK4 is issued by packet issuing unit 24, control unit 23 waits until it is time to send packet PK4. When it is time to send packet PK4, control unit 23 supplies packet PK4 to transmission unit 21.

[0093] The transmitting unit 21 sends packet PK4 to the command address bus CA_bus. This allows the controller 2 to notify all memory chips 3 in advance of the size (e.g., the number of bytes to be transferred).

[0094] The receiving unit 31 of memory chip 3 checks the designation of all memory chips included in packet PK4. Depending on the designation of all memory chips, the receiving unit 31 receives packet PK4 via the command address bus CA_bus.

[0095] The control unit 34 waits until packet PK4 is received, and when packet PK4 is received by the receiving unit 31, it passes packet PK4 to the packet decoder 33.

[0096] The packet decoder 33 decodes packet PK4 and extracts the specification of all memory chips and the size specification from packet PK4. The packet decoder 33 may also decode the "Pre-defined Trans Num ALL LUN" packet and extract the specification of all memory chips and the size specification from the "Pre-defined Trans Num ALL LUN" packet. The "Pre-defined Trans Num" packet is not a packet in the SCA protocol, but it may be newly defined and pre-configured in the packet decoder 33. The packet decoder 33 passes the specification of all memory chips and the size specification as the decoding result to the control unit 34.

[0097] The control unit 34 reads data DT of the specified size from the memory cell array 35 and waits until it is time to transmit the data. When it is time to transmit the data, it passes the read data to the transmission unit 32 and notifies the transmission unit 32 of the specified size.

[0098] The transmitting unit 32 sends data DT of the specified size to the data bus DQ_bus.

[0099] The communication method differs from the first embodiment in the following respects, as shown in Figures 8 and 9. Figures 8 and 9 are diagrams illustrating the communication method according to the third embodiment, respectively. In Figures 8 and 9, the horizontal axis represents time. Figures 8(a) and 9(a) show the sequence of packets transferred on the command address bus CA_bus, respectively. Figures 8(b) and 9(b) show the sequence of data transferred on the data bus DQ_bus, respectively.

[0100] At timing t41, a "Pre-defined Trans Num ALL LUN" packet PK4, which includes the specification of all memory chips "ALL LUN" and the size DS1 specification, is sent from controller 2 to the command address bus CA_bus. Subsequently, the "Pre-defined Trans Num ALL LUN" packet PK4 is received by memory chips 3_LUN0 to 3_LUN3, respectively.

[0101] At timings t2 to t3, the same operation as in the first embodiment is performed.

[0102] At timing t42, in response to SCE packet PK12, which contains the identification information "LUN0" for memory chip 3_LUN0 and an instruction to start the transfer, data DT1 of size DS1 specified in packet PK4 begins to be sent from memory chip 3_LUN0 to the data bus DQ_bus.

[0103] At timings t5 to t7, the same operation as in the first embodiment is performed.

[0104] At timing t43, in response to SCE packet PK14, which contains the identification information "LUN1" for memory chip 3_LUN1 and an instruction to start the transfer, data DT5 of size DS1 specified in packet PK4 begins to be sent from memory chip 3_LUN1 to the data bus DQ_bus.

[0105] At timing t44, the "DQ Related LUN2" packet PK22, which contains the identification information "LUN2" for memory chip 3_LUN2 and a transfer instruction, is sent from controller 2 to the command address bus CA_bus. Subsequently, the "DQ Related LUN2" packet PK22 is received by memory chip 3_LUN2.

[0106] At timing t45, SCE packet PK23, containing the identification information "LUN2" for memory chip 3_LUN2 and an instruction to start the transfer, is sent from controller 2 to the command address bus CA_bus. Subsequently, SCE packet PK23 is received by memory chip 3_LUN2.

[0107] At timing t46, data DT6 of size DS1, specified in packet PK4, begins to be sent from memory chip 3_LUN2 to data bus DQ_bus.

[0108] At timing t47, the "DQ Related LUN3" packet PK24, which contains the identification information "LUN3" for memory chip 3_LUN3 and a transfer instruction, is sent from controller 2 to the command address bus CA_bus. Subsequently, the "DQ Related LUN3" packet PK22 is received by memory chip 3_LUN3.

[0109] At timing t48, the size of data DT6 reaches DS1, and the transmission of data DT6 from memory chip 3_LUN2 to command address bus CA_bus is completed.

[0110] At timing t49, upon completion of the transmission of data DT6, the data bus DQ_bus is released by memory chip 3_LUN2. This makes the other memory chips 3_LUN0, 3_LUN1, and 3_LUN3 able to use the data bus DQ_bus.

[0111] Accordingly, SCE packet PK25, containing the identification information "LUN3" for memory chip 3_LUN3 and an instruction to start the transfer, is sent from controller 2 to the command address bus CA_bus. Subsequently, SCE packet PK25 is received by memory chip 3_LUN3.

[0112] At timing t50, data DT6 of size DS1, specified in packet PK4, begins to be sent from memory chip 3_LUN3 to data bus DQ_bus.

[0113] At timing t51, the size of data DT7 reaches DS1, and the transmission of data DT7 from memory chip 3_LUN3 to command address bus CA_bus is completed.

[0114] At timing t52, upon completion of the transmission of data DT7, the data bus DQ_bus is released by memory chip 3_LUN3. This makes the other memory chips 3_LUN0 to 3_LUN2 able to use the data bus DQ_bus.

[0115] At timing t53, the "Pre-defined Trans Num ALL LUN0 size0" packet PK3b, which includes the specification "ALL LUN" for all memory chips and the specification of size "0", is sent from controller 2 to the command address bus CA_bus. Subsequently, the "Pre-defined Trans Num ALL LUN0 size0" packet PK3b is received by memory chips 3_LUN0 to 3_LUN3, respectively. This terminates the continued application of the "Pre-defined Trans Num ALL LUN" packet PK4 in each of the memory chips 3_LUN0 to 3_LUN3.

[0116] As described above, in the third embodiment, the controller 2 can issue and transmit a packet PK4 that includes the designation of all memory chips 3 and the size of the packet, and each memory chip 3 can receive and recognize it. This allows each memory chip 3 to sequentially transmit data of the specified size to the data bus, and each memory chip 3 to release the data bus after completing the transmission. In other words, since each memory chip 3 that receives the packet PK4 can release the data bus without the transmission or reception of SCT packets, which are recommended as a transfer completion notification in the SCA protocol, the degradation of transfer performance due to the SCT issuance time can be suppressed. That is, data transfer from the memory chips 3 to the data bus can be performed efficiently.

[0117] (Fourth embodiment) Next, we will describe the memory system 1 according to the fourth embodiment. Below, we will focus on the differences from the first to third embodiments.

[0118] In the third embodiment, the sending and receiving of packets including the specification of all memory chips and the specification of their size, and the data transfer using those packets are illustrated, while in the fourth embodiment, the cancellation of such data transfer is illustrated.

[0119] The packet issuing unit 24 of the controller 2 shown in Figure 2 may issue an SCT packet PK26 containing the identification information of a specific memory chip 3 and an instruction to terminate the transfer if it wants to interrupt the data transfer by packet PK4, which includes the specification of all memory chips and the size DS1, for a specific memory chip 3.

[0120] When the SCT packet PK26 is issued by the packet issuing unit 24, the control unit 23 waits until it is time to send the SCT packet PK26. When it is time to send the SCT packet PK26, the control unit 23 supplies the SCT packet PK26 to the transmitting unit 21.

[0121] The transmitting unit 21 sends SCT packet PK26 to the command address bus CA_bus. This allows the controller 2 to have the data transfer by packet PK4, which includes the specification of all memory chips and the size DS1, interrupted by a specific memory chip 3 midway through.

[0122] The receiving unit 31 of the memory chip 3 checks the identification information of the memory chip 3 contained in the SCT packet PK26. If the identification information of the memory chip 3 contained in the SCT packet PK26 matches its own identification information, the receiving unit 31 receives the SCT packet PK26 via the command address bus CA_bus.

[0123] The control unit 34 waits until the SCT packet PK26 is received, and when the receiving unit 31 receives the SCT packet PK26, it passes the SCT packet PK26 to the packet decoder 33.

[0124] The packet decoder 33 decodes the SCT packet PK26, extracts the instruction to complete the transfer from the SCT packet PK26, and passes it to the transmission unit 32 via the control unit 34.

[0125] In response to the instruction to complete the transfer, the transmitting unit 32 stops the transmission of data DT to the data bus DQ_bus midway through.

[0126] The communication method differs from the third embodiment in the following respects, as shown in Figure 10. Figure 10 is a diagram illustrating the communication method according to the fourth embodiment. In Figure 10, the horizontal axis represents time. Figure 10(a) shows the sequence of packets transferred on the command address bus CA_bus. Figure 10(b) shows the sequence of data transferred on the data bus DQ_bus.

[0127] At timings t41 to t5, the same operations as in the third embodiment are performed, and then at timing t61, SCT packet PK26 containing the identification information "LUN0" for memory chip 3_LUN0 and an instruction to complete the transfer is sent from controller 2 to command address bus CA_bus. Subsequently, SCT packet PK26 is received by memory chip 3_LUN0.

[0128] In response, the transmission of data DT1 from memory chip 3_LUN0 to data bus DQ_bus is interrupted midway.

[0129] At timing t62, the data bus DQ_bus is released by memory chip 3_LUN0. This makes the other memory chips 3_LUN1 to 3_LUN3 able to use the data bus DQ_bus.

[0130] At timing t43, in response to SCE packet PK14, which contains the identification information "LUN1" for memory chip 3_LUN1 and an instruction to start the transfer, data DT5 of size DS1 specified in packet PK4 begins to be sent from memory chip 3_LUN1 to the data bus DQ_bus.

[0131] Subsequently, from timing t44 onward, the same operation as in the third embodiment is performed.

[0132] As described above, in the fourth embodiment, in the communication method, the controller 2 can issue and transmit a packet PK26 containing the identification information of the memory chip 3 and an instruction to terminate the transfer, and the memory chip 3 can receive and recognize it. This makes it possible to interrupt the transfer of data of the size specified by packet PK4, which includes the designation of all memory chips 3 and the size specification, for a specific memory chip 3, causing that memory chip 3 to release the data bus.

[0133] (Fifth embodiment) Next, we will describe the memory system 1 according to the fifth embodiment. Below, we will focus on the differences from the first to fourth embodiments.

[0134] The first to fourth embodiments illustrate the initiation of data transfer by the memory chip 3 in response to an SCE packet, while the fifth embodiment illustrates the initiation of data transfer by the memory chip 3 in response to a notification from a signal line.

[0135] The channel CH shown in Figure 2 may further include a ready busy signal line Rd / Bsy in addition to the command address bus CA_bus, clock line CA_CLK, data bus DQ_bus, and read enable line RE￣ / RE. The ready busy signal line Rd / Bsy is used to transmit the ready busy signal, which is a signal that indicates the access status of the memory chip 3.

[0136] The ready-busy signal lines Rd / Bsy could also be assigned to be used to notify the completion of data transfer from memory chip 3, instead of notifying the access status of memory chip 3.

[0137] The packet issuing unit 24 of controller 2 may issue packet PK5 which includes a specification for assigning the ready busy signal lines Rd / Bsy to transfer completion notification. The packet issuing unit 24 may also issue a "Next Trigger" packet as packet PK5 which includes a specification for assigning the ready busy signal lines Rd / Bsy to transfer completion notification. The "Next Trigger" packet is not a packet in the SCA protocol, but it may be newly defined and pre-configured in the packet issuing unit 24.

[0138] When packet PK5 is issued by packet issuing unit 24, control unit 23 waits until it is time to send packet PK5. When it is time to send packet PK5, control unit 23 supplies packet PK5 to transmission unit 21.

[0139] The transmitting unit 21 sends packet PK5 to the command address bus CA_bus. This allows the controller 2 to notify each memory chip 3 to send a Next Trigger signal, which is a signal indicating the completion of data transfer, to the ready busy signal lines Rd / Bsy.

[0140] The receiving unit 31 of the memory chip 3 confirms that packet PK5 does not contain the identification information of the memory chip or the designation of all memory chips. Accordingly, the receiving unit 31 receives packet PK5 via the command address bus CA_bus.

[0141] The control unit 34 waits until packet PK5 is received, and when packet PK5 is received by the receiving unit 31, it passes packet PK5 to the packet decoder 33.

[0142] The packet decoder 33 decodes packet PK5 and extracts the assignment specification for the ready busy signal line Rd / Bsy to transfer completion notification from packet PK5. The packet decoder 33 may also decode the "Next Trigger" packet and extract the assignment specification for the ready busy signal line Rd / Bsy to transfer completion notification from the "Next Trigger" packet. The "Next Trigger" packet is not a packet in the SCA protocol, but it may be newly defined and pre-configured in the packet decoder 33. The packet decoder 33 passes the assignment specification for the ready busy signal line Rd / Bsy to transfer completion notification as the decoding result to the control unit 34.

[0143] The control unit 34 generates an active-level Next Trigger signal and passes it to the transmission unit 32 upon completion of data transfer, in accordance with the assignment of the ready busy signal line Rd / Bsy to the transfer completion notification.

[0144] The transmitter 32 sends an active-level Next Trigger signal to the ready-busy signal lines Rd / Bsy. This allows other memory chips 3 to be notified that data transfer by memory chip 3 has been completed.

[0145] The communication method differs from the first embodiment in the following respects, as shown in Figure 11. Figure 11 is a diagram showing the communication method according to the fifth embodiment. In Figure 11, the horizontal axis represents time. Figure 11(a) shows the sequence of packets transferred on the command address bus CA_bus. Figure 11(b) shows the sequence of data transferred on the data bus DQ_bus. Figure 11(c) shows the sequence of Next Trigger signals transferred on the ready busy signal lines Rd / Bsy.

[0146] At timing t71, a "Next Trigger" packet PK5, which specifies the assignment of the ready busy signal lines Rd / Bsy for transfer completion notification, is sent from controller 2 to the command address bus CA_bus. Subsequently, the "Next Trigger" packet PK5 is received by each memory chip 3_LUN0 to 3_LUN3.

[0147] At timings t1 to t6, the same operations as in the first embodiment are performed, and then at timing t72, the data bus DQ_bus is released by memory chip 3_LUN0 in response to the completion of the transmission of data DT1. This makes the other memory chips 3_LUN1 to 3_LUN3 able to use the data bus DQ_bus.

[0148] Simultaneously, the Next Trigger signal transitions from a non-active level to an active level, and the active-level Next Trigger signal is sent from memory chip 3_LUN0 to the ready-busy signal line Rd / Bsy.

[0149] At timing t73, the Next Trigger signal transitions from the active level to the inactive level, and the inactive level Next Trigger signal is sent from memory chip 3_LUN0 to the ready busy signal line Rd / Bsy.

[0150] At timing t74, the Next Trigger signal transitions from inactive level to active level and then back to inactive level, and the completion of data transfer by memory chip 3_LUN0 is recognized by memory chip 3_LUN1. In response, data DT2 of size DS2, specified in packet PK2, begins to be sent from memory chip 3_LUN1 to the data bus DQ_bus.

[0151] Simultaneously, a "Pre-defined Trans Num LUN2" packet PK2a, containing the identification information "LUN2" and the size specification DS2a for memory chip 3_LUN2, is sent from controller 2 to the command address bus CA_bus. Subsequently, the "Pre-defined Trans Num LUN2" packet PK2a is received by memory chip 3_LUN2.

[0152] At timing t75, a "DQ Related LUN2" packet PK13a containing the identification information "LUN2" for memory chip 3_LUN2 and a transfer instruction is sent from controller 2 to the command address bus CA_bus. Subsequently, the "DQ Related LUN2" packet PK13a is received by memory chip 3_LUN2.

[0153] At timing t10, the same operation as in the first embodiment is performed, and then at timing t76, the data bus DQ_bus is released by memory chip 3_LUN1 in response to the completion of the transmission of data DT2. This makes the other memory chips 3_LUN0, 3_LUN2, and 3_LUN3 able to use the data bus DQ_bus.

[0154] Simultaneously, the Next Trigger signal transitions from a non-active level to an active level, and the active-level Next Trigger signal is sent from memory chip 3_LUN1 to the ready-busy signal line Rd / Bsy.

[0155] At timing t77, the Next Trigger signal transitions from the active level to the inactive level, and the inactive level Next Trigger signal is sent from memory chip 3_LUN1 to the ready busy signal line Rd / Bsy.

[0156] At timing t78, the Next Trigger signal transitions from inactive level to active level and then back to inactive level, and the completion of data transfer by memory chip 3_LUN1 is recognized by memory chip 3_LUN2. In response, data DT2a of size DS2a, specified in packet PK2a, begins to be sent from memory chip 3_LUN2 to the data bus DQ_bus.

[0157] Simultaneously, a "Pre-defined Trans Num LUN3" packet PK2b, containing the identification information "LUN3" and the size specification DS4 for memory chip 3_LUN3, is sent from controller 2 to the command address bus CA_bus. Subsequently, the "Pre-defined Trans Num LUN3" packet PK2b is received by memory chip 3_LUN3.

[0158] At timing t79, the "DQ Related LUN3" packet PK13b, which contains the identification information "LUN3" for memory chip 3_LUN3 and a transfer instruction, is sent from controller 2 to the command address bus CA_bus. Subsequently, the "DQ Related LUN3" packet PK13b is received by memory chip 3_LUN3.

[0159] At timing t80, the size of data DT2a reaches DS2a, and the transmission of data DT2a from memory chip 3_LUN2 to data bus DQ_bus is completed.

[0160] At timing t81, upon completion of the transmission of data DT2a, the data bus DQ_bus is released by memory chip 3_LUN2. This makes the other memory chips 3_LUN0, 3_LUN1, and 3_LUN3 able to use the data bus DQ_bus.

[0161] Simultaneously, the Next Trigger signal transitions from a non-active level to an active level, and the active-level Next Trigger signal is sent from memory chip 3_LUN2 to the ready-busy signal line Rd / Bsy.

[0162] At timing t82, the Next Trigger signal transitions from the active level to the inactive level, and the inactive level Next Trigger signal is sent from memory chip 3_LUN2 to the ready busy signal line Rd / Bsy.

[0163] At timing t83, the Next Trigger signal transitions from inactive level to active level and then back to inactive level, and the completion of data transfer by memory chip 3_LUN2 is recognized by memory chip 3_LUN3. In response, data DT2b of size DS2b, specified in packet PK2b, begins to be sent from memory chip 3_LUN3 to the data bus DQ_bus.

[0164] As described above, in the fifth embodiment, in the communication method, the controller 2 can issue and transmit packet PK5, which includes the assignment of the ready busy signal lines Rd / Bsy for transfer completion notification, and each memory chip 3 can receive and recognize it. This allows each memory chip 3 to be notified to send a Next Trigger signal, which is a signal that notifies the completion of data transfer, to the ready busy signal lines Rd / Bsy. In other words, each memory chip 3 that receives packets PK1, PK2, PK2a, and PK2b can start data transfer without the transmission and reception of SCE packets, which are recommended in the SCA protocol as a specification for the start of transfer, thus suppressing the degradation of transfer performance due to the time it takes to issue SCE packets. In other words, data transfer from the memory chip 3 to the data bus can be performed more efficiently.

[0165] (Sixth embodiment) Next, we will describe the memory system 1 according to the sixth embodiment. Below, we will focus on the differences from the first to fifth embodiments.

[0166] The fifth embodiment illustrates the initiation of data transfer for individual memory chips 3 in response to an SCE packet, while the sixth embodiment illustrates the initiation of data transfer for all memory chips 3 in response to a notification from a signal line.

[0167] The communication method differs from the fifth embodiment in the following respects, as shown in Figure 12. Figure 12 is a diagram showing the communication method according to the sixth embodiment. In Figure 12, the horizontal axis represents time. Figure 12(a) shows the sequence of packets transferred on the command address bus CA_bus. Figure 12(b) shows the sequence of data transferred on the data bus DQ_bus. Figure 12(c) shows the sequence of Next Trigger signals transferred on the ready busy signal lines Rd / Bsy.

[0168] At timing t71, a "Next Trigger" packet PK5, which specifies the assignment of the ready busy signal lines Rd / Bsy for transfer completion notification, is sent from controller 2 to the command address bus CA_bus. Subsequently, the "Next Trigger" packet PK5 is received by each memory chip 3_LUN0 to 3_LUN3.

[0169] At timing t41, a "Pre-defined Trans Num ALL LUN" packet PK4, which includes the specification of all memory chips "ALL LUN" and the size DS1 specification, is sent from controller 2 to the command address bus CA_bus. Subsequently, the "Pre-defined Trans Num ALL LUN" packet PK4 is received by memory chips 3_LUN0 to 3_LUN3, respectively.

[0170] From timing t2 onward, packets PK2, PK2a, and PK2b are not sent to the command address bus CA_bus, and the operation is the same as in the fifth embodiment, except that the sizes of data DT1, DT2, DT2a, and DT2b are the same.

[0171] As described above, in the sixth embodiment, in the communication method, the controller 2 can issue and transmit packet PK5, which includes the assignment of the ready busy signal lines Rd / Bsy for transfer completion notification, and each memory chip 3 can receive and recognize it. This allows each memory chip 3 to be notified to send a Next Trigger signal, which is a signal that notifies the completion of data transfer, to the ready busy signal lines Rd / Bsy. In other words, each memory chip 3, which is the recipient of packet PK4, can sequentially start data transfer without the transmission and reception of SCE packets, which are recommended as a specification for the start of transfer in the SCA protocol, thus suppressing the degradation of transfer performance due to the time it takes to issue SCE packets. In other words, data transfer from the memory chip 3 to the data bus can be performed more efficiently.

[0172] (Seventh Embodiment) Next, we will describe the memory system 1 according to the seventh embodiment. Below, we will focus on the differences from the first to sixth embodiments.

[0173] The first to sixth embodiments illustrate the operation in which the size specification by packet PK1 is continuously applied, while the seventh embodiment illustrates the operation in which a different size specification is made as an interrupt to that continuous application.

[0174] The packet issuing unit 24 of the controller 2 shown in Figure 2 may issue packet PK6 which includes the identification information of the memory chip 3 and the size specification via interrupt. The packet issuing unit 24 may also issue an "OverRide Pre-defined Trans Num" packet as packet PK6 which includes the identification information of the memory chip 3 and the size specification via interrupt. The "OverRide Pre-defined Trans Num" packet is not a packet in the SCA protocol, but it may be newly defined and pre-configured in the packet issuing unit 24. The number of interrupts may be as few as one. This packet may be used when it is desired to temporarily set a different transfer size when a random access for a file system update occurs during sequential access with a set transfer size.

[0175] When packet PK6 is issued by packet issuing unit 24, control unit 23 waits until it is time to send packet PK6. When it is time to send packet PK6, control unit 23 supplies packet PK6 to transmission unit 21.

[0176] The transmitting unit 21 sends packet PK6 to the command address bus CA_bus. This allows the controller 2 to notify the memory chip 3 of a size different from the specified size of packet PK1 (for example, the number of bytes transferred).

[0177] The receiving unit 31 of the memory chip 3 checks the identification information of the memory chip 3 contained in packet PK6. If the identification information of the memory chip 3 contained in packet PK1 matches its own identification information, the receiving unit 31 receives packet PK6 via the command address bus CA_bus.

[0178] The control unit 34 waits until packet PK6 is received, and when packet PK6 is received by the receiving unit 31, it passes packet PK6 to the packet decoder 33.

[0179] The packet decoder 33 decodes packet PK6 and extracts the size specification from packet PK6 via an interrupt. The packet decoder 33 may also decode the "OverRide Pre-defined Trans Num" packet and extract the size specification from the "OverRide Pre-defined Trans Num" packet via an interrupt. The "OverRide Pre-defined Trans Num" packet is not a packet in the SCA protocol, but it may be newly defined and pre-configured in the packet decoder 33. The packet decoder 33 passes the size specification from the interrupt as the decoding result to the control unit 34.

[0180] The control unit 34 reads data DT of the size specified by the interrupt from the memory cell array 35 and waits until it is time to send the data. When it is time to send the data, it passes the read data to the transmission unit 32 and notifies the transmission unit 32 of the size specification given by the interrupt.

[0181] The transmitter 32 sends data DT of the size specified by the interrupt to the data bus DQ_bus.

[0182] Subsequently, the size specification via interrupt in the control unit 34 and the transmission unit 32 is released, and the continued application of the size specification by packet PK1 is resumed.

[0183] The communication method differs from the first embodiment in the following respects, as shown in Figures 13 and 14. Figures 13 and 14 are diagrams illustrating the communication method according to the seventh embodiment, respectively. In Figures 13 and 14, the horizontal axis represents time. Figures 13(a) and 14(a) show the sequence of packets transferred on the command address bus CA_bus, respectively. Figures 13(b) and 14(b) show the sequence of data transferred on the data bus DQ_bus.

[0184] After the same operations as in the first embodiment are performed at timings t1 to t7, at timing t91, an "OverRide Pre-defined Trans Num" packet PK6 containing the identification information "LUN0" for memory chip 3_LUN0 and the size DS11 specification in the interrupt is sent from controller 2 to the command address bus CA_bus. The size DS11 is different from the size DS1 specified in packet PK1. Subsequently, the "OverRide Pre-defined Trans Num" packet PK6 is received by memory chip 3_LUN0.

[0185] At the same time, data DT2 of size DS2, specified in packet PK2, begins to be sent from memory chip 3_LUN1 to data bus DQ_bus.

[0186] After the same operation as in the first embodiment is performed at timings t9 to t12, at timing t92, an "OverRide Pre-defined Trans Num" packet PK6a containing the identification information "LUN1" for memory chip 3_LUN1 and the size DS12 specification in the interrupt is sent from controller 2 to the command address bus CA_bus. Subsequently, the "OverRide Pre-defined Trans Num" packet PK6a is received by memory chip 3_LUN1.

[0187] At the same time, the data DT8 of size DS11, which was specified as an interrupt in packet PK6, begins to be sent from memory chip 3_LUN0 to data bus DQ_bus.

[0188] At timing t14, the same operation as in the first embodiment is performed, and then at timing t93, the size of data DT8 reaches DS11, and the transmission of data DT8 from memory chip 3_LUN0 to command address bus CA_bus is completed.

[0189] At timing t16, the same operation as in the first embodiment is performed, and then at timing t94, data DT9 of size DS12, specified by the interrupt in packet PK6a, begins to be sent from memory chip 3_LUN1 to data bus DQ_bus.

[0190] At timing t95, the size of data DT9 reaches DS12, and the transmission of data DT9 from memory chip 3_LUN1 to command address bus CA_bus is completed.

[0191] As described above, in the seventh embodiment, in the communication method, the controller 2 can issue and transmit a packet PK6 that includes the identification information of the memory chip 3 and the size specification in the interrupt, and the memory chip 3 can receive and recognize it. This makes it possible to temporarily transfer data of the size specified by the interrupt in packet PK6 while the data transfer of the size specified in packet PK1 is continuously being applied. This improves the flexibility of size specification in data transfer.

[0192] (Eighth embodiment) Next, we will describe the memory system 1j according to the eighth embodiment. Below, we will focus on the differences from the first to seventh embodiments.

[0193] The first to seventh embodiments illustrate how the size can be specified using packet PK1, while the eighth embodiment illustrates how the size can be specified via setting a feature register in the memory chip 3j.

[0194] In the memory system 1j, each memory chip 3j may further have a feature register 36j, as shown in Figure 15. The feature register 36j is configured to allow setting of parameters for specifying the size of the data.

[0195] The packet issuing unit 24j of the controller 2j issues packet PK7, which includes identification information for the memory chip 3j and a specification for storing the size parameter in the feature register 36j. The packet issuing unit 24j may also issue a "Set Feature" command packet as packet PK7. The "Set Feature" command packet is defined in the SCA protocol to be sent by specifying the Set Feature command as an argument within the packet when sending a command packet.

[0196] The "Set Feature" command packet can be issued to release the data bus DQ_bus after the recipient has transferred data of the size specified by the size parameter, by specifying the storage of the size parameter. The size parameter set in feature register 36j is applied continuously at the recipient after being issued once. The "Set Feature" command packet can also be issued to terminate this continuous application at the recipient by including a specification for storing a zero-size size parameter.

[0197] When packet PK7 is issued by packet issuing unit 24j, control unit 23 waits until it is time to send packet PK7. When it is time to send packet PK7, control unit 23 supplies packet PK7 to transmission unit 21.

[0198] The transmitting unit 21 sends packet PK7 to the command address bus CA_bus. This allows the controller 2j to instruct the memory chip 3j to store the size parameter (e.g., the number of bytes to be transferred) in advance.

[0199] The receiving unit 31 checks the identification information of the memory chip 3j contained in packet PK7. If the identification information of the memory chip 3j contained in packet PK7 matches its own identification information, the receiving unit 31 receives packet PK7 via the command address bus CA_bus.

[0200] The control unit 34 waits until packet PK7 is received, and when packet PK7 is received by the receiving unit 31, it passes packet PK7 to the packet decoder 33j.

[0201] The packet decoder 33j decodes packet PK7 and extracts the specification for storing the size parameter from packet PK7. The packet decoder 33j may also decode the "Set Feature" command packet and extract the specification for storing the size parameter from the "Set Feature" command packet. The "Set Feature" command packet is not a packet in the SCA protocol, but it may be newly defined and pre-configured in the packet decoder 33j. The packet decoder 33j passes the specification for storing the size parameter as the decoding result to the control unit 34.

[0202] The control unit 34 accesses the feature register 36j and sets the specified size parameter in the feature register 36j. The control unit 34 reads the data DT of the size specified by the size parameter from the memory cell array 35, passes the read data to the transmission unit 32, and notifies the transmission unit 32 of the size specification based on the size parameter.

[0203] The transmitting unit 32 sends data DT of the size specified by the size parameter to the data bus DQ_bus.

[0204] The communication method differs from the first embodiment in the following respects, as shown in Figures 16 and 17. Figures 16 and 17 are diagrams illustrating the communication method according to the eighth embodiment, respectively. In Figures 16 and 17, the horizontal axis represents time. Figures 16(a) and 17(a) show the sequence of packets transferred on the command address bus CA_bus, respectively. Figures 16(b) and 17(b) show the sequence of data transferred on the data bus DQ_bus.

[0205] At timing t101, a "Set Feature" command packet PK7 containing the identification information "LUN0" for memory chip 3j_LUN0 and a specification for storing a size parameter indicating size DS1 is sent from controller 2j to the command address bus CA_bus. Subsequently, the "Set Feature" command packet PK7 is received by memory chip 3j_LUN0, and the size parameter indicating size DS1 is stored in the feature register 36j of memory chip 3j_LUN0.

[0206] After the same operation as in the first embodiment is performed at timings t2 to t3, at timing t102, data DT1 of size DS1, specified by the size parameter of feature register 36j, begins to be sent from memory chip 3j_LUN0 to data bus DQ_bus.

[0207] Simultaneously, a "Set Feature" command packet PK7a, containing the identification information "LUN1" for memory chip 3j_LUN1 and a specification for storing a size parameter indicating size DS2, is sent from controller 2j to the command address bus CA_bus. Subsequently, the "Set Feature" command packet PK7a is received by memory chip 3j_LUN1, and the size parameter indicating size DS2 is stored in the feature register 36j of memory chip 3j_LUN1.

[0208] After the same operations as in the first embodiment are performed at timings t5 to t19, at timing t103, a "Set Feature" command packet PK3j, which includes the identification information "LUN0" for memory chip 3j_LUN0 and the specification of storing a size parameter indicating size "0", is sent from controller 2j to the command address bus CA_bus. Subsequently, the "Set Feature" command packet PK3j is received by memory chip 3j_LUN0. This terminates the continued application of the size parameter of feature register 36j in memory chip 3j_LUN0.

[0209] At timing t104, a "Set Feature" command packet PK3ja containing the identification information "LUN1" for memory chip 3j_LUN1 and a size parameter indicating size "0" is sent from controller 2j to the command address bus CA_bus. Subsequently, the "Set Feature" command packet PK3ja is received by memory chip 3j_LUN1. This terminates the continued application of the size parameter to feature register 36j in memory chip 3j_LUN1.

[0210] As described above, in the eighth embodiment, in the communication method, the controller 2j can issue and transmit a packet PK7 that includes identification information of the memory chip 3j and a specification for storing the size parameter, and the memory chip 3j can receive and recognize it. This allows the memory chip 3j, which has sent data of the size specified by the size parameter to the data bus, to release the data bus after transmission is complete. In other words, the memory chip 3j that receives packet PK7 can release the data bus without sending or receiving an SCT packet, which is recommended as a transfer completion notification in the SCA protocol, thus suppressing the degradation of transfer performance due to the time it takes to issue the SCT. That is, data transfer from the memory chip 3 to the data bus can be performed efficiently.

[0211] The packet issuing unit 24j of the controller 2j may issue packet PK107 which includes the specification of all memory chips and the specification of storing the size parameter in the feature register 36j. The packet issuing unit 24j may also issue a "Set Feature" command packet as packet PK107 which includes the specification of all memory chips and the specification of storing the size parameter in the feature register 36j.

[0212] Alternatively, the feature register 36j of each memory chip 3j may be configured to allow setting of a parameter indicating the assignment of the ready-busy signal line Rd / Bsy for transfer completion notification.

[0213] The packet issuing unit 24j of controller 2j may issue packet PK207 which includes a specification for storing parameters indicating the assignment of the ready busy signal lines Rd / Bsy for transfer completion notification. The packet issuing unit 24j may also issue a "Set Feature" command packet as packet PK207 which includes a specification for storing parameters indicating the assignment of the ready busy signal lines Rd / Bsy for transfer completion notification in the feature register 36j.

[0214] Alternatively, the feature register 36j of each memory chip 3j may be configured to allow setting a size parameter that indicates the size to be specified in an interrupt.

[0215] The packet issuing unit 24j of the controller 2j may issue packet PK307 which includes identification information for the memory chip 3j and a specification for storing a size parameter indicating the size specification in the interrupt. The packet issuing unit 24j may also issue a "Set Feature" command packet as packet PK307 which includes a specification for storing a size parameter indicating the size specification in the feature register 36j in the interrupt.

[0216] Alternatively, as a modification of the eighth embodiment, the memory system 1k may further include an interface chip 4k, as shown in Figure 18. Figure 18 shows the configuration of the memory system 1j according to a modification of the eighth embodiment.

[0217] Interface chip 4k has an additional feature register 46k compared to interface chip 4i (see Figure 6). Feature register 46k is configured similarly to the feature register 36j of each memory chip 3j.

[0218] The interface chip 4k forwards the "Set Feature" command packet from the controller 2j directly to the memory chip 3j. At that time, the control unit 45 of the interface chip 4k sets the size parameter specified in the "Set Feature" command packet to the feature register 46k. In all other respects, the communication method performed by the memory system 1k is the same as the communication method shown in Figures 3 and 4.

[0219] Even in such a memory system 1k, the controller 2j can issue and transmit a packet PK7 containing the identification information of the memory chip 3j and the storage specification of the size parameter, and the memory chip 3j can receive and recognize it. This allows the memory chip 3j, which has sent data of the size specified by the size parameter to the data bus, to release the data bus after the transmission is complete.

[0220] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0221] 1.1i, 1j, 1k system; 2.2j controller; 3.3j memory chip; 4.i, 4k interface chip.

Claims

1. A first packet containing the identification information of the first chip and the specification of the first size is transmitted from the controller to the first bus, In response to the first packet being received by the first chip, the first data of the first size becomes transferable from the first chip to the second bus, After the transfer of the first data is completed, the second bus is released. A communication method that includes this.

2. A second packet containing the identification information of the first chip and an instruction to terminate the transfer is transmitted from the controller to the first bus, In response to the second packet being received by the first chip during the transfer of the first size of data, the transfer of the first size of data by the first chip is interrupted. Includes The communication method according to claim 1.

3. A third packet containing the identification information of the first chip and a zero-size specification is transmitted from the controller to the first bus, In response to the third packet being received by the first chip, the continuous data transfer of the first size by the first chip on the second bus is terminated, Includes The communication method according to claim 1.

4. A fourth packet, including the specification of all chips and the specification of the first size, is transmitted from the controller to the first bus. As the fourth packet is received by each chip, the first data of the first size becomes sequentially transferable from each chip to the second bus, The second bus is released after the transfer is completed from each chip. The communication method according to claim 1.

5. A fifth packet, including the assignment of the first signal line for transfer completion notification, is transmitted from the controller to the first bus, In response to the fifth packet being received by the first chip, after the transfer of the first data is completed, the level of the first signal line of the first chip transitions to a level indicating a transfer completion notification. In response to a transition to a level indicating completion of the transfer of the first signal line, the second data is transferred from the second chip to the second bus. Includes The communication method according to claim 1.

6. A sixth packet, including the identification information of the first chip and the specification of the second size in the interrupt, is transmitted from the controller to the first bus. In response to the sixth packet being received by the first chip, a second data of the second size is transferred from the first chip to the second bus by interrupt, instead of the first size. After the transfer of the second data is completed, the specification of the second size in the interrupt is released, and the second bus is released. Includes The communication method according to claim 1.

7. A seventh packet, including the identification information of the first chip and a setting instruction to a feature register of the first size, is transmitted from the controller to the first bus. In response to the seventh packet being received by the first chip, the third data of the first size becomes transferable from the first chip to the second bus, After the transfer of the third data is completed, the second bus is released. Includes The communication method according to claim 1.

8. The aforementioned communication method is performed in accordance with the SCA protocol. The communication method according to claim 1.

9. A packet issuing unit that issues a first packet including identification information of a first chip and a specification of a first size, A transmitting unit that transmits the first packet to the first bus, A controller equipped with [a specific feature / feature].

10. The packet issuing unit further issues a second packet containing the identification information of the first chip and an instruction to terminate the transfer. The transmitting unit further transmits the second packet to the first bus. The controller according to claim 9.

11. The packet issuing unit further issues a third packet including the identification information of the first chip and a zero size specification. The transmitting unit further transmits the third packet to the first bus. The controller according to claim 9.

12. The packet issuing unit further issues a fourth packet which includes the specification of all chips and the specification of the first size. The transmitting unit further transmits the fourth packet to the first bus. The controller according to claim 9.

13. The packet issuing unit further issues a fifth packet which includes the identification information of the first chip and the assignment of the first signal line for transfer completion notification. The transmitting unit further transmits the fifth packet to the first bus. The controller according to claim 9.

14. The packet issuing unit further issues a seventh packet which includes the identification information of the first chip and a setting instruction to a feature register of the first size. The transmitting unit transmits the seventh packet to the first bus. The controller according to claim 9.

15. A receiving unit that receives a first packet containing chip identification information and a first size specification via a first bus, A transmitting unit transmits first data of the first size to a second bus in response to the reception of the first packet by the receiving unit, A chip equipped with a chip.

16. The receiving unit receives a second packet containing the chip's identification information and an instruction to terminate the transfer via the first bus. The transmitting unit, in response to the receiving unit receiving the first packet of data of the first size while it is being transmitted, interrupts the transmission of the data of the first size to the second bus. The chip according to claim 15.

17. The receiving unit receives a third packet containing the chip's identification information and a zero-size specification via the first bus. The transmitting unit terminates the continuous transmission of the first size data on the second bus in response to the third packet being received by the receiving unit. The chip according to claim 15.

18. The receiving unit receives a fourth packet via the first bus, which includes the specification of all chips and the specification of the first size. The transmitting unit transmits the first data of the first size to the second bus in response to the fourth packet being received by the receiving unit. The chip according to claim 15.

19. The receiving unit receives a fifth packet via the first bus, which includes the identification information of its own chip and a specification for assignment to the first signal line for transfer completion notification. The level of the first signal line transitions to a level indicating a transfer completion notification after the transmission of the first data by the transmitting unit is completed, in response to the fifth packet being received by the receiving unit. The chip according to claim 15.

20. The receiving unit receives a seventh packet via the first bus, which includes the identification information of its own chip and a setting instruction to the first size feature register. The transmitting unit transmits the third data of the first size to the second bus in response to the seventh packet being received by the receiving unit. The chip according to claim 15.

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