Electronic devices and methods for manufacturing electronic devices

Abstract

The present invention provides electronic devices and methods for manufacturing electronic devices. [Solution] The electronic device 100 comprises a connection substrate 10 on which a plurality of capacitor structures 12 are provided, an electronic element 20 provided above the connection substrate 10, and a connection wiring 32 connecting the electronic element 20 and the connection substrate 10. The plurality of capacitor structures 12 have at least one connected capacitor section 13 connected to the connection wiring 32 and at least one unconnected capacitor section 14 not connected to the connection wiring 32. The at least one unconnected capacitor section 14 may be a capacitor in a short-circuited or open state. The connection substrate 10 may be a first semiconductor wafer.

Description

Technical Field

[0001] The present invention relates to an electronic device and a method for manufacturing an electronic device.

Background Art

[0002] Patent Document 1 describes, "Provided is a trench capacitor and a method for manufacturing a trench capacitor capable of improving the yield." (Abstract) Patent Document 2 describes, "Provided is a capacitor component applicable to a decoupling capacitor corresponding to further high frequency of a semiconductor element." (Abstract) Patent Document 3 describes, "A method for detecting a mounting defect of a capacitor surely with ordinary inspection equipment with a small number of inspection man-hours." (Abstract) Patent Document 4 describes, "Surely inspect whether there is a connection defect or the like in a capacitor built in a substrate." (Abstract) Patent Document 5 describes, "Provided is an interposer type capacitor capable of sufficiently increasing the capacitance while sufficiently preventing a short circuit in a capacitor structure." (Abstract) [Prior Art Documents] [Patent Documents] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2020-136455 [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2006-185935 [Patent Document 3] Japanese Unexamined Patent Application Publication No. 2014-187127 [Patent Document 4] Japanese Unexamined Patent Application Publication No. 2014-112081 ​​​​​​​​​The device includes connecting wiring that connects electronic elements to a connecting substrate. Each of the multiple capacitor structures has at least one connected capacitor section connected to the connecting wiring and at least one unconnected capacitor section not connected to the connecting wiring.

[0004] The unconnected capacitor section may be a capacitor in a short-circuited or open-circuited state.

[0005] In any of the above electronic devices, the connecting substrate may be a first semiconductor wafer.

[0006] In any of the above electronic devices, the capacitor structure may be a trench structure provided from the top surface to the interior of the first semiconductor wafer.

[0007] In any of the above electronic devices, the connecting capacitor portion may include a first capacitor electrode provided on the inner wall of the trench structure. The first capacitor electrode may be in contact with the first semiconductor wafer.

[0008] In any of the above-described electronic devices, the first semiconductor wafer may be provided with an information section that includes region information indicating a region on the first semiconductor wafer, and capacitor information indicating the capacitor characteristics of at least one capacitor structure in the region.

[0009] Any of the above electronic devices may further comprise a second semiconductor wafer. The electronic elements may be provided on the second semiconductor wafer.

[0010] In any of the above electronic devices, the connecting substrate may have at least one first connecting electrode that covers the upper part of the connecting capacitor section and is connected to the connecting capacitor section, and at least one second connecting electrode that covers the upper part of the non-connecting capacitor section and is connected to the non-connecting capacitor section. The first connecting electrode may be connected to the connecting wiring. The second connecting electrode does not need to be connected to the connecting wiring.

[0011] Any of the above electronic devices may further include a circuit board provided below the connection board. The connection board may further include a plurality of through-via structures. The plurality of through-via structures may have at least one connecting through-via electrically connected to the circuit board and at least one non-connecting through-via not electrically connected to the circuit board.

[0012] In any of the above electronic devices, an unconnected through-via may be a through-via whose electrical resistance exceeds a resistance threshold. A connected through-via may be a through-via whose electrical resistance is less than or equal to a resistance threshold.

[0013] In any of the above electronic devices, the connection substrate may further have at least one third connection electrode that covers the lower part of the connection via and is connected to the connection via. The third connection electrode may be electrically connected to the circuit board.

[0014] In any of the above electronic devices, the through-connection via may be electrically connected to the first connecting electrode.

[0015] A second aspect of the present invention provides a method for manufacturing an electronic device. The method for manufacturing an electronic device comprises an electrical element formation step of forming a plurality of electrical elements on a connecting substrate made of semiconductor material, an evaluation step of evaluating the electrical characteristics of each of the plurality of electrical elements, and a wiring formation step of forming a connecting wire to connect to at least one of the plurality of electrical elements based on the evaluation results of the electrical characteristics.

[0016] The electrical element formation process may be a process of forming multiple electrical elements of the same structure, and forming more electrical elements than the number of electrical elements that should be connected to the connecting wiring. The wiring formation process may be a process of not forming connecting wiring on at least one of the multiple electrical elements, based on the results of the evaluation of electrical characteristics.

[0017] In any of the above methods for manufacturing electronic devices, the connecting substrate may be a first semiconductor wafer, and the electrical element may be a capacitor structure. The evaluation step may be a step of evaluating the capacitor characteristics of each of the multiple capacitor structures formed on the first semiconductor wafer in the electrical element formation step. The above method for manufacturing electronic devices may further include a classification step of classifying the multiple capacitor structures into connected capacitor parts that are connected to connecting wiring and unconnected capacitor parts that are not connected to connecting wiring, based on the evaluation results of the capacitor characteristics. The wiring formation step may be a step of forming connecting wiring based on the classification results of the classification step.

[0018] In any of the above methods for manufacturing electronic devices, the evaluation step may be a step of evaluating the characteristics of each capacitor while the capacitor structure is formed on the first semiconductor wafer.

[0019] In any of the above methods for manufacturing electronic devices, the wiring formation step may be a step in which connecting wiring is formed on the first semiconductor wafer based on the classification result of the classification step.

[0020] The manufacturing method for any of the above electronic devices may further include an electrode forming step of forming cover electrodes above each of the capacitor structural parts. The evaluation step may be a step of evaluating the capacitor characteristics of each of the multiple capacitor structural parts via the cover electrodes. The classification step may be a step of further classifying the cover electrodes, based on the evaluation results of the capacitor characteristics, into at least one first connecting electrode that covers the upper part of the connected capacitor part and connects to the connected capacitor, and at least one second connecting electrode that covers the upper part of the unconnected capacitor part and connects to the unconnected capacitor part.

[0021] In the method for manufacturing any of the above electronic devices, the connection substrate may be a first semiconductor wafer, and the electrical element may be a capacitor structure portion. The method for manufacturing any of the above electronic devices may further include a specifying step of specifying a group of capacitor structure portions having a capacitance value equal to or greater than a predetermined capacitance value and including at least one capacitor structure portion, based on the evaluation result of the capacitor characteristics in the capacitor structure portion. The wiring formation step may be a step of forming a connection wiring based on the specifying result of the specifying step.

[0022] The method for manufacturing any of the above electronic devices may further include an information portion forming step of forming an information portion including region information indicating a region in the first semiconductor wafer and capacitor information indicating the capacitor characteristics of at least one capacitor structure portion in the region, on the first semiconductor wafer.

[0023] In the method for manufacturing any of the above electronic devices, the evaluation step may include a step of maintaining each of the plurality of capacitor structure portions at a predetermined temperature or applying a predetermined voltage to each of the plurality of capacitor structure portions.

[0024] The method for manufacturing any of the above electronic devices may further include a photosensitive material forming step of forming a photosensitive material on the connection substrate after the electrical element forming step, and a via pattern forming step of forming a via pattern above the connection capacitor portion in the photosensitive material and not forming a via pattern above the non-connection capacitor portion. The wiring formation step may be a step of forming a connection wiring in the via pattern.

[0025] The method for manufacturing any of the above electronic devices may further include a liquid crystal layer forming step of forming a liquid crystal layer above the connection substrate after the electrical element forming step. The evaluation step may be a step of evaluating the electrical characteristics of each of the plurality of electrical elements by applying a voltage between the upper surface of the liquid crystal layer and the connection substrate. The method for manufacturing any of the above electronic devices may further include a liquid crystal layer removing step of removing the liquid crystal layer after the evaluation step and before the wiring formation step.

[0026] The manufacturing method of any of the above electronic devices may further include a second semiconductor wafer mounting step of mounting a second semiconductor wafer provided with electronic elements above the first semiconductor wafer after the wiring formation step.

[0027] Note that the above summary of the invention does not enumerate all the features of the present invention. Also, sub-combinations of these feature groups can also be inventions.

Brief Description of the Drawings

[0028] [Figure 1] It is a diagram showing an example of an electronic device 100 according to one embodiment of the present invention. [Figure 2] It is a diagram showing another example of an electronic device 100 according to one embodiment of the present invention. [Figure 3A] It is an enlarged view of an example of one capacitor structure portion 12 in FIG. 2. [Figure 3B] It is an enlarged view of another example of one capacitor structure portion 12 in FIG. 2. [Figure 4] It is a diagram showing an example in a top view of the upper surface of the first semiconductor wafer 60. [Figure 5] It is an enlarged view of one region 62 in FIG. 4. [Figure 6] It is a diagram showing an example of the cross section taken along the line A-A' of FIG. 5. [Figure 7] It is a diagram showing another example of an electronic device 100 according to one embodiment of the present invention. [Figure 8] It is a block diagram showing an example of an electronic device design system 200 according to one embodiment of the present invention. [Figure 9] It is a diagram showing an example of the manufacturing method of an electronic device according to one embodiment of the present invention. [Figure 10] It is a diagram showing an example of the manufacturing method of an electronic device according to one embodiment of the present invention. [Figure 11] It is a diagram showing an example of the manufacturing method of an electronic device according to one embodiment of the present invention. [Figure 12]This figure shows an example of a method for manufacturing an electronic device according to one embodiment of the present invention. [Figure 13] This figure shows an example of a method for manufacturing an electronic device according to one embodiment of the present invention. [Figure 14] This figure shows another example of a method for manufacturing an electronic device according to one embodiment of the present invention. [Figure 15] This is a block diagram showing another example of an electronic device design system 200 according to one embodiment of the present invention. [Figure 16] This figure shows another example of a method for manufacturing an electronic device according to one embodiment of the present invention. [Figure 17] This figure shows another example of a method for manufacturing an electronic device according to one embodiment of the present invention. [Figure 18] This is a schematic diagram of a portion of the upper surface of the liquid crystal layer 290 when a voltage is applied between the upper surface of the liquid crystal layer 290 and the connecting substrate 10. [Modes for carrying out the invention]

[0029] The present invention will be described below through embodiments of the invention, but these embodiments are not intended to limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0030] Figure 1 shows an example of an electronic device 100 according to one embodiment of the present invention. The electronic device 100 in this example is a semiconductor package in which a connection board 10 is mounted on top of a circuit board 40, and a semiconductor chip 22 is mounted on top of the connection board 10. The electronic device 100 comprises a connection board 10, an electronic element 20, and connection wiring 32. In this example, the semiconductor chip 22 has the electronic element 20.

[0031] The connecting substrate 10 is a substrate that electrically connects the circuit board 40 and the semiconductor chip 22. The connecting substrate 10 is, for example, an interposer provided between the circuit board 40 and the semiconductor chip 22. The connecting substrate 10 may be a first semiconductor wafer 60 (described later). When the connecting substrate 10 is a first semiconductor wafer 60 (described later), the electronic device 100 in Figure 1 is in the form of a so-called CoWoS (Chip on Wafer on Substrate, registered trademark).

[0032] The electronic device 100 may include a circuit board 40. The circuit board 40 is, for example, a printed circuit board (PCB).

[0033] In this specification, electronic element 20 refers to an active element that operates based on supplied power. Such active elements include, for example, transistors and diodes. In this specification, electrical element 120 (described later) refers to the above-mentioned active element and a passive element that stores or consumes the supplied power. Such passive elements include, for example, capacitors, resistors, and coils. The capacitor structure 12 is an example of an electrical element 120.

[0034] The connection board 10 is provided with a plurality of capacitor structures 12. The capacitor structures 12 are structural parts of the connection board 10 designed as capacitors. These structures include at least one of a conductive material or other component additionally provided to the insulating connection board 10, and grooves, irregularities, or other parts formed on the connection board 10. In this example, the capacitor structure 12 is a trench structure provided from the upper surface 16 to the interior of the connection board 10.

[0035] The ratio of the depth in the Z-axis direction to the width in the Y-axis direction of the trench structure (the so-called aspect ratio) may be between 2.5 and 30, or between 10 and 20. The width in the Y-axis direction is, for example, between 2 μm and 4 μm. The depth in the Z-axis direction is, for example, between 10 μm and 60 μm. The ratio of the width in the X-axis direction to the width in the Y-axis direction of the trench structure may be between 0.5 and 1.5, or between 0.6 and 1.4, or between 0.8 and 1.2.

[0036] The upper surface 16 is the side of the connection substrate 10 that faces the electronic element 20. The lower surface 18 is the side of the connection substrate 10 that faces the circuit board 40. Figure 1 shows 24 capacitor structures 12 (capacitor structures 12-1 to 12-24).

[0037] Each of the multiple capacitor structures 12 has at least one connected capacitor section 13 and at least one disconnected capacitor section 14. The connected capacitor section 13 is connected to the connecting wiring 32. The disconnected capacitor section 14 is not connected to the connecting wiring 32. Figure 1 shows 16 connected capacitor sections 13 (connected capacitor sections 13-1 to 13-16) and 8 disconnected capacitor sections 14 (disconnected capacitor sections 14-1 to 14-8).

[0038] In Figure 1, the connected capacitor section 13-1 refers to the capacitor structure section 12-5 that functions as a connected capacitor. That is, the connected capacitor section 13-1 and the capacitor structure section 12-5 are the same structure. Similarly, connected capacitor sections 13-2 to 13-16 refer to the capacitor structure sections 12-6 to 12-12 and 12-17 to 12-24. In Figure 1, the unconnected capacitor section 14-1 refers to the capacitor structure section 12-1 that functions as an unconnected capacitor. That is, the unconnected capacitor section 14-1 and the capacitor structure section 12-1 are the same structure. Similarly, unconnected capacitor sections 14-2 to 14-8 refer to the capacitor structure sections 12-2 to 12-4 and 12-13 to 12-16.

[0039] The connected capacitor section 13 is a capacitor structure section 12 that functions as a capacitor as designed. That is, the connected capacitor section 13 is a good capacitor. The multiple unconnected capacitor sections 14 include capacitor structure sections 12 that, despite being designed as capacitors, have difficulty functioning as capacitors. That is, at least one unconnected capacitor section 14 is a defective capacitor. In the example in Figure 1, the black rectangular capacitor structure sections 12-3 and 12-14 are defective capacitors, respectively. These defective capacitors are the unconnected capacitor sections 14-3 and 14-6. The multiple unconnected capacitor sections 14 may include good capacitors. In the example in Figure 1, the white rectangular capacitor structure sections 12-1, 12-2, 12-4, 12-13, 12-15, and 12-16 are good capacitors, respectively. The capacitors in question are the disconnected capacitor section 14-1, disconnected capacitor section 14-2, disconnected capacitor section 14-4, disconnected capacitor section 14-5, disconnected capacitor section 14-7, and disconnected capacitor section 14-8.

[0040] When multiple capacitor structures 12 are formed on the connecting substrate 10, the yield of the multiple capacitor structures 12 may be less than 100%. The yield of the multiple capacitor structures 12 refers to the ratio of good capacitors (white rectangular capacitor structures 12 in Figure 1) to the total number of multiple capacitor structures 12.

[0041] At least one disconnected capacitor section 14 may be a short-circuited or open-circuited capacitor. This at least one disconnected capacitor section 14 is a defective capacitor (the black rectangular capacitor structure 12 in Figure 1). A short-circuited state refers to a state in which the two electrodes of a capacitor are short-circuited, causing a leakage current to flow between the two electrodes. A capacitor in which the current flowing between the two electrodes is greater than or equal to a predetermined threshold may be considered a short-circuited capacitor. An open-circuited state refers to a state in which at least one of the two wires connected to each of the two electrodes is broken, resulting in an infinite resistance between the two electrodes. A capacitor in which the electrical resistance between the two electrodes is greater than or equal to a predetermined resistance threshold may be considered an open-circuited capacitor. A capacitor structure 12 whose capacitance value is outside the allowable range may be considered a defective product. This allowable range may be predetermined by the user or manufacturer.

[0042] Multiple capacitor structures 12 may correspond to a single electronic element 20. The correspondence of a capacitor structure 12 to an electronic element 20 means that the electronic element 20 and the capacitor structure 12 are connected in a circuit. In this example, eight capacitor structures 12 correspond to a single electronic element 20. In this example, capacitor structures 12-1 to 12-8 correspond to electronic element 20-1, capacitor structures 12-9 to 12-16 correspond to electronic element 20-2, and capacitor structures 12-17 to 12-24 correspond to electronic element 20-3.

[0043] In this specification, technical matters may be described using the Cartesian coordinate axes X, Y, and Z. In this specification, the planes parallel to the substrate surfaces of the connecting substrate 10 and the circuit board 40 are defined as the XY plane, and the direction from the circuit board 40 to the semiconductor chip 22 is defined as the Z-axis direction. In this specification, the direction from the capacitor structure 12-1 to the capacitor structure 12-24 in the XY plane is defined as the Y-axis direction, and the direction perpendicular to the Y-axis in the XY plane is defined as the X-axis direction. The Z-axis direction may be parallel to the vertical direction, and the XY plane may be a horizontal plane.

[0044] In this specification, the semiconductor chip 22 side of the electronic device 100 is referred to as "top," and the circuit board 40 side is referred to as "bottom." In this specification, the view from the semiconductor chip 22 towards the circuit board 40 is referred to as a top view.

[0045] The connection board 10 may be provided with a plurality of through-via structures 17. The through-via structures 17 are structural parts of the connection board 10 designed as through-vias. The through-via structures 17 may be formed by filling trench-shaped openings formed from the upper surface 16 to the lower surface 18 with a metal such as Cu (copper).

[0046] The through-via structure 17 may be provided alongside the capacitor structure 12 in the Y-axis direction. Two adjacent through-via structures 17 in the Y-axis direction (for example, through-via structure 17-1 and through-via structure 17-2) may be spaced apart by a predetermined distance in the Y-axis direction. Multiple capacitor structures 12 may be provided between two adjacent through-via structures 17 in the Y-axis direction. In this example, capacitor structures 12-1 to 12-8 are provided between through-via structure 17-1 and through-via structure 17-2, capacitor structures 12-9 to 12-16 are provided between through-via structure 17-2 and through-via structure 17-3, and capacitor structures 12-17 to 12-24 are provided between through-via structure 17-3 and through-via structure 17-4.

[0047] The electronic element 20 is located above the connecting substrate 10. The electronic element 20 is, for example, a transistor, a diode, etc. The connecting wiring 32 electrically connects the electronic element 20 and the connecting substrate 10. The electronic device 100 may include the first bump 24.

[0048] The electronic device 100 may further include a wiring layer 30. In this example, the wiring layer 30 is provided in contact with the upper surface 16 of the connection substrate 10. The wiring layer 30 may be formed of a photosensitive material 38.

[0049] The connection substrate 10 may have at least one first connection electrode 34 and at least one second connection electrode 36. The first connection electrode 34, the second connection electrode 36, and the connection wiring 32 may be provided inside the wiring layer 30. The first connection electrode 34 is connected to the connection capacitor section 13. The first connection electrode 34 may be provided covering the upper part of the connection capacitor section 13. One first connection electrode 34 may be provided covering the upper part of one connection capacitor section 13. The second connection electrode 36 is connected to the non-connection capacitor section 14. The second connection electrode 36 may be provided covering the upper part of the non-connection capacitor section 14. One second connection electrode 36 may be provided covering the upper part of one non-connection capacitor section 14. The first connection electrode 34 is connected to the connection wiring 32. The second connection electrode 36 is not connected to the connection wiring 32.

[0050] The connection substrate 10 may further include at least one upper electrode 37. The upper electrode 37 may be provided inside the wiring layer 30. The upper surface of the upper electrode 37 may be exposed to the upper surface of the wiring layer 30. In the Z-axis direction, one upper electrode 37 may be provided above one first connection electrode 34 or one second connection electrode 36. The first connection electrode 34 and the upper electrode 37 are connected by a connection wire 32. The second connection electrode 36 and the upper electrode 37 are not connected by a connection wire 32. The connection wire 32 may be positioned so as to overlap with the first connection electrode 34 and the upper electrode 37 when viewed from above.

[0051] A first bump 24 may be provided in contact with the upper electrode 37. In this example, power supplied from the connecting substrate 10 is supplied to the electronic element 20 via the first connecting electrode 34, connecting wiring 32, upper electrode 37, and first bump 24.

[0052] In semiconductor devices such as electronic device 100, the operating voltage of electronic elements 20 has recently tended to be reduced in order to lower power consumption. Furthermore, the increasing scale of the circuits mounted on electronic device 100 has led to an increase in the number of electronic elements 20. As a result, the total power consumed by multiple electronic elements 20 tends to increase. Additionally, the increasing scale of the circuits mounted on electronic device 100 has led to a larger power supply network. Consequently, the power consumption of electronic device 100 tends to increase. Due to these trends, voltage drop on the power supply wiring can become a problem in electronic device 100. This voltage drop can be suppressed using capacitors, thereby ensuring the quality of the power supply voltage.

[0053] When suppressing voltage drops on power supply wiring using a capacitor, a large capacitor capacity is preferable. However, increasing the capacitor's capacity tends to increase its area. Therefore, it is preferable to increase the capacitor's capacity while ensuring sufficient capacitance per unit area of ​​the connection board 10.

[0054] In the electronic device 100, the connection wiring 32 is arranged based on the state of the capacitor structure 12. The state of the capacitor structure 12 may refer to either good or bad, or its capacitance value. In this example, the connection wiring 32 is connected to good capacitor structures 12 but not to defective capacitor structures 12. That is, the connection wiring 32 is connected to good capacitor structures 12 while avoiding defective ones. This makes it easier to secure capacitance per unit area of ​​the connection board 10. Furthermore, by pre-fabricating surplus capacitor structures 12 on the connection board 10, even if some capacitor structures 12 become defective, the remaining capacitor structures 12 can be used to form the wiring afterward, preventing the entire connection board 10 or the electronic device 100 from becoming defective.

[0055] The first connecting electrode 34 and the second connecting electrode 36 may be provided on the upper surface 16 of the connecting substrate 10. Two or more capacitor structures 12 may be connected to the first connecting electrode 34. Two or more connecting capacitor sections 13 may be connected to the first connecting electrode 34. A good capacitor may be connected to the first connecting electrode 34, but a defective capacitor does not have to be connected. Two or more capacitor structures 12 may be connected to the second connecting electrode 36. One or more unconnected capacitor sections 14 may be connected to the second connecting electrode 36. At least one defective capacitor may be connected to the second connecting electrode 36. A good capacitor does not have to be connected to the second connecting electrode 36, or it may be.

[0056] In this example, multiple capacitor structures 12 are connected to the same first connecting electrode 34. For each first connecting electrode 34, it is determined whether or not a connecting wire 32 is provided. The first connecting electrode 34 corresponding to a defective capacitor (e.g., capacitor structure 12-3) does not have a connecting wire 32. Therefore, in addition to the defective capacitor (e.g., capacitor structure 12-3), good capacitors (e.g., capacitor structures 12-1, 12-2, 12-4) corresponding to the same first connecting electrode 34 as the defective capacitor also become unconnected capacitor sections 14. On the other hand, if all of the multiple capacitors connected to a common first connecting electrode 34 are good, these capacitors become connected capacitor sections 13.

[0057] The circuit board 40 is located below the connecting board 10. The circuit board 40 may have a second bump 42. The second bump 42 may be located on the upper surface of the circuit board. In this example, the second bump 42 and the through-via structure 17 of the connecting board 10 are electrically connected. The second bump 42 and the through-via structure 17 may be connected on the lower surface 18 of the connecting board 10.

[0058] Figure 2 shows another example of an electronic device 100 according to one embodiment of the present invention. In this example of the electronic device 100, the connecting substrate 10 is a first semiconductor wafer 60. In this example of the electronic device 100, a second semiconductor wafer 70 is provided instead of the semiconductor chip 22 in Figure 1. In this example, one or more electronic elements 20 are provided on the second semiconductor wafer 70. In these respects, the electronic device 100 in this example differs from the electronic device 100 in Figure 1. The electronic device 100 in Figure 2 is in the so-called WoW (Wafer on Wafer) configuration.

[0059] The first semiconductor wafer 60 and the second semiconductor wafer 70 may be substrates cut from an ingot and before being pieced. The first semiconductor wafer 60 and the second semiconductor wafer 70 may be disc-shaped substrates on which orientation flats or notches representing the crystal orientation of the semiconductor are formed.

[0060] The first semiconductor wafer 60 and the second semiconductor wafer 70 may be Si (silicon) wafers, GaAs (gallium arsenide) wafers, GaN (gallium nitride) wafers, or InP (indium phosphide) wafers. The semiconductor material of the first semiconductor wafer 60 and the semiconductor material of the second semiconductor wafer 70 may be the same or different.

[0061] If the first semiconductor wafer 60 is a Si (silicon) wafer, the through-via structure 17 is, for example, a TSV (Through Silicon Via). The through-via structure 17 is provided extending from the upper surface 16 to the lower surface 18.

[0062] In this example, a second semiconductor wafer 70 on which the electronic element 20 is formed is mounted on a first semiconductor wafer 60 on which the capacitor structure 12 is formed. As will be described later, the second semiconductor wafer 70 is mounted on the first semiconductor wafer 60 by aligning the position of the second semiconductor wafer 70 in the wafer plane direction with the position of the first semiconductor wafer 60 in the wafer plane direction. For this reason, it is preferable that the wafer size of the first semiconductor wafer 60 and the wafer size of the second semiconductor wafer 70 are the same.

[0063] Figure 3A is an enlarged view of an example of one capacitor structure 12 in Figure 2. Figure 3A is an example where the capacitor structure 12 is a connected capacitor section 13. The capacitor structure 12 in Figure 3A is a simplified example compared to the capacitor structure 12 in Figure 3B, which will be described later. The capacitor structure 12 may be a trench structure provided from the upper surface 16 to the interior of the first semiconductor wafer 60. A trench structure provided from the upper surface 16 to the interior refers to a recess provided from the upper surface 16 in the direction from the upper surface 16 to the lower surface 18, and a recess that does not penetrate from the upper surface 16 to the lower surface 18. A capacitor having a trench structure like this example is sometimes called an eDTC (embedded Deep Trench Capacitor). The capacitor structure 12 is a structure in which it is difficult to individually determine the quality of each of the multiple capacitor structures 12.

[0064] The connected capacitor section 13 includes a first capacitor electrode 50, a dielectric 52, and a second capacitor electrode 54. In this example, the first capacitor electrode 50 is provided on the inner wall 51 of a trench structure provided on the first semiconductor wafer 60. The first capacitor electrode 50 may also be provided at the bottom 53 of the trench structure. The first capacitor electrode 50 may be provided continuously from the inner wall 51 to the bottom 53. The position of the upper end of the first capacitor electrode 50 in the Z-axis direction and the position of the upper surface 16 in the Z-axis direction may be the same.

[0065] The dielectric 52 may be provided inside the first capacitor electrode 50 in the trench structure, in contact with the first capacitor electrode 50. The dielectric 52 may also be provided on the upper surface 16 of the connecting substrate 10. The dielectric 52 may be provided continuously from the inside of the first capacitor electrode 50 to the upper surface 16.

[0066] The second capacitor electrode 54 may be provided inside the dielectric 52 in the trench structure, in contact with the dielectric 52. The position of the upper end of the second capacitor electrode 54 in the Z-axis direction and the position of the upper end of the dielectric 52 in the Z-axis direction may be the same.

[0067] The first connecting electrode 34 may be provided above the connecting substrate 10 via a dielectric 52. The first connecting electrode 34 may be provided in contact with the upper surface of the dielectric 52 provided on the upper surface 16. In this example, the first connecting electrode 34 is electrically connected to the second capacitor electrode 54, but not to the first capacitor electrode 50.

[0068] The first capacitor electrode 50 may be in contact with the first semiconductor wafer 60. By the first capacitor electrode 50 being in contact with the first semiconductor wafer 60, the first capacitor electrode 50 and the first semiconductor wafer 60 are electrically connected without the need for wiring or other intermediaries. This can improve the area density of the capacitor structure 12. The area density of the capacitor structure 12 may refer to the capacitance per unit area of ​​the upper surface 16 of the first semiconductor wafer 60 when viewed from above, or it may refer to the number of capacitor structures 12 per unit area.

[0069] Figure 3B is an enlarged view of another example of one of the capacitor structures 12 in Figure 2. Figure 3B is an example where the capacitor structure 12 is a connected capacitor section 13, similar to Figure 3A. In this example, the connected capacitor section 13 further includes a third capacitor electrode 55.

[0070] In this example, dielectric material 52-1 is provided on the inner wall 51, bottom 53, and top surface 16. The first capacitor electrode 50 may be provided inside dielectric material 52-1 in the trench structure, in contact with dielectric material 52-1. Dielectric material 52-2 may be provided inside the first capacitor electrode 50 in the trench structure, in contact with the first capacitor electrode 50. The second capacitor electrode 54 may be provided inside dielectric material 52-2 in the trench structure, in contact with dielectric material 52-2. Dielectric material 52-3 may be provided inside the second capacitor electrode 54 in the trench structure, in contact with the second capacitor electrode 54. The third capacitor electrode 55 may be provided inside dielectric material 52-3 in the trench structure, in contact with dielectric material 52-3.

[0071] In this example, the first connecting electrode 34 is provided in contact with the upper surface of the dielectric 52-3. In this example, the dielectric 52-1 is in contact with the first capacitor electrode 50. In this example, the first connecting electrode 34 is electrically connected to the third capacitor electrode 55.

[0072] Figure 4 shows an example of a top view of the first semiconductor wafer 60. The first semiconductor wafer 60 has multiple regions 62 within the wafer surface. One region 62 is provided with a capacitor structure 12 (see Figure 2) and a through-via structure 17 (see Figure 2). The region 62 is arranged translationally symmetrically in the X-axis and Y-axis directions within the wafer surface.

[0073] Figure 5 is an enlarged view of one region 62 in Figure 4. The first semiconductor wafer 60 may be provided with an information unit 64. The information unit 64 includes region information 66 and capacitor information 68. Region information 66 is information indicating region 62 on the first semiconductor wafer 60. Region information 66 may be information indicating the position of region 62 on the wafer surface of the first semiconductor wafer 60. Capacitor information 68 is information indicating the capacitor characteristics of at least one capacitor structure 12 in region 62. Capacitor information 68 may be information indicating whether the capacitor structure 12 is a connected capacitor section 13 (i.e., a good capacitor structure 12) or a disconnected capacitor section 14 (i.e., a defective capacitor structure 12), and may also be information indicating the capacitance value of the capacitor structure 12.

[0074] By including region information 66 and capacitor information 68 in a single region 62, the electronic device design system 200 (described later) can more easily recognize capacitor information at a specific location on the wafer surface of the first semiconductor wafer 60. By including region information 66 and capacitor information 68 in a single region 62, the designer of the electronic device 100 can more easily recognize the location on the wafer surface of the first semiconductor wafer 60 where the fragmented semiconductor chips were placed, and the capacitor information of the fragmented semiconductor chips, even after the first semiconductor wafer 60 has been fragmented into regions 62.

[0075] Figure 6 shows an example of the A-A' cross-section in Figure 5. In Figure 6, the semiconductor chip 22, first bump 24, second bump 42, and circuit board 40 in Figure 2 are omitted. The information unit 64 may have a first dummy electrode 56, a second dummy electrode 58, and a dummy via hole 57. The first dummy electrode 56, the second dummy electrode 58, and the dummy via hole 57 may be provided in the wiring layer 30. The first dummy electrode 56 may be provided on the upper surface 16. The upper surface of the second dummy electrode 58 may be exposed on the upper surface of the wiring layer 30. The dummy via hole 57 may be positioned to overlap with the first dummy electrode 56 and the second dummy electrode 58 when viewed from above.

[0076] In this example, region information 66 and capacitor information 68 are indicated by the presence or absence of dummy via holes 57 at each location. For example, the presence or absence of a dummy via hole 57 at one location indicates 1 bit of information. The presence or absence of dummy via holes 57 can be identified from the image, or from the electrical characteristics that can be measured by contacting a probe or the like at each location. In Figure 5, dummy via holes 57 are provided at the locations marked with black circles, and dummy via holes 57 are not provided at the locations marked with white circles. Dummy via holes 57 may be provided below all first dummy electrodes 56 in the information unit 64. When dummy via holes 57 are provided below all first dummy electrodes 56, region information 66 and capacitor information 68 may be indicated by the presence or absence of dummy connection wiring provided in the dummy via holes 57.

[0077] Figure 7 shows another example of an electronic device 100 according to one embodiment of the present invention. The electronic device 100 in this example differs from the electronic device 100 in Figure 1 in that it includes a wiring layer 80 instead of the second bump 42. The wiring layer 80 may be provided between the connecting substrate 10 and the circuit board 40 in the Z-axis direction. The wiring layer 80 may be formed of a photosensitive material 88. In this example, the connecting substrate 10 may be a first semiconductor wafer 60 (see Figure 2), or it may not be a first semiconductor wafer 60.

[0078] The connection board 10 may be provided with a plurality of through-via structures 17. Each of the plurality of through-via structures 17 may have at least one connecting through-via 11 and at least one non-connecting through-via 19. The connecting through-via 11 may be electrically connected to the circuit board 40. The non-connecting through-via 19 does not need to be electrically connected to the circuit board 40.

[0079] The connected through via 11 is a through via structure 17 that functions as a through via as designed. The unconnected through via 19 is a through via structure 17 that, despite being designed as a through via, has difficulty functioning as a through via. In Figure 7, connected through via 11-1 refers to the through via structure 17-1 that functions as a through via. That is, connected through via 11-1 and through via structure 17-1 are the same structure. Similarly, connected through via 11-2 and through via structure 17-3 are the same structure, and connected through via 11-3 and through via structure 17-4 are the same structure. In Figure 1, unconnected through via 19-1 refers to the through via structure 17-2 that functions as an unconnected through via. That is, unconnected through via 19-1 and through via structure 17-2 are the same structure.

[0080] When multiple through-via structures 17 are formed on the connection substrate 10, the yield of the multiple through-via structures 17 may be less than 100%, similar to the case of the capacitor structure 12. The yield of the multiple through-via structures 17 refers to the ratio of the number of connection through-vias 11 to the total number of multiple through-via structures 17.

[0081] An unconnected through-via 19 may be an open through-via. An open through-via refers to a through-via in which the electrical resistance value of the through-via structure 17 between the upper surface 16 and the lower surface 18 exceeds a predetermined resistance threshold due to defects in the metal filling of the through-hole for forming the through-via. An unconnected through-via 19 is a defective through-via. It is preferable that the unconnected through-via 19 is not used to connect the circuit board 40 and the electronic element 20. A connected through-via 11 is a through-via in which the electrical resistance value of the through-via structure 17 between the upper surface 16 and the lower surface 18 is below a predetermined resistance threshold. A connected through-via 11 is a good through-via.

[0082] The connection substrate 10 may have at least one third connection electrode 84 and at least one fourth connection electrode 86. The third connection electrode 84, the fourth connection electrode 86 and the connection wiring 82 may be provided inside the wiring layer 80. The third connection electrode 84 and the fourth connection electrode 86 may be provided on the lower surface 18 of the connection substrate 10.

[0083] The third connecting electrode 84 is connected to the connecting through via 11. The third connecting electrode 84 may be provided covering the lower part of the connecting through via 11. One third connecting electrode 84 may be provided covering the lower part of one connecting through via 11. The fourth connecting electrode 86 is connected to the non-connecting through via 19. The fourth connecting electrode 86 may be provided covering the lower part of the non-connecting through via 19. One fourth connecting electrode 86 may be provided covering the lower part of one non-connecting through via 19. The third connecting electrode 84 is connected to the connecting wiring 82. The fourth connecting electrode 86 is not connected to the connecting wiring 82.

[0084] The connection substrate 10 may further include at least one lower electrode 87. The lower electrode 87 may be provided inside the wiring layer 80. The lower surface of the lower electrode 87 may be exposed to the lower surface of the wiring layer 80. In the Z-axis direction, one lower electrode 87 may be provided below one third connection electrode 84 or one fourth connection electrode 86. The connection wiring 82 may be positioned so as to overlap the third connection electrode 84 and the lower electrode 87 when viewed from above.

[0085] The third connecting electrode 84 is electrically connected to the circuit board 40. In this example, the third connecting electrode 84 and the lower electrode 87 are connected by a connecting wire 82. This connects the third connecting electrode 84 to the circuit board 40. In this example, the fourth connecting electrode 86 and the lower electrode 87 are not connected by a connecting wire 82. This connects the fourth connecting electrode 86 to the circuit board 40. In this example, power supplied from the circuit board 40 is supplied to the electronic element 20 via the lower electrode 87, the connecting wire 82, the third connecting electrode 84, the connecting through via 11, the first connecting electrode 34, the connecting wire 32, the upper electrode 37, and the first bump 24.

[0086] The connecting through via 11 may be electrically connected to the first connecting electrode 34. That is, the connecting through via 11 and the connecting capacitor section 13 (see Figure 1) may be electrically connected. This ensures that the quality of the power supply voltage is maintained while the power supply voltage is supplied from the circuit board 40 to the electronic element 20. The non-connecting through via 19 may or may not be electrically connected to the first connecting electrode 34.

[0087] In the electronic device 100 of this example, the connection wiring 82 is positioned based on the state of the through-via structure 17. The state of the through-via structure 17 may refer to either good or bad condition of the through-via structure 17, or to its electrical resistance value. In this example, the connection wiring 82 is connected to good through-via structures 17, but not to defective through-via structures 17. That is, the connection wiring 82 is connected to good through-via structures 17 while avoiding defective ones. As a result, the electronic device design system 200 (described later) can efficiently connect the circuit board 40 and the electronic elements 20 electrically.

[0088] Figure 8 is a block diagram showing an example of an electronic device design system 200 according to one embodiment of the present invention. The electronic device manufacturing apparatus 300 is an apparatus for manufacturing an electronic device 100 (see Figures 1 to 7). The electronic device design system 200 manufactures the electronic device 100 by controlling the electronic device manufacturing apparatus 300.

[0089] The electronic device design system 200 in this example comprises a measurement unit 210, a data generation unit 220, a control unit 230, a storage unit 240, and an activation signal application unit 250. The measurement unit 210, the data generation unit 220, the storage unit 240, and the activation signal application unit 250 will be described later in the electronic device manufacturing method.

[0090] Part or all of the electronic device design system 200 may be implemented by a computer. The control unit 230 may be the CPU (Central Processing Unit) of the computer. If the electronic device design system 200 is implemented by a computer, the computer may have a program installed that allows it to function as the electronic device design system 200.

[0091] Figures 9 to 13 show an example of a method for manufacturing an electronic device according to one embodiment of the present invention. The method for manufacturing an electronic device comprises an electrical element formation step S100, an evaluation step S104, and a wiring formation step S120. The method for manufacturing an electronic device may also include an electrode formation step S102, a classification step S106, a photosensitive material formation step S108, a via pattern formation step S110, an information section formation step S112, a dummy electrode formation step S122, a through-via exposure step S130, a connection substrate mounting step S140, and a second semiconductor wafer mounting step S200. The method for manufacturing an electronic device will be explained using the electronic device 100 shown in Figures 1 to 7 and the electronic device design system 200 shown in Figure 8 as examples.

[0092] The electrical element formation process S100 is a process of forming a plurality of electrical elements 120 on a connecting substrate 10 made of semiconductor material. In the example in Figure 9, the electrical elements 120 are a capacitor structure 12 and a through-via structure 17. As described above, the electrical elements 120 may be passive elements other than the capacitor structure 12. The connecting substrate 10 may be a first semiconductor wafer 60 (see Figure 2).

[0093] The electrical element formation step S100 may be a step of forming multiple electrical elements 120 of the same structure on the connecting substrate 10. When multiple types of electrical elements 120 are formed on the connecting substrate 10, the electrical element formation step S100 may be a step of forming multiple electrical elements 120 of the same structure for one type of electrical element 120. In this example, the electrical element formation step S100 is a step of forming a capacitor structure 12 and a through-via structure 17 of the same structure.

[0094] The electrical element formation step S100 may be a step in which more electrical elements 120 are formed than the number of electrical elements 120 that should be connected to the connecting wiring 32 (see Figures 1, 2, and 7). As described above, the yield of electrical elements 120 may be less than 100%. Therefore, it is preferable in the electrical element formation step S100 to form more electrical elements 120 than the number of electrical elements 120 that should be connected to the connecting wiring 32.

[0095] The electrode formation step S102 is a step of forming a cover electrode 340 above each of the multiple capacitor structure parts 12. The electrode formation step S102 may be a step of further forming a first dummy electrode 56 (see Figure 6) at a predetermined position in one region 62 (see Figure 4) of the first semiconductor wafer 60. The electrode formation step S102 may be a step of further forming the first dummy electrode 56 in each of the multiple regions 62 of the first semiconductor wafer 60.

[0096] The evaluation step S104 is a step in which the electrical characteristics of each of the multiple electrical elements 120 are evaluated. When the connecting substrate 10 is the first semiconductor wafer 60, the evaluation step S104 is a step in which the capacitor characteristics of each of the multiple capacitor structures 12 formed on the first semiconductor wafer 60 in the electrical element formation step S100 are evaluated. When the connecting substrate 10 is the first semiconductor wafer 60, the evaluation step S104 may be a step in which the capacitor characteristics of each are evaluated while the capacitor structures 12 are formed on the first semiconductor wafer 60. The first semiconductor wafer 60 may be a substrate that has been cut from an ingot and before being pieced. The first semiconductor wafer 60 may be a disc-shaped substrate on which orientation flats or notches representing the crystal orientation of the semiconductor are formed.

[0097] The evaluation step S104 may be a step in which the capacitor characteristics of each of the multiple capacitor structures 12 are evaluated via the cover electrode 340. In the example in Figure 9, the evaluation step S104 is a step in which the measurement unit 210 (see Figure 8) uses the wafer probe 400 to evaluate the capacitor characteristics of each of the multiple capacitor structures 12.

[0098] In evaluation step S104, the measurement unit 210 (see Figure 8) may determine whether each capacitor structure 12 is a connected capacitor section 13 or an unconnected capacitor section 14 by measuring the capacitance value of each capacitor structure 12. In evaluation step S104, the measurement unit 210 may measure the position of the determined capacitor structure 12 within the wafer surface of the first semiconductor wafer 60. The measurement unit 210 may have an encoder circuit for specifying the position of the capacitor structure 12 within the wafer surface of the first semiconductor wafer 60.

[0099] The evaluation step S104 may include a step of maintaining each of the multiple capacitor structures 12 at a predetermined temperature, or applying a predetermined voltage to each of the multiple capacitor structures 12. In the evaluation step S104, the signal application unit 250 (see Figure 8) may activate defects in the capacitor structures 12 by maintaining each of the multiple capacitor structures 12 at a predetermined constant temperature for a certain period of time via the wafer probe 400. Activation of defects in the capacitor structures 12 refers to activating defects that may potentially exist in the capacitor structures 12. The predetermined constant temperature may be 100°C or higher, 120°C or higher, or 130°C or higher. The predetermined constant time may be 10 minutes or more, 20 minutes or more, 40 minutes or more, or 1 hour or more.

[0100] In evaluation step S104, the signal application unit 250 (see Figure 8) may activate defects in the capacitor structures 12 by alternately maintaining each of the multiple capacitor structures 12 at a predetermined first temperature for a first time and then at a predetermined second temperature for a second time via the wafer probe 400. Here, the second temperature is higher than the first temperature. The predetermined first temperature may be 0°C or lower, -20°C or lower, or -40°C or lower. The predetermined second temperature may be 100°C or higher, 120°C or higher, or 130°C or higher. The predetermined first and second times may be 10 minutes or more, 20 minutes or more, 40 minutes or more, or 1 hour or more.

[0101] The signal application unit 250 may activate defects in the capacitor structures 12 by applying a voltage to each of the multiple capacitor structures 12 via the wafer probe 400. This voltage may be a constant voltage determined by the breakdown voltage of the capacitor structures 12. If the signal application unit 250 (see Figure 8) is capable of applying a variable voltage, the voltage determined by the breakdown voltage of the capacitor structures 12 is the maximum operating voltage of the signal application unit 250. Activation of defects in the capacitor structures 12 is what is known as burn-in of the capacitor structures 12.

[0102] The evaluation step S104 may include a step of evaluating the electrical characteristics of each of the multiple through-via structures 17. When the connecting substrate 10 is a first semiconductor wafer 60, the evaluation step S104 is a step of evaluating the electrical characteristics of each of the multiple through-via structures 17 formed on the first semiconductor wafer 60 in the electrical element formation step S100. The evaluation step S104 may be a step of evaluating the electrical characteristics of each through-via structure 17 while the through-via structures 17 are formed on the first semiconductor wafer 60.

[0103] In evaluation step S104, the measurement unit 210 (see Figure 8) may determine whether each through-via structure 17 is a connected through-via 11 or an unconnected through-via 19 by measuring the electrical resistance value of each through-via structure 17. In evaluation step S104, the measurement unit 210 may measure the position of the measured through-via structure 17 within the wafer surface of the first semiconductor wafer 60.

[0104] The classification step S106 is a step in which multiple capacitor structures 12 are classified into connected capacitor sections 13 and unconnected capacitor sections 14 based on the evaluation results of the capacitor characteristics in the evaluation step S104. The classification step S106 may be a step in which multiple capacitor structures 12 are classified into connected capacitor sections 13 and unconnected capacitor sections 14 by having the measurement unit 210 (see Figure 8) measure the capacitance value of each capacitor structure 12.

[0105] The classification step S106 may include a storage step in which the storage unit 240 (see Figure 8) stores the classification results. This storage step may involve the storage unit 240 storing the positions of the capacitor structures 12 on the wafer surface of the first semiconductor wafer 60 in association with the classification results of the capacitor structures 12. In this storage step, the storage unit 240 may store the capacitance values ​​of each capacitor structure 12 measured in the evaluation step S104. In this storage step, the storage unit 240 may store the positions of the through-via structures 17 on the wafer surface of the first semiconductor wafer 60 in association with the electrical resistance values ​​of each through-via structure 17 measured in the evaluation step S104.

[0106] The classification step S106 may be a step of further classifying the cover electrode 340 (see step S102) into at least one first connecting electrode 34 and at least one second connecting electrode 36 based on the evaluation results of the capacitor characteristics in the evaluation step S104. The first connecting electrode 34 covers the upper part of the connected capacitor portion 13 and connects to the connected capacitor portion 13. The second connecting electrode 36 covers the upper part of the unconnected capacitor portion 14 and connects to the unconnected capacitor portion 14.

[0107] The photosensitive material formation step S108 is a step of forming a photosensitive material 38 on the connecting substrate 10. The photosensitive material formation step S108 may be a step of forming the photosensitive material 38 on the upper surface 16 of the connecting substrate 10, on the first connecting electrode 34, and on the second connecting electrode 36.

[0108] The via pattern formation step S110 is a step in which a via pattern 350 is formed above the connected capacitor portion 13 in the photosensitive material 38, and a via pattern 350 is not formed above the unconnected capacitor portion 14. The via pattern formation step S110 may include a data generation step in which the data generation unit 220 (see Figure 8) generates data relating to the coordinates for forming the via pattern based on the position of the capacitor structure portion 12 on the wafer surface of the first semiconductor wafer 60 and the classification result of the capacitor structure portion 12, which are stored in association with the memory unit 240 (see Figure 8). The via pattern formation step S100 may be a step in which the maskless aligner 360 forms a via pattern 350 above the connected capacitor portion 13, and a via pattern 350 is not formed above the unconnected capacitor portion 14, based on the data generated in the data generation step.

[0109] The information unit formation step S112 is a step in which an information unit 64 containing region information 66 and capacitor information 68 is formed on the first semiconductor wafer 60. In this example, the information unit formation step S112 is a step in which dummy via holes 57 are formed on the first semiconductor wafer 60 as the information unit 64. The information unit formation step S112 may be a step in which a data generation unit 220 (see Figure 8) generates position data for dummy via holes 57 based on the position of the capacitor structure 12 on the wafer surface of the first semiconductor wafer 60 and the classification result of the capacitor structure 12 stored in the storage unit 240 (see Figure 8), and then forms dummy via holes 57 at the position of the position data.

[0110] The via pattern formation process S110 and the information unit formation process S112 may be performed simultaneously. Alternatively, the via pattern formation process S110 and the information unit formation process S112 may be performed at different times.

[0111] The wiring formation step S120 is a step of forming connection wiring 32 to connect to at least one of the multiple electrical elements 120 based on the evaluation results of the electrical characteristics of the electrical elements 120 in the evaluation step S104. The wiring formation step S120 may be a step of forming connection wiring 32 based on the classification results in the classification step S106 (see Figure 10). The wiring formation step S120 may be a step of forming connection wiring 32 on a via pattern 350 (see step S110). In the example in Figure 11, the wiring formation step S120 is a step of forming connection wiring 32 to connect to the connecting capacitor section 13 based on the evaluation results of the capacitor characteristics of the capacitor structure section 12.

[0112] The wiring formation step S120 may be a step in which, based on the evaluation results of the electrical characteristics of the electrical element 120 in the evaluation step S104, a connecting wire 32 is not formed on at least one of the other electrical elements 120. In the example in Figure 11, the wiring formation step S120 is a step in which, based on the evaluation results of the capacitor characteristics of the capacitor structure 12, a connecting wire 32 connected to the unconnected capacitor section 14 is not formed.

[0113] The wiring formation step S102 may be a step in which the connecting wiring 32 is formed on the first semiconductor wafer 60 based on the classification result of the classification step S106 (see Figure 10), while the capacitor structure 12 is formed on the first semiconductor wafer 60. Forming the connecting wiring 32 while the capacitor structure 12 is formed on the first semiconductor wafer 60 means forming the connecting wiring 32 on the first semiconductor wafer 60 before it is cut from the ingot and separated into individual pieces.

[0114] In the classification step S106, multiple capacitor structures 12 are classified into connected capacitor sections 13 and unconnected capacitor sections 14. The memory unit 240 (see Figure 8) stores the positions of the capacitor structures 12 on the wafer surface of the first semiconductor wafer 60 and the classification results of the capacitor structures 12 in association with each other. In the data generation step, the data generation unit 220 (see Figure 8) generates data relating to the coordinates for forming the via pattern based on the positions of the capacitor structures 12 on the wafer surface of the first semiconductor wafer 60 and the classification results of the capacitor structures 12 stored in association with each other in the memory unit 240. In the via pattern formation step S100, based on the data generated in the data generation step, the maskless aligner 360 forms a via pattern 350 above the connected capacitor sections 13 and does not form a via pattern 350 above the unconnected capacitor sections 14. These processes ensure that, even when the connection wiring 32 is formed in the wiring formation process S102 while the capacitor structure 12 is formed on the first semiconductor wafer 60, the yield of the multiple electronic elements 20 (see Figures 1, 2, and 7) is not significantly reduced. The yield of the multiple electronic elements 20 refers to the ratio of the number of electronic elements 20 that function normally to the total number of multiple electronic elements 20 formed on the first semiconductor wafer 60.

[0115] The wiring formation step S120 may include the step of forming an upper electrode 37 above one first connecting electrode 34 or one second connecting electrode 36 in the Z-axis direction. This step may be performed after the step of forming the connecting wiring 32.

[0116] The dummy electrode formation step S122 is a step of forming at least one second dummy electrode 58 above the first dummy electrode 56. The dummy electrode formation step S122 may be performed simultaneously with the step of forming the upper electrode 37 in the wiring formation step S120, or it may be performed at a different timing.

[0117] The through-via exposure process S130 is a process of exposing the through-via structure 17 to the lower surface 18. The through-via exposure process S130 may be a process of exposing the through-via structure 17 by cutting the lower surface of the connecting substrate 10. The through-via exposure process S130 may be a process of exposing the through-via structure 17 by grinding the lower surface of the first semiconductor wafer 60.

[0118] The connection board mounting step S140 is a step of mounting the connection board 10 onto the circuit board 40. The connection board mounting step S140 may be a step of mounting the connection board 10 onto the circuit board 40 while aligning the position of the through via structure 17 in the XY plane with the position of the second bump 42 in the XY plane.

[0119] The second semiconductor wafer mounting step S200 is a step of mounting the second semiconductor wafer 70, on which the electronic elements 20 are provided, on top of the first semiconductor wafer 60. The second semiconductor wafer mounting step S200 may include a step of forming the second bump 42 in contact with the upper surface of the upper electrode 37. The second semiconductor wafer mounting step S200 may be a step of mounting the second semiconductor wafer 70 on top of the first semiconductor wafer 60 while aligning the first semiconductor wafer 60 and the second semiconductor wafer 70 in the XY plane. By performing the second semiconductor wafer mounting step S200, the electronic device 100 (see Figure 2) is completed.

[0120] Figure 14 shows another example of a method for manufacturing an electronic device according to one embodiment of the present invention. The method for manufacturing an electronic device in this example differs from the method for manufacturing an electronic device in Figures 9 to 13 in that it includes a specific step S107 instead of a classification step S106. In this example, the electronic element formation step S100 to the evaluation step S104, and the photosensitive material formation step S108 to the second semiconductor wafer mounting step S200 are the same as the method for manufacturing an electronic device in Figures 9 to 13.

[0121] The identification step S107 is a step in which a group 122 of capacitor structural parts 12 whose capacitance value is greater than or equal to a predetermined value is identified based on the evaluation results of the capacitor characteristics in the evaluation step S104. Group 122 of capacitor structural parts 12 includes at least one capacitor structural part 12. Figure 14 shows two groups 122 (group 122-1 and group 122-2). Group 122-1 includes capacitor structural parts 12-1 to 12-16. Group 122-2 includes capacitor structural parts 12-21 to 12-24.

[0122] The specific step S107 is a step of grouping the capacitor structures 12 such that the total capacitance value of all capacitor structures 12 in a group 122 is equal to or greater than a predetermined capacitance value. For this reason, a group 122 may include disconnected capacitor sections 14. In the example in Figure 14, group 122-1 includes two disconnected capacitor sections 14.

[0123] The specific step S107 may be a step in which the capacitor structures 12 are not grouped if the total capacitance value of all capacitor structures 12 in one group 122 does not exceed a predetermined capacitance value. For this reason, even if it is a connected capacitor section 13, there may be capacitor structures 12 that are not included in any group 122. In the example in Figure 14, connected capacitor sections 13-15 to 13-18 are capacitor structures 12 that are not included in any group 122.

[0124] The specific step S107 may be a step of further classifying the cover electrode 340 (see step S102) into at least one first connecting electrode 34 and at least one second connecting electrode 36 based on the evaluation results of the capacitor characteristics in the evaluation step S104. The first connecting electrode 34 covers the upper part of at least one capacitor structure 12 in each group 122 and connects to a connected capacitor section 13 or an unconnected capacitor section 14. The second connecting electrode 36 covers the upper part of a capacitor structure 12 that is not included in any of the groups 122 and connects to a connected capacitor section 13 or an unconnected capacitor section 14.

[0125] In this example, the wiring formation step S110 (see Figure 10) is a step in which the connecting wiring 32 is formed based on the identification result of group 122 in the identification step S107. The connecting wiring 32 may be formed above the first connecting electrode 34 in Figure 14.

[0126] A single group 122 may be a single closed region in a top view of the connection substrate 10. A single group 122 may consist of two or more closed regions in a top view of the connection substrate 10. These two or more closed regions may be spaced apart from each other in a top view of the connection substrate 10. In this example, the connection wiring 32 is formed based on the result of the identification of group 122 in the identification step S107. Therefore, even if a single group 122 consists of two or more spaced-apart regions, the formation of the connection wiring 32 allows the total capacitance value of all capacitor structures 12 in a single group 122 to be greater than or equal to a predetermined capacitance value.

[0127] Figure 15 is a block diagram showing another example of an electronic device design system 200 according to one embodiment of the present invention. This example of the electronic device design system 200 differs from the electronic device design system 200 of Figure 8 in that it includes an optical characteristic measurement unit 280 instead of a measurement unit 210. The optical characteristic measurement unit 280 may include a light source 282 and a light receiving unit 284.

[0128] Figures 16 and 17 show another example of a method for manufacturing an electronic device according to one embodiment of the present invention. The method for manufacturing an electronic device in this example further comprises a liquid crystal layer formation step S1090 and a liquid crystal layer removal step S1094, and includes an evaluation step S1092 instead of an evaluation step S104, which is the same as the method for manufacturing an electronic device in Figures 9 to 13. In this example, the electronic element formation step S100, wiring formation step S102, classification step S106 and photosensitive material formation step S108, and via pattern formation step S110 to second semiconductor wafer mounting step S200 are the same as the method for manufacturing an electronic device in Figures 9 to 13.

[0129] The liquid crystal layer formation step S1090 is a step of forming a liquid crystal layer 290 on top of the connecting substrate 10. In this example, the liquid crystal layer formation step S1090 is a step of forming a liquid crystal layer 290 on the upper surface of the photosensitive material 38 in the wiring layer 30.

[0130] The evaluation step S1092 is a step in which the electrical characteristics of each of the multiple electrical elements 120 (capacitor structure 12 in this example) are evaluated by applying a voltage between the upper surface of the liquid crystal layer 290 and the connecting substrate 10. The optical characteristic measurement unit 280 may further include a first lens 285, a second lens 287, a spectroscopic unit 288, and a voltage application unit 286. The voltage between the upper surface of the liquid crystal layer 290 and the connecting substrate 10 may be applied by the voltage application unit 286. The liquid crystal layer removal step S1094 is a step in which the liquid crystal layer 290 formed in the liquid crystal layer formation step S1090 is removed.

[0131] Figure 18 is a schematic diagram of a portion of the upper surface of the liquid crystal layer 290 when a voltage is applied between the upper surface of the liquid crystal layer 290 and the connecting substrate 10. In this example, one circle in Figure 18 corresponds to four capacitor structures 12 (for example, capacitor structures 12-1 to 12-4 in Figure 16). When a voltage is applied between the upper surface of the liquid crystal layer 290 and the connecting substrate 10 in evaluation step S1092, the twisting state of the liquid crystal layer 290 changes depending on the number and position of connected capacitor sections 13 and unconnected capacitor sections 14. This change in state may appear as an optical contrast on the upper surface of the liquid crystal layer 290. In evaluation step S1092, the optical characteristic measurement unit 280 (see Figure 15) evaluates the capacitor characteristics of the capacitor structures 12 by detecting this optical contrast of the liquid crystal layer 290.

[0132] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0133] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of Symbols]

[0134] 10...Connecting substrate, 11...Connecting through-via, 12...Capacitor structure, 13...Connecting capacitor section, 14...Non-connecting capacitor section, 16...Top surface, 17...Through-via structure, 18...Bottom surface, 19...Non-connecting through-via, 20...Electronic element, 22...Semiconductor chip, 24...First bump, 30...Wiring layer, 32...Connecting wiring, 34...First connecting electrode, 36...Second connection Electrode, 37... Upper electrode, 38... Photosensitive material, 40... Circuit board, 42... Second bump, 50... First capacitor electrode, 51... Inner wall, 52... Dielectric material, 53... Bottom, 54... Second capacitor electrode, 55... Third capacitor electrode, 56... First dummy electrode, 57... Dummy via hole, 58... Second dummy electrode, 60... First semiconductor wafer, 62... Region, 64... Information Information section, 66... ​​Area information, 68... Capacitor information, 70... Second semiconductor wafer, 80... Wiring layer, 82... Connection wiring, 84... Third connection electrode, 86... Fourth connection electrode, 87... Lower electrode, 88... Photosensitive material, 100... Electronic device, 120... Electrical element, 200... Electronic device design system, 210... Measurement section, 220... Data generation section, 230... Control section, 24 0...Memory unit, 250...Signal application unit, 280...Optical characteristic measurement unit, 282...Light source, 284...Light receiving unit, 285...First lens, 286...Voltage application unit, 287...Second lens, 288...Spectroscopy unit, 290...Liquid crystal layer, 300...Electronic device manufacturing equipment, 340...Cover electrode, 350...Via pattern, 360...Maskless aligner, 400...Wafer probe

Claims

1. A connection board provided with multiple capacitor structures, An electronic element provided above the aforementioned connecting substrate, A connecting wire that connects the aforementioned electronic element and the connecting substrate, Equipped with, The plurality of capacitor structures each have at least one connected capacitor section connected to the connecting wiring and at least one unconnected capacitor section not connected to the connecting wiring. Electronic devices.

2. At least one of the disconnected capacitor sections is a capacitor in a short-circuited or open-circuited state. The electronic device according to claim 1.

3. The electronic device according to claim 1, wherein the connecting substrate is a first semiconductor wafer.

4. The electronic device according to claim 3, wherein the capacitor structure is a trench structure provided from the upper surface to the interior of the first semiconductor wafer.

5. The connecting capacitor section includes a first capacitor electrode provided on the inner wall of the trench structure. The first capacitor electrode is in contact with the first semiconductor wafer. The electronic device according to claim 4.

6. The electronic device according to claim 3, wherein the first semiconductor wafer is provided with an information unit that includes region information indicating a region on the first semiconductor wafer, and capacitor information indicating the capacitor characteristics of at least one of the capacitor structures in the region.

7. Further equipped with a second semiconductor wafer, The aforementioned electronic element is provided on the second semiconductor wafer. The electronic device according to any one of claims 3 to 6.

8. The connecting substrate is provided covering the upper part of the connecting capacitor section and has at least one first connecting electrode connected to the connecting capacitor section, and at least one second connecting electrode provided covering the upper part of the non-connecting capacitor section and connected to the non-connecting capacitor section. The first connecting electrode is connected to the connecting wiring, The second connecting electrode is not connected to the connecting wiring. The electronic device according to claim 1.

9. The circuit board is further provided below the aforementioned connection board, The aforementioned connection board is further provided with a plurality of through-via structures, The plurality of through-via structures each have at least one connecting through-via electrically connected to the circuit board and at least one non-connecting through-via not electrically connected to the circuit board. The electronic device according to claim 8.

10. The electronic device according to claim 9, wherein the unconnected through-via is a through-via whose electrical resistance value exceeds a resistance threshold, and the connected through-via is a through-via whose electrical resistance value is less than or equal to the resistance threshold.

11. The connecting substrate is provided covering the lower part of the connecting through via and further has at least one third connecting electrode connected to the connecting through via. The third connecting electrode is electrically connected to the circuit board. The electronic device according to claim 9.

12. The electronic device according to any one of claims 9 to 11, wherein the connecting through via is electrically connected to the first connecting electrode.

13. An electrical element formation process in which multiple electrical elements are formed on a connecting substrate made of semiconductor, An evaluation step of evaluating the electrical characteristics of each of the aforementioned multiple electrical elements, A wiring formation step in which a connecting wire is formed to connect to at least one of the plurality of electrical elements based on the evaluation results of the electrical characteristics, A method for manufacturing electronic devices, comprising:

14. The electrical element formation step is a step of forming a plurality of electrical elements having the same structure, and a step of forming more electrical elements than the number of electrical elements to be connected to the connecting wiring. The wiring formation step is a step of not forming the connecting wiring on at least one of the plurality of electrical elements based on the evaluation result of the electrical characteristics. A method for manufacturing an electronic device according to claim 13.

15. The aforementioned connecting substrate is a first semiconductor wafer, The aforementioned electrical element is a capacitor structure, The evaluation step is a step of evaluating the capacitor characteristics of each of the plurality of capacitor structures formed on the first semiconductor wafer in the electrical element formation step, The process further includes a classification step of classifying the plurality of capacitor structures into connected capacitor sections that are connected to the connecting wiring and unconnected capacitor sections that are not connected to the connecting wiring, based on the evaluation results of the capacitor characteristics. The wiring formation step is a step of forming the connecting wiring based on the classification results of the classification step. A method for manufacturing an electronic device according to claim 13.

16. The method for manufacturing an electronic device according to claim 15, wherein the evaluation step is a step of evaluating the characteristics of each capacitor while the capacitor structure is formed on the first semiconductor wafer.

17. The method for manufacturing an electronic device according to claim 15 or 16, wherein the wiring formation step is a step of forming the connecting wiring based on the classification result of the classification step, while the capacitor structure is formed on the first semiconductor wafer.

18. The process further includes an electrode formation step for forming cover electrodes above each of the capacitor structural parts, The evaluation step is a step of evaluating the capacitor characteristics of each of the multiple capacitor structures via the cover electrode. The classification step is a step of further classifying the cover electrode into, based on the evaluation result of the capacitor characteristics, at least one first connecting electrode that covers the upper part of the connected capacitor portion and connects to the connected capacitor, and at least one second connecting electrode that covers the upper part of the unconnected capacitor portion and connects to the unconnected capacitor portion. A method for manufacturing an electronic device according to claim 15.

19. The aforementioned connecting substrate is a first semiconductor wafer, The aforementioned electrical element is a capacitor structure, The process further includes a selection step of identifying a group of capacitor structures that have a capacitance value equal to or greater than a predetermined value, and which includes at least one of the capacitor structures, based on the evaluation results of the capacitor characteristics of the capacitor structure. The wiring formation step is a step of forming the connecting wiring based on the results of the specified step. A method for manufacturing an electronic device according to claim 13.

20. A method for manufacturing an electronic device according to any one of claims 15, 16, 18, and 19, further comprising an information section forming step of forming an information section on the first semiconductor wafer, the information section including region information indicating a region on the first semiconductor wafer and capacitor information indicating the capacitor characteristics of at least one of the capacitor structures in the region.

21. The method for manufacturing an electronic device according to any one of claims 15, 16, 18, and 19, wherein the evaluation step includes the step of maintaining each of the plurality of capacitor structures at a predetermined temperature or applying a predetermined voltage to each of the plurality of capacitor structures.

22. After the electrical element formation step, a photosensitive material formation step is performed in which a photosensitive material is formed on the connecting substrate, A via pattern forming step of forming a via pattern above the connecting capacitor portion of the photosensitive material and not forming a via pattern above the non-connecting capacitor portion, Furthermore, The wiring formation step is a step of forming the connection wiring in the via pattern. A method for manufacturing an electronic device according to any one of claims 15, 16, and 18.

23. The process further comprises a liquid crystal layer formation step, after the electrical element formation step, in which a liquid crystal layer is formed on top of the connecting substrate. The evaluation step is a step of evaluating the electrical characteristics of each of the plurality of electrical elements by applying a voltage between the upper surface of the liquid crystal layer and the connecting substrate. The evaluation step is followed by a liquid crystal layer removal step, which is performed before the wiring formation step, and the evaluation step is followed by a liquid crystal layer removal step. A method for manufacturing an electronic device according to any one of claims 13 to 16, 18, and 19.

24. A method for manufacturing an electronic device according to any one of claims 15, 16, 18, and 19, further comprising a second semiconductor wafer mounting step of mounting a second semiconductor wafer on which electronic elements are provided on top of the first semiconductor wafer after the wiring formation step.

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