Semiconductor memory

Abstract

To provide a semiconductor memory device that can be suitably manufactured. [Solution] The semiconductor memory device comprises a plurality of conductive layers (110) stacked in the stacking direction (Z), a plurality of memory cells connected to the plurality of conductive layers arranged in the stacking direction, a first contact electrode (CC) extending in the stacking direction and connected to one of the plurality of conductive layers, and a second contact electrode (Ch) extending in the stacking direction and connected to one end of the first contact electrode in the stacking direction. The first contact electrode comprises a first conductive member (151) extending in the stacking direction, an insulating column (152) extending in the stacking direction with its outer peripheral surface covered by the first conductive member, and a second conductive member (153) provided at the end of the first contact electrode on the second contact electrode side in the stacking direction, with its outer peripheral surface in contact with the first conductive member and its surface on the second contact electrode side in the stacking direction in contact with the second contact electrode.

Description

[Technical Field]

[0001] This embodiment relates to a semiconductor memory device. [Background technology]

[0002] A semiconductor memory device is known that comprises a plurality of conductive layers stacked in the stacking direction, a plurality of memory cells aligned in the stacking direction and connected to the plurality of conductive layers, and a contact electrode stretched in the stacking direction and connected to one of the plurality of conductive layers. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2021-150408 [Patent Document 2] Japanese Patent Publication No. 2023-045239 [Overview of the project] [Problems that the invention aims to solve]

[0004] To provide a semiconductor memory device that can be suitably manufactured. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a plurality of conductive layers stacked in the stacking direction, a plurality of memory cells connected to the plurality of conductive layers arranged in the stacking direction, a first contact electrode extending in the stacking direction and connected to one of the plurality of conductive layers, and a second contact electrode extending in the stacking direction and connected to one end of the first contact electrode in the stacking direction. The first contact electrode includes a first conductive member extending in the stacking direction, an insulating column extending in the stacking direction with its outer peripheral surface covered by the first conductive member, and a second conductive member provided at the end of the first contact electrode on the second contact electrode side in the stacking direction, with its outer peripheral surface in contact with the first conductive member and its surface on the second contact electrode side in the stacking direction in contact with the second contact electrode. [Brief explanation of the drawing]

[0006] [Figure 1] This is a schematic circuit diagram of a semiconductor memory device according to the first embodiment. [Figure 2] This is a schematic plan view of a memory die (MD). [Figure 3] This is a schematic plan view of a semiconductor column region (RMH). [Figure 4] This is a schematic cross-sectional view of the semiconductor columnar region RMH. [Figure 5] This is a schematic cross-sectional view of the semiconductor columnar region RMH. [Figure 6] This is a schematic cross-sectional view of the semiconductor columnar region RMH. [Figure 7] This is a schematic plan view illustrating the hookup region (RHU). [Figure 8] This is a schematic plan view illustrating the hookup region (RHU). [Figure 9] This is a schematic cross-sectional view of the hookup region (RHU). [Figure 10] This is a schematic cross-sectional view of the hookup region (RHU). [Figure 11] This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 12] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 13] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 14] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 15] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 16] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 17] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 18] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 19] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 20] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 21] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 22] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 23] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 24] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 25] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 26] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 27] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 28] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 29] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 30] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 31] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 32] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 33] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 34] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 35] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 36] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 37]This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 38] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 39] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 40] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 41] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 42] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 43] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 44] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 45] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 46] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 47] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 48] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 49] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 50] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 51] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 52] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 53] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 54] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 55] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 56] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 57] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 58] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 59] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 60] This is a schematic cross-sectional view of a semiconductor memory device according to the second embodiment. [Figure 61] This is a schematic cross-sectional view of a semiconductor memory device according to the third embodiment. [Figure 62] This is a schematic cross-sectional view of a semiconductor memory device according to the fourth embodiment. [Figure 63] This is a schematic cross-sectional view of a semiconductor memory device according to the fifth embodiment. [Figure 64] This is a schematic cross-sectional view of a semiconductor memory device according to the sixth embodiment. [Figure 65] This is a schematic cross-sectional view of a semiconductor memory device according to another embodiment. [Modes for carrying out the invention]

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. Furthermore, the following drawings are schematic, and some components may be omitted for illustrative purposes. Also, common parts in multiple embodiments are denoted by the same reference numerals, and their descriptions may be omitted.

[0008] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die, or to a memory system including a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). It may also refer to a configuration including a host computer, such as a smartphone, tablet device, or personal computer.

[0009] Furthermore, in this specification, when we say that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or it may be connected to the second configuration via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0010] Furthermore, in this specification, when it is said that a circuit "conducts" two wires, it may mean, for example, that the circuit includes a transistor, that this transistor is located in the current path between the two wires, and that this transistor is in the ON state.

[0011] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0012] Furthermore, in this specification, the direction intersecting the surface of the substrate may be referred to as the stacking direction. Also, the direction along a predetermined plane intersecting the stacking direction may be referred to as the first direction, and the direction intersecting the first direction along this plane may be referred to as the second direction. The stacking direction may or may not coincide with the Z direction. Also, the first and second directions may or may not correspond to either the X direction or the Y direction.

[0013] Furthermore, in this specification, expressions such as "top" and "bottom" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "top," and the direction approaching the substrate along the Z direction is called "bottom." Also, when referring to the bottom surface or bottom end of a configuration, it means the surface or end of that configuration that is on the substrate side, and when referring to the top surface or top end, it means the surface or end of that configuration that is on the opposite side from the substrate. In addition, surfaces that intersect with the X direction or Y direction are called sides, etc.

[0014] Furthermore, in this specification, when we refer to the "width," "length," or "thickness" of a component, member, etc., in a predetermined direction, it may mean the width, length, or thickness of a cross-section observed by SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy), etc.

[0015] [First Embodiment] [Circuit Configuration] Figure 1 is a schematic circuit diagram of a semiconductor memory device according to the first embodiment. The semiconductor memory device according to this embodiment includes a memory block BLK. The memory block BLK includes a plurality of string units SU. Each of these string units SU includes a plurality of memory strings MS. One end of each of these memory strings MS is connected to a peripheral circuit via a bit line BL. The other end of each of these memory strings MS is connected to a peripheral circuit via a common source line SL.

[0016] The memory string MS comprises drain-side selection transistors STDT, STD, one or more dummy memory cells DMD, multiple memory cells MC (memory transistors), one or more dummy memory cells DMS, and source-side selection transistors STS, STSB. The drain-side selection transistors STDT, STD, one or more dummy memory cells DMD, multiple memory cells MC, one or more dummy memory cells DMS, and source-side selection transistors STS, STSB are connected in series between the bit line BL and the source line SL. Hereinafter, the drain-side selection transistors STDT, STD and the source-side selection transistors STS, STSB may simply be referred to as selection transistors STDT, STD, STS, STSB.

[0017] A memory cell MC is a field-effect transistor. A memory cell MC comprises a portion of a semiconductor column, a gate insulating film, and a gate electrode. The portion of the semiconductor column functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge storage film. A memory cell MC stores one or more bits of data. Word lines WL are connected to the gate electrodes of multiple memory cell MCs corresponding to one memory string MS. These word lines WL are commonly connected to all memory string MS in one memory block BLK.

[0018] Dummy memory cells DMD and DMS are basically configured the same as memory cells MC. However, no data is stored in dummy memory cells DMD and DMS. One or more dummy memory cells DMD corresponding to one memory string MS have dummy word lines DWD connected to their gate electrodes. These dummy word lines DWD are each connected in common to all memory string MS in one memory block BLK. Similarly, one or more dummy memory cells DMS corresponding to one memory string MS have dummy word lines DWS connected to their gate electrodes. These dummy word lines DWS are each connected in common to all memory string MS in one memory block BLK.

[0019] The selection transistors STDT, STD, STS, and STSB are field-effect transistors. Each selection transistor comprises a portion of a semiconductor column, a gate insulating film, and a gate electrode. The portion of the semiconductor column functions as a channel region. The gate electrodes of the selection transistors STDT, STD, STS, and STSB are connected to the selection gate lines SGDT, SGD, SGS, and SGSB, respectively. The drain-side selection gate line SGDT is commonly connected to all memory strings MS in one memory block BLK. The drain-side selection gate line SGD is commonly connected to all memory strings MS in one string unit SU. The source-side selection gate line SGS is commonly connected to all memory strings MS in one memory block BLK. The source-side selection gate line SGSB is commonly connected to all memory strings MS in one memory block BLK.

[0020] [structure] Figure 2 is a schematic plan view of a memory die MD. The memory die MD comprises a semiconductor substrate Sub. In the illustrated example, the semiconductor substrate Sub has four memory cell array regions R arranged in the X and Y directions. MCA A system is in place.

[0021] Memory cell array region R MCA It comprises multiple finger structures FS arranged in the Y direction. In this embodiment, one finger structure FS functions as one memory block BLK (Figure 1). However, multiple finger structures FS may function as one memory block BLK.

[0022] Also, the memory cell array region R MCA These are two semiconductor column regions R aligned in the X direction. MH And the hookup region R provided between these HU It is equipped with the following. The structures within these regions will be described in order below.

[0023] [Semiconductor column region R MH Internal structure] First, referring to FIGS. 3 to 6, the structure in the semiconductor pillar region R will be described. MH The structure in the semiconductor pillar region R will be described. FIG. 3 is a schematic plan view of the semiconductor pillar region R, and the portion indicated by A in FIG. 3 is shown enlarged. In a part of the region of FIG. 3, an XY cross-section at the height position corresponding to the conductive layer 110 (WL) described later is shown. In the remaining region of FIG. 3, a view of the portion indicated by A in FIG. 3 as seen from above is shown. Also, in this remaining region, the insulating layers 102 and 103 described later, and the conductive layer 110 (SGDT) described later are omitted. Also, in a part of this remaining region, the bit line BL is omitted. FIG. 4 is a schematic cross-sectional view of the semiconductor pillar region R, showing a cross-section obtained by cutting the structure shown in FIG. 3 along the line B - B' and viewed along the direction of the arrow. FIG. 5 is a schematic cross-sectional view of the semiconductor pillar region R, showing the portion indicated by C in FIG. 4 enlarged. Note that although FIG. 5 shows a YZ cross-section, the same structure as FIG. 5 is observed when observing a cross-section other than the YZ cross-section along the central axis of the semiconductor pillar 120 described later (for example, an XZ cross-section). FIG. 6 is a schematic cross-sectional view of the semiconductor pillar region R.

[0024] The finger structure FS includes, for example, five string units SU arranged in the Y direction as shown in FIG. 3. A finger - between structure ST is provided between two adjacent finger structures FS in the Y direction. Also, an inter - string insulating member SHE such as silicon oxide (SiO2) is provided between two adjacent string units SU in the Y direction. Note that the finger structure FS may include two to four string units SU or six or more string units SU.

[0025] As shown in FIG. 6, the finger structure FS includes three memory cell array layers L MCA1 , L MCA2 , L MCA3 arranged in the Z direction. Each of the memory cell array layers L MCA1 , L MCA2 , L MCA3 includes a plurality of conductive layers 110 arranged in the Z direction. The memory cell array layer L MCA1 ​​​​​​​​A conductive layer 113 is provided below it. Furthermore, the finger structure FS is formed by these three memory cell array layers L MCA1 ,L MCA2 ,L MCA3 The device comprises multiple semiconductor columns 120 extending in the Z direction. Furthermore, as shown in Figure 4, gate insulating films 130 are provided between each of the multiple conductive layers 110 and the multiple semiconductor columns 120.

[0026] The conductive layer 110 has a substantially plate-like shape that extends in the X direction. The conductive layer 110 may contain, for example, a laminated film of a barrier conductive film 111 such as titanium nitride (TiN) and a metal film 112 such as tungsten (W), as shown in Figure 5, or it may contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). In addition, a high dielectric constant insulating film 104 may be provided on the upper and lower surfaces of the conductive layer 110 and on the surface facing the semiconductor column 120. The high dielectric constant insulating film 104 may contain, for example, a metal oxide film such as aluminum oxide (AlO), hafnium oxide (HfO), or zirconium oxide (ZrO).

[0027] As shown in Figure 6, each memory cell array layer L MCA1 ,L MCA2 ,L MCA3 Each comprises a plurality of conductive layers 110 and a plurality of insulating layers 101 arranged alternately in the Z direction, and an insulating layer 102 provided above them. MCA3 An insulating layer 103 is provided above it. The insulating layers 101, 102, and 103 contain silicon oxide (SiO2), etc. For example, the thickness of insulating layers 102 and 103 in the Z direction is greater than the thickness of insulating layer 101 in the Z direction.

[0028] Multiple conductive layers 110 function as gate electrodes for the word line WL (Figure 1) and the multiple memory cells MC (Figure 1) connected thereto. In the following description, such conductive layers 110 may be referred to as conductive layer 110(WL), for example, as shown in Figure 4. Each of the multiple conductive layers 110(WL) is electrically independent for each finger structure FS. The positive and negative Y-direction sides of conductive layer 110(WL) are electrically insulated from the components in other finger structures FS via the inter-finger structure ST.

[0029] One or more conductive layers 110 located below the multiple conductive layers 110(WL) function as gate electrodes for the dummy word line DWS (Figure 1) and the multiple dummy memory cells DMS (Figure 1) connected thereto. In the following description, such conductive layers 110 may be referred to as conductive layer 110(DWS). Conductive layer 110(DWS) is configured similarly to conductive layer 110(WL).

[0030] One or more conductive layers 110 located below one or more conductive layers 110 (DWS) function as gate electrodes for the source-side selection gate line SGS (Figure 1) and multiple source-side selection transistors STS (Figure 1) connected thereto. In the following description, such conductive layers 110 may be referred to as conductive layer 110 (SGS). Conductive layer 110 (SGS) is configured similarly to conductive layer 110 (WL).

[0031] One or more conductive layers 110 located below one or more conductive layers 110 (SGS) function as gate electrodes for the source-side selection gate line SGSB (Figure 1) and the multiple source-side selection transistors STSB (Figure 1) connected thereto. In the following description, such conductive layers 110 may be referred to as conductive layer 110 (SGSB). Conductive layer 110 (SGSB) is configured similarly to conductive layer 110 (WL).

[0032] One or more conductive layers 110 located above multiple conductive layers 110(WL) function as gate electrodes for dummy word lines DWD (Figure 1) and multiple dummy memory cells DMD (Figure 1) connected thereto. In the following description, such conductive layers 110 may be referred to as conductive layers 110(DWD). Some conductive layers 110(DWD) may be configured similarly to conductive layers 110(WL). Other conductive layers 110(DWD) located above these conductive layers 110(DWD) may be configured similarly to conductive layers 110(SGD) described later. However, five conductive layers 110(DWD) aligned in the Y direction at a predetermined height within a single finger structure FS are electrically conductive to each other.

[0033] One or more conductive layers 110 located above one or more conductive layers 110 (DWD) function as gate electrodes for the drain-side selection gate wire SGD (Figure 1) and the multiple drain-side selection transistors STD (Figure 1) connected thereto. In the following description, such conductive layers 110 may be referred to as conductive layer 110 (SGD).

[0034] As shown in Figure 3, the finger structure FS includes five conductive layers 110 (SGD) aligned in the Y direction via the string unit insulating member SHE at a predetermined height position. The width of the conductive layer 110 (SGD) in the Y direction is Y SGD This is the width Y in the Y direction of the conductive layer 110 (WL). WL It is smaller than that. Each of these five conductive layers 110 (SGD) is electrically independent for each string unit SU. In each finger structure FS, the conductive layers 110 (SGD) corresponding to the 1st and 5th string units SU, counting from one side in the Y direction (e.g., the negative side in the Y direction), are electrically insulated from the components in other finger structures FS via inter-finger structures ST provided between the finger structures FS. In addition, in each finger structure FS, two adjacent conductive layers 110 (SGD) in the Y direction are electrically insulated via inter-string unit insulating members SHE.

[0035] One or more conductive layers 110 located above conductive layer 110 (SGD) function as gate electrodes for the drain-side selection gate wire SGDT (Figure 1) and the multiple drain-side selection transistors STDT (Figure 1) connected thereto. In the following description, such conductive layers 110 may be referred to as conductive layer 110 (SGDT). Conductive layer 110 (SGDT) is basically constructed in the same way as conductive layer 110 (SGD). However, five conductive layers 110 (SGDT) aligned in the Y direction at a predetermined height within a single finger structure FS are electrically conductive to each other.

[0036] The conductive layer 113 (Figure 4) may contain, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). Furthermore, a conductive layer such as a metal such as tungsten (W), a tungsten silicide, or another conductive layer may be provided on the underside of the conductive layer 113. An insulating layer 101, such as silicon oxide (SiO2), is provided between the conductive layer 113 and the conductive layer 110. An insulating layer 100, such as silicon oxide (SiO2), is also provided below the conductive layer 113.

[0037] The conductive layer 113 functions as part of the source line SL (Figure 1). The conductive layer 113 is, for example, in the memory cell array region R MCA This is a common feature for all finger structures FS included in (Figure 3).

[0038] The semiconductor columns 120 are arranged in a predetermined pattern in the X and Y directions, as shown in Figure 3, for example. For example, the finger structure FS comprises 24 semiconductor column rows SC provided from one side in the Y direction to the other side in the Y direction. Each of these 24 semiconductor column rows SC comprises multiple semiconductor columns 120 arranged in the X direction. Of these 24 semiconductor column rows SC, those located at positions 5n+1 to 5n+4 (where n is an integer between 0 and 4) from one side in the Y direction are included in the string unit SU. Furthermore, the 5th, 10th, 15th, and 20th columns are located in positions that overlap with the string unit insulating member SHE when viewed from the Z direction, and therefore do not function as devices.

[0039] The semiconductor column 120 includes, for example, polycrystalline silicon (Si). The semiconductor column 120 has a substantially cylindrical shape, as shown in Figure 4, for example, and an insulating column 127 made of silicon oxide (SiO2) or the like is provided in the central part.

[0040] The semiconductor column 120 comprises a region 121 provided at its lower end, a region 122 provided above region 121 and below the upper surface of the uppermost conductive layer 110, and a region 123 provided above region 122.

[0041] Region 121 contains N-type impurities such as phosphorus (P). Region 121 has a substantially cylindrical shape. Region 121 is connected to the conductive layer 113.

[0042] Region 122 faces multiple conductive layers 110. Region 122 functions as the channel region for memory cell MC (Figure 1), dummy memory cells DMD, DMS (Figure 1), and selection transistors STDT, STD, STS, STSB (Figure 1). Region 122 does not need to contain N-type impurities such as phosphorus (P).

[0043] Region 123 contains N-type impurities such as phosphorus (P). Region 123 is electrically connected to the bit wire BL (Figure 3), which extends in the Y direction, via contact electrodes Ch and Vy (Figure 3), which extend in the Z direction. Contact electrodes Ch and Vy may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The bit wire BL may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu).

[0044] The gate insulating film 130 comprises a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133, which are laminated between the semiconductor column 120 and the conductive layer 110, as shown in Figure 5, for example. The tunnel insulating film 131 and the block insulating film 133 contain, for example, silicon oxide (SiO2). The charge storage film 132 is a charge-storing film, for example, silicon nitride (SiN). The gate insulating film 130 has a substantially cylindrical shape and extends in the Z direction along the outer circumferential surface of the semiconductor column 120, excluding the contact portion between the semiconductor column 120 and the conductive layer 113.

[0045] The interfinger structure ST comprises, for example, interfinger electrodes 141 extending in the X and Z directions, and interfinger insulating members 142 made of silicon oxide (SiO2) or the like, provided on the Y-direction side of the interfinger electrodes 141, as shown in Figures 3 and 4. The lower end of the interfinger electrodes 141 is connected to the conductive layer 113. The upper end of the interfinger electrodes 141 is located above the upper surface of the conductive layer 110, which is the uppermost layer. The interfinger electrodes 141 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The interfinger electrodes 141 may also include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). The interfinger electrodes 141 function, for example, as part of the source wire SL (Figure 1).

[0046] The string unit insulating member SHE includes, for example, silicon oxide (SiO2). The string unit insulating member SHE is provided between two string units SU aligned in the Y direction in the memory block BLK, as shown in Figure 3, and extends in the X direction. As shown in Figure 4, the string unit insulating member SHE extends in the Z direction within a height range corresponding to the insulating layer 102, conductive layers 110 (SGDT), 110 (SGD), and some conductive layers 110 (DWD), as well as the insulating layer 101 provided on the upper and lower surfaces of these conductive layers 110, and divides these components in the Y direction.

[0047] [Hookup area R HU Internal structure] Next, referring to Figures 7 to 10, the hookup region R HU Let's explain the internal structure. Figures 7 and 8 show the hookup region R. HU This is a schematic plan view to explain the following. In Figure 7, the insulating layers 102, 103, conductive layer 110 (SGDT), etc. are omitted. Figure 8 shows the XY cross-section at the height corresponding to the conductive layer 110 (WL). Figure 9 shows the hookup region R. HU This is a schematic cross-sectional view, showing the structure shown in Figures 7 and 8 cut along the DD' line and viewed along the direction of the arrow. Figure 10 shows the hook-up region R HU This is a schematic cross-sectional view, showing an enlarged portion of Figure 9.

[0048] Figure 7 illustrates the hookup region R. HU This is the bridge region R BRD and multiple terrace regions R T It is equipped with the following.

[0049] Bridge region R BRD The conductive layers 110(WL), 110(DWD), 110(DWS), 110(SGS), and 110(SGSB) are provided. As illustrated in Figures 8 and 9, the conductive layers 110(WL), 110(DWD), 110(DWS), 110(SGS), and 110(SGSB) form a bridge region R BRD In the hookup region R HU It extends in the X direction from one end to the other end in the X direction.

[0050] Terrace area R T Multiple conductive layers 110 are provided in the Z direction, corresponding to the bridge region R BRD These are provided on one side in the Y direction. T Each of these comprises a corresponding terrace portion T of the conductive layer 110. The terrace portion T is, for example, a portion that does not overlap with other conductive layers 110 when viewed from above. The terrace portion T is covered by an insulating layer 102, as shown in Figure 9. In this embodiment, for example, as shown in Figure 10, the thickness Z in the Z direction of the terrace portion T of the conductive layer 110 is 110TThis refers to the thickness Z in the Z direction of the portion of the conductive layer 110 that is different from the terrace portion T. 110O It is larger than that.

[0051] Also, the hookup region R HU Multiple support insulating columns HR are provided. The support insulating columns HR may, for example, contain silicon oxide (SiO2), or may have a configuration corresponding to the semiconductor column 120, insulating column 127, and gate insulating film 130. As shown in Figure 9, the support insulating columns HR are connected to three memory cell array layers L MCA1 ,L MCA2 ,L MCA3 It extends in the Z direction over [a certain distance]. The outer surface of the support insulating column HR is surrounded by an insulating layer 102, and through holes provided in a plurality of conductive layers 110 and a plurality of insulating layers 101. In the illustrated example, the lower end of the support insulating column HR is covered by an oxide layer ox provided between the conductive layer 113 and the lower end of the support insulating column HR.

[0052] The support insulating columns HR are arranged in a predetermined pattern in the X and Y directions, as shown in Figure 7, for example. For example, the finger structure FS comprises 10 rows of support insulating columns HC extending from one side in the Y direction to the other side in the Y direction. Each of these 10 rows of support insulating columns HC comprises multiple support insulating columns HR arranged in the X direction. Note that in the illustrated example, the terrace region R T In some of the support insulation column rows HC located at the corresponding positions, some of the support insulation columns HR are omitted, and instead, contact electrodes CC are provided.

[0053] Each contact electrode CC is provided corresponding to multiple terraces T. As shown in Figure 9, the contact electrode CC is located in three memory cell array layers L MCA1 ,L MCA2 ,L MCA3 It extends in the Z direction over [a certain distance]. The upper end of contact electrode CC is connected to contact electrode Ch.

[0054] The contact electrode CC consists of three memory cell array layers L MCA1 ,LMCA2 ,L MCA3 It comprises three hierarchical sections cc1, cc2, and cc3 aligned in the Z direction. For example, each of the hierarchical sections cc1, cc2, and cc3 expands in diameter from its lower end upwards. That is, the width in the X and Y directions (diameter and cross-sectional area in the XY cross-section) at the upper end of the hierarchical sections cc1, cc2, and cc3 is greater than the width in the X and Y directions (diameter and cross-sectional area in the XY cross-section) at the lower end of the hierarchical sections cc1, cc2, and cc3. In addition, the memory cell array layer L MCA1 ,L MCA2 ,L MCA3 At the boundary, the diameter (and cross-sectional area) of the lower portion of the contact electrode CC is larger than the diameter (and cross-sectional area) of the upper portion, and the three hierarchical parts cc1, cc2, and cc3 of the contact electrode CC are formed with discontinuous shapes on their sides at these hierarchical boundaries.

[0055] Furthermore, the hierarchical sections cc1, cc2, and cc3 may have a bowing shape in which their width in the X and Y directions (diameter and cross-sectional area in the XY cross-section) is maximized at the height position between their upper and lower ends. Here, the memory cell array layer L MCA1 ,L MCA2 ,L MCA3 At the boundary, the diameter (and cross-sectional area) of the lower part of the contact electrode CC and the diameter (and cross-sectional area) of the upper part may be approximately equal. Even with such a configuration, the three hierarchical parts cc1, cc2, and cc3 of the contact electrode CC have discontinuous shapes on their sides at their hierarchical boundaries.

[0056] Furthermore, the contact electrode CC is provided at a height corresponding to the terrace portion T of the corresponding conductive layer 110, and the connection region R is in contact with the terrace portion T of the conductive layer 110. C And, the connection region R C A drawer region R is provided above and extends in the Z direction. L And, the connection region R C A penetrating region R is provided below and extends in the Z direction. TH And, it comprises. For example, Figure 9 shows a memory cell array layer L MCA2The contact electrode CC corresponding to the conductive layer 110 inside is shown. The connection region R of this contact electrode CC. C The memory cell array layer L MCA2 It is located inside. Connection area R C The outer surface is in contact with the conductive layer 110. Draw-out region R L The outer surface is surrounded by through holes provided in the insulating layer 102. Through-hole region R TH The outer surface is surrounded by through holes provided in multiple conductive layers 110 and multiple insulating layers 101.

[0057] Furthermore, the contact electrode CC consists of three memory cell array layers L MCA1 ,L MCA2 ,L MCA3 A conductive member 151 extending in the Z direction and three memory cell array layers L MCA1 ,L MCA2 ,L MCA3 The device comprises an insulating column 152 extending in the Z direction and having its outer surface covered by a conductive member 151, and a conductive member 153 provided at the upper end of the contact electrode CC, with its outer surface in contact with the conductive member 151 and its upper surface in contact with the contact electrode Ch.

[0058] Connection area R of conductive member 151 C The outer surface of the portion provided is in contact with the conductive layer 110. The lead-out region R of the conductive member 151 L The portion provided extends in the Z direction, penetrating the insulating layer 102. Penetration region R of the conductive member 151 TH The portion provided extends in the Z direction, penetrating multiple conductive layers 110 aligned in the Z direction. Also, the penetrating region R of the conductive member 151 THOn the outer peripheral surface of the portion provided in [the relevant part], a plurality of insulating layers 108 arranged in the Z direction corresponding to the plurality of conductive layers 110 are provided. The conductive member 151 is insulated from the plurality of conductive layers 110 through these plurality of insulating layers 108. The insulating layer 108 may contain silicon oxide (SiO2) or the like. Also, in the illustrated example, the lower end portion of the conductive member 151 is provided below the upper surface of the conductive layer 113, and the lower end portion of the conductive member 151 is covered by an oxide layer ox provided between the conductive layer 113 and the lower end portion of the conductive member 151. The conductive member 151 is insulated from the conductive layer 113 through this oxide layer ox. The oxide layer ox may contain silicon oxide (SiO2) or the like.

[0059] The conductive member 151 includes, for example, as shown in FIG. 10, a barrier conductive film 154 extending in the Z direction, and a metal film 155 extending in the Z direction, the outer peripheral surface and the lower end portion of which are covered by the barrier conductive film 154 and which is in contact with the barrier conductive film 154. The barrier conductive film 154 may contain, for example, titanium nitride (TiN), tantalum nitride (TaN), or the like. The metal film 155 may contain, for example, tungsten (W), molybdenum (Mo), ruthenium (Ru), or the like. The barrier conductive film 154 and the metal film 155 extend in the Z direction over the extraction region R L , the connection region R C and the through region R TH .

[0060] The portions of the barrier conductive film 154 and the metal film 155 provided in the extraction region R L , the connection region R C and the through region R TH are each formed in a substantially cylindrical shape. In FIG. 10, the widths (diameters in the XY cross-section) of the portions of the barrier conductive film 154 and the metal film 155 provided in the connection region R C in the X direction and the Y direction are shown as widths W RC154 , W RC155 respectively. Similarly, the widths (diameters in the XY cross-section) of the portions of the extraction region R L in the X direction and the Y direction are shown as widths W RL154 , W RL155is shown as such. Similarly, for the through region R TH the widths in the X and Y directions (diameter in the XY cross-section) of the portion provided in are, respectively, width W RTH154 ,W RTH155 is shown as such. Width W RC154 is RL154 ,W RTH154 larger than. Width W RC155 is RL155 ,W RTH155 larger than.

[0061] The insulating column 152 may contain, for example, silicon oxide (SiO2) or the like. The insulating column 152 extends in the Z direction across the extraction region R L , the connection region R C and the through region R TH . The upper end portion of the insulating column 152 is covered by the conductive member 153 and is in contact with the conductive member 153 (more specifically, the barrier conductive film 156 described later). The lower end portion and the outer peripheral surface of the insulating column 152 are covered by the conductive member 151 and are in contact with the conductive member 151 (more specifically, the metal film 155).

[0062] The portions of the insulating column 152 provided in the extraction region R L , the connection region R C and the through region R TH are each formed in a substantially cylindrical shape. In FIG. 10, the widths in the X and Y directions (diameter in the XY cross-section) of the portion of the insulating column 152 provided in the connection region R C are shown as width W RC152 . Similarly, the widths in the X and Y directions (diameter in the XY cross-section) of the portion provided in the extraction region R L are shown as width W RL152 . Similarly, the widths in the X and Y directions (diameter in the XY cross-section) of the portion provided in the through region R TH are shown as width W RTH152 . Width W RC152 is RL152 ,W RTH152 larger than.

[0063] The conductive member 153 comprises a barrier conductive film 156 extending in the Z direction, and a metal film 157 extending in the Z direction, with its outer surface and lower end covered by the barrier conductive film 156 and in contact with the barrier conductive film 156. The barrier conductive film 156 may contain, for example, titanium nitride (TiN), tantalum nitride (TaN), etc. The metal film 157 may contain, for example, tungsten (W), molybdenum (Mo), ruthenium (Ru), etc.

[0064] [Manufacturing method] Next, a method for manufacturing a semiconductor memory device according to the first embodiment will be described with reference to Figures 11 to 59. Figures 11 to 57 are schematic cross-sectional views illustrating the manufacturing method. Figures 11, 14, 15, 30, and 42 to 50 show cross-sections corresponding to Figure 4. Figures 12, 13, 16 to 23, 26, 27, 31 to 35, 40, 41, and 51 show cross-sections corresponding to Figure 9. Figures 24, 25, 28, and 29 show cross-sections corresponding to Figure 6. Figures 36 to 39 and 52 to 59 show cross-sections corresponding to Figure 10.

[0065] In manufacturing the semiconductor memory device according to this embodiment, an insulating layer 100 is formed on top of a semiconductor substrate (not shown), for example, as shown in Figure 11. Next, a semiconductor layer 113A such as silicon, a sacrificial layer 113B such as silicon oxide, a sacrificial layer 113C such as silicon, a sacrificial layer 113D such as silicon oxide, and a semiconductor layer 113E such as silicon are formed on the insulating layer 100. MCA1 Multiple insulating layers 101 and multiple sacrificial layers 110A are alternately formed corresponding to the memory cell array layer L. The sacrificial layer 110A includes, for example, silicon nitride (SiN). MCA1 A portion of the corresponding insulating layer 102 is formed. This process is carried out, for example, by a method such as CVD (Chemical Vapor Deposition).

[0066] Next, although not shown in the diagram, the hookup region R HU Multiple terrace areas R within TIn this step, the insulating layer 102, a plurality of insulating layers 101, and a portion of the plurality of sacrificial layers 110A are removed to form a plurality of terrace portions TA (see Figure 17). The terrace portions TA are, for example, portions of the sacrificial layer 110A that do not overlap with other sacrificial layers 110A when viewed from above. In this step, for example, the memory cell array layer L MCA1 A resist is formed on the upper surface of the corresponding insulating layer 102. Furthermore, the removal of the sacrificial layer 110A, the removal of the insulating layer 101, and the removal of a portion of the resist are repeatedly performed. The resist is removed by isotropic etching, such as wet etching.

[0067] Next, although not shown in the diagram, the terrace portion TA is thickened using a method described later, for example, referring to Figures 18 to 20.

[0068] Next, although the diagram is omitted, the memory cell array layer L MCA1 A portion of the corresponding insulating layer 102 is formed. This step is carried out, for example, by a method such as CVD.

[0069] Next, as shown in Figure 12, for example, via holes HRA are formed at positions corresponding to the support insulating column HR. Contact holes CCA are also formed at positions corresponding to the contact electrode CC. Furthermore, grooves STA are formed at positions corresponding to the inter-finger structure ST. These via holes HRA, contact holes CCA, and grooves STA extend in the Z direction, forming the memory cell array layer L. MCA1 The insulating layer 102, as well as the insulating layer 101 and the sacrificial layer 110A, are penetrated to expose the upper surface of the semiconductor layer 113E. This process is carried out, for example, by a method such as RIE (Reactive Ion Etching).

[0070] Next, the semiconductor layer 113E is oxidized at the bottom surfaces of the via hole HRA, contact hole CCA, and groove STA to form an oxide layer ox. In this step, polycrystalline silicon is selectively oxidized without oxidizing silicon nitride, for example, by a method such as thermal oxidation treatment.

[0071] Next, as shown in Figure 13, for example, the memory cell array layer L MCA1 At the corresponding height positions, sacrificial films HRB, CCB, and STB made of polycrystalline silicon are formed in the via hole HRA, contact hole CCA, and groove STA. This process is carried out by methods such as CVD.

[0072] Next, as shown in Figure 14, for example, memory holes MH are formed at positions corresponding to the semiconductor pillars 120. These memory holes MH extend in the Z direction and form the memory cell array layer L MCA1 The insulating layer 102, insulating layer 101, and sacrificial layer 110A, as well as the semiconductor layer 113E, sacrificial layer 113D, sacrificial layer 113C, and sacrificial layer 113B, are penetrated, and the upper surface of the semiconductor layer 113A is exposed. This process is carried out, for example, by a method such as RIE.

[0073] Next, as shown in Figure 15, for example, the memory cell array layer L MCA1 A sacrificial film 120A is formed inside the memory hole MH at the corresponding height position. This process is carried out by, for example, a method such as CVD.

[0074] Next, as shown in Figure 16, for example, the memory cell array layer L MCA2 Multiple insulating layers 101 and multiple sacrificial layers 110A corresponding to are formed alternately. Also, the memory cell array layer L MCA2 A portion of the corresponding insulating layer 102 is formed. This step is carried out, for example, by a method such as CVD.

[0075] Next, as shown in Figure 17, for example, the hookup region R HU Multiple terrace areas R within T In this process, the insulating layer 102, a portion of the multiple insulating layers 101, and a portion of the multiple sacrificial layers 110A are removed to form multiple terrace portions TA. In this process, for example, the memory cell array layer L MCA2 A resist is formed on the upper surface of the corresponding insulating layer 102. Furthermore, the removal of the sacrificial layer 110A, the removal of the insulating layer 101, and the removal of a portion of the resist are repeated. The removal of the resist is performed by isotropic etching, such as wet etching.

[0076] Next, as shown in Figure 18, for example, the memory cell array layer L MCA2 Sacrificial layers 110A' and insulating layers 101' are formed on the upper surface of the insulating layer 102, the upper surface of the terrace portion TA, and on the sides of the multiple sacrificial layers 110A and insulating layer 101 that are formed together with the terrace portion TA. Sacrificial layer 110A' includes, for example, silicon nitride (SiN). The portion of sacrificial layer 110A' formed on the upper surface of the terrace portion TA becomes part of the terrace portion TA, thereby thickening the terrace portion TA of sacrificial layer 110A. Insulating layer 101' includes, for example, silicon oxide (SiO2). MCA2 The film thickness of the portion formed on the upper surface of the insulating layer 102 and the upper surface of the terrace portion TA is greater than the film thickness of the portion formed on the side surfaces of the multiple sacrificial layers 110A and the insulating layer 101. This process is carried out by a method such as CVD.

[0077] Next, as shown in Figure 19, for example, a portion of the insulating layer 101' is removed to expose the portion of the sacrificial layer 110A' formed on the multiple sacrificial layers 110A and the above-mentioned side surface of the insulating layer 101. In this step, the insulating layer 101', memory cell array layer L MCA2 The upper surface of the corresponding insulating layer 102 and the portion formed on the upper surface of the terrace portion TA are left intact. This process is carried out, for example, by a method such as wet etching.

[0078] Next, as shown in Figure 20, for example, a portion of the sacrificial layer 110A' is removed to expose the aforementioned sides of the multiple sacrificial layers 110A and the insulating layer 101. In this step, the thickened terrace portions TA are separated from the other terrace portions TA and the sacrificial layer 110A. This step is performed, for example, by a method such as wet etching.

[0079] Next, as shown in Figure 21, for example, the memory cell array layer L is subjected to a method such as CVD. MCA2A portion of the insulating layer 102 corresponding to this is formed. In addition, the insulating layer 102 is planarized by methods such as CMP (Chemical Mechanical Polishing), and the portions of the insulating layer 101' and the sacrificial layer 110A' that were formed on the upper surface of the insulating layer 102 in the process described with reference to Figure 18 are removed.

[0080] Next, as shown in Figure 22, for example, via holes HRA are formed at positions corresponding to the support insulating column HR. Contact holes CCA are also formed at positions corresponding to the contact electrode CC. Furthermore, grooves STA are formed at positions corresponding to the inter-finger structure ST. These via holes HRA, contact holes CCA, and grooves STA extend in the Z direction, forming the memory cell array layer L. MCA2 The insulating layer 102 corresponds to the insulating layer 101 and the sacrificial layer 110A, and the memory cell array layer L penetrates through the insulating layer 101 and the sacrificial layer 110A. MCA1 The upper ends of the sacrificial films HRB, CCB, and STB, which are positioned at the corresponding height, are exposed. This process is carried out, for example, by a method such as RIE.

[0081] Next, as shown in Figure 23, for example, the memory cell array layer L MCA2 At the corresponding height positions, sacrificial films HRB, CCB, and STB made of polycrystalline silicon are formed in the via hole HRA, contact hole CCA, and groove STA. This process is carried out by methods such as CVD.

[0082] Next, as shown in Figure 24, for example, memory holes MH are formed at positions corresponding to the semiconductor pillars 120. These memory holes MH extend in the Z direction and form the memory cell array layer L MCA2 The insulating layer 102 corresponds to the insulating layer 101 and the sacrificial layer 110A, and the memory cell array layer L penetrates through the insulating layer 101 and the sacrificial layer 110A. MCA1 The upper surface of the sacrificial film 120A, which is positioned at the corresponding height, is exposed. This step is performed, for example, by a method such as RIE.

[0083] Next, as shown in Figure 25, for example, the memory cell array layer L MCA2A sacrificial film 120A is formed inside the memory hole MH at the corresponding height position. This process is carried out by, for example, a method such as CVD.

[0084] Next, as shown in Figure 26, for example, the memory cell array layer L MCA3 Multiple insulating layers 101 and multiple sacrificial layers 110A corresponding to are formed alternately. Also, the memory cell array layer L MCA3 A portion of the corresponding insulating layer 102 is formed. This step is carried out, for example, by a method such as CVD.

[0085] Next, although not shown in the diagram, the hookup region R HU Multiple terrace areas R within T In this step, a portion of the insulating layer 102, the multiple insulating layers 101, and the multiple sacrificial layers 110A is removed to form multiple terrace portions TA (see Figure 17). This step is performed, for example, in the same manner as the step described with reference to Figure 17.

[0086] Next, although not shown in the diagram, the terrace portion TA is thickened using a method such as the one described with reference to Figures 18 to 20.

[0087] Next, as shown in Figure 27, for example, the memory cell array layer L MCA3 A portion of the corresponding insulating layer 102 is formed. This step is carried out, for example, by a method such as CVD.

[0088] Next, as shown in Figure 28, for example, memory holes MH are formed at positions corresponding to the semiconductor pillars 120. These memory holes MH extend in the Z direction and form the memory cell array layer L MCA3 The insulating layer 102 corresponds to the insulating layer 101 and the sacrificial layer 110A, and the memory cell array layer L penetrates through the insulating layer 101 and the sacrificial layer 110A. MCA2 The upper surface of the sacrificial film 120A, which is positioned at the corresponding height, is exposed. This step is performed, for example, by a method such as RIE.

[0089] Next, as shown in Figure 29, for example, the memory cell array layer L MCA1 ,L MCA2The sacrificial film 120A, which is located at the corresponding height position, is removed. This process is carried out, for example, by wet etching.

[0090] Next, as shown in Figure 30, for example, the memory cell array layer L MCA1 ,L MCA2 ,L MCA3 At the corresponding height position, an insulating film 130A, a semiconductor column 120B, and an insulating column 127 are formed inside the memory hole MH. The insulating film 130A is basically configured the same way as the gate insulating film 130, but it also covers the outer surface of the semiconductor column 120B at the height positions of the sacrificial layers 113B, 113C, and 113D. The semiconductor column 120B is basically configured the same way as the semiconductor column 120, but a region 121 containing N-type impurities is not formed at its lower end. This process is carried out by a method such as CVD.

[0091] Next, although the diagram is omitted, the memory cell array layer L MCA3 A portion of the insulating layer 102 corresponding to this is formed. Through this process, the upper surface of the internal structure of the memory hole MH (insulating film 130A, semiconductor column 120B, and insulating column 127) is covered by a portion of the insulating layer 102. This process is carried out, for example, by a method such as CVD.

[0092] Next, as shown in Figure 31, for example, via holes HRA are formed at positions corresponding to the support insulating column HR. Contact holes CCA are also formed at positions corresponding to the contact electrode CC. Furthermore, grooves STA are formed at positions corresponding to the inter-finger structure ST. These via holes HRA, contact holes CCA, and grooves STA extend in the Z direction, forming the memory cell array layer L. MCA3 The insulating layer 102, insulating layer 101, and sacrificial layer 110A are penetrated, and the memory cell array layer L MCA2 The upper ends of the sacrificial films HRB, CCB, and STB, which are positioned at the corresponding height, are exposed. This process is carried out, for example, by a method such as RIE.

[0093] Next, as shown in Figure 32, for example, the memory cell array layer L MCA3At the corresponding height positions, sacrificial films HRB, CCB, and STB made of polycrystalline silicon are formed in the via hole HRA, contact hole CCA, and groove STA. This process is carried out by methods such as CVD.

[0094] Next, as shown in Figure 33, for example, the memory cell array layer L MCA1 ,L MCA2 ,L MCA3 The sacrificial film HRB located at the corresponding height position is removed. This step is performed, for example, by a method such as wet etching.

[0095] Next, as shown in Figure 34, for example, the memory cell array layer L MCA1 ,L MCA2 ,L MCA3 At the corresponding height position, a support insulating column HR is formed in the via hole HRA. This process is carried out, for example, by a method such as CVD.

[0096] Next, as shown in Figures 35 and 36, for example, the memory cell array layer L MCA1 ,L MCA2 ,L MCA3 The sacrificial film CCB located at the corresponding height position is removed. This step is performed, for example, by a method such as wet etching.

[0097] Next, as shown in Figure 37, for example, a portion of the sacrificial layer 110A is removed from the inner circumferential surface of the contact hole CCA. This creates multiple recesses 108A at positions corresponding to multiple insulating layers 108. Also, the connection region R C (Figure 10) The recess R is located at the corresponding position. C A is formed. This process is carried out, for example, by wet etching.

[0098] Next, as shown in Figure 38, for example, the memory cell array layer L MCA3An insulating layer 108B is formed on the upper surface of the insulating layer 102 corresponding to the recess R, and on the inner circumferential surface of the multiple contact holes CCA. In this case, the thickness of the insulating layer 108B is greater than half the width of the recess 108A in the Z direction (the thickness of the sacrificial layer 110A in the Z direction). Therefore, the recess 108A is filled by the insulating layer 108B. On the other hand, the thickness of the insulating layer 108B is greater than half the width of the recess R C The size is less than half the width of A in the Z direction (the thickness of the terrace portion TA of the sacrificial layer 110A in the Z direction). Therefore, the recess R C A is not filled by the insulating layer 108B. Furthermore, the thickness of the insulating layer 108B is smaller than the radius of the contact hole CCA. Therefore, the contact hole CCA is also not filled by the insulating layer 108B. This process is carried out, for example, by a method such as CVD.

[0099] Next, as shown in Figure 39, for example, a portion of the insulating layer 108B is removed. In this step, the memory cell array layer L of the insulating layer 108B is removed. MCA3 The portions formed on the upper surface of the insulating layer 102, the side surface of the insulating layer 102, the side surfaces of the multiple insulating layers 101, and the side surfaces of the terrace portion TA of the sacrificial layer 110A are removed. As a result, the upper surface of the insulating layer 102, the side surface of the insulating layer 102, the side surfaces of the multiple insulating layers 101, and the side surfaces of the terrace portion TA of the sacrificial layer 110A are exposed inside the contact hole CCA. This process is performed, for example, by wet etching. In this process, multiple insulating layers 108 are formed at positions corresponding to the multiple recesses 108A.

[0100] Next, as shown in Figure 40, for example, the memory cell array layer L MCA1 ,L MCA2 ,L MCA3 At the corresponding height position, a sacrificial layer CCD is formed inside the contact hole CCA. This process is carried out, for example, by a method such as CVD.

[0101] Next, as shown in Figures 41 and 42, for example, the memory cell array layer L MCA1 ,L MCA2 ,L MCA3The sacrificial film STB, located at the corresponding height position, is removed. This step is performed, for example, by a method such as wet etching.

[0102] Next, as shown in Figure 43, for example, a protective film STSW is formed on the inner wall and bottom surface of the groove STA by a method such as CVD. Furthermore, the oxide layer ox, semiconductor layer 113E, and sacrificial layer 113D are removed from the bottom surface of the groove STA by a method such as RIE, exposing the sacrificial layer 113C.

[0103] Next, as shown in Figure 44, for example, the sacrificial layer 113B, sacrificial layer 113C, sacrificial layer 113D, and a portion of the gate insulating film 130 are removed. This step is performed by a method such as wet etching. In this step, the gate insulating film 130 is formed.

[0104] Next, a conductive layer 113 is formed, for example, as shown in Figure 45. This step is carried out by a method such as epitaxial growth. In this step, the semiconductor column 120 is formed by diffusing N-type impurities into the lower end of the semiconductor column 120B.

[0105] Next, the protective film STSW is removed, for example, as shown in Figure 46. This step is performed by a method such as wet etching.

[0106] Next, as shown in Figure 47, for example, the sacrificial layer 110A is removed through the groove STA to form multiple voids 110B. This forms a hollow structure including multiple insulating layers 101 and 102 aligned in the Z direction, the structure within the memory hole MH that supports them (semiconductor column 120, gate insulating film 130, and insulating column 127), and the supporting insulating column HR. This process is carried out by a method such as wet etching.

[0107] Next, a conductive layer 110 is formed in the void 110B, for example, as shown in Figure 48. This step is carried out by a method such as CVD. In this step, before forming the conductive layer 110, a high dielectric constant insulating film 104, as explained with reference to Figure 5, is formed.

[0108] Next, as shown in Figure 49, for example, an inter-finger structure ST is formed within the groove STA. This step is carried out by methods such as CVD and RIE.

[0109] Next, as shown in Figure 50, for example, an insulating member SHE between string units is formed. This process is carried out by methods such as RIE and CVD.

[0110] Next, the sacrificial CCD is removed, for example, as shown in Figures 51 and 52. This step is performed by a method such as wet etching.

[0111] Next, as shown in Figure 53, for example, recess R C In A, the high dielectric constant insulating film 104 is removed. This removes the recess R C At A, the side surface of the conductive layer 110 is exposed. This step is performed, for example, by a method such as wet etching.

[0112] Next, as shown in Figure 54, for example, the memory cell array layer L MCA3 The upper surface of the insulating layer 102 and the memory cell array layer L corresponding to this layer MCA1 ,L MCA2 ,L MCA3 A barrier conductive film 154A, a metal film 155A, and an insulating layer 152A are formed inside the contact hole CCA located at a corresponding height position. This process is carried out by methods such as CVD. The metal film 155A is formed by methods such as CVD using tungsten hexafluoride (WF6).

[0113] Next, as shown in Figure 55, for example, among the insulating layer 152A, the memory cell array layer L MCA3 The portion covering the upper surface of the corresponding insulating layer 102, and the portion located in the region near the upper end of the contact hole CCA are removed. This process forms the insulating column 152. This process is carried out, for example, by a method such as RIE.

[0114] Next, as shown in Figure 56, for example, the memory cell array layer LMCA3 The insulating layer 102 and the memory cell array layer L are located above the corresponding insulating layer 102. MCA3 In the region near the upper end of the corresponding contact hole CCA, a barrier conductive film 156A and a metal film 157A are formed on the upper surface and inner circumferential surface of the metal film 155A. This process is carried out by, for example, a method such as CVD.

[0115] Next, as shown in Figure 57, for example, a portion of the barrier conductive film 154A, metal film 155A, barrier conductive film 156A, and metal film 157A is removed, and the memory cell array layer L MCA3 The upper surface of the corresponding insulating layer 102 is exposed. This process forms the contact electrode CC. This process is carried out by, for example, a method such as CMP.

[0116] Next, as shown in Figure 58, for example, the memory cell array layer L MCA3 An insulating layer 103 is formed on the corresponding insulating layer 102 and the upper surface of the contact electrode CC. This process is carried out, for example, by CVD.

[0117] Next, as shown in Figure 59, for example, a contact hole ChA is formed at a position corresponding to the contact electrode Ch. The contact hole ChA extends in the Z direction, penetrates the insulating layer 103, and exposes the upper surface of the contact electrode CC, for example, the upper surface of the metal film 157. This step is performed by a method such as RIE.

[0118] Subsequently, a contact electrode Ch is formed inside the contact hole ChA, thereby creating the structure shown in Figure 10. Furthermore, by forming bit lines BL and the like, the semiconductor memory device according to the first embodiment is formed.

[0119] [effect] With the increasing integration of semiconductor memory devices, the number of conductive layers 110 (Figure 4) aligned in the Z direction is increasing. Consequently, the aspect ratio of the contact electrode CC (the ratio of the length in the Z direction to the diameter in the XY cross-section) is also increasing. To form a contact electrode CC with a large aspect ratio, it is conceivable to form a contact hole with a large aspect ratio using a method such as RIE, and then form a metal film inside this contact hole using a method such as CVD.

[0120] In the manufacturing method according to the first embodiment, the contact hole CCA is formed in three separate steps: the step described with reference to Figure 12, the step described with reference to Figure 22, and the step described with reference to Figure 31. Such a method is easier to implement than forming contact holes with a large aspect ratio all at once.

[0121] Furthermore, if such a method is adopted, the contact hole CCA formed in the process described with reference to Figure 12, the process described with reference to Figure 22, and the process described with reference to Figure 31 may be formed in a shape that expands in diameter from the lower end upwards, for example. As a result, the contact electrode CC according to this embodiment may have three tiered sections cc1, cc2, and cc3 (Figure 9) that expand in diameter from bottom to top.

[0122] Furthermore, in this embodiment, the contact electrode CC connected to the conductive layer 110 is not located at the lower end, but rather in a connection region R formed between the upper and lower ends. C It comes into contact with the conductive layer 110.

[0123] Here, in order to form a contact electrode connected to the conductive layer 110 at the lower end, one could consider, for example, forming a contact hole after the conductive layer 110 is formed and using the terrace portion T of the conductive layer 110 as an etching stopper. However, the height positions of the multiple terrace portions T corresponding to the multiple conductive layers 110 are all different. Therefore, in such a method, relatively early after the formation of the contact hole begins, the upper surface of the terrace portion T located relatively high up is exposed to the bottom of the contact hole. Such a terrace portion T continues to be exposed to the RIE gas until the upper surface of the terrace portion T located relatively low down is exposed to the bottom of the contact hole. As a result, there is a concern that the contact hole may penetrate the terrace portion T. Consequently, there is a risk that two or more conductive layers 110 aligned in the Z direction may be short-circuited via the contact electrode.

[0124] In this regard, the contact electrode CC according to the first embodiment has a structure that assumes the contact hole CCA penetrates multiple conductive layers 110 during manufacturing, and can suppress short circuits between the conductive layers 110 via the contact electrode CC.

[0125] Furthermore, as a result of adopting this structure, the contact electrode CC according to this embodiment has a connection region R in contact with the conductive layer 110, as explained with reference to Figure 10. C And, the connection region R C A drawer area R located above L And, the connection region R C Penetration area R located below TH And, it will be equipped with. Also, the connection region R C The width W of the contact electrode CC in RC154 However, the drawer area R L and penetration area R TH The width W of the contact electrode CC in RL154 ,W RTH154 It will become larger than that.

[0126] Here, for example, in the process described with reference to Figure 54, if the insulating layer 152A is not formed and the contact hole CCA is to be filled with the metal film 155A, there is a possibility that a void will be formed inside the contact hole CCA. For example, the contact electrode CC according to this embodiment has three layered sections cc1, cc2, and cc3 (Figure 9) that expand in diameter from bottom to top, so it is conceivable that the contact hole CCA may be blocked at the lower ends of the layered sections cc2 and cc3, and CVD gas will no longer be supplied to the inside of the layered sections cc1 and cc2, thus forming a void inside the layered sections cc1 and cc2. Also, if the position of the contact hole CCA formed in each process described with reference to Figures 12, 22, and 31 is shifted by a certain amount or more, even if the three layered sections cc1, cc2, and cc3 do not expand in diameter from bottom to top, it is conceivable that the contact hole CCA may be blocked at the boundary between layered sections cc3 and cc2, or at the boundary between layered sections cc2 and cc1, and a void may be formed inside the layered sections cc1 and cc2. Furthermore, for example, the connection region R C Because it has a relatively large volume, the extraction region R is created before this part is embedded. L The metal film 155A is embedded, and the connection region R C It is also possible that voids may form inside it.

[0127] As explained with reference to Figure 54, if the metal film 155A is formed by a method such as CVD using tungsten hexafluoride (WF6), fluorine gas remains in the void inside the contact hole CCA. This can cause a portion of the insulating layer 101 to be removed, potentially leading to a decrease in insulation between the two conductive layers 110 aligned in the Z direction.

[0128] Therefore, in this embodiment, in the process described with reference to Figure 54, the contact hole CCA is filled with an insulating layer 152A instead of a metal film 155A. With this method, even if a void is formed inside the contact hole CCA, it is possible to suppress the retention of fluorine gas. Accordingly, it is possible to suitably suppress the decrease in insulating properties between the two conductive layers 110 aligned in the Z direction.

[0129] Furthermore, in this embodiment, in the process described with reference to Figures 55 to 57, a conductive member 153 is formed on the upper part of the insulating column 152. With this configuration, in the process described with reference to Figure 59, the upper surface of the contact electrode CC is exposed on the bottom surface of the contact hole ChA, making it possible to suitably connect the contact electrode Ch and the contact electrode CC.

[0130] Furthermore, in this embodiment, the outer circumferential surface of the conductive member 153 is in contact with the inner circumferential surface of the conductive member 151. With this configuration, it is possible to increase the area of ​​the metal film 155 that is in contact with the metal film 157 via the barrier conductive film 156. This makes it possible to form a low-resistance contact electrode CC.

[0131] [Second Embodiment] The contact electrode CC according to the first embodiment includes a conductive member 151 extending in the Z direction, an insulating column 152 extending in the Z direction with its outer circumferential surface covered by the conductive member 151, and a conductive member 153 provided at the upper end of the contact electrode CC with its outer circumferential surface in contact with the conductive member 151. Furthermore, the conductive member 151 includes a barrier conductive film 154 and a metal film 155, and the conductive member 153 includes a barrier conductive film 156 and a metal film 157.

[0132] However, this configuration is merely illustrative, and the film configurations of the conductive member 151, insulating column 152, and conductive member 153 can be adjusted as appropriate. Below, as a second embodiment, a contact electrode CC2 having a different film configuration from the contact electrode CC will be described.

[0133] Figure 60 is a schematic cross-sectional view of a semiconductor memory device according to the second embodiment. In the following description, components similar to those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0134] The semiconductor memory device according to the second embodiment is basically configured the same as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the second embodiment includes a contact electrode CC2 instead of a contact electrode CC.

[0135] The contact electrode CC2 according to the second embodiment is basically configured the same as the contact electrode CC according to the first embodiment. However, the contact electrode CC2 includes a conductive member 251 instead of the conductive member 151.

[0136] The conductive member 251 is basically configured in the same way as the conductive member 151. However, in addition to the barrier conductive film 154 and the metal film 155, the conductive member 251 further comprises a barrier conductive film 254. The barrier conductive film 254 is stretched in the Z direction, and its outer surface and lower end are covered by the metal film 155 and are in contact with the metal film 155. The barrier conductive film 254 may contain, for example, titanium nitride (TiN), tantalum nitride (TaN), etc. The barrier conductive film 254 has an extraction region R L , connection region R C and penetration area R TH It extends in the Z direction over (see Figure 9).

[0137] Extraction region R of the barrier conductive film 254 L , connection region R C and penetration area R TH The portions provided therein are each formed in a roughly cylindrical shape. Figure 60 shows the connection region R of the barrier conductive film 254. C The width of the portion provided in the X and Y directions (diameter in the XY cross-section) is defined as width W. RC254 It is shown as follows. Similarly, the drawout region R L The width of the portion provided in the X and Y directions (diameter in the XY cross-section) is defined as width W. RL254 It is shown as follows. Similarly, through region R TH The width of the portion provided in the X and Y directions (diameter in the XY cross-section) is defined as width W. RTH254 It is shown as width W. RC254 is width W RL254 ,W RTH254Larger.

[0138] In the second embodiment, the lower end and outer surface of the insulating column 152 are in contact with the conductive member 251 (more specifically, the barrier conductive film 254).

[0139] This embodiment can also achieve the same effects as the semiconductor memory device according to the first embodiment. Furthermore, with this configuration, the risk of abnormal oxidation of the metal film 155 caused by oxygen in the insulating column 152 can be suppressed.

[0140] [Third Embodiment] As described above, the film configurations of the conductive member 151, the insulating column 152, and the conductive member 153 can be adjusted as appropriate. In the second embodiment, an example was described in which the contact electrode CC2 includes a conductive member 251 with a different film configuration from the conductive member 151 of the contact electrode CC. Hereinafter, as a third embodiment, a contact electrode CC3 having a film configuration even different from that of the contact electrode CC will be described.

[0141] Figure 61 is a schematic cross-sectional view of a semiconductor memory device according to the third embodiment. In the following description, components similar to those in the second embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0142] The semiconductor memory device according to the third embodiment is basically configured the same as the semiconductor memory device according to the second embodiment. However, the semiconductor memory device according to the third embodiment includes a contact electrode CC3 instead of a contact electrode CC2.

[0143] The contact electrode CC3 according to the third embodiment is basically configured the same as the contact electrode CC2 according to the second embodiment. However, the contact electrode CC3 is equipped with an insulating column 352 instead of an insulating column 152.

[0144] The upper end of the insulating column 352 is covered by a conductive member 153 and is in contact with the conductive member 153 (more specifically, the barrier conductive film 156). The lower end and outer circumferential surface of the insulating column 352 are covered by a conductive member 251 and are in contact with the conductive member 251 (more specifically, the barrier conductive film 254).

[0145] The insulating column 352 comprises, for example, a barrier insulating film 353 extending in the Z direction, and an insulating film 354 extending in the Z direction, with its outer surface and lower end covered by the barrier insulating film 353 and in contact with the barrier insulating film 353, as shown in Figure 61. The barrier insulating film 353 may contain, for example, silicon nitride (SiN). The insulating film 354 may contain, for example, silicon oxide (SiO2). The barrier insulating film 353 and the insulating film 354 are located in the extraction region R L , connection region R C and penetration area R TH It extends in the Z direction over [a certain distance].

[0146] Extraction region R of barrier insulating film 353 L , connection region R C and penetration area R TH The portions provided therein are each formed in a substantially cylindrical shape. The extraction region R of the insulating film 354 L , connection region R C and penetration area R TH The portions provided therein are each formed in a roughly cylindrical shape. Figure 61 shows the connection region R of the barrier insulating film 353 and the insulating film 354. C The width of the portion provided in the X and Y directions (diameter in the XY cross-section) is defined as width W, respectively. RC353 ,W RC354 It is shown as follows. Similarly, the drawout region R L The width of the portion provided in the X and Y directions (diameter in the XY cross-section) is defined as width W, respectively. RL353 ,W RL354 It is shown as follows. Similarly, through region R TH The width of the portion provided in the X and Y directions (diameter in the XY cross-section) is defined as width W, respectively. RTH353 ,W RTH354 It is shown as width W.RC353 is width W RL353 ,W RTH353 Larger. Width W RC354 is width W RL354 ,W RTH354 Larger.

[0147] This embodiment can also achieve the same effects as the semiconductor memory device according to the first embodiment. Furthermore, with this configuration, the risk of abnormal oxidation of the metal film 155 caused by oxygen in the insulating column 152 can be more effectively suppressed.

[0148] [Fourth Embodiment] The contact electrode CC according to the first embodiment has a connection region R C It is equipped with a connection area R C The outer surface is in contact with the conductive layer 110. However, the film configurations described in the first to third embodiments are applicable to various contact electrodes. Hereinafter, as a fourth embodiment, the connection region R C The contact electrode CC4 that is in contact with the conductive layer 110 on the lower surface will be described below.

[0149] Figure 62 is a schematic cross-sectional view of a semiconductor memory device according to the fourth embodiment. In the following description, components similar to those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0150] The semiconductor memory device according to the fourth embodiment is basically configured the same as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the fourth embodiment includes a contact electrode CC4 instead of the contact electrode CC.

[0151] The contact electrode CC4 according to the fourth embodiment is basically configured the same as the contact electrode CC according to the first embodiment. However, the contact electrode CC4 includes a conductive member 451 instead of the conductive member 151.

[0152] The conductive member 451 is basically configured in the same manner as the conductive member 151. However, the conductive member 451 includes a barrier conductive film 454 instead of the barrier conductive film 154. The barrier conductive film 454 is basically configured in the same manner as the barrier conductive film 154. However, the portion provided in the connection region R C of the barrier conductive film 454 is connected to the conductive layer 110 on the lower surface rather than on the outer peripheral surface.

[0153] In the semiconductor memory device according to the fourth embodiment, a terrace portion T4 is provided on the conductive layer 110 instead of the terrace portion T. The terrace portion T4 is basically configured in the same manner as the terrace portion T. However, the thickness of the terrace portion T4 in the Z direction is substantially the same as the thickness of the other portions of the conductive layer 110 in the Z direction.

[0154] Also, in the semiconductor memory device according to the fourth embodiment, an insulating layer 101 and an insulating member 110' are provided above the terrace portion T4. The insulating member 110' includes, for example, silicon oxide (SiO2) or the like. The thickness Z of the insulating member 110' in the Z direction[[ID=十一]] 110´ is smaller than the length Z in the Z direction of the connection region R C of the contact electrode CC4 and larger than the thickness Z of the conductive layer 110 in the Z direction. A high dielectric constant insulating film 104 is provided on the upper surface, lower surface, and side surfaces in the X and Y directions of the insulating member 110'. The outer peripheral surface of the portion provided in the connection region R RC4 of the barrier conductive film 454 is in contact with the insulating layer 101 and the insulating member 110' on the terrace portion T4. 110O C C Here, although not shown in the drawings, the contact electrode CC4 according to the fourth embodiment also includes three hierarchical portions cc1, cc2, cc3 arranged in the Z direction (see FIG. 9) in the same manner as the contact electrode CC according to the first embodiment. Therefore, voids can also be formed inside the hierarchical portions cc_{1} and cc_{2} in the contact electrode CC4.

[0155] Also, the connection region R

[0156] ​​The width of the contact electrode CC4 in [the relevant part] is larger than the width of the contact electrode CC in the extraction region R L and the through region R TH . Even in such a contact electrode CC4, voids can be formed in the connection region R C .

[0157] Therefore, even in the contact electrode CC4 that contacts the conductive layer 110 on the lower surface of the connection region R C , by forming the insulating column 152 inside the conductive member 451, it is possible to preferably suppress the remaining of fluorine gas. Thereby, it is possible to preferably suppress the decrease in insulation between two conductive layers 110 arranged in the Z direction.

[0158] Also, by forming the conductive member 153 on the upper part of the insulating column 152, it is possible to preferably connect the contact electrode Ch and the contact electrode CC4.

[0159] Also, since the outer peripheral surface of the conductive member 153 contacts the inner peripheral surface of the conductive member 151, it is possible to form a low-resistance contact electrode CC4.

[0160] Incidentally, the conductive member 451 may further include the barrier conductive film 254 described with reference to FIG. 60. Also, the contact electrode CC4 may include the insulating column 352 described with reference to FIG. 61 instead of the insulating column 152.

[0161] [Fifth Embodiment] As described above, the film configurations described in the first to third embodiments are applicable to various contact electrodes. Hereinafter, as the fifth embodiment, a contact electrode CC5 connected to the conductive layer 110 at the lower end will be described.

[0162] FIG. 63 is a schematic cross-sectional view of a semiconductor memory device according to the fifth embodiment. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

[0163] The semiconductor memory device according to the fifth embodiment is basically configured the same as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the fifth embodiment includes a contact electrode CC5 instead of the contact electrode CC. Also, it includes a terrace portion T4 instead of the terrace portion T.

[0164] The contact electrode CC5 is provided corresponding to multiple terrace portions T4. The contact electrode CC5 extends in the Z direction, is connected at its lower end to the upper surface of the corresponding terrace portion T4 of the conductive layer 110, and is connected at its upper end to the contact electrode Ch. The outer circumferential surface of the contact electrode CC5 is surrounded by an insulating layer 102.

[0165] Although not shown in the diagram, among the contact electrodes CC5, the memory cell array layer L MCA1 The conductive layer 110 inside corresponds to the three memory cell array layers L MCA1 ,L MCA2 ,L MCA3 It has three hierarchical sections cc1, cc2, and cc3 aligned in the Z direction (see Figure 9). Among the contact electrodes CC5, among the contact electrodes CC5, the memory cell array layer L MCA2 The conductive layer 110 inside corresponds to the two memory cell array layers L MCA2 ,L MCA3 It has two hierarchical sections cc2 and cc3 aligned in the Z direction (see Figure 9). Among the contact electrodes CC5, the memory cell array layer L MCA3 The corresponding conductive layer 110 inside is the memory cell array layer L MCA3 It includes a corresponding hierarchical section cc3 (see Figure 9).

[0166] Furthermore, the contact electrode CC5 includes a conductive member 551 extending in the Z direction, an insulating column 552 extending in the Z direction with its outer circumferential surface covered by the conductive member 551, and a conductive member 153 provided at the upper end of the contact electrode CC5, with its outer circumferential surface in contact with the conductive member 551 and its upper surface in contact with the contact electrode Ch.

[0167] The lower end of the conductive member 551 is in contact with the conductive layer 110. The conductive member 551 extends in the Z direction, penetrating the insulating layer 102. The conductive member 551 comprises, for example, a barrier conductive film 554 extending in the Z direction, and a metal film 555 extending in the Z direction, with its outer surface and lower end covered by the barrier conductive film 554 and in contact with the barrier conductive film 554. The barrier conductive film 554 may contain, for example, titanium nitride (TiN), tantalum nitride (TaN), etc. The metal film 555 may contain, for example, tungsten (W), molybdenum (Mo), ruthenium (Ru), etc. The barrier conductive film 554 and the metal film 555 are each formed in a substantially cylindrical shape.

[0168] The insulating column 552 may contain, for example, silicon oxide (SiO2). The upper end of the insulating column 552 is covered by a conductive member 153 and is in contact with the conductive member 153 (more specifically, a barrier conductive film 156). The lower end and outer surface of the insulating column 552 are covered by a conductive member 551 and are in contact with the conductive member 551 (more specifically, a metal film 555). The insulating column 552 is formed in a substantially cylindrical shape.

[0169] Here, although not shown in the diagram, some contact electrodes CC5 have three tiered sections cc1, cc2, and cc3 (see Figure 9) aligned in the Z direction, similar to the contact electrode CC in the first embodiment. In such contact electrodes CC5, voids may be formed inside the tiered sections cc1 and cc2. In other cases, some contact electrodes CC5 have two tiered sections cc2 and cc3 (see Figure 9) aligned in the Z direction. In such contact electrodes CC5, voids may be formed inside the tiered section cc2.

[0170] Therefore, even in the contact electrode CC5 that contacts the conductive layer 110 at its lower end, the residual fluorine gas can be effectively suppressed by forming an insulating column 552 inside the conductive member 551. This effectively suppresses the decrease in insulation between the two conductive layers 110 aligned in the Z direction.

[0171] Furthermore, by forming a conductive member 153 on the upper part of the insulating column 552, it is possible to suitably connect the contact electrode Ch and the contact electrode CC5.

[0172] Furthermore, since the outer surface of the conductive member 153 is in contact with the inner surface of the conductive member 551, it is possible to form a low-resistance contact electrode CC5.

[0173] Furthermore, the conductive member 551 may further include the barrier conductive film 254 described with reference to Figure 60. Also, the contact electrode CC5 may include, similar to the insulating column 352 described with reference to Figure 61, a barrier insulating film such as silicon nitride (SiN) stretched in the Z direction, and an insulating film such as silicon oxide (SiO2) stretched in the Z direction, with its outer surface and lower end covered by this barrier insulating film.

[0174] [Sixth Embodiment] Figure 64 is a schematic cross-sectional view of a semiconductor memory device according to the sixth embodiment. In the following description, components similar to those in the fifth embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0175] The semiconductor memory device according to the sixth embodiment is basically configured the same as the semiconductor memory device according to the fifth embodiment. However, the semiconductor memory device according to the sixth embodiment includes a contact electrode CC6 instead of a contact electrode CC5.

[0176] The contact electrode CC6 is basically configured the same as the contact electrode CC5. However, the outer surface of the contact electrode CC6 is surrounded by through holes provided in all conductive layers 110 except for conductive layers 110(SGD) and 110(SGDT), which are located above the corresponding conductive layer 110. In addition, the outer surface of the contact electrode CC6 is provided with a plurality of insulating layers 108 arranged in the Z direction corresponding to the plurality of conductive layers 110. The conductive member 551 according to this embodiment is insulated from the plurality of conductive layers 110 via these plurality of insulating layers 108.

[0177] Even in the contact electrode CC6 as exemplified in the present embodiment, by forming the insulating column 552 inside the conductive member 551, it is possible to suitably suppress the remaining of fluorine gas. Thereby, it is possible to suitably suppress the decrease in insulation between the two conductive layers 110 arranged in the Z direction.

[0178] Also, by forming the conductive member 153 on the upper part of the insulating column 552, it is possible to suitably connect the contact electrode Ch and the contact electrode CC6.

[0179] Further, since the outer peripheral surface of the conductive member 153 is in contact with the inner peripheral surface of the conductive member 551, it is possible to form a low-resistance contact electrode CC6.

[0180] Note that the contact electrode CC6 may include a barrier insulating film such as silicon nitride (SiN) extending in the Z direction and an insulating film such as silicon oxide (SiO2) extending in the Z direction and having its outer peripheral surface and lower end portion covered by this barrier insulating film, similar to the insulating column 352 described with reference to FIG. 61.

[0181] [Other Embodiments] The semiconductor memory devices according to the first to sixth embodiments have been described above. However, these configurations are merely examples, and the specific configurations can be adjusted as appropriate.

[0182] For example, as described with reference to FIG. 9, the contact electrode CC according to the first embodiment includes three hierarchical portions cc1, cc2, and cc3 arranged in the Z direction corresponding to the three memory cell array layers L MCA1 , L MCA2 , L MCA3 The same applies to the second to sixth embodiments. However, the contact electrode may include one or two hierarchical portions, or may include four or more hierarchical portions.

[0183] Furthermore, in the first embodiment, for example, the sacrificial layer 113C formed in the process described with reference to Figure 11 contains silicon. However, the sacrificial layer 113C may also contain silicon nitride. Also, the via holes HRA, contact holes CCA, and grooves STA formed in the process described with reference to Figure 12 have their lower ends reaching the semiconductor layer 113E. However, the lower ends of these via holes HRA, contact holes CCA, and grooves STA may also reach the semiconductor layer 113A. Figure 65 is a schematic cross-sectional view of a semiconductor memory device according to another embodiment, showing a structure manufactured using such a method. When such a method is employed, for example, as shown in Figure 65, an insulating layer 108 is provided on the outer circumferential surface of the conductive member 151 at a position below the upper surface of the conductive layer 113 and above the lower end of the contact electrode CC. The semiconductor memory devices according to the first to fourth embodiments may have such configurations.

[0184] [others] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0185] 101, 102, 103…Insulating layer, 104…High dielectric constant insulating film, 108…Insulating layer, 110…Conductive layer, 120…Semiconductor column, 127…Insulating column, 130…Gate insulating film, 151…Conductive member, 152…Insulating column, 153…Conductive member, 154…Barrier conductive film, 155…Metal film, 156…Barrier conductive film, 157…Metal film, CC, Ch…Contact electrode, R C ...connection region, R L ...drawer area, R TH ...penetration area, T...terrace section.

Claims

1. Multiple conductive layers stacked in the stacking direction, A plurality of memory cells arranged in the stacking direction and connected to the plurality of conductive layers, A first contact electrode stretched in the lamination direction and connected to one of the plurality of conductive layers, A second contact electrode is extended in the stacking direction and connected to one end of the first contact electrode in the stacking direction. Equipped with, The first contact electrode is A first conductive member extending in the lamination direction, An insulating column extending in the lamination direction, with its outer surface covered by the first conductive member, A second conductive member is provided at the end of the first contact electrode on the second contact electrode side in the stacking direction, with its outer peripheral surface in contact with the first conductive member and its surface on the second contact electrode side in the stacking direction in contact with the second contact electrode. A semiconductor memory device equipped with the following features.

2. The first contact electrode is A first region is provided at a position in the stacking direction corresponding to one of the plurality of conductive layers, and is in contact with one of the plurality of conductive layers. A second region is provided on the second contact electrode side in the stacking direction relative to the first region, and extends in the stacking direction, A third region is provided on the side opposite to the second contact electrode in the stacking direction relative to the first region, and extends in the stacking direction. Equipped with, The width of the first region in the first direction intersecting the stacking direction is greater than the width of the second region in the first direction and the width of the third region in the first direction. The semiconductor memory device according to claim 1.

3. The outer surface of the first region is in contact with one of the plurality of conductive layers. The semiconductor memory device according to claim 2.

4. The surface of the first region opposite to the second contact electrode in the stacking direction is in contact with one of the plurality of conductive layers. The semiconductor memory device according to claim 2.

5. The first contact electrode comprises a plurality of layered portions arranged in the stacking direction, with the shapes of their sides being discontinuously formed. The semiconductor memory device according to claim 1.

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