Memory system and control method

Abstract

A memory card capable of holding other memory cards is recognized as a single memory card and records data in parallel to two non-volatile memory devices. [Solution] The memory system of the embodiment includes a first non-volatile memory, a first memory controller that controls the first non-volatile memory via a first interface and is connectable to a host device, and a connection unit to which a memory card can be connected that includes a second non-volatile memory and a second memory controller that controls the second non-volatile memory. When a memory card is connected to the memory system, the first memory controller obtains the identifier of the memory card from the memory card, and in response to a write request from the host device, if the first identification ID, which is the identifier of the memory system, and the second identifier, which is the identifier of the acquired memory card, match, it writes data based on the data specified in the write request to the first non-volatile memory and the second non-volatile memory.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory system and a control method.

Background Art

[0002] Conventionally, there is a host device such as a camera equipped with a plurality of slots (for example, two slots) for accommodating a plurality of SD cards. For example, a camera equipped with two slots records captured images in parallel with respect to the non-volatile memories of two SD cards respectively. This application aims to back up the captured images.

[0003] On the other hand, in a camera equipped with one slot, since only one SD card can be accommodated, captured images cannot be recorded in parallel with respect to the non-volatile memories of each SD card. Also, conventionally, there is an SD card adapter that can accommodate other SD cards.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0005] An object of one embodiment of the present invention is to provide a memory system and a control method in which a memory card capable of accommodating other memory cards is recognized as one memory card and can be recorded in parallel in two non-volatile memories.

Means for Solving the Problems

[0006] The memory system of the embodiment includes a first non-volatile memory, a first memory controller that controls the first non-volatile memory via a first interface and is connectable to a host device, and a connection section to which a memory card can be connected that includes a second non-volatile memory and a second memory controller that controls the second non-volatile memory. When a memory card is connected to the memory system, the first memory controller obtains the identifier of the memory card from the memory card, and in response to a write request from the host device, if the first identification ID, which is the identifier of the memory system, and the second identification ID, which is the identifier of the acquired memory card, match, it writes data based on the data specified in the write request to the first non-volatile memory and the second non-volatile memory. [Brief explanation of the drawing]

[0007] [Figure 1] A schematic diagram showing the general configuration of the memory system according to the first embodiment. [Figure 2] A schematic diagram illustrating how the memory system according to the first embodiment connects to a memory card. [Figure 3] A schematic diagram illustrating how the memory system according to the first embodiment connects to a memory card. [Figure 4] A schematic diagram illustrating the logic-physical transformation table according to the first embodiment. [Figure 5] A schematic diagram showing the general configuration of the memory system according to the first embodiment. [Figure 6] A schematic diagram showing the general configuration of a host device and memory card according to the first embodiment. [Figure 7] A flowchart illustrating the operation of the memory system according to the first embodiment. [Figure 8] A flowchart illustrating the operation of the memory system according to the first embodiment. [Figure 9] A flowchart illustrating the operation of the memory system according to the first embodiment. [Figure 10] A flowchart illustrating the operation of the memory system according to the first embodiment. [Figure 11] A flowchart illustrating the operation of the memory card according to the first embodiment. [Figure 12] A schematic diagram showing the general configuration of the memory system according to the first modified example. [Figure 13] A schematic diagram showing the general configuration of the memory system according to the second embodiment. [Figure 14] A flowchart illustrating the operation of the memory system according to the second embodiment. [Figure 15] A flowchart illustrating the operation of the memory system according to the second embodiment. [Figure 16] A flowchart illustrating the operation of the memory system in the second modified example. [Figure 17] A schematic diagram showing the general configuration of the memory system according to the third modified example. [Figure 18] A schematic diagram showing the general configuration of the memory system according to the fourth modified example. [Figure 19] A flowchart illustrating the operation of the memory system in the fifth modified example. [Modes for carrying out the invention]

[0008] The memory system and control method according to the embodiments will be described in detail below with reference to the attached drawings. However, the present invention is not limited to the following embodiments.

[0009] (First Embodiment) First, the memory system according to the first embodiment will be described in detail with reference to the drawings. FIG. 1 is a schematic diagram showing the schematic configuration of the memory system according to the first embodiment. As shown in FIG. 1, the memory system 2 includes a first plurality of terminals 21, a first memory controller 22, and a first non-volatile memory 23. The memory system 2 is a memory card or the like in which the first plurality of terminals 21, the first memory controller 22, and the first non-volatile memory 23 are configured as one package. The memory system 2 is, for example, an SD card. The first plurality of terminals 21 are terminals compliant with the SD standard.

[0010] The first memory controller 22 is a controller that can be connected to the host device 1 and communicates with the host device 1 in accordance with the SD standard via the first plurality of terminals 21. The host device 1 may be an electronic device such as a personal computer or a mobile terminal. The first memory controller 22 communicates with the host device 1 via, for example, the SD interface 4. Also, the first memory controller 22 controls the first non-volatile memory 23 via the first interface 5. The first interface 5 is, for example, a NAND interface.

[0011] The first non-volatile memory 23 is a non-volatile memory that stores data non-volatilely, and is, for example, a NAND type flash memory (hereinafter simply referred to as a NAND memory).

[0012] Also, the memory system 2 can be connected to the memory card 3 and includes a slot capable of housing the memory card 3. The memory system 2 includes the memory card 3. For example, when the memory card 3 is housed in the memory system 2, the memory system 2 controls the second non-volatile memory 33 included in the memory card 3 via the second interface 8.

[0013] Memory card 3 is a memory card, etc., in which a second set of terminals 31, a second memory controller 32, and a second non-volatile memory 33 are configured as a single package. Memory card 3 is an SD card with a different shape from memory system 2, for example, a microSD card. Also, for example, the storage capacity of the first non-volatile memory 23 and the second non-volatile memory 33 are the same.

[0014] The second set of terminals 31 are terminals compliant with the SD standard. The second memory controller 32 is a controller that can be connected to the host device 1 and is configured to communicate with the host device 1 in accordance with the SD standard via the second set of terminals 31. The second memory controller 32 controls the second non-volatile memory 33 via interface 6, which is, for example, a NAND interface. The second non-volatile memory 33 is a non-volatile memory that stores data non-volatilely, and is, for example, a NAND flash memory.

[0015] Here, the configuration in which the memory system 2 connects to the memory card 3 will be explained using Figures 2 and 3. Figures 2 and 3 are schematic diagrams illustrating the configuration in which the memory system 2 according to the first embodiment connects to the memory card 3.

[0016] For example, as shown in Figure 2, the memory system 2 has terminal 24, and the memory card 3 has terminal 34. Terminal 24 is a terminal for connecting to the memory card 3. Terminal 34 is a terminal for connecting to the memory system 2. Terminal 34 is, for example, a NAND interface terminal. For example, when a user inserts the memory card 3 into the slot of the memory system 2, terminal 24 of the memory system 2 and terminal 34 of the memory card 3 are connected, as shown in Figure 2.

[0017] Figure 3 shows the first memory controller 22 and the memory card 3 of the memory system 2. When the first memory controller 22 detects the connection of the memory card 3, it connects to the second non-volatile memory 33 of the memory card 3 via the second interface 8. The second interface 8 is, for example, a NAND interface.

[0018] Next, an example of signals exchanged between the first memory controller 22 and the first non-volatile memory 23 will be described. The first memory controller 22 exchanges signals with the first non-volatile memory 23 via the first interface 5, such as the chip enable signal CEZ, command latch enable signal CLE, address latch enable signal ALE, write enable signal WEZ, read enable signals RE / REZ, data strobe signals DQS / DQSZ, ready / busy signal RB, and input / output signals I / O. Similarly, the first memory controller 22 exchanges signals with the second non-volatile memory 33 via the second interface 8.

[0019] In other words, the first memory controller 22 exchanges signals with the second non-volatile memory 33, such as the chip enable signal CEZ, command latch enable signal CLE, address latch enable signal ALE, write enable signal WEZ, read enable signal RE / REZ, data strobe signals DQS / DQSZ, ready / busy signal RB, and input / output signal I / O.

[0020] The chip enable signal CEZ is a signal for enabling the second non-volatile memory 33. The command latch enable signal CLE and the address latch enable signal ALE are signals that notify the second non-volatile memory 33 that the input I / O signals to the second non-volatile memory 33 are a command and an address, respectively.

[0021] The write enable signal WEZ is a signal that causes the input signal I / O to be read into the second non-volatile memory 33. The read enable signals RE / REZ are signals that allow the output signal I / O to be read from the second non-volatile memory 33. The data strobe signals DQS / DQSZ are signals that instruct the second non-volatile memory 33 to read the data transmitted and received by the input / output signal I / O.

[0022] The ready / busy signal RB indicates whether the second non-volatile memory 33 is in a ready state or a busy state. The ready state means that the second non-volatile memory 33 is able to receive instructions from the first memory controller 22. The busy state means that the second non-volatile memory 33 is unable to receive instructions from the first memory controller 22.

[0023] The input / output signal (I / O) is, for example, an 8-bit signal. The input / output signal (I / O) is the entity of data transmitted and received between the second non-volatile memory 33 and the first memory controller 22. The input / output signal (I / O) includes commands, addresses, status, write data, and read data. This enables the memory system 2 to read from and write to the second non-volatile memory 33.

[0024] Returning to Figure 1, let's continue the explanation. The first non-volatile memory 23 stores the first firmware 231, the first identification ID 232, the first logic-physical conversion table 233, and the first user data 234. The second non-volatile memory 33 stores the second firmware 331, the second identification ID 332, the second logic-physical conversion table 333, and the second user data 334.

[0025] The first firmware 231 is a program for controlling the entire first memory controller 22. The first memory controller 22 controls the entire first memory controller 22 by, for example, copying the first firmware 231 to RAM (Random Access Memory) (not shown), and having the CPU (Central Processing Unit) built into the first memory controller 22 execute the first firmware 231. The control modes of the first memory controller 22 include a mode in which the memory system 2 starts in read and write mode and a mode in which it starts in read mode.

[0026] The second firmware 331 is a program for controlling the entire second memory controller 32. The second memory controller 32 controls the entire second memory controller 32 by, for example, copying the second firmware 331 to RAM (not shown), and having the CPU built into the second memory controller 32 execute the second firmware 331. The control modes of the second memory controller 32 include a mode in which the memory card 3 is started in read mode.

[0027] The first identification ID 232 is, for example, during the manufacturing of the memory system 2, when the memory card 3 is stored in the memory system 2, and the host device 1 writes the first identification ID 232, which is the identifier of the memory system 2, to the first non-volatile memory 23. The host device 1 also writes the second identification ID 332, which is the identifier of the memory card 3, to the second non-volatile memory 33. The first identification ID 232 and the second identification ID 332 are unique identifiers that associate the first non-volatile memory 23 and the second non-volatile memory 33, and are the same identifier. After the first identification ID 232 is written to the first non-volatile memory 23 and the second identification ID 332 is written to the second non-volatile memory 33, the memory system 2 is shipped.

[0028] The first logic-physical conversion table 233 and the second logic-physical conversion table 333 show the correspondence between logical addresses and physical addresses. The first logic-physical conversion table 233 and the second logic-physical conversion table 333 will be explained using Figure 4. Figure 4 is a schematic diagram for explaining the logic-physical conversion table according to the first embodiment. Figure 4 shows the logical address 11 of the host device 1 (the address of the space virtually used by the host device 1), the first logic-physical conversion table 233, the physical address 235 of the first non-volatile memory 23, the second logic-physical conversion table 333, and the physical address 335 of the second non-volatile memory 33.

[0029] Logical address 11 is an address specified by the host device 1. Physical address 235 is an address specified by the first memory controller 22 and indicates the storage location of the first non-volatile memory 23. Physical address 335 is an address specified by the first memory controller 22 and indicates the storage location of the second non-volatile memory 33. A predetermined logical address 12 within logical address 11 is associated with a predetermined physical address 236 of physical address 235 and a predetermined physical address 336 of physical address 335.

[0030] For example, when host device 1 requests to write data, it sends a write request to the first memory controller 22 that includes a write command (write instruction), a predetermined logical address 12 (the data logical address to be written) within logical address 11, and the data to be written. The first memory controller 22 refers to the first logical-physical conversion table 233 and converts the predetermined logical address 12 included in the received write request to a predetermined physical address 236 at physical address 235. Using the converted predetermined physical address 236, it accesses the first non-volatile memory 23 and writes the data to be written (the data specified in the write request) included in the write request.

[0031] Furthermore, the first memory controller 22 refers to the second logic-physical conversion table 333, converts a predetermined logical address 12 included in the received write request to a predetermined physical address 336 of physical address 335, accesses the second non-volatile memory 33 by specifying the predetermined physical address 336, and writes the data to be written included in the write request.

[0032] For example, when host device 1 requests to read data, it sends a read request to the first memory controller 22 that includes a read command (read instruction) and a predetermined logical address 12. The first memory controller 22 refers to the first logic-physical conversion table 233 and converts the predetermined logical address 12 included in the received read request to a predetermined physical address 236 of physical address 235. Using the converted predetermined physical address 236, it accesses the first non-volatile memory 23 and reads the data.

[0033] Furthermore, the first memory controller 22 may refer to the second logic-physical conversion table 333 to convert a predetermined logical address 12 included in the received read request to a predetermined physical address 336 of physical address 335, and then access the second non-volatile memory 33 using the converted predetermined physical address 336 to read the data.

[0034] Returning to Figure 1, let's continue the explanation. The first user data 234 is data that the first memory controller 22 wrote to the first non-volatile memory 23 based on the data specified by the host device 1 in a write request. The second user data 334 is data that the first memory controller 22 wrote to the second non-volatile memory 33 based on the data specified by the host device 1 in a write request. Since the first user data 234 and the second user data 334 are data specified by the host device 1 in a write request, the information in the data is the same. Hereafter, the first user data 234 and the second user data 334 will also be simply referred to as data.

[0035] Next, we will describe the processes executed by the first memory controller 22. For example, we will describe the startup process of the memory system 2 when a user connects the memory system 2 containing the memory card 3 to the host device 1.

[0036] First, when the host device 1 recognizes the memory system 2, the first memory controller 22's power supply VDD 25 is turned ON. Then, the first memory controller 22 performs a process to detect the connection of the memory card 3. Next, the first memory controller 22 performs a process to determine whether the memory card 3 is present.

[0037] Here, the first memory controller 22 detects the connection of the memory card 3 and, upon determining that the memory card 3 is present, performs the process of reading the first identification ID 232 stored in the first non-volatile memory 23 and the second identification ID 332 stored in the second non-volatile memory 33.

[0038] For example, when the memory card 3 is placed in the slot, the first memory controller 22 connects to the first non-volatile memory 23 via the first interface 5, reads the first identification ID 232 from the first non-volatile memory 23 via the first interface 5, and obtains the first identification ID 232. When the first non-volatile memory 23 receives a read command for the first identification ID 232 from the first memory controller 22 via the first interface 5, it outputs the first identification ID 232 to the first memory controller 22.

[0039] Furthermore, when the memory card 3 is inserted into the slot, the first memory controller 22 connects to the second non-volatile memory 33 via the second interface 8, reads the second identification ID 332 from the second non-volatile memory 33 via the second interface 8, and obtains the second identification ID 332. When the second non-volatile memory 33 receives a read command for the second identification ID 332 from the first memory controller 22 via the second interface 8, it outputs the second identification ID 332 to the first memory controller 22.

[0040] The first memory controller 22 then performs a process to determine whether the acquired first identification ID 232 and the second identification ID 332 match. If the first memory controller 22 determines that the acquired first identification ID 232 and the second identification ID 332 match, it performs a read operation of the first firmware 231 stored in the first non-volatile memory 23.

[0041] Next, the first memory controller 22 performs initialization and reads the first logical-physical conversion table 233 stored in the first non-volatile memory 23. Subsequently, the first memory controller 22 reads the second logical-physical conversion table 333 stored in the second non-volatile memory 33. Then, the first memory controller 22 starts the memory system 2 in read-write mode for the first non-volatile memory 23 and the second non-volatile memory 33.

[0042] On the other hand, if the first memory controller 22 cannot detect the connection of the memory card 3 and determines that there is no memory card 3, it performs an initialization process and reads the first firmware 231 stored in the first non-volatile memory 23. Subsequently, the first memory controller 22 reads the first logic-physical conversion table 233 stored in the first non-volatile memory 23. Then, the first memory controller 22 starts the memory system 2 in read mode only for the first non-volatile memory 23.

[0043] Furthermore, if the first memory controller 22 determines that the acquired first identification ID 232 and the second identification ID 332 do not match, it performs initialization processing and reads the first firmware 231 stored in the first non-volatile memory 23. Next, the first memory controller 22 reads the first logic-physical conversion table 233 stored in the first non-volatile memory 23. Then, the first memory controller 22 starts the memory system 2 in read mode only for the first non-volatile memory 23.

[0044] In other words, if the memory system 2 detects the connection of the memory card 3 and the first identification ID 232 and the second identification ID 332 match, it starts up in read / write mode, performing read / write operations on the first non-volatile memory 23 and the second non-volatile memory 33. If the memory system 2 cannot detect the connection of the memory card 3, or if the first identification ID 232 and the second identification ID 332 do not match, it starts up in read mode, performing read operations only on the first non-volatile memory 23.

[0045] Next, we will explain the data writing process of the memory system 2 when the host device 1 requests a write to the memory system 2, which has been started in read / write mode.

[0046] First, the first memory controller 22 processes the request to write from the host device 1. Upon receiving the request to write from the host device 1, the first memory controller 22 refers to the first logic-physical conversion table 233, identifies the physical address corresponding to the logical address included in the request, and writes the received data to the second non-volatile memory 33 in parallel with the first non-volatile memory 23 to the identified physical address. Subsequently, the first memory controller 22 reads the written data from the first non-volatile memory 23 and the second non-volatile memory 33, respectively. Next, the first memory controller 22 determines whether there are any read errors in the data read from the first non-volatile memory 23 and the second non-volatile memory 33.

[0047] Here, if the first memory controller 22 determines that there are no read errors in the data read from the first non-volatile memory 23 and the second non-volatile memory 33, it then performs a process to determine if the read data matches. If the first memory controller 22 determines that the data read from the first non-volatile memory 23 and the second non-volatile memory 33 matches, it returns a write completion status to the host device 1 and terminates the data writing process.

[0048] On the other hand, if the first memory controller 22 determines that there is a read error in the data read from both the first non-volatile memory 23 and the second non-volatile memory 33, or if it determines that the data read from the first non-volatile memory 23 and the second non-volatile memory 33 do not match, it returns an error to the host device 1 and terminates the data writing process.

[0049] Furthermore, if the first memory controller 22 determines that there is a read error in the data read from either the first non-volatile memory 23 or the second non-volatile memory 33, it performs a write operation (background processing) to the data written to the second non-volatile memory 33 at a physical address different from the physical address where the read error occurred in the first non-volatile memory 23, returns a successful write completion status to the host device 1, and terminates the data writing process.

[0050] Here, because background processing takes time, the size of the second user data 334 to be written to the second non-volatile memory 33 is divided, and instead of writing to the second non-volatile memory 33 all at once, the processing is distributed little by little in parallel with the timing of processing from the first memory controller 22 to the first non-volatile memory 23. The first memory controller 22 performs background processing so as not to exceed the time allowed for the response to the host device 1 from the command from the host device 1.

[0051] Next, we will describe the data retrieval process in memory system 2 when host device 1 requests a read from memory system 2, which has been started in read / write mode.

[0052] First, the first memory controller 22 receives a data read command (Read command) from the host device 1. Next, the first memory controller 22 refers to the first logic-physical conversion table 233, identifies the physical address corresponding to the logical address included in the read request, and reads the data from the identified physical address. Subsequently, the first memory controller 22 determines whether there are any read errors in the first user data 234 read from the first non-volatile memory 23. The first memory controller 22 determines whether there are any errors in the read first user data 234, for example, using an error correction circuit (ECC circuit) implemented inside the first memory controller 22.

[0053] At this point, if the first memory controller 22 determines that there are no read errors in the first user data 234 read from the first non-volatile memory 23, it returns the first user data 234 read from the first non-volatile memory 23 to the host device 1. Then, the first memory controller 22 terminates the data read process.

[0054] On the other hand, if the first memory controller 22 determines that there is a read error in the first user data 234 read from the first non-volatile memory 23, it performs a read operation on the second user data 334 stored in the second non-volatile memory 33. For example, the first memory controller 22 refers to the second logical-physical conversion table 333, identifies the physical address corresponding to the logical address included in the read request, and performs a process to read the data from the identified physical address. Subsequently, the first memory controller 22 performs a process to determine whether there is a read error in the second user data 334 read from the second non-volatile memory 33.

[0055] Here, if the first memory controller 22 determines that there are no read errors in the second user data 334 read from the second non-volatile memory 33, it writes the data written to the second non-volatile memory 33 to a physical address different from the physical address where the read error occurred in the first non-volatile memory 23 (background processing). Then, the first memory controller 22 returns the second user data 334 read from the second non-volatile memory 33 to the host device 1. Finally, the first memory controller 22 terminates the data reading process.

[0056] On the other hand, if the first memory controller 22 determines that there is a read error in the second user data 334 read from the second non-volatile memory 33, it returns an error to the host device 1 and terminates the data reading process.

[0057] Next, we will describe the read process of the memory system 2 when the host device 1 requests a read from the memory system 2 which has been started in read mode. Figure 5 is a schematic diagram showing the general configuration of the memory system 2 according to the first embodiment. As shown in Figure 5, the memory system 2 started in read mode does not have the memory card 3 installed.

[0058] First, the first memory controller 22 performs initialization processing. Next, the first memory controller 22 reads the first firmware 231 stored in the first non-volatile memory 23. Subsequently, the first memory controller 22 reads the first logic-physical conversion table 233 stored in the first non-volatile memory 23.

[0059] The first memory controller 22 then receives a request command from the host device 1 and determines the type of the request command. If the first memory controller 22 determines that the request command received from the host device 1 is a data read command, it refers to the first logical-physical conversion table 233, identifies the physical address corresponding to the logical address included in the read request, and performs the process of reading the data from the identified physical address. On the other hand, if the first memory controller 22 determines that the request command received from the host device 1 is a data write command, it returns an error to the host device 1.

[0060] Next, we will describe the read process of the memory card 3 in the memory system 2 when the host device 1 is connected to the memory card 3 and the host device 1 requests a read from the memory card 3. Figure 6 is a schematic diagram showing the general configuration of the host device 1 and memory card 3 according to the first embodiment. The memory card 3 is connectable to the host device 1, and Figure 6 shows it in a connected state to the host device 1. The second memory controller 32 communicates with the host device 1, for example, via the SD interface 9.

[0061] First, the second memory controller 32 performs initialization processing. Next, the second memory controller 32 reads the second firmware 331 stored in the second non-volatile memory 33. Subsequently, the second memory controller 32 reads the second logic-physical conversion table 333 stored in the second non-volatile memory 33.

[0062] The second memory controller 32 then receives a request command from the host device 1 and determines the type of the request command. If the second memory controller 32 determines that the request command received from the host device 1 is a data write command, it returns an error to the host device 1.

[0063] On the other hand, when the second memory controller 32 determines that the request command received from the host device 1 is a command to read the second user data 334, it refers to the second logical-physical conversion table 333, identifies the physical address corresponding to the logical address included in the read request, and performs the process of reading the data from the identified physical address.

[0064] For example, as shown in Figures 5 and 6, when memory card 3 is removed from the slot of memory system 2, both memory system 2 and memory card 3 operate in read mode. Therefore, with a single write request from host device 1, data is recorded in parallel on both SD cards, and even if one of the SD cards is damaged, the data can be read from the other SD card.

[0065] Figures 7 to 10 are flowcharts illustrating the operation of the memory system 2 according to the first embodiment. The flowchart shown in Figure 7 illustrates the startup process of the memory system 2. The process in Figure 7 starts from a state where the host device 1 recognizes the memory system 2, and the first memory controller 22 turns ON based on the power supply VDD25 of the first memory controller 22 supplied from the host device 1 via the first plurality of terminals 21.

[0066] First, the first memory controller 22 performs a process to detect the connection of the memory card 3 (step S71). Next, the first memory controller 22 performs a process to determine whether the memory card 3 is present (step S72). If the first memory controller 22 fails to detect the connection of the memory card 3 and determines that there is no memory card 3 (step S72: No), it proceeds to step S79. On the other hand, if the first memory controller 22 detects the connection of the memory card 3 and determines that there is a memory card 3 (step S72: Yes), it proceeds to step S73.

[0067] In step S73, the first memory controller 22 reads the first identification ID 232 stored in the first non-volatile memory 23 and the second identification ID 332 stored in the second non-volatile memory 33 (step S73). Subsequently, the first memory controller 22 determines whether the acquired first identification ID 232 and the second identification ID 332 match (step S74). If the first memory controller 22 determines that the acquired first identification ID 232 and the second identification ID 332 do not match (step S74: No), it proceeds to step S79. On the other hand, if the first memory controller 22 determines that the acquired first identification ID 232 and the second identification ID 332 do match (step S74: Yes), it proceeds to step S75.

[0068] In step S75, the first memory controller 22 performs initialization and reads the first firmware 231 stored in the first non-volatile memory 23 (step S75). Next, the first memory controller 22 performs initialization and reads the first logic-physical conversion table 233 stored in the first non-volatile memory 23 (step S76). Next, the first memory controller 22 reads the second logic-physical conversion table 333 stored in the second non-volatile memory 33 (step S77). Then, the first memory controller 22 performs a process to start the memory system 2 in read-write mode for the first non-volatile memory 23 and the second non-volatile memory 33 (step S78). This completes the process for starting the memory system 2.

[0069] In step S79, the first memory controller 22 performs initialization and reads the first firmware 231 stored in the first non-volatile memory 23 (step S79). Subsequently, the first memory controller 22 reads the first logic-physical conversion table 233 stored in the first non-volatile memory 23 (step S80). Subsequently, the first memory controller 22 starts the memory system 2 in read mode only for the first non-volatile memory 23 (step S81). This completes the process for starting the memory system 2.

[0070] The flowchart shown in Figure 8 illustrates the data writing process of memory system 2 when host device 1 issues a write request to memory system 2 which has been started in read / write mode. The process in Figure 8 starts from the state in which memory system 2 is in read / write mode after performing the process of step S78 shown in Figure 7 described above.

[0071] First, the first memory controller 22 processes a data write command from the host device 1 (step S91). Next, the first memory controller 22 refers to the first logic-physical conversion table 233, identifies the physical address corresponding to the logical address included in the write request, and writes the received data to the second non-volatile memory 33 in parallel with the first non-volatile memory 23 to the identified physical address (step S92). Subsequently, the first memory controller 22 reads the written data from the first non-volatile memory 23 and the second non-volatile memory 33 (step S93).

[0072] Next, the first memory controller 22 performs a process to determine whether there are any read errors in the data read from the first non-volatile memory 23 and the second non-volatile memory 33 (step S94). If the first memory controller 22 determines that there are read errors in the data read from both the first non-volatile memory 23 and the second non-volatile memory 33 (step S94: Yes), it proceeds to step S96. Alternatively, if the first memory controller 22 determines that there is a read error in the data read from either the first non-volatile memory 23 or the second non-volatile memory 33 (step S94: Yes), it proceeds to step S97.

[0073] On the other hand, if the first memory controller 22 determines that there are no read errors in the data read from the first non-volatile memory 23 and the second non-volatile memory 33 (step S94: No), it proceeds to step S95. In step S95, the first memory controller 22 performs a process to determine whether the read data matches (step S95). Here, if the first memory controller 22 determines that the data read from the first non-volatile memory 23 and the second non-volatile memory 33 matches (step S95: Yes), it proceeds to step S98. On the other hand, if the first memory controller 22 determines that the data read from the first non-volatile memory 23 and the second non-volatile memory 33 does not match (step S95: No), it proceeds to step S96.

[0074] In step S96, the first memory controller 22 returns an error to the host device 1 (step S96). In step S97, the first memory controller 22 writes the data written to the second non-volatile memory 33 to a physical address different from the physical address where the read error occurred in the first non-volatile memory 23 (step S97). In step S98, the first memory controller 22 returns a successful write completion message to the host device 1 (step S98). In step S99, the first memory controller 22 terminates the data writing process.

[0075] The flowchart shown in Figure 9 illustrates the data retrieval process from memory system 2 when host device 1 requests a read from memory system 2 which has been started in read / write mode. The process in Figure 9 starts from the state where memory system 2 is in read / write mode after performing the process in step S78 shown in Figure 7 described above.

[0076] First, the first memory controller 22 processes a data read command from the host device 1 (step S101). The first memory controller 22 refers to the first logic-physical conversion table 233, identifies the physical address corresponding to the logical address included in the read request, and reads the data from the identified physical address (step S102). Subsequently, the first memory controller 22 processes whether there are any read errors in the first user data 234 read from the first non-volatile memory 23 (step S103).

[0077] Here, if the first memory controller 22 determines that there is a read error in the first user data 234 read from the first non-volatile memory 23 (step S103: Yes), it proceeds to step S105. On the other hand, if the first memory controller 22 determines that there is no read error in the first user data 234 read from the first non-volatile memory 23 (step S103: No), it proceeds to step S104. In step S104, the first memory controller 22 performs the process of returning the first user data 234 read from the first non-volatile memory 23 to the host device 1 (step S104).

[0078] In step S105, the first memory controller 22 reads the second user data 334 stored in the second non-volatile memory 33. Subsequently, the first memory controller 22 determines whether there are any read errors in the second user data 334 read from the second non-volatile memory 33 (step S106).

[0079] Here, if the first memory controller 22 determines that there is a read error in the second user data 334 read from the second non-volatile memory 33 (step S106: Yes), it proceeds to step S108. On the other hand, if the first memory controller 22 determines that there is no read error in the second user data 334 read from the second non-volatile memory 33 (step S106: No), it proceeds to step S107.

[0080] In step S107, the first memory controller 22 writes the data written to the second non-volatile memory 33 to a physical address different from the physical address where the read error occurred in the first non-volatile memory 23 (step S107). In step S108, the first memory controller 22 returns an error to the host device 1 (step S108). In step S109, the first memory controller 22 terminates the data read operation.

[0081] The flowchart shown in Figure 10 illustrates the data retrieval process from memory system 2 when host device 1 requests a read from memory system 2 which has been started in read mode. The process in Figure 10 starts from the state in which memory system 2 is in read mode after performing the process of step S81 shown in Figure 7 described above. Also, as shown in Figure 5, in the process in Figure 10, memory system 2 started in read mode does not have a memory card 3 inserted.

[0082] First, the first memory controller 22 performs an initialization process (step S111). Next, the first memory controller 22 reads the first firmware 231 stored in the first non-volatile memory 23 (step S112). Next, the first memory controller 22 reads the first logic-physical conversion table 233 stored in the first non-volatile memory 23 (step S113).

[0083] Next, the first memory controller 22 receives a request command from the host device 1 (step S114). Subsequently, the first memory controller 22 determines the type of request command received from the host device 1 (step S115).

[0084] Here, if the first memory controller 22 determines that the request command received from the host device 1 is a data read command (step S115: Read), it proceeds to step S117. On the other hand, if the first memory controller 22 determines that the request command received from the host device 1 is a data write command (step S115: Write), it proceeds to step S116.

[0085] In step S116, the first memory controller 22 performs a process to return an error to the host device 1 (step S116). In step S117, the first memory controller 22 refers to the first logical-physical conversion table 233, identifies the physical address corresponding to the logical address included in the read request, and performs a process to read data from the identified physical address (step S117). When the processing in step S116 or step S117 is completed, the first memory controller 22 proceeds to step S114.

[0086] Figure 11 is a flowchart illustrating the operation of the memory card 3 according to the first embodiment. The process shown in Figure 11 is the process of the memory card 3 when it is connected to the host device 1, as shown in Figure 6.

[0087] First, the second memory controller 32 performs an initialization process (step S121). Next, the second memory controller 32 reads the second firmware 331 stored in the second non-volatile memory 33 (step S122). Next, the second memory controller 32 reads the second logic-physical conversion table 333 stored in the second non-volatile memory 33 (step S123).

[0088] Next, the second memory controller 32 receives a request command from the host device 1 (step S124). Subsequently, the second memory controller 32 determines the type of request command received from the host device 1 (step S125).

[0089] Here, if the second memory controller 32 determines that the request command received from the host device 1 is a data read command (step S125: Read), it proceeds to step S127. On the other hand, if the second memory controller 32 determines that the request command received from the host device 1 is a data write command (step S125: Write), it proceeds to step S126.

[0090] In step S126, the second memory controller 32 returns an error to the host device 1 (step S126). In step S127, the second memory controller 32 refers to the second logic-physical conversion table 333, identifies the physical address corresponding to the logical address included in the read request, and reads the data from the identified physical address (step S127).

[0091] As described above, in the first embodiment, when the memory card 3 is connected to the memory system 2, the memory system 2 obtains the identification ID of the second non-volatile memory 33 from the memory card 3, and in response to a write request from the host device 1, if the first identification ID 232, which is the identification ID of the first non-volatile memory 23, and the second identification ID 332, which is the identification ID of the second non-volatile memory 33 obtained, match, the memory system 2 writes data based on the data specified in the write request to the first non-volatile memory 23 and the second non-volatile memory 33. In other words, the first memory controller 22 writes data based on the data specified in the write request from the host device 1 to the first non-volatile memory 23 and the second non-volatile memory 33 only if it has authenticated the association between the first non-volatile memory 23 and the second non-volatile memory 33.

[0092] As a result, for example, in a camera acting as a host device 1 equipped with a slot capable of storing one SD card, the image captured by the camera is recorded in parallel in the non-volatile memory of the first SD card and the second SD card only if the identifier of the non-volatile memory of the SD card (first SD card) stored in the camera's slot matches the identifier of the non-volatile memory of the SD card (second SD card) stored in a slot provided on the first SD card.

[0093] For example, a user can record images captured by the camera onto different SD cards, thus creating backup data. Therefore, in the first embodiment, a memory card capable of storing other memory cards can be recognized as a single memory card and recorded in parallel to two non-volatile memories.

[0094] Furthermore, in the first embodiment described above, when the second SD card is removed from the slot of the first SD card, both the first and second SD cards operate in read mode. Therefore, no response from the host device is required, and data is recorded in parallel on both SD cards with a single write operation. For example, even if one of the SD cards is damaged, the data can be read from the other SD card.

[0095] (First variation) In the first embodiment described above, the memory system 2 is connected to the memory card 3 via a NAND interface, but it is not limited to this. The memory system 2 according to the first modification will be described using Figures 12 and 13 to show a configuration in which the memory system 2 is connected to the memory card 3 via an SD interface. Figure 12 is a schematic diagram illustrating the configuration in which the memory system 2 according to the first modification is connected to the memory card 3. Components similar to those in the above embodiment are denoted by the same reference numerals and detailed descriptions are omitted.

[0096] Figure 12 is a schematic diagram showing the general configuration of the memory system 2 according to the first modified example. In Figure 12, the configuration in which the memory system 2 connects to the memory card 3 is different from that in Figure 1. In Figure 12, the first memory controller 22 of the memory system 2 is connected to the second memory controller 32 of the memory card 3 via an SD interface 81.

[0097] For example, when a user inserts memory card 3 into the slot of memory system 2, the terminals of memory system 2 and the terminals of memory card 3 are connected. Here, the terminals of memory card 3 in the first modified example are the SD interface 81, which is an example of a third set of terminals. When the first memory controller 22 detects the connection of memory card 3, it connects to the second memory controller 32 via the SD interface 81.

[0098] When the memory card 3 is connected to the memory system 2, the first memory controller 22 obtains the identifier of the second non-volatile memory 33 from the memory card 3, and in response to a write request from the host device 1, if the first identification ID 232, which is the identifier of the first non-volatile memory 23, matches the second identification ID 332, which is the identifier of the second non-volatile memory 33 obtained, it writes data based on the data specified in the write request to the second non-volatile memory 33 via the third set of terminals.

[0099] (Second embodiment) In the second embodiment, the first memory controller 22 of the memory system 2 is equipped with an encryption circuit, and the host device 1 writes data specified in a write request to the first non-volatile memory 23, and the form of the data writing process to the second non-volatile memory 33 encrypted by the encryption circuit is described. Components similar to those in the above embodiment are denoted by the same reference numerals and detailed descriptions are omitted.

[0100] Figure 13 is a schematic diagram showing the general configuration of the memory system 2 according to the second embodiment. The memory system 2 shown in Figure 13 further includes an encryption circuit 221 in the first memory controller 22, and a first non-volatile memory 23 that stores the public key 237. The encryption circuit 221 encrypts the data using an encryption scheme. The encryption circuit 221 can be implemented using hardware such as a logic circuit or software.

[0101] The public key 237 stored in the first non-volatile memory 23 is stored in the first non-volatile memory 23, for example, by the user writing to the memory system 2, which houses the memory card 3, from the host device 1. Furthermore, for example, the private key for decryption corresponding to the public key 237 is held by the user.

[0102] Next, we will explain the data writing process of the memory system 2 when the host device 1 requests a write to the memory system 2, which has been started in read / write mode.

[0103] In the second embodiment, the first memory controller 22 processes a data write command from the host device 1. The first memory controller 22 then refers to the first logic-physical conversion table 233 to identify the physical address corresponding to the logical address included in the write request, and performs the data writing process to the first non-volatile memory 23 at the identified physical address.

[0104] The first memory controller 22 then reads the public key 237 from the first non-volatile memory 23 and instructs the encryption circuit 221 to encrypt the data received in the first non-volatile memory 23 using the read public key 237. The first memory controller 22 then refers to the second logic-physical conversion table 333 to identify the physical address corresponding to the logical address included in the write request, and writes the second user data 334, encrypted by the encryption circuit 221, to the identified physical address in the second non-volatile memory 33.

[0105] Here, the first non-volatile memory 23 stores unencrypted first user data 234. For example, if the host device 1 is a camera, the user may want to immediately check the image data captured by the camera. If the first non-volatile memory 23 stores image data encrypted by the encryption circuit 221, the camera will decrypt the encrypted image data using a secret key and output the decrypted image data. Therefore, the camera may take a long time to output the image data because it is performing the decryption process. In other words, it may take time for the user to check the image data captured by the camera. For this reason, the first memory controller 22 stores the first user data 234, which is not encrypted by the encryption circuit 221, in the first non-volatile memory 23.

[0106] Next, we will describe the data retrieval process in memory system 2 when host device 1 requests a read from memory system 2, which has been started in read / write mode.

[0107] In the second embodiment, the first memory controller 22 refers to the first logical-physical conversion table 233, identifies the physical address corresponding to the logical address included in the read request, and reads the data from the identified physical address. Subsequently, the first memory controller 22 determines whether there are any read errors in the first user data 234 read from the first non-volatile memory 23.

[0108] At this point, if the first memory controller 22 determines that there are no read errors in the first user data 234 read from the first non-volatile memory 23, it returns the first user data 234 read from the first non-volatile memory 23 to the host device 1. Then, the first memory controller 22 terminates the data read process.

[0109] On the other hand, if the first memory controller 22 determines that there is a read error in the first user data 234 read from the first non-volatile memory 23, it returns an error to the host device 1 and terminates the data read process.

[0110] The reason why the first memory controller 22 does not read the second user data 334, which has been encrypted by the encryption circuit 221 stored in the second non-volatile memory 33, is that the first non-volatile memory 23 does not store the secret key for decrypting the encrypted data.

[0111] Next, we will describe the read process of memory system 2 when host device 1 requests a read from memory system 2 which has been started in read mode. As shown in Figure 5, memory system 2 started in read mode does not have a memory card 3 installed.

[0112] In the second embodiment, the first memory controller 22 performs initialization processing. Subsequently, the first memory controller 22 reads the first firmware 231 stored in the first non-volatile memory 23. Subsequently, the first memory controller 22 reads the first logic-physical conversion table 233 stored in the first non-volatile memory 23.

[0113] The first memory controller 22 then receives a request command from the host device 1 and determines the type of the request command. If the first memory controller 22 determines that the request command received from the host device 1 is a data read command, it performs a read operation on the data read from the first non-volatile memory 23. On the other hand, if the first memory controller 22 determines that the request command received from the host device 1 is a data write command, it returns an error to the host device 1.

[0114] Next, we will describe the read process of the memory card 3 by the memory system 2 when the host device 1 is connected to the memory card 3 and a read request is made to the memory card 3.

[0115] First, the second memory controller 32 performs initialization processing. Next, the second memory controller 32 reads the second firmware 331 stored in the second non-volatile memory 33. Subsequently, the second memory controller 32 reads the second logic-physical conversion table 333 stored in the second non-volatile memory 33.

[0116] The second memory controller 32 then receives a request command from the host device 1 and determines the type of the request command. If the second memory controller 32 determines that the request command received from the host device 1 is a data write command, it returns an error to the host device 1.

[0117] On the other hand, when the second memory controller 32 determines that the request command received from the host device 1 is a command to read the second user data 334, it refers to the second logic-physical conversion table 333, identifies the physical address corresponding to the logical address included in the read request, reads the data encrypted by the encryption circuit 221 from the identified physical address, and returns the data encrypted by the encryption circuit 221 to the host device 1.

[0118] Here, if the host device 1 stores a secret decryption key corresponding to the public key 237, it decrypts the data encrypted by the encryption circuit 221 returned from the second memory controller 32 using the secret key. On the other hand, if the host device 1 does not store a secret decryption key corresponding to the public key 237, it cannot decrypt the data encrypted by the encryption circuit 221 returned from the second memory controller 32. In other words, the host device 1 can read the encrypted data from the second non-volatile memory 33, but since the read data is encrypted, it cannot decrypt the encrypted data unless the host device 1 stores the secret key.

[0119] Figures 14 and 15 are flowcharts illustrating the operation of the memory system 2 according to the second embodiment. The flowchart in Figure 14 illustrates the data writing process of the memory system 2 when the host device 1 issues a write request to the memory system 2, which has been started in read / write mode. The process in Figure 14 starts from the state in which the memory system 2 is in read / write mode after performing the process of step S78 shown in Figure 7 described above. Steps S91 and S99 in Figure 14 are the same processes as steps S91 and S99 shown in Figure 8, so their explanation is omitted.

[0120] In step S141, the first memory controller 22 refers to the first logic-physical translation table 233 to identify the physical address corresponding to the logical address included in the write request, and performs a write operation of the received data to the first non-volatile memory 23 at the identified physical address (step S141). In step S142, the first memory controller 22 reads the public key 237 from the first non-volatile memory 23, has the encryption circuit 221 encrypt the data received in the first non-volatile memory 23 using the read public key 237, refers to the second logic-physical translation table 333 to identify the physical address corresponding to the logical address included in the write request, and performs a write operation of the second user data 334 encrypted by the encryption circuit 221 to the second non-volatile memory 33 at the identified physical address (step S142).

[0121] The flowchart in Figure 15 illustrates the data retrieval process from memory system 2 when host device 1 requests a read from memory system 2 which has been started in read / write mode. The process in Figure 15 starts from the state where memory system 2 is in read / write mode after performing the process in step S78 shown in Figure 7 described above. Steps S101 and S109 in Figure 15 are the same processes as steps S101 and S109 shown in Figure 9, so their explanation is omitted.

[0122] In step S151, the first memory controller 22 refers to the first logical-physical conversion table 233, identifies the physical address corresponding to the logical address included in the read request, and reads the data from the identified physical address (step S151). In step S152, the first memory controller 22 determines whether there are any read errors in the first user data 234 read from the first non-volatile memory 23 (step S152).

[0123] Here, if the first memory controller 22 determines that there is a read error in the first user data 234 read from the first non-volatile memory 23 (step S152: Yes), it proceeds to step S154. On the other hand, if the first memory controller 22 determines that there is no read error in the first user data 234 read from the first non-volatile memory 23 (step S152: No), it proceeds to step S153.

[0124] In step S153, the first memory controller 22 performs a process to return the data read from the first non-volatile memory 23 to the host device 1 (step S153). In step S154, the first memory controller 22 performs a process to return an error to the host device 1 (step S154).

[0125] As described above, in the second embodiment, an encryption circuit 221 is provided, and when the memory card 3 is connected to the memory system 2, the identification ID of the second non-volatile memory 33 is obtained from the memory card 3, and in response to a write request from the host device 1, if the first identification ID 232, which is the identifier of the first non-volatile memory 23, and the second identification ID 332, which is the identifier of the second non-volatile memory 33 obtained, match, the host device 1 writes data based on the data specified in the write request to the first non-volatile memory 23, and the host device 1 has the encryption circuit 221 encrypt the data based on the data specified in the write request and writes the encrypted data to the second non-volatile memory 33.

[0126] As a result, for example, in a camera acting as a host device 1 equipped with a slot capable of storing one SD card, if the identifier of the non-volatile memory of the SD card (first SD card) stored in the camera's slot matches the identifier of the non-volatile memory of the SD card (second SD card) stored in a slot provided on the first SD card, the image captured by the camera can be written to the non-volatile memory of the first SD card, and the image encrypted by the encryption circuit 221 can be written to the non-volatile memory of the second SD card, thereby recording data in parallel.

[0127] For example, a user can record encrypted and unencrypted images captured by the camera onto different SD cards, thereby improving security while creating backup data. Therefore, in the second embodiment, a memory card capable of storing other memory cards can be recognized as a single memory card and record in parallel to two non-volatile memories.

[0128] (Second variation) In the second modification, the processing of the memory system 2, which is started in a read mode different from that of the second embodiment described above, will be explained. The memory system 2 started in the read mode according to the second modification is in a state where the memory card 3 is not inserted, as shown in Figure 5.

[0129] For example, in the second modified memory system 2, if the memory card 3 is not stored, and the system determines that the request command received from the host device 1 is a data read command, it may return an error to the host device 1. This process can be used, for example, as a more stringent method of data management when the memory card 3 is not stored in the memory system 2.

[0130] In the second modified example, the first memory controller 22 performs an initialization process. Subsequently, the first memory controller 22 reads the first firmware 231 stored in the first non-volatile memory 23. Subsequently, the first memory controller 22 reads the first logic-physical conversion table 233 stored in the first non-volatile memory 23.

[0131] The first memory controller 22 then receives a request command from the host device 1 and determines the type of the request command. If the first memory controller 22 determines that the request command received from the host device 1 is a data read command, it returns an error to the host device 1. If the first memory controller 22 determines that the request command received from the host device 1 is a data write command, it returns an error to the host device 1.

[0132] Figure 16 is a flowchart illustrating the operation of the memory system 2 according to the second modified example. The flowchart in Figure 16 describes the data reading process of the memory system 2 when the host device 1 requests a read from the memory system 2 which has been started in read mode. The process in Figure 16 starts from the state in which the memory system 2 has entered read mode after performing the process of step S81 shown in Figure 7 described above.

[0133] Furthermore, as shown in Figure 5, the memory system 2, which was started in read mode, does not have the memory card 3 inserted. In addition, steps S111 to S116 shown in Figure 16 are the same as steps S111 to S116 shown in Figure 10, so their explanation is omitted.

[0134] In step S161, the first memory controller 22 returns an error to the host device 1. As a result, in the second modified example, if the memory card 3 is not placed in the memory system 2, the data cannot be read. For example, a user can use this as a way to make data management in the memory system 2 more stringent when the memory card 3 is not placed in the memory system 2.

[0135] (Third variation) In a third modified example, the second non-volatile memory 33 may include the public key 237. Note that components similar to those in the above embodiments are denoted by the same reference numerals and their detailed descriptions are omitted.

[0136] Figure 17 is a schematic diagram showing the general configuration of the memory system 2 according to the third modified example. The memory system 2 shown in Figure 17 differs from that in Figure 14 in that the second non-volatile memory 33 stores the public key 237.

[0137] The public key 237 stored in the second non-volatile memory 33 is stored in the second non-volatile memory 33, for example, by the user writing to the memory system 2, which houses the memory card 3, from the host device 1. Furthermore, for example, the private key for decryption corresponding to the public key 237 is held by the user.

[0138] The process of writing data to the memory system 2 when the host device 1 requests a write to the memory system 2 which has been started in read / write mode, and the process of reading data from the memory system 2 when the host device 1 requests a read, are the same as the processes described in the second embodiment, so no explanation is provided.

[0139] Furthermore, the read process of the memory system 2 when the host device 1 requests a read from the memory system 2 which has been started in read mode is the same as the process described in the second embodiment, so no explanation is provided.

[0140] (Fourth variation) In the fourth modified example, the memory card 3 may include an encryption circuit and a public key 237. Note that components similar to those in the above embodiments are denoted by the same reference numerals and their detailed descriptions are omitted.

[0141] Figure 18 is a schematic diagram showing the general configuration of the memory system 2 according to the fourth modified example. Unlike the memory system 2 shown in Figure 13, in which the memory system 2 is equipped with an encryption circuit 321 and a public key 237, the memory card 3 is equipped with the encryption circuit 321 and the public key 237.

[0142] The memory system 2 and memory card 3 shown in Figure 18 differ in that the second memory controller 32 of the memory card 3 is equipped with an encryption circuit 321, the second non-volatile memory 33 of the memory card 3 stores the public key 237, the memory card 3 is connected to the memory system 2 via an SD interface 81, and the first memory controller 22 issues a data writing instruction to the second non-volatile memory 33 to the second memory controller 32 via the SD interface 81.

[0143] The second memory controller 32, when writing data to the second non-volatile memory 33, causes the encryption circuit 321 to perform encryption using an encryption key, and writes the encrypted data to the second non-volatile memory 33. The encryption circuit 321 encrypts the data using an encryption method. The encryption circuit 321 can be implemented using hardware such as a logic circuit or software.

[0144] The public key 237 stored in the second non-volatile memory 33 is stored in the second non-volatile memory 33, for example, by the user writing to the memory system 2, which houses the memory card 3, from the host device 1. Furthermore, for example, the private key for decryption corresponding to the public key 237 is held by the user.

[0145] Next, we will explain the data writing process of the memory system 2 when the host device 1 requests a write to the memory system 2, which has been started in read / write mode.

[0146] The first memory controller 22 according to the fourth modified example processes a data write command from the host device 1. The first memory controller 22 then refers to the first logic-physical conversion table 233, identifies the physical address corresponding to the logical address included in the write request, and performs the write process of the data to be written by the write command to the first non-volatile memory 23 at the identified physical address.

[0147] The second memory controller 32 reads the public key 237 from the second non-volatile memory 33 and instructs the encryption circuit 321 to encrypt the data to be written to the first non-volatile memory 23 using the read public key 237. The first memory controller 22 then refers to the second logic-physical conversion table 333 to identify the physical address of the second non-volatile memory 33 corresponding to the logical address specified in the write request, and performs the write operation of the second user data 334, encrypted by the encryption circuit 321, to the identified physical address.

[0148] When the host device 1 requests a read from the memory system 2, which has been started in read / write mode and read mode, the read process of the memory system 2 is the same as the process described in the second embodiment, so no explanation is provided.

[0149] (Fifth variation) In the fifth variation, a configuration is described in which the memory system 2 sets write-once areas for the first non-volatile memory 23 and the second non-volatile memory 33. Specifically, in order to enhance data integrity, the memory system 2 sets write-once areas in the first non-volatile memory 23 and the second non-volatile memory 33, where data can be written only once, and writes to the first non-volatile memory 23 and the second non-volatile memory 33. If the logical address to which the host device 1 is to write has already been written, the memory system 2 prohibits writing data based on the data specified in the write request to the first non-volatile memory 23 and the second non-volatile memory 33.

[0150] For example, the first memory controller 22 processes a data write command from the host device 1. Next, the first memory controller 22 processes a logical address of the write command from the host device 1. Then, the first memory controller 22 determines whether the logical address to be written from the host device 1 is writable (a logical address that has never been written to before) or write-protected (a logical address that has already been written to).

[0151] The first non-volatile memory 23 according to the fourth modified example stores written logical address information together with the first logical-physical conversion table 233. The written logical address information includes information on whether the logical address to be written to is already written or unused. For example, the first memory controller 22 refers to the first logical-physical conversion table 233 and the written logical address information to determine whether the logical address to be written to from the host device 1 is writable or write-protected.

[0152] Here, the first memory controller 22 determines that the identified logical address is a writable logical address, then converts the logical address to a physical address by referring to the respective logical-physical conversion tables, writes the received data to the first non-volatile memory 23 and the second non-volatile memory 33, and then terminates the data writing process.

[0153] On the other hand, if the first memory controller 22 determines that the identified logical address has already been written to and is therefore unwriteable, it returns an error to the host device 1 and terminates the data writing process.

[0154] Figure 19 is a flowchart illustrating the operation of the memory system 2 according to the fifth modified example. Steps S91 and S92 shown in Figure 19 are the same processes as steps S91 and S92 shown in Figure 8, so their explanation is omitted.

[0155] In step S191, the first memory controller 22 performs a process to identify the logical address of the write command from the host device 1 (step S191). In step S192, the first memory controller 22 performs a process to determine whether the logical address specified by the write command from the host device 1 is writable or write-protected (step S192).

[0156] Here, if the first memory controller 22 determines that the identified logical address is a writable logical address (step S192: Yes), it proceeds to step S92. On the other hand, if the first memory controller 22 determines that the identified logical address has already been written to and is not writable (step S192: No), it proceeds to step S193. In step S193, the first memory controller 22 returns an error to the host device 1 (step S193).

[0157] As described above, in the fifth modification, a write-once area is set in the first non-volatile memory 23 and the second non-volatile memory 33, allowing data to be written only once. If the logical address to which data is to be written from the host device 1 has already been written, writing data based on the data specified in the write request to the first non-volatile memory 23 and the second non-volatile memory 33 is prohibited. This enhances data integrity in the fifth modification.

[0158] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0159] 1...Host device, 2...Memory system, 3...Memory card 4…SD interface, 5…First interface, 8...Second interface, 22...First memory controller, 23...First non-volatile memory, 32...Second memory controller, 33…Second non-volatile memory

Claims

1. The first non-volatile memory, A first memory controller that controls the first non-volatile memory via a first interface and is connectable to a host device, A connection section to which a memory card comprising a second non-volatile memory and a second memory controller for controlling the second non-volatile memory can be connected, A memory system comprising, The first memory controller is When the memory card is connected to the memory system, the identifier of the second non-volatile memory is obtained from the memory card. In response to a write request from the host device, if the first identification ID, which is the identifier of the first non-volatile memory, matches the second identification ID, which is the identifier of the second non-volatile memory that has been obtained, data based on the data specified in the write request is written to the first non-volatile memory and the second non-volatile memory. Memory system.

2. The memory system comprises a first set of terminals, The first memory controller communicates with the host device in accordance with the SD standard via the first plurality of terminals. The memory system according to claim 1.

3. The memory card is equipped with a second set of terminals, The second memory controller is capable of communicating with the host device in accordance with the SD standard via the second set of terminals. The memory system according to claim 1.

4. The second non-volatile memory is equipped with a third set of terminals, The first memory controller writes data based on the data specified in the write request to the second non-volatile memory via the third plurality of terminals. The memory system according to claim 1.

5. The first memory controller includes an encryption circuit, The first memory controller writes data based on the data specified in the write request to the first non-volatile memory, encrypts the data based on the data specified in the write request using the encryption circuit, and writes the encrypted data to the second non-volatile memory. The memory system according to claim 1.

6. The first non-volatile memory stores the public key used for encryption by the encryption circuit, The first memory controller reads the public key from the first non-volatile memory and causes the encryption circuit to encrypt using the read public key. The memory system according to claim 5.

7. The first non-volatile memory and the second non-volatile memory are configured with a write-once area in which the data can be written only once. The first memory controller prohibits writing data based on the data specified in the write request to the first non-volatile memory and the second non-volatile memory if the logical address to which the host device is to write has already been written. The memory system according to claim 1.

8. The memory system is an SD card. The memory card is an SD card with a different shape from the memory system. The memory system according to claim 2 or 3.

9. The first identification ID is stored in the first non-volatile memory. The first memory controller reads the first identification ID from the first non-volatile memory and obtains the first identification ID. The memory system according to claim 1.

10. The aforementioned connection part is a slot capable of storing the memory card. The memory system according to claim 1.

11. The second identification ID is stored in the second non-volatile memory. The first memory controller connects to the second non-volatile memory via a second interface when the memory card is placed in the slot, reads the second identification ID from the second non-volatile memory via the second interface, and obtains the second identification ID. The memory system according to claim 10.

12. The second non-volatile memory, upon receiving a read command for the second identification ID from the first memory controller via the second interface, outputs the second identification ID to the first memory controller. The memory system according to claim 11.

13. A control method performed by a first memory controller that controls a first non-volatile memory via a first interface and is connectable to a host device, wherein When a memory card comprising a second non-volatile memory and a second memory controller for controlling the second non-volatile memory is connected, the identifier of the memory card is obtained from the memory card, In response to a write request from the host device, if the first identification ID, which is the identifier of the memory system, and the second identification ID, which is the identifier of the acquired memory card, match, data based on the data specified in the write request is written to the first non-volatile memory and the second non-volatile memory. Control method.

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