Semiconductor integrated circuits

Abstract

One embodiment aims to provide a semiconductor integrated circuit that can appropriately cut off power to a connected destination. [Solution] According to one embodiment, a semiconductor integrated circuit is provided having a switch, a first control circuit, and a second control circuit. The switch is connected between a first power supply and a second power supply. The switch turns off when it receives a first level at its control terminal. The first control circuit has an input node and an output node. The output node is connected to the control terminal of the switch. The second control circuit has an output node and an input node. The input node is connected to the control terminal of the switch. The semiconductor integrated circuit satisfies at least one of the following: in the first control circuit, the driving force to a first level is greater than the driving force to a second level; and in the second control circuit, the driving force to a second level is greater than the driving force to a first level.

Description

[Technical Field]

[0001] This embodiment relates to a semiconductor integrated circuit. [Background technology]

[0002] Semiconductor integrated circuits, such as power switches, can receive power and supply or interrupt that power to connected circuits. In semiconductor integrated circuits, it is desirable to properly interrupt the power supply to connected circuits. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2004-236001 [Overview of the project] [Problems that the invention aims to solve]

[0004] One embodiment aims to provide a semiconductor integrated circuit that can appropriately cut off power to a connected destination. [Means for solving the problem]

[0005] According to one embodiment, a semiconductor integrated circuit is provided having a switch, a first control circuit, and a second control circuit. The switch is connected between a first power supply and a second power supply. The switch turns off when it receives a first level at its control terminal. The first control circuit has an input node and an output node. The output node is connected to the control terminal of the switch. The second control circuit has an output node and an input node. The input node is connected to the control terminal of the switch. The semiconductor integrated circuit satisfies at least one of the following: in the first control circuit, the driving force to a first level is greater than the driving force to a second level; and in the second control circuit, the driving force to a second level is greater than the driving force to a first level. [Brief explanation of the drawing]

[0006] [Figure 1] A plan view showing the configuration of a semiconductor integrated circuit according to the first embodiment. [Figure 2] A circuit diagram showing the configuration of a semiconductor integrated circuit according to the first embodiment. [Figure 3] A circuit diagram showing the configuration of the power switch in the first embodiment. [Figure 4] A circuit diagram showing the detailed configuration of the power switch in the first embodiment. [Figure 5] A figure showing the threshold voltage distribution of SVT and LVT in the first embodiment. [Figure 6] Waveform diagram showing the operation of the power switch in the first embodiment. [Figure 7] A circuit diagram showing the configuration of the power switch in the second embodiment. [Figure 8] A circuit diagram showing the detailed configuration of the power switch in the second embodiment. [Figure 9] A diagram showing the leakage current path in the second embodiment. [Figure 10] A circuit diagram showing the configuration of the power switch in the third embodiment. [Figure 11] A circuit diagram showing the detailed configuration of the power switch in the third embodiment. [Figure 12] A diagram showing the adjustment of the voltage division ratio by the assist circuit in the third embodiment. [Figure 13] A circuit diagram showing the detailed configuration of the power switch in the fourth embodiment. [Modes for carrying out the invention]

[0007] The semiconductor integrated circuit according to the embodiment will be described in detail below with reference to the attached drawings. However, the present invention is not limited to these embodiments.

[0008] (First Embodiment) The semiconductor integrated circuit according to the first embodiment receives power and can supply the received power to the circuit at the connection destination or cut off the supply. However, a device for appropriately cutting off the power supply to the connection destination is provided.

[0009] As shown in FIG. 1, the semiconductor integrated circuit 1 has a power supply terminal TM1, a control terminal TM2, a power supply circuit 2, a plurality of circuit blocks 3A to 3C, and a control circuit 4. FIG. 1 is a plan view showing the configuration of the semiconductor integrated circuit.

[0010] The power supply circuit 2 is connected to the power supply terminal TM1, the control circuit 4, and the plurality of circuit blocks 3A to 3C. The control circuit 4 is connected to the control terminal TM2 and the power supply circuit 2. Each of the plurality of circuit blocks 3A to 3C is connected to the power supply circuit 2.

[0011] The control circuit 4 receives a control signal CTR from the outside (for example, a controller) via the control terminal TM2. The control circuit 4 generates control signals CNTA, CNTB, and CNTC according to the control signal CTR and supplies them to the power supply circuit 2.

[0012] The power supply circuit 2 receives a power supply voltage TVDD from the outside (for example, a controller) via the power supply terminal TM1. The power supply circuit 2 generates power supply voltages VDD_A, VDD_B, and VDD_C using the power supply voltage TVDD. The power supply circuit 2 supplies or cuts off the power supply voltages VDD_A, VDD_B, and VDD_C to the circuit blocks 3A, 3B, and 3C, respectively, according to the control signals CNTA, CNTB, and CNTC.

[0013] As shown in FIG. 2, the power supply circuit 2 is configured to supply power and cut off power to the plurality of circuit blocks 3A, 3B, and 3C, respectively. FIG. 2 is a circuit diagram showing the configuration of the power supply circuit 2.

[0014] The power supply circuit 2 has multiple power switch groups 2A, 2B, and 2C. These power switch groups 2A, 2B, and 2C correspond to multiple circuit blocks 3A, 3B, and 3C, and to multiple control lines CNTA, CNTB, and CNTC. Each power switch group 2 is connected between the power supply terminal TM1 and the corresponding circuit block 3.

[0015] The power switch group 2A is connected to power terminal TM1 via the global power line TVDD, to circuit block 3A via the local power line VDD_A, and to control circuit 4 via the control line CNTA.

[0016] Let n be any integer greater than or equal to 2. The power switch group 2A is configured to supply power to and cut off power to circuit block 3A, respectively. The power switch group 2A has n power switches (PSWs) 21_1 to 21_n. The n PSWs 21_1 to 21_n are connected in parallel between the global power line TVDD and the local power line VDD_A, and in series with respect to the control line CNTA.

[0017] Each PSW21 has its input node IN connected to the control line CNTA or the previous PSW21, its output node OUT connected to the next PSW21, its power node TVDD connected to the global power line TVDD, and its power node VDD connected to the corresponding circuit block 3A via the local power line VDD_A.

[0018] The n PSW21_1 to 21_n receive the control signal CNTA serially. Each PSW21 supplies or cuts off power to circuit block 3A according to the control signal CNTA.

[0019] The PSW group 2B is connected to power terminal TM1 via the global power line TVDD, to circuit block 3B via the local power line VDD_B, and to control circuit 4 via the control line CNTB.

[0020] The PSW group 2B is configured to supply and cut off power to circuit block 3B, respectively. The PSW group 2B has n PSWs 22_1 to 22_n. The n PSWs 22_1 to 22_n are connected in parallel between the global power line TVDD and the local power line VDD_B, and in series with the control line CNTB.

[0021] Each PSW22 has its input node IN connected to the control line CNTB or the previous PSW22, its output node OUT connected to the next PSW22, its power node TVDD connected to the global power line TVDD, and its power node VDD connected to circuit block 3B via the local power line VDD_B.

[0022] The n PSW22_1 to 22_n receive the control signal CNTB serially. Each PSW22 supplies or cuts off power to circuit block 3B according to the control signal CNTB.

[0023] The PSW group 2C is connected to power terminal TM1 via the global power line TVDD, to circuit block 3C via the local power line VDD_C, and to control circuit 4 via the control line CNTC.

[0024] The PSW group 2C is configured to supply and cut off power to circuit block 3C, respectively. The PSW group 2C has n PSWs 23_1 to 23_n. The n PSWs 23_1 to 23_n are connected in parallel between the global power line TVDD and the local power line VDD_C, and in series with the control line CNTC.

[0025] Each PSW23 has its input node IN connected to the control line CNTC or the previous PSW23, its output node OUT connected to the next PSW23, its power node TVDD connected to the global power line TVDD, and its power node VDD connected to circuit block 3C via the local power line VDD_C.

[0026] The n PSW23_1 to 23_n receive the control signal CNTC serially. Each PSW23 supplies or cuts off power to circuit block 3C according to the control signal CNTC.

[0027] Next, the configuration of each PSW21 will be explained using Figure 3. Figure 3 is a circuit diagram showing the configuration of PSW21. Figure 3 shows an example of the configuration of PSW21, but the configurations of PSW22 and PSW23 are the same as those of PSW21.

[0028] The PSW21 includes a switch 213, a control circuit 211, and a control circuit 212.

[0029] Switch 213 is connected between power node TVDD and power node VDD. One end 213a of switch 213 is connected to power node TVDD, the other end 213b is connected to power node VDD, and the control terminal 213c is connected to node N1. Switch 213 turns off when it receives a high level at the control terminal 213c.

[0030] Switch 213 may include transistor PM1. Transistor PM1 is, for example, a PMOS transistor. Transistor PM1 has its source connected to power node TVDD, its drain connected to power node VDD, and its gate connected to node N1. Transistor PM1 turns off when it receives a high level at its gate.

[0031] The control circuit 211 is connected between the input node IN and node N1 of the PSW21. The control circuit 211 has input node 211a connected to input node IN, output node 211b connected to control terminal 213c of switch 213 via node N1, and power node 211c connected to power node TVDD.

[0032] The control circuit 211 may include an inverter INV1. The inverter INV1 has an input node connected to input node IN and an output node connected to node N1.

[0033] The control circuit 212 is connected between node N1 and the output node OUT of PSW21. The control circuit 212 has input node 211a connected to the control terminal 213c of switch 213 via node N1, output node 212b connected to output node OUT, and power node 212c connected to power node TVDD.

[0034] The control circuit 212 may include an inverter INV2. The inverter INV2 has an input node connected to node N1 and an output node connected to output node OUT.

[0035] The PSW21 is configured such that the driving force to the H level in the control circuit 211 is greater than the driving force to the L level, and the driving force to the L level in the control circuit 212 is greater than the driving force to the H level.

[0036] The PSW21 may be configured as shown in Figure 4. Figure 4 is a circuit diagram showing the detailed configuration of the PSW21.

[0037] The inverter INV1 of the control circuit 211 has transistors PM11 and NM11. Transistors PM11 and NM11 are inverter-connected. Transistor PM11 may be a PMOS transistor. Transistor NM11 may be an NMOS transistor. The gates of transistors PM11 and NM11 are commonly connected and connected to the input node IN, and the drains are commonly connected and connected to node N1. The source of transistor PM11 is connected to the power node TVDD. The source of transistor NM11 is connected to the ground node VSS.

[0038] The threshold voltage of transistor PM11 is lower than the threshold voltage of transistor NM11. For example, the difference between the center voltage of the threshold voltage distribution of transistor PM11 and the center voltage of the threshold voltage distribution of transistor NM11 is greater than the half-width of the threshold voltage distribution of transistor PM11 (see Figure 5(b)). As a result, the driving force to the H level in the control circuit 211 may be greater than the driving force to the L level.

[0039] Transistor PM11 may be composed of an LVT (Low threshold voltage transistor). Transistor NM11 may be composed of an SVT (Standard threshold voltage transistor).

[0040] Inverter INV1 is composed of an LVT transistor PM11 and an SVT transistor NM11, so the output tends to be high when the input is low. The threshold voltage distribution of the LVT PMOS is shown by the solid line in Figure 5(b), and the threshold voltage distribution of the SVT NMOS is shown by the dashed line in Figure 5(b). Figure 5 shows the threshold voltage distributions of the SVT and LVT. In Figure 5(b), the vertical axis represents the number of transistors and the horizontal axis represents voltage.

[0041] The threshold voltage distribution of the PMOS in an LVT is shifted to a lower voltage side compared to the threshold voltage distribution of the NMOS in an SVT. The center voltage Vcp of the threshold voltage distribution of the PMOS in an LVT is lower than the center voltage Vcn of the threshold voltage distribution of the NMOS in an SVT. The difference between the center voltages Vcp and Vcn is greater than or equal to the half-width HWp of the threshold voltage distribution of the PMOS in an LVT.

[0042] As shown in Figure 5(b), due to variations, even if the threshold voltage of the LVT's PMOS is higher (●) and the threshold voltage of the SVT's NMOS is lower (○), when an L level (e.g., V1) is supplied to the inverter's input node, the NMOS may turn off, the PMOS may turn on, and an H level may be output from the inverter's output node.

[0043] The inverter INV2 of the control circuit 212 has transistors PM12 and NM12. Transistors PM12 and NM12 are inverter-connected. Transistor PM12 may be a PMOS transistor. Transistor NM12 may be an NMOS transistor. The gates of transistors PM12 and NM12 are commonly connected and connected to node N1, and the drains are commonly connected and connected to the output node OUT. The source of transistor PM12 is connected to the power node TVDD. The source of transistor NM12 is connected to the ground node VSS.

[0044] The threshold voltage of transistor NM12 is lower than the threshold voltage of transistor PM12. For example, the difference between the center voltage of the threshold voltage distribution of transistor NM12 and the center voltage of the threshold voltage distribution of transistor PM12 is greater than the half-width of the threshold voltage distribution of transistor NM12. As a result, the driving force to the L level in the control circuit 212 may be greater than the driving force to the H level.

[0045] Transistor NM12 may be composed of an LVT (Low threshold voltage transistor). Transistor PM12 may be composed of an SVT (Standard threshold voltage transistor).

[0046] Inverter INV2 is composed of an LVT transistor NM12 and an SVT transistor PM12, so when the input is at a high level, the output tends to be at a low level.

[0047] The threshold voltage distribution of the NMOS in an LVT is shifted to a lower voltage side compared to the threshold voltage distribution of the PMOS in an SVT. The center voltage of the threshold voltage distribution of the NMOS in an LVT is lower than the center voltage of the threshold voltage distribution of the PMOS in an SVT. The difference between the center voltage of the threshold voltage distribution of the NMOS in an LVT and the center voltage of the threshold voltage distribution of the PMOS in an SVT is greater than the half-width of the threshold voltage distribution of the NMOS in an LVT.

[0048] Due to variations, even if the threshold voltage of the LVT's NMOS is higher and the threshold voltage of the SVT's PMOS is lower, when a high level is supplied to the inverter's input node, the PMOS may turn off, the NMOS may turn on, and a low level may be output from the inverter's output node.

[0049] For example, as shown in Figure 6(b), the potential of the control signal CNTA supplied to the input node IN of the first stage PSW21_1 is maintained at an L level, and as shown in Figure 6(a), at timing t1, the potential of the power supply line TVDD begins to rise from an L level. Figure 6 is a waveform diagram showing the operation of PSW21.

[0050] At this time, transistor PM1 of switch 213 is turned off.

[0051] Immediately after timing t1, in the inverter INV1 of PSW21_1, transistor PM11 turns on because it is composed of an LVT, although the gate-source voltage is relatively small. As a result, the potential of node N1 begins to follow at a high level close to the potential of the power line TVDD, as shown by the dashed line in Figure 6(c). Consequently, transistor PM1 of switch 213 remains in the off state.

[0052] Accordingly, in the inverter INV2 of PSW21_1, transistor NM12 turns on because it is composed of an LVT, although its gate-source voltage is relatively small. As a result, the potentials of the output node OUT of PSW21_1 and the input node IN of the next stage PSW21_2 are maintained near the L level, as shown by the dashed line in Figure 6(d).

[0053] At timing t2, in the inverter INV1 of PSW21_1, transistor PM11 can remain on because it is composed of an LVT, although its gate-source voltage is relatively small. As a result, the potential of node N1 can continue to follow at a high level close to the potential of the power line TVDD, as shown by the dashed line in Figure 6(c). Consequently, transistor PM1 of switch 213 remains in the off state.

[0054] Accordingly, in the inverter INV2 of PSW21_1, transistor NM12 can remain on because it is composed of an LVT, although its gate-source voltage is relatively small. As a result, the potential of the output node OUT of PSW21_1 and the input node IN of the next stage PSW21_2 are maintained near the L level, as shown in Figure 6(d).

[0055] At timing t3, in the inverter INV1 of PSW21_1, transistor PM11 remains on because the gate-source voltage is relatively high. As a result, the potential of node N1 can continue to follow at a high level close to the potential of the power line TVDD, as shown by the dashed line in Figure 6(c). Consequently, transistor PM1 of switch 213 remains in the off state.

[0056] Accordingly, in the inverter INV2 of PSW21_1, transistor NM12 remains on because the gate-source voltage is relatively large. As a result, the potentials of the output node OUT of PSW21_1 and the input node IN of the next stage PSW21_2 are maintained at an L level, as shown in Figure 6(d).

[0057] From timing t3 onward, in the inverter INV1 of PSW21_1, transistor PM11 is stably turned on, and the potential of node N1 stably follows at a high level close to the potential of the power line TVDD, as shown by the dashed line in Figure 6(c). As a result, transistor PM1 of switch 213 is stably kept in the off state.

[0058] In response, in the inverter INV2 of PSW21_1, transistor NM12 is stably turned on, and the potentials of the output node OUT of PSW21_1 and the input node IN of the next stage PSW21_2 are stably maintained at an L level, as shown in Figure 6(d).

[0059] As described above, in the first embodiment, in the semiconductor integrated circuit 1, the PSW21 is configured such that the driving force to the H level in the control circuit 211 is greater than the driving force to the L level. This suppresses leakage at power-up in the switch 213 that should be turned off, and reduces power consumption in the standby state. Therefore, the power to the destination connected to the PSW21 can be appropriately cut off.

[0060] Furthermore, in the first embodiment, the PSW21 in the semiconductor integrated circuit 1 is configured such that the driving force to the L level in the control circuit 212 is greater than the driving force to the H level. This makes it easy to suppress the signal transmitted to the next stage PSW21 to the L level, suppresses leakage caused by the influence of the preceding stage when the power is started up in the switch 213 that should be turned off, and reduces power consumption in the standby state. Therefore, the power to the connected destination can also be appropriately cut off for the next stage PSW21.

[0061] For example, if an inverter is composed of SVT PMOS and SVT NMOS transistors, the output may be low when the input is low. The threshold voltage distribution of the SVT PMOS is shown by the solid line in Figure 5(a), and the threshold voltage distribution of the SVT NMOS is shown by the dashed line in Figure 5(a). Figure 5 shows the threshold voltage distributions of SVT and LVT. In Figure 5(a), the vertical axis represents the number of transistors and the horizontal axis represents voltage. The threshold voltage distributions of the SVT PMOS and the SVT NMOS almost overlap. The center voltage Vcp of the SVT PMOS threshold voltage distribution and the center voltage Vcn of the SVT NMOS threshold voltage distribution are approximately equal.

[0062] As shown in Figure 5(a), due to variations, the threshold voltage of the SVT's PMOS may be higher, as shown by ●, and the threshold voltage of the SVT's NMOS may be lower, as shown by ○. When an L level (e.g., V1) is supplied to the inverter's input node, the NMOS may turn on and the PMOS may turn off, resulting in an L level being output from the inverter's output node.

[0063] For example, consider PSW21s, which is a modified version of PSW21 shown in Figure 4, in which the inverter INV1s of the control circuit 211s includes SVT transistors PM11s and NM11, and the inverter INV2s of the control circuit 212s includes SVT transistors PM12 and NM12s.

[0064] As shown in Figure 6(b), the potential of the control signal CNTS supplied to the input node IN of the first stage PSW21s_1 is maintained at an L level, and as shown in Figure 6(a), at timing t1, the potential of the power supply line TVDD begins to rise from an L level.

[0065] At this time, transistor PM1 of switch 213 is turned off.

[0066] Immediately after timing t1, in the inverter INV1s of PSW21s_1, transistor PM11s is off because its gate-source voltage is relatively small and it is composed of an SVT. As a result, the potential of node N1 begins to dissociate from the potential of the power line TVDD to an L level, as shown by the dotted line in Figure 6(c). Consequently, transistor PM1 of switch 213 begins to enter a half-on state.

[0067] Accordingly, in the inverter INV2s of PSW21s_1, the transistor NM12s is turned off because its gate-source voltage is relatively small and it is configured as an SVT. As a result, the potentials of the output node OUT of PSW21s_1 and the input node IN of the next stage PSW21s_2 begin to follow at a high level close to the potential of the power supply line TVDD, as shown by the dotted line in Figure 6(d).

[0068] At timing t2, in the inverter INV1s of PSW21s_1, transistor PM11s is off because its gate-source voltage is relatively small and it is composed of an SVT. As a result, the potential of node N1 continues to dissociate to an L level from the potential of the power line TVDD, as shown by the dotted line in Figure 6(c). Consequently, transistor PM1 of switch 213 enters an even stronger half-on state.

[0069] Accordingly, in the inverter INV2s of PSW21s_1, the transistor NM12s remains off because its gate-source voltage is relatively small and it is configured as an SVT. As a result, the potentials of the output node OUT of PSW21s_1 and the input node IN of the next stage PSW21s_2 continue to follow at a high level close to the potential of the power line TVDD, as shown by the dotted line in Figure 6(d).

[0070] At timing t3, in the inverter INV1s of PSW21s_1, transistor PM11s turns on because the gate-source voltage is relatively large. As a result, the potential of node N1 begins to follow at a high level close to the potential of the power line TVDD, as shown by the dotted line in Figure 6(c). Consequently, transistor PM1 of switch 213 transitions from the half-on state to the off state and begins to remain in the off state.

[0071] In response, in the inverter INV2s of PSW21s_1, transistor NM12s turns on because the gate-source voltage is relatively large. As a result, the potential of the output node OUT of PSW21s_1 and the input node IN of the next stage PSW21_2 become L level, as shown by the dotted lines in Figure 6(d), and begin to be maintained at L level.

[0072] In other words, in PSW21s, the transistor PM1 of switch 213 is in a half-on state during timings t1 to t3, so the power consumption in standby mode tends to increase due to leakage from transistor PM1.

[0073] On the other hand, in this embodiment, the PSW21 is configured such that the inverter INV1 of the control circuit 211 includes the LVT transistor PM11 and the SVT transistor NM11, and the inverter INV1 of the control circuit 212 includes the SVT transistor PM12 and the LVT transistor NM12. This suppresses leakage at power startup in the switch 213 that should be turned off, and reduces power consumption in the standby state.

[0074] Furthermore, PSW21' may be configured such that the driving force to the H level in the control circuit 211 is greater than the driving force to the L level, and the driving force to the L level and the driving force to the H level are equal in the control circuit 212s. PSW21' may be modified to include the SVT transistor PM12 and the SVT transistor NM12s in the inverter INV2 shown in Figure 4, thereby configuring the inverter INV2s of the control circuit 212s. In this case, since the driving force to the H level in the control circuit 211 of PSW21' is greater than the driving force to the L level, node N1 can be easily brought to the H level when the power is started up. This suppresses leakage at the switch 213 that should be turned off when the power is started up.

[0075] Alternatively, PSW21” may be configured such that the driving force to the H level and the driving force to the L level are equal in the control circuit 211s, and the driving force to the L level is greater than the driving force to the H level in the control circuit 212. PSW21” may be configured as the inverter INV1s of the control circuit 211s by modifying the inverter INV1 shown in Figure 4 to include the SVT transistor PM11s and the SVT transistor NM11. In this case, since the driving force to the L level in the control circuit 212 of PSW21” is greater than the driving force to the H level, the output node OUT can be easily set to the L level when the power is started up. This suppresses leakage caused by the preceding stage at power start-up in the switch 213 that should be turned off.

[0076] (Second embodiment) Next, a semiconductor integrated circuit 1i according to the second embodiment will be described. The following description will focus on the differences from the first embodiment.

[0077] In the first embodiment, a configuration is shown in which leakage of the switch 213 is reduced by adjusting the driving force of the control circuit in the PSW, while in the second embodiment, a configuration is shown in which leakage of the switch 213 is reduced by adding an assist circuit in the PSW.

[0078] In the semiconductor integrated circuit 1i, the PSW21i (or 22i, 23i) may be configured as shown in Figure 7. Figure 7 is a circuit diagram showing the configuration of PSW21i in the second embodiment. While Figure 7 illustrates the configuration of PSW21i, the configurations of PSW22i and PSW23i are the same as those of PSW21i.

[0079] The PSW21i has control circuits 211s and 212s instead of control circuits 211 and 212 (see Figure 3), and further has assist circuits 214i and 215i.

[0080] The control circuit 211s may have equal driving force to the H level and driving force to the L level. The inverter INV1s of the control circuit 211s may include the SVT transistor PM11s and the SVT transistor NM11, as shown in Figure 8. Figure 8 is a circuit diagram showing the detailed configuration of the PSW21i in the second embodiment.

[0081] The control circuit 212s shown in Figure 7 may have equal driving force to the H level and driving force to the L level. The inverter INV2s of the control circuit 212s may include the SVT transistor PM11s and the SVT transistor NM11, as shown in Figure 8.

[0082] The assist circuit 214i shown in Figure 7 is connected between the control circuit 211s and the switch 213. The assist circuit 214i may also be connected between the control circuit 211s and node N1. The assist circuit 214i is connected between the power supply potential TVDD and the ground potential VSS at a position between the control circuit 211s and the switch 213. The assist circuit 214i may also be connected between the power supply potential TVDD and the ground potential VSS at a position between the control circuit 211s and node N1. As a result, the assist circuit 214i assists in the appearance of an H level at the output node of the control circuit 211s when an L level is input to the input node of the control circuit 211s while the switch 213 remains off.

[0083] The assist circuit 214i includes at least one of transistor PM21 or transistor NM21, as shown in Figure 8. Figure 8 illustrates an assist circuit 214i including transistors PM21 and NM21. Transistors PM21 and NM21 are connected in reverse diode configuration. Transistor PM21 may be a PMOS transistor. Transistor NM21 may be an NMOS transistor.

[0084] Transistors PM21 and NM21 are connected to node N1 with their drains connected in common. Transistor PM21's gate, source, and back gate are each connected to the power node TVDD. Transistor NM21's source is connected to the power node TVDD, and its gate and back gate are each connected to the ground node VSS.

[0085] In transistor PM21, as shown in Figure 9(b), the gate is connected to the power node TVDD and is therefore kept in the off state. However, since the source is connected to the power node TVDD and the drain is floating, leakage current flows from the source to the drain. This causes a small amount of charge to be accumulated in the drain, which can raise the potential towards the high level.

[0086] In transistor NM21, as shown in Figure 9(a), the gate is connected to the ground node VSS and is therefore kept in the off state. However, since the source is connected to the power node TVDD and the drain is floating, leakage current flows from the source to the drain. This allows a small amount of charge to be accumulated in the drain, potentially raising its potential towards the high level.

[0087] This helps ensure that when an L level is input to the input node of the control circuit 211s while the switch 213 remains in the OFF position, an H level appears at the output node of the control circuit 211s.

[0088] The assist circuit 215i shown in Figure 7 is connected between the control circuit 212s and the output node OUT. The assist circuit 215i is connected between the power supply potential TVDD and the ground potential VSS at a position between the control circuit 212s and the output node OUT. As a result, the assist circuit 215i assists in the appearance of an L level at the output node of the control circuit 212s when an H level is input to the input node of the control circuit 212s while the switch 213 remains OFF.

[0089] The assist circuit 215i includes at least one of transistor PM22 or transistor NM22, as shown in Figure 8. Figure 8 illustrates an assist circuit 215i including transistors PM22 and NM22. Transistors PM22 and NM22 are connected in reverse diode configuration. Transistor PM22 may be a PMOS transistor. Transistor NM22 may be an NMOS transistor.

[0090] Transistors PM22 and NM22 have their drains connected in common and are connected to the output node OUT. Transistor PM22 has its source connected to the ground node VSS, and its gate and back gate connected to the power node TVDD. Transistor NM22 has its source, gate, and back gate connected to the ground node VSS.

[0091] In transistor PM22, as shown in Figure 9(d), the gate is connected to the power node TVDD and is therefore kept in the off state. However, the source is connected to the ground node VSS and the drain is floating, so leakage current flows from the drain to the source. This causes a small amount of charge to discharge from the drain, which can draw the potential towards the L level.

[0092] In transistor NM22, as shown in Figure 9(c), the gate is connected to the ground node VSS and therefore remains in the off state. However, since the source is connected to the ground node VSS and the drain is floating, leakage current flows from the drain to the source. This causes a small amount of charge to discharge from the drain, potentially drawing the potential towards the L level.

[0093] This helps ensure that when an H level is input to the input node of the control circuit 212s while the switch 213 remains in the OFF position, an L level appears at the output node of the control circuit 212s.

[0094] As described above, in the second embodiment, in the PSW21i of the semiconductor integrated circuit 1i, the assist circuit 214i assists in the appearance of an H level at the output node of the control circuit 211s when an L level is input to the input node of the control circuit 211s while the switch 213 is kept off. This suppresses leakage at power-up in the switch 213 that should be turned off, and reduces power consumption in the standby state. Therefore, power to the destination connected to the PSW21i can be appropriately cut off.

[0095] Furthermore, in the second embodiment, in the PSW21i of the semiconductor integrated circuit 1i, the assist circuit 215i assists in ensuring that an L level appears at the output node of the control circuit 212s when an H level is input to the input node of the control circuit 212s while the switch 213 is kept off. This makes it easy to suppress the signal transmitted to the next stage PSW21i to an L level, suppresses leakage caused by the influence of the preceding stage when the power is started up in the switch 213 which should be turned off, and reduces power consumption in the standby state. Therefore, the power to the connected destination can also be appropriately cut off for the next stage PSW21i.

[0096] Note that PSW21i' may be configured without the assist circuit 214i. In this case, in PSW21i', the assist circuit 215i assists in ensuring that an L level appears at the output node of the control circuit 212s when an H level is input to the input node of the control circuit 212s while the switch 213 remains OFF. This makes it easy to suppress the signal transmitted to the next stage PSW21i to an L level, and suppresses leakage caused by the influence of the preceding stage when the power is started up in the switch 213 which should be turned OFF.

[0097] Alternatively, the PSW21i” may be configured in which the assist circuit 215i is omitted. In this case, the assist circuit 214i in the PSW21i” assists in ensuring that an H level appears at the output node of the control circuit 211s when an L level is input to the input node of the control circuit 211s while the switch 213 is kept off. This suppresses leakage at power-up in the switch 213 that should be turned off.

[0098] (Third embodiment) Next, a semiconductor integrated circuit 1j according to the third embodiment will be described. The following description will focus on the differences from the first and second embodiments.

[0099] In the second embodiment, an assist circuit utilizing leakage is illustrated, while in the third embodiment, an assist circuit utilizing capacitance is illustrated.

[0100] In the semiconductor integrated circuit 1j, the PSW21j (or 22j, 23j) may be configured as shown in Figure 10. Figure 10 is a circuit diagram showing the configuration of PSW21j in the third embodiment. While Figure 10 illustrates the configuration of PSW21j, the configurations of PSW22j and PSW23j are similar to those of PSW21j.

[0101] The PSW21j has assist circuits 214j and 215j instead of assist circuits 214i and 215i (see Figure 7).

[0102] The assist circuit 214j shown in Figure 10 is connected between the control circuit 211s and the switch 213. The assist circuit 214j may also be connected between the control circuit 211s and node N1. The assist circuit 214j is connected between the power supply potential TVDD and node N1 at a position between the control circuit 211s and the switch 213. The assist circuit 214j may also be connected between the power supply potential TVDD and node N1 at a position between the control circuit 211s and node N1. As a result, the assist circuit 214j assists in the appearance of an H level at the output node of the control circuit 211s when an L level is input to the input node of the control circuit 211s while the switch 213 remains off.

[0103] The assist circuit 214j has a capacitive element C1. One end of the capacitive element C1 is connected to the control terminal of the switch 213 and the other end is connected to the power node TVDD.

[0104] The assist circuit 214j includes a transistor PM31, as shown in Figure 11. The transistor PM31 is capacitively connected. The transistor PM31 may also be a PMOS transistor.

[0105] Transistor PM31 has its source and drain commonly connected to power node TVDD, and its gate connected to node N1. This allows transistor PM31 to function as a capacitive element C1.

[0106] For example, assume that the gate-drain capacitance C of transistor PM1 GD and the gate-source capacitance C of transistor PM1 GS are both equal to C. When the assist circuit 214j is omitted, as shown in Fig. 12(a), near the node N1, there is a capacitance C GD between the power supply node TVDD and the power supply node VDD and the capacitance C GS between the node N1 and the capacitance C, which are connected in series.

[0107] The voltage division ratio between the voltage V11 between the power supply node VDD and the node N1 and the voltage V12 between the node N1 and the power supply node TVDD is V11:V12 = 1 / C:1 / C = 1:1. When the power supply is started, since the power supply node VDD is at approximately the ground potential (≒0V), the potential of the node N1 becomes about TVDD×1 / 2.

[0108] On the other hand, assume that the gate capacitance of transistor PM31 is C MOS and the capacitance C MOS is equal to C. When the assist circuit 214j is provided, as shown in Fig. 12(b), near the node N1, there is a capacitance C MOS between the power supply node TVDD and the node N1 and the capacitance C GD which are connected in parallel, and a capacitance C GD is connected between the node N1 and the power supply node VDD, forming a configuration.

[0109] The voltage division ratio between the voltage V1 between the power supply node VDD and the node N1 and the voltage V2 between the node N1 and the power supply node TVDD is V1:V2 = 1 / (C + C):1 / C = 1:2. When the power supply is started, since the power supply node VDD is at approximately the ground potential (≒0V), the potential of the node N1 becomes about TVDD×2 / 3.

[0110] That is, by providing the assist circuit 214j, the voltage division ratio above and below the node N1 can be adjusted so that the potential of the node N1 becomes higher when the power supply is started.

[0111] This helps ensure that when an L level is input to the input node of the control circuit 211s while the switch 213 remains in the OFF position, an H level appears at the output node of the control circuit 211s.

[0112] The assist circuit 215j shown in Figure 10 is connected between the control circuit 212s and the output node OUT. The assist circuit 215j is connected between the output node OUT and the ground potential VSS at a position between the control circuit 212s and the output node OUT. As a result, the assist circuit 215j assists in the appearance of an L level at the output node of the control circuit 212s when an H level is input to the input node of the control circuit 212s while the switch 213 remains OFF.

[0113] The assist circuit 215j has a capacitive element C2. One end of the capacitive element C2 is connected to the output node of the control circuit 212s and the other end is connected to the power supply node VDD.

[0114] The assist circuit 215j includes a transistor NM32, as shown in Figure 11. The transistor NM32 is capacitively connected. The transistor NM32 may also be an NMOS transistor.

[0115] The transistor NM32 has its source and drain commonly connected to the power node VDD, and its gate connected to the output node OUT. This allows the transistor NM32 to function as a capacitive element C2.

[0116] For example, if the assist circuit 215j is omitted, when the power is started up, the potential of node N1 does not rise sufficiently and remains near the L level, causing transistor PM12 to be half-on, allowing drain current to flow in and easily charge the parasitic capacitance Cp of the line near output node OUT, which can easily raise the potential of output node OUT.

[0117] On the other hand, when the assist circuit 215j is provided, at power-up, the potential of node N1 does not rise sufficiently and is near the L level, causing transistor PM12 to be half-on and drain current to flow in. However, in addition to the parasitic capacitance Cp of the line, the capacitive element C2 is also charged, making it difficult for the potential of output node OUT to rise easily.

[0118] In other words, by providing the assist circuit 215j, the capacitive load near the output node OUT can be adjusted so that the potential of the output node OUT becomes lower when the power is started up.

[0119] This helps ensure that when an H level is input to the input node of the control circuit 212s while the switch 213 remains in the OFF position, an L level appears at the output node of the control circuit 212s.

[0120] As described above, in the third embodiment, in the PSW21j of the semiconductor integrated circuit 1j, the assist circuit 214j assists in the appearance of an H level at the output node of the control circuit 211s when an L level is input to the input node of the control circuit 211s while the switch 213 is kept off. This suppresses leakage at power-up in the switch 213 that should be turned off, and reduces power consumption in the standby state. Therefore, power to the destination connected to the PSW21j can be appropriately cut off.

[0121] Furthermore, in the third embodiment, in the PSW21j of the semiconductor integrated circuit 1j, the assist circuit 215j assists in ensuring that an L level appears at the output node of the control circuit 212s when an H level is input to the input node of the control circuit 212s while the switch 213 is kept off. This makes it easy to suppress the signal transmitted to the next stage PSW21j to an L level, suppresses leakage due to the influence of the preceding stage when the power is started up in the switch 213 which should be turned off, and reduces power consumption in the standby state. Therefore, the power to the connected destination can also be appropriately cut off for the next stage PSW21j.

[0122] Note that PSW21j' may be configured without the assist circuit 214j. In this case, in PSW21j', the assist circuit 215j assists in ensuring that an L level appears at the output node of the control circuit 212s when an H level is input to the input node of the control circuit 212s while the switch 213 remains OFF. This makes it easy to suppress the signal transmitted to the next stage PSW21j to an L level, and suppresses leakage caused by the preceding stage's influence when the power is started up in the switch 213, which should be turned OFF.

[0123] Alternatively, the PSW21j" may be configured in which the assist circuit 215j is omitted. In this case, the assist circuit 214j in the PSW21j" assists in ensuring that an H level appears at the output node of the control circuit 211s when an L level is input to the input node of the control circuit 211s while the switch 213 is kept off. This suppresses leakage at power-up in the switch 213 that should be turned off.

[0124] Alternatively, the assist circuit 214j may be implemented in a layout configuration that adds coupling capacitance to the line between the control circuit 211s and the switch 213, instead of the capacitive element C1. For example, such a configuration can be realized by arranging the line between the control circuit 211s and the switch 213 in parallel with the other lines.

[0125] Alternatively, the assist circuit 215j may be implemented in a layout configuration that adds coupling capacitance to the line between the control circuit 212s and the output node OUT, instead of the capacitive element C2. For example, such a configuration can be realized by arranging the line between the control circuit 212s and the output node OUT in parallel with other lines.

[0126] (Fourth embodiment) Next, we will describe the semiconductor integrated circuit 1k according to the fourth embodiment. Below, we will mainly describe the parts that differ from the first to third embodiments.

[0127] In the first embodiment, a configuration is exemplified in which the control circuit 211 makes the driving force to the H level greater than the driving force to the L level, and the control circuit 212 adjusts whether the driving force to the L level is greater than the driving force to the H level using the threshold of the transistor. In the fourth embodiment, a configuration is exemplified in which the adjustment is made using the ratio of the gate width to the gate length of the transistor.

[0128] In the semiconductor integrated circuit 1k, PSW21k may be configured as shown in Figure 13. Figure 13 is a circuit diagram showing the detailed configuration of PSW21k. Figure 13 illustrates the configuration of PSW21k, but the configurations of PSW22k and PSW23k are similar to those of PSW21k.

[0129] The inverter INV1k of the control circuit 211k is configured such that the ratio of the gate width to the gate length of a P-type transistor is greater than the ratio of the gate width to the gate length of an N-type transistor. The inverter INV1k may achieve this configuration by making the ratio of the gate width to the gate length of one P-type transistor greater than the ratio of the gate width to the gate length of one N-type transistor. Alternatively, the inverter INV1k may achieve this configuration by connecting multiple transistors in parallel on the power node TVDD side and multiple transistors in series on the ground node VSS side.

[0130] The inverter INV1k has transistors PM111, PM112, NM111, and NM112.

[0131] Transistors PM111 and PM112 are connected in parallel between the power node TVDD and the output node of inverter INV1k. Transistors NM111 and NM112 are connected in series between the output node of inverter INV1k and the ground node VSS. The parallel connection of transistors PM111 and PM112 and the series connection of transistors NM111 and NM112 are connected by an inverter.

[0132] Transistors PM111 and PM112 may each be PMOS transistors. Transistors NM111 and NM112 may each be NMOS transistors.

[0133] Transistors PM111, PM112, NM111, and NM112 have their gates connected in common and are connected to the input node IN. Transistors PM111, PM112, and NM112 have their drains connected in common and are connected to node N1. The source of transistor NM112 is connected to transistor NM111. The drain of transistor NM111 is connected to transistor NM112. The sources of transistors PM111 and PM112 are connected to the power node TVDD, respectively. The source of transistor NM111 is connected to the ground node VSS.

[0134] In inverter INV1k, assuming all transistors are the same size, with gate length L and gate width W, the ratio of gate width to gate length for transistors PM111 and PM112 combined is 2 × W / L, which is greater than the ratio of gate width to gate length for transistors NM111 and NM112 combined is W / (2 × L). This allows the control circuit 211k to provide a driving force to the H level greater than the driving force to the L level.

[0135] In addition, in inverter INV1k, the number of transistors connected in parallel on the power node TVDD side may be three or more, and the number of transistors connected in series on the ground node VSS side may be three or more.

[0136] The inverter INV2k of the control circuit 212k is configured such that the ratio of the gate width to the gate length of an N-type transistor is greater than the ratio of the gate width to the gate length of a P-type transistor. The inverter INV2k may achieve this configuration by making the ratio of the gate width to the gate length of one N-type transistor greater than the ratio of the gate width to the gate length of one P-type transistor. Alternatively, the inverter INV2k may achieve this configuration by connecting multiple transistors in series on the power node TVDD side and multiple transistors in parallel on the ground node VSS side.

[0137] The inverter INV2k has transistors PM121, PM122, NM121, and NM122.

[0138] Transistors PM121 and PM122 are connected in series between the power node TVDD and the output node of inverter INV2k. Transistors NM121 and NM122 are connected in parallel between the output node of inverter INV2k and the ground node VSS. The series connection of transistors PM121 and PM122 and the parallel connection of transistors NM121 and NM122 are connected by an inverter.

[0139] Transistors PM121 and PM122 may each be PMOS transistors. Transistors NM121 and NM122 may each be NMOS transistors.

[0140] Transistors PM121, PM122, NM121, and NM122 have their gates connected in common and are connected to node N1. Transistors PM122, NM121, and NM122 have their drains connected in common and are connected to the output node OUT. The source of transistor PM122 is connected to transistor PM121. The drain of transistor PM121 is connected to transistor PM122. The sources of transistors NM121 and NM122 are connected to the ground node VSS, respectively. The source of transistor PM121 is connected to the power node TVDD.

[0141] In inverter INV2k, assuming all transistors are the same size, with gate length L and gate width W, the ratio of gate width to gate length for transistors NM121 and NM122 combined is 2 × W / L, which is greater than the ratio of gate width to gate length for transistors PM121 and PM122 combined is W / (2 × L). This allows the control circuit 212k to provide a driving force to L level greater than the driving force to H level.

[0142] In the INV2k inverter, the number of transistors connected in series on the power node TVDD side may be three or more, and the number of transistors connected in parallel on the ground node VSS side may be three or more.

[0143] Furthermore, the operation of PSW21k (or PSW22k, PSW23k) is the same as in the first embodiment.

[0144] As described above, in the fourth embodiment, in the semiconductor integrated circuit 1k, the PSW 21k is configured such that the driving force to the H level in the control circuit 211k is greater than the driving force to the L level. This suppresses leakage at power startup in the switch 213 that should be turned off, and reduces power consumption in the standby state. Therefore, the power to the destination connected to the PSW 21k can be appropriately cut off.

[0145] Furthermore, in the fourth embodiment, in the semiconductor integrated circuit 1k, the PSW 21k is configured such that the driving force to the L level in the control circuit 212k is greater than the driving force to the H level. This makes it easy to suppress the signal transmitted to the next stage PSW 21k to the L level, suppresses leakage caused by the influence of the preceding stage when the power is started up in the switch 213 that should be turned off, and reduces power consumption in the standby state. Therefore, the power to the connected destination can also be appropriately cut off for the next stage PSW 21k.

[0146] Furthermore, PSW21k' may be configured such that the driving force to the H level in control circuit 211k is greater than the driving force to the L level, and the driving force to the L level and the driving force to the H level are equal in control circuit 212s. PSW21k' may be configured as inverter INV2s of control circuit 212s by omitting transistor PM121 and transistor NM121 from inverter INV2k shown in Figure 13. In this case, since the driving force to the H level in control circuit 211 of PSW21k' is greater than the driving force to the L level, node N1 can be easily brought to the H level when the power is started up. This suppresses leakage at power start-up in switch 213 which should be turned off.

[0147] Alternatively, PSW21k" may be configured such that the driving force to the H level and the driving force to the L level are equal in the control circuit 211s, and the driving force to the L level is greater than the driving force to the H level in the control circuit 212k. PSW21k" may be configured as inverter INV1s of control circuit 211s by omitting transistor PM111 and transistor NM111 compared to inverter INV1k shown in Figure 13. In this case, since the driving force to the L level in control circuit 212 of PSW21k" is greater than the driving force to the H level, the output node OUT can be easily set to the L level when the power is started up. This suppresses leakage caused by the preceding stage at power start-up in switch 213 which should be turned off.

[0148] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0149] 1,1i,1j,1k: Semiconductor integrated circuits; 211,211k,211s,212,212k,212s: Control circuits; 213: Switches; 214i,214j,215i,215j: Assist circuits.

Claims

1. A switch connected between the first power node and the second power node, which turns off when it receives a first level at the control terminal, A first control circuit having an input node and an output node connected to the control terminal of the switch, A second control circuit having an output node and an input node connected to the control terminal of the switch, Equipped with, In the first control circuit, the driving force to the first level is greater than the driving force to the second level, and in the second control circuit, the driving force to the second level is greater than the driving force to the first level, satisfying at least one of these conditions. Semiconductor integrated circuit.

2. The semiconductor integrated circuit satisfies the condition that in the first control circuit, the driving force to the first level is greater than the driving force to the second level. The first control circuit is, It has an inverter-connected first P-type transistor and a first N-type transistor, wherein the threshold voltage of the first P-type transistor is lower than the threshold voltage of the first N-type transistor. The semiconductor integrated circuit according to claim 1.

3. The semiconductor integrated circuit satisfies the condition that in the second control circuit, the driving force to the second level is greater than the driving force to the first level. The second control circuit is, It has an inverter-connected second P-type transistor and a second N-type transistor, wherein the threshold voltage of the second N-type transistor is lower than the threshold voltage of the second P-type transistor. The semiconductor integrated circuit according to claim 1.

4. The semiconductor integrated circuit satisfies the condition that in the first control circuit, the driving force to the first level is greater than the driving force to the second level. The first control circuit is, It has a plurality of first P-type transistors and a plurality of first N-type transistors connected in an inverter, wherein the plurality of first P-type transistors are connected in parallel and the plurality of first N-type transistors are connected in series. The semiconductor integrated circuit according to claim 1.

5. The semiconductor integrated circuit satisfies the condition that in the second control circuit, the driving force to the second level is greater than the driving force to the first level. The second control circuit is, It has a plurality of inverter-connected second P-type transistors and a plurality of second N-type transistors, the plurality of second N-type transistors are connected in parallel and the plurality of second P-type transistors are connected in series. The semiconductor integrated circuit according to claim 1.

6. A switch connected between the first power node and the second power node, which turns off when it receives a first level at the control terminal, A first control circuit having an input node and an output node connected to the control terminal of the switch, A second control circuit having an output node and an input node connected to the control terminal of the switch, Equipped with, A first assist circuit assists in the appearance of a second level, which is the logical inversion of the first level, at the output node of the first control circuit when a first level is input to the input node of the first control circuit while the switch is kept off. A second assist circuit that assists the appearance of the first level at the output node of the second control circuit when the second level is input to the input node of the second control circuit while the switch is kept off, Further comprising at least one of the Semiconductor integrated circuit.

7. The semiconductor integrated circuit includes the first assist circuit, The first assist circuit is, The device has at least one of a third P-type transistor or a third N-type transistor, the drain of which is commonly connected to the control terminal of the switch and the source of which is commonly connected to the power supply potential, wherein the third P-type transistor has a gate and a back gate, each connected to the power supply potential, and the third N-type transistor has a gate and a back gate, each connected to the ground potential. The semiconductor integrated circuit according to claim 6.

8. The semiconductor integrated circuit comprises the second assist circuit, The second assist circuit is, The device has at least one of a fourth P-type transistor or a fourth N-type transistor, the drain of which is commonly connected to the control terminal of the switch and the source of which is commonly connected to the ground potential, wherein the fourth P-type transistor has a gate and a back gate, each connected to the power supply potential, and the fourth N-type transistor has a gate and a back gate, each connected to the ground potential. The semiconductor integrated circuit according to claim 6.

9. The semiconductor integrated circuit includes the first assist circuit, The first assist circuit is, It has a first capacitive element, one end of which is connected to the control terminal of the switch and the other end of which is connected to the first power node. The semiconductor integrated circuit according to claim 6.

10. The semiconductor integrated circuit comprises the second assist circuit, The second assist circuit is, It has a second capacitive element, one end of which is connected to the output node of the second control circuit and the other end of which is connected to the second power supply node. The semiconductor integrated circuit according to claim 6.

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