Memory system

Abstract

We provide a memory system that can retain data over long periods of time. [Solution] The memory system comprises a non-volatile memory having multiple blocks, each having multiple memory cells, and a memory controller that manages at least one of the number of writes and erases of a block. When the memory controller writes data to a memory cell, it writes N bits of data (where N is an integer of 2 or more) per memory cell. When at least one of the number of writes and erases of a block exceeds a first number, the memory controller determines whether there is free space of a predetermined size. If there is free space, it invalidates a logical address corresponding to the predetermined size and writes data to the block by writing M bits of data (where M is an integer of 1 or more and less than N) per memory cell.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a memory system.

Background Art

[0002] In recent years, memory systems equipped with non-volatile memory have become widely popular. In a memory system, for example, NAND-type flash memory is used as the non-volatile memory. In such a memory system, a multi-level technology for realizing a large capacity of the non-volatile memory has been introduced.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a memory system capable of retaining data over a long period of time.

Means for Solving the Problems

[0005] The memory system according to this embodiment includes a non-volatile memory having multiple blocks, each having multiple memory cells, and a memory controller that manages at least one of the number of writes and erases of a block. When the memory controller writes data to a memory cell, it writes N bits of data (where N is an integer of 2 or more) per memory cell. When at least one of the number of writes and erases of a block exceeds a first number, the memory controller determines whether there is free space of a predetermined size in the non-volatile memory. If there is free space, it invalidates a logical address corresponding to the predetermined size and writes data to the block by writing M bits of data (where M is an integer of 1 or more and less than N) per memory cell. [Brief explanation of the drawing]

[0006] [Figure 1] This block diagram shows the configuration of an information processing system including a memory system according to one embodiment. [Figure 2] This block diagram shows the memory configuration of a memory system according to one embodiment. [Figure 3] This is a perspective view showing the configuration of a memory cell array according to one embodiment. [Figure 4] This is a cross-sectional view showing the configuration of a memory cell according to one embodiment. [Figure 5] This is a circuit diagram showing the configuration of a memory cell array according to one embodiment. [Figure 6] This flowchart shows the process of checking exhaustion information and changing the writing mode of an information processing system according to one embodiment. [Figure 7] This diagram illustrates the assignment of logical addresses in a memory cell array according to one embodiment. [Figure 8] This figure illustrates the relationship between the capacity of a memory cell array according to one embodiment and the write and erase thresholds (W / E lifespan) of the block. [Figure 9] This figure illustrates the relationship between the capacity of a memory cell array according to one embodiment and the write and erase thresholds (W / E lifespan) of the block. [Modes for carrying out the invention]

[0007] The following description will explain the information processing systems, including the memory systems of each embodiment, with reference to the drawings. In the following description, components having the same or similar functions and configurations will be denoted by a common reference numeral. When distinguishing between multiple components having a common reference numeral, subscripts (e.g., uppercase letters, numbers, hyphens and uppercase letters and numbers, etc.) will be added to the common reference numeral to distinguish them, and redundant explanations may be omitted.

[0008] <First Embodiment> <1-1. Overall configuration of the memory system> Referring to Figure 1, the overall configuration of the information processing system 1, including the memory system according to the first embodiment, will be described. Figure 1 is a block diagram illustrating the configuration of the information processing system 1. The information processing system 1 includes a memory system 2 and a host device 3. The memory system is also referred to as a memory device or a memory card.

[0009] Memory system 2 is configured to communicate with host device 3 based on a client-server model. Memory system 2 acts as the target, and host device 3 acts as the initiator. More specifically, memory system 2 is a UFS memory device, and host device 3 is a host device that supports UFS memory devices. Host device 3 may be, for example, a system-on-chip (SoC) device, and may be a device installed in a smartphone or digital camera, etc.

[0010] The memory system 2 includes a plurality of non-volatile semiconductor memories 11 (hereinafter referred to as "memories") and a controller 12 for controlling the memories 11. The controller 12 controls each of the plurality of memories 11.

[0011] Memory 11 performs data writing and reading operations in specific write units consisting of multiple bits. Furthermore, memory 11 erases data in erase units consisting of multiple write units. For example, memory 11 consists of one or more NAND flash memories. Each NAND flash memory contains multiple blocks, and each block contains multiple pages. If memory 11 is a NAND flash memory, memory 11 performs write and read operations in page units and erases in block units.

[0012] When the memory cell's write mode is SLC (Single Level Cell), one page is composed of multiple memory cells connected to one word line. When the memory cell's write mode is MLC (Multi Level Cell), two pages (2 bits (2) are composed of multiple memory cells connected to one word line. 2 If it is a TLC (Triple Level Cell), then 3 pages (3 bits (2) are made up of multiple memory cells connected to one word line. 3 If it is a QLC (Quad Level Cell), then four pages (4 bits (2) are made up of multiple memory cells connected to one word line. 4 A configuration of 16 values ​​is formed. If the memory cell is a multi-bit cell, multiple pages can be supported by setting a single memory cell to a multi-bit threshold voltage.

[0013] The capacity of a memory cell depends on its write mode (number of bits). The capacity of a memory cell increases with the number of bits. The capacity of memory cells is greater for MLC than for SLC, greater for TLC than for MLC, and greater for QLC than for TLC. The write mode of a memory cell is set on a block-by-block basis. Each block is set to one of the following write modes: SLC, MLC, TLC, or QLC.

[0014] The tolerance of the memory 11 to read and write operations is finite. Therefore, when a predetermined number of read and write operations are performed on a specific memory cell, the electrical characteristics of the memory cell deteriorate. When the electrical characteristics of the memory cell deteriorate, the memory cell loses its function of storing data. In the following embodiments, the deterioration of the electrical characteristics of the memory cells in the memory 11 is referred to as "fatigue". The degree of such fatigue (the degree of deterioration of the electrical characteristics) is referred to as the "fatigue degree". The deterioration of the electrical characteristics of the memory cell depends, for example, on the number of operations such as write operations and read operations performed on the memory cell. Therefore, in this case, the number of times these operations are performed is referred to as "fatigue information". In the following embodiments, since the write and read operations are performed in page units, the terms of the above-mentioned fatigue, fatigue degree, and fatigue information are used for pages.

[0015] The definition of "fatigue information" differs depending on the type of non-volatile memory. For example, in the case of a non-volatile memory that is equally fatigued by both write and read operations, the number of times the write and read operations are performed on the target page can be the fatigue information. In the case of a non-volatile memory that is more easily fatigued by write operations than read operations, a value obtained by increasing the proportion of the number of write operations performed on the target page compared to the number of read operations can be the fatigue information. In the case of a non-volatile memory that is more easily fatigued by read operations than write operations, a value obtained by increasing the proportion of the number of read operations performed on the target page compared to the number of write operations can be the fatigue information. In the case of a non-volatile memory that is fatigued by an erase operation in addition to write and read operations, in addition to the above-mentioned write and read operations, the number of times the erase operation is performed on the target block can be the fatigue information.

[0016] For example, when the memory cells provided in the target page are exhausted by read and write operations for the pages adjacent to the target page, in addition to the number of times the write and read operations for the target page are executed, the number of times the write and read operations for the adjacent pages are executed can become exhaustion information.

[0017] In the memory 11, when the exhaustion information of the memory cells provided in the target page exceeds a threshold value (W / E life), the memory cells can no longer store data, or the data stored in the memory cells disappears. Therefore, it is preferable to track and manage the exhaustion information of the memory cells.

[0018] The threshold value of the exhaustion information of the memory cells depends on the write mode (number of bits) of the memory cells. The threshold value of the exhaustion information of the memory cells becomes smaller as the number of bits increases. The threshold value of the exhaustion information of the memory cells is smaller for MLC than for SLC, smaller for TLC than for MLC, and smaller for QLC than for TLC.

[0019] Hereinafter, the case where the memory 11 is a three-dimensional stacked NAND flash memory in which memory cell transistors are three-dimensionally stacked above a semiconductor substrate will be described. Note that the memory is not limited to a three-dimensional stacked NAND flash memory, and may be a planar NAND flash memory in which memory cell transistors are two-dimensionally arranged on a semiconductor substrate, or other non-volatile memories. Details of the memory 11 will be described later.

[0020] Memory system 2 includes I / O 21, core logic unit 22, and I / O 23. I / O 21 includes hardware configuration for memory system 2 to connect to host device 3. Memory system 2 is connected to host device 3 via a host bus. If information processing system 1 conforms to the UFS standard, the host bus corresponds to a serial interface. Signals transmitted and received between memory system 2 and host device 3 include RESET, REF_CLK, DOUT, DOUT_c, DIN, and DIN_c. RESET, REF_CLK, DOUT, DOUT_c, DIN, and DIN_c are communicated between host device 3 and I / O 21 via the host bus. RESET is a hardware reset signal. REF_CLK is a reference clock signal. DOUT and DOUT_c are signals that form a differential signal pair and are transmitted from host device 3 to memory system 2. DIN and DIN_c are signals that form a differential signal pair and are transmitted from memory system 2 to host device 3.

[0021] The core logic unit 22 is the main part of the controller 12, excluding I / O 21 and I / O 23. I / O 23 includes the hardware configuration for the controller 12 to connect to the memory 11.

[0022] The core logic unit 22 includes a host interface 31, a buffer 32, a data bus 33, a memory interface 34, a buffer 35, an ECC circuit (error correcting code) 36, a control bus 41, a CPU (central processing unit) 42, a ROM (read-only memory) 43, a RAM (random access memory) 44, and registers 45.

[0023] I / O21 is connected to the host interface 31. The host interface 31 performs the necessary processing for communication between the memory system 2 and the host device 3. More specifically, the host interface 31 handles communication between the memory system 2 and the host device 3 in accordance with the communication protocol to which both the memory system 2 and the host device 3 comply. If the memory system 2 is a UFS memory device, for example, the host interface 31 is a UFS interface. The UFS interface conforms to the M-PHY standard for the physical layer and the UniPro standard for the link layer.

[0024] The host interface 31 is connected to the buffer 32. The buffer 32 receives data sent from the host device 3 to the memory system 2 via the host interface 31 and temporarily holds it. The buffer 32 also temporarily holds data sent from the memory system 2 to the host device 3 via the host interface 31. The buffer 32 is connected to the data bus 33.

[0025] I / O 23 is connected to the memory interface 34. The memory interface 34 performs the processing necessary for the controller 12 to communicate with the memory 11. More specifically, the memory interface 34 transmits instructions (control signals) from the core logic unit 22 in a form that the memory 11 can recognize. Furthermore, the memory interface 34 sends and receives signals DQ with the memory 11 and receives ready / busy signals R / Bn from the memory 11. Signal DQ includes, for example, data, address, and command. Signal R / Bn is a signal that indicates the memory 11 is busy. If the memory 11 is a NAND flash memory, the memory interface 34 is a NAND flash interface.

[0026] The memory interface 34 is connected to the buffer 35. The buffer 35 receives data transmitted from the memory 11 to the controller 12 via the memory interface 34 and temporarily holds it. The buffer 35 also temporarily holds data that is scheduled to be transmitted from the controller 12 to the memory 11 via the memory interface 34. The buffer 35 is connected to the data bus 33. Note that buffers 32 and 35 may be a single buffer. The memory interface 34 and buffer 35 are connected to the ECC circuit 36. The ECC circuit 36 ​​receives write data from the host device 3 via the data bus 33, adds an error correction code (hereinafter referred to as "parity") to the write data, and supplies the parity-corrected write data to the buffer 35. The ECC circuit 36 ​​also receives data supplied from the memory 11 via the buffer 35, performs error correction using the parity added to this data, and supplies the error-corrected data to the data bus 33.

[0027] The control bus 41 is connected to the CPU 42, ROM 43, RAM 44, and registers 45. The CPU 42, ROM 43, RAM 44, and registers 45 communicate with each other via the control bus 41.

[0028] The CPU 42 controls the overall operation of the memory system 2. The CPU 42 executes predetermined processes (such as write operations, read operations, or erase operations) according to the control programs (instructions) stored in the ROM 43. For example, the CPU 42 may execute predetermined processes on the memory 11 according to commands received from the host device 3.

[0029] When CPU42 receives a read request (instruction) from host device 3 that includes a command and a logical address, it reads the logical address translation data corresponding to the logical address to be read from the address translation table (lookup table LUT) stored in memory 11, which associates logical addresses with physical addresses, and translates the logical address to a physical address. The physical address identifies a part of the memory space in memory 11. It then instructs memory I / F34 to perform a read operation to read the data from that physical address. When CPU42 receives a write request from host device 3 that includes a command, write data, and a logical address, it assigns a new physical address corresponding to the logical address and manages the lookup table LUT. It then instructs memory I / F34 to perform a write operation to write the data to that physical address.

[0030] CPU42 also performs garbage collection (GC) processing. Garbage collection (GC) is a process to increase the number of usable blocks among the physical blocks. For example, it means collecting valid data from multiple active blocks that contain both valid and invalid data, rewriting it into another block, and securing free blocks. Here, an active block is a physical block in which valid data is recorded. A free block is a physical block in which no valid data is recorded. After erasure, a free block can be reused as an erased block. A free block includes both blocks before erasure (in which no valid data is recorded) and erased blocks. Valid data is data associated with a logical address (described later), while invalid data is data not associated with a logical address. An erased block becomes an active block when data is written to it. For example, CPU42 counts the number of free blocks, and if the number of free blocks is below a predetermined threshold, it performs GC. If the number of free blocks is greater than the predetermined threshold, CPU42 does not need to perform GC processing.

[0031] Furthermore, the CPU 42 obtains and manages fatigue information from the memory 11, corresponding to the physical address of the memory 11 and the page located at that physical address. For example, in this embodiment, the CPU 42 manages the number of times a write operation has been performed on a page located at a predetermined physical address (hereinafter referred to as "write count"). The CPU 42 stores the write count corresponding to a specific page, along with the physical address of that page, in the RAM 44. In other words, the RAM 44 functions as a counter where page fatigue information is stored. The CPU 42 manages the write count by updating the fatigue counter in response to the execution of a write operation. In other words, the CPU 42 updates the fatigue counter based on the fatigue information. The fatigue counter manages the physical address of a page in association with the write count corresponding to that page.

[0032] ROM43 stores control programs and other data that are executed by the CPU42. The programs stored in ROM43 are read by the CPU42 and executed as needed.

[0033] RAM44 is used as a work area for CPU42 and temporarily stores variables necessary for CPU42 operations (such as write data and read data). Furthermore, RAM44 may be provided with storage areas for various values ​​used during processing (e.g., "number of writes") and various tables (e.g., lookup table LUT). RAM44 may be located outside of controller12.

[0034] Register 45 holds various values ​​necessary for the operation of memory system 2. Register 45 also holds various values ​​necessary for host device 3 to control memory system 2.

[0035] The control bus 41 is further connected to a host interface 31, a buffer 32, a memory interface 34, and a buffer 35. The CPU 42 controls the host interface 31, buffer 32, memory interface 34, and buffer 35 based on the control program and instructions from the host device 3. Furthermore, the controller 12 may be provided with an analog circuit 51 that functions as a voltage regulator to supply a stabilized voltage, for example.

[0036] <1-2. Memory Configuration> The configuration of the memory 11 will be explained using Figure 2. Figure 2 is a block diagram showing the configuration of the memory 11 in the memory system according to this embodiment. In Figure 2, some of the connections between blocks are shown by arrow lines, but the connections between blocks are not limited to the arrow lines shown in Figure 2.

[0037] As shown in Figure 2, the memory 11 includes an input / output circuit 100, a logic control circuit 101, a status register 102, an address register 103, a command register 104, a sequencer 105, a ready / busy circuit 106, a voltage generation circuit 107, a memory cell array 108, a row decoder 109, a sense amplifier 110, a data register 111, and a column decoder 112.

[0038] The input / output circuit 100 controls the input and output of the signal DQ to the controller 12. More specifically, the input / output circuit 100 sends the data DAT (write data) received from the controller 12 to the data register 111, the address ADD to the address register 103, and the command CMD to the command register 104. The input / output circuit 100 also sends the status information STS received from the status register 102, the data DAT (read data) received from the data register 111, and the address ADD received from the address register 103 to the controller 12.

[0039] The logic control circuit 101 receives various control signals from the controller 12. The logic control circuit 101 then controls the input / output circuit 100 and the sequencer 105 according to the received control signals.

[0040] The status register 102 temporarily holds status information STS for write, read, and erase operations, and notifies the controller 12 whether the operation was completed successfully.

[0041] The address register 103 temporarily holds the address ADD received from the controller 12 via the input / output circuit 100. The address register 103 then transfers the row address RA to the row decoder 109 and the column address CA to the column decoder 112.

[0042] The command register 104 temporarily stores the command CMD received from the controller 12 via the input / output circuit 100 and transfers it to the sequencer 105.

[0043] The sequencer 105 controls the operation of the entire memory 11. More specifically, the sequencer 105 controls, for example, the status register 102, the ready / busy circuit 106, the voltage generation circuit 107, the row decoder 109, the sense amplifier 110, the data register 111, and the column decoder 112, etc., in response to the command CMD held in the command register 104, and performs write operations, read operations, erase operations, etc.

[0044] The ready / busy circuit 106 sends a ready / busy signal R / Bn to the controller 12 according to the operating status of the sequencer 105.

[0045] The voltage generation circuit 107 generates the voltages necessary for writing, reading, and erasing operations in response to the control of the sequencer 105, and supplies these generated voltages to, for example, the memory cell array 108, the row decoder 109, and the sense amplifier 110. The row decoder 109 and the sense amplifier 110 apply the voltage supplied by the voltage generation circuit 107 to the memory cell transistors in the memory cell array 108.

[0046] The memory cell array 108 includes a plurality of non-volatile memory cell transistors (hereinafter also referred to as "memory cells") associated with rows and columns. The memory cell array 108 includes a user area 130 and a system area 131 as memory spatial regions.

[0047] The user area 130 is the area where the write data specified by the write command received from the host device 3 (hereinafter referred to as "user data") is stored. It is preferable to allocate the user area 130 to a range other than the first quarter of the logical address range.

[0048] The system area 131 is an area where information for managing the memory system 2 (hereinafter referred to as "system data") is stored, such as control programs in memory 11, logical conversion data, or various setting parameters such as applied voltage during write operations. The system area 131 is an area that the host device 3 cannot access during write and read operations of data received from the host device 3. It is preferable to allocate the system area 131 within the first quarter of the logical address range.

[0049] The row decoder 109 decodes the row address RA. Based on the decoding result, the row decoder 109 applies a predetermined voltage to the memory cell array 108.

[0050] During a read operation, the sense amplifier 110 senses the data read from the memory cell array 108. The sense amplifier 110 then outputs the read data to the data register 111. During a write operation, the sense amplifier 110 writes the write data to the memory cell array 108.

[0051] The data register 111 includes multiple latch circuits. The latch circuits temporarily hold write data or read data. For example, during a write operation, the data register 111 temporarily holds the write data received from the input / output circuit 100 and transmits it to the sense amplifier 110. Similarly, during a read operation, the data register 111 temporarily holds the read data received from the sense amplifier 110 and transmits it to the input / output circuit 100.

[0052] The column decoder 112 decodes the column address CA during operations such as write, read, and erase, and selects a latch circuit in the data register 111 according to the decoding result.

[0053] <1-3. Configuration of Memory Cell Array> The configuration of the memory cell array 108 will be explained using Figure 3. Figure 3 is a schematic perspective view showing the arrangement of each element of the memory cell array 108 according to this embodiment.

[0054] In Figure 3, the two directions parallel to the main surface of the substrate S and mutually orthogonal are called the X direction and the Y direction, and the plane parallel to the main surface of the substrate S is called the XY plane. The direction perpendicular to both the X direction and the Y direction is called the Z direction (lamination direction).

[0055] As shown in Figure 3, the memory cell array 108 includes a substrate S, a stacked body 10 provided on the substrate S, a plurality of columnar body portions CL, and a plurality of bit lines BL provided on the stacked body 10.

[0056] The laminate 10 has multiple conductive layers that are insulated from each other and periodically stacked in a direction perpendicular to the main surface of the substrate S (the stacking direction), corresponding to a selection gate line SGS, multiple word lines WL, and a selection gate line SGD from the substrate side. The laminate 10 has openings ST and MH. The openings ST and MH extend in the stacking direction (Z direction) and penetrate the laminate 10 to reach the substrate S. The opening ST extends in the X direction, separating the laminate 10 into multiple blocks in the Y direction. A columnar portion CL is formed in the opening MH (see Figure 4).

[0057] The columnar sections CL are formed as cylinders that extend in the stacking direction within the laminate 10. Multiple columnar sections CL may be arranged, for example, in a staggered pattern. Alternatively, multiple columnar sections CL may be arranged in a square grid along the X and Y directions.

[0058] Multiple bit lines BL are separated from each other in the X direction, and each bit line BL extends in the Y direction.

[0059] The upper end of the semiconductor layer 20 (see Figure 4), described later, of the columnar portion CL is connected to the bit line BL via the contact portion Cb. Multiple columnar portions CL, one selected from each block separated in the Y direction by the aperture ST, are connected to a common bit line BL.

[0060] Furthermore, an insulating layer is formed between adjacent word lines WL in the stacking direction. An insulating layer is formed in the slit ST, and an insulating layer is formed on top of the laminate 10. However, for the sake of explanation, these insulating layers are omitted in Figure 3.

[0061] Figure 4 is a cross-sectional view showing the configuration of the memory cell according to this embodiment. Figure 4 is an enlarged cross-sectional view of the columnar portion CL in Figure 3.

[0062] As shown in Figure 4, the columnar portion CL is a structure having a memory layer M, a semiconductor layer 20, and an insulating core layer 50. The semiconductor layer 20 is continuously stretched in the stacking direction (Z direction) within the laminate 10. The material of the semiconductor layer 20 includes, for example, amorphous or polycrystalline silicon. The core layer 50 is provided inside the cylindrical semiconductor layer 20. The material of the core layer 50 includes, for example, silicon oxide. The memory layer M is provided between the word line WL and the semiconductor layer 20. The memory layer M surrounds the semiconductor layer 20 from the outer periphery.

[0063] The memory layer M has a tunnel insulating layer M1, a charge storage layer M2, and a block insulating layer M3 (here, when the tunnel insulating layer M1, charge storage layer M2, and block insulating layer M3 are not distinguished, they are referred to as the memory layer M). The block insulating layer M3, charge storage layer M2, and tunnel insulating layer M1 are extended continuously in the stacking direction of the laminate 10 together with the semiconductor layer 20. Between the word line WL and the semiconductor layer 20, the block insulating layer M3, charge storage layer M2, and tunnel insulating layer M1 are provided in order from the word line WL side. The tunnel insulating layer M1 is in contact with the semiconductor layer 20. The block insulating layer M3 is in contact with the word line WL. The charge storage layer M2 is provided between the block insulating layer M3 and the tunnel insulating layer M1.

[0064] The semiconductor layer 20, the memory layer M, and the word line WL constitute a memory cell MC. In Figure 5, one memory cell MC is schematically represented by a dashed line. The memory cell MC has a vertical transistor structure in which the semiconductor layer 20 is surrounded by the word line WL via the memory layer M.

[0065] In this vertical transistor memory cell MC, the semiconductor layer 20 functions as a channel, and the word line WL functions as the control gate of the memory cell. The charge storage layer M2 functions as a data layer that stores the charge injected from the semiconductor layer 20.

[0066] As described above, multiple memory cells (MCs) are arranged in the stacking direction of multiple word lines (WLs), and each of the multiple word lines (WLs) is connected to multiple memory cells (MCs). A word line (WL) near the block insulating layer (M3) functions as a control gate. By controlling the voltage to the word line (WL) connected to the memory cell (MC), writing to or erasing from the memory cell (MC) can be controlled.

[0067] A memory cell MC is, for example, a charge-trap type memory cell. The charge storage layer M2 has numerous trap sites for capturing charge within the insulating layer. The material of the charge storage layer M2 includes, for example, silicon nitride.

[0068] The tunnel insulating layer M1 acts as a potential barrier when charge is injected from the semiconductor layer 20 to the charge storage layer M2, or when charge stored in the charge storage layer M2 diffuses towards the semiconductor layer 20. The material of the tunnel insulating layer M1 includes, for example, silicon oxide.

[0069] The block insulating layer M3 prevents the charge accumulated in the charge storage layer M2 from diffusing to the word line WL. The material of the block insulating layer M3 includes, for example, silicon oxide.

[0070] Figure 5 is a circuit diagram of a block BLK included in the memory cell array 108 of memory 11. While block BLK0 is used as an example, the other blocks BLK1, 2, ... have similar circuits. Note that the circuit diagram shown in Figure 5 is an example and does not limit the circuit diagram of the memory cell array 108 of the first embodiment. In the description of the memory cell array 108, descriptions of configurations identical or similar to those in Figures 1 to 4 may be omitted.

[0071] Block BLK0 includes N bit lines BL (BL0, BL1, ..., BL(N-1) (where N is an integer greater than or equal to 2)) arranged in a column, and a plurality of NAND strings 116 and source lines SL arranged in a matrix. The NAND strings 116 are connected between the N bit lines BL and the source lines SL. The NAND strings 116 include, for example, eight memory cell transistors MT (MT0 to MT7), as well as selection transistors ST1 and ST2. The memory cell transistors MT have a control gate and a charge storage layer and hold data non-volatilely. The memory cell transistors MT are connected in series between the source of selection transistor ST1 and the drain of selection transistor ST2. The NAND strings 116 are provided on the N bit lines BL to form a string unit SU (SU0, SU1). In Figure 5, the NAND string 116 includes, for example, eight memory cell transistors MT, but the number of memory cell transistors MT included in the NAND string 116 is not limited to eight. For example, the number of memory cell transistors MT may be i, and the integer i may be greater than or less than 8.

[0072] The selection transistor ST1 is connected to the selection gate line SGD0. The gates of the selection transistor ST1 in each string unit SU are connected to the selection gate lines SGD (SGD0, SGD1, ...; when multiple SGD0, SGD1, ... are not distinguished, they are referred to as the selection gate line SGD). The gates of the eight memory cell transistors MT (MT0~MT7) are each connected to their corresponding word lines WL (WL7~WL0). In addition, the gates of the selection transistor ST2 in each string unit SU are connected to the selection gate line SGS. The gates of the selection transistor ST1 connected to each of the multiple bit lines BL within the same string unit SU are connected to the common selection gate line SGD. The gates of the memory cell transistors MT (MT0~MT7) within the same string unit SU are each connected to the common word lines WL (WL0~WL7). The gates of multiple selection transistors ST2 within the same block BLK are connected to the common selection gate line SGS. The source line SL is shared, for example, between multiple block BLKs.

[0073] Within the same string unit SU, memory cell transistors MT connected to the same word line WL (WL0 to WL7) constitute a unit for read and write operations. For example, the memory cell transistors MT7 in each NAND string 116 included in the string unit SU corresponding to the selected gate line SGD0 constitute a memory cell group MG as a unit for read and write operations, and read and write operations are performed collectively for the memory cell group MG.

[0074] <1-4. About Wear Leveling Process> The controller 12 performs write and erase operations to the memory 11 in accordance with write and erase requests from the host device 3. However, write and erase operations may be repeatedly performed on a concentrated portion of certain pages. If write and erase operations are repeatedly performed on a concentrated portion of the memory 11, it may become exhausted and lose its function as a memory cell.

[0075] To avoid such problems, the controller 12 performs wear leveling. Wear leveling is a process that, for example, overwrites data stored in a block of non-volatile memory with a high number of write cycles (source block) to a block of non-volatile memory with a low number of write cycles (destination block). Wear leveling changes the correspondence between logical addresses and physical addresses (lookup table LUT). As a result of this change in correspondence, even if write and erase requests from the host device 3 are executed many times for a particular logical address, the write and erase operations are performed for pages with different physical addresses. Therefore, it is possible to suppress the concentration of fatigue on memory cells located in some pages.

[0076] For example, in wear leveling, at least one of the write count and erase count is managed on a block-by-block basis, and the correspondence between logical addresses and physical addresses is changed on a block-by-block basis. However, the wear leveling process may also change the correspondence between logical addresses and physical addresses on a page-by-page basis. Furthermore, the wear leveling process may change the correspondence between logical addresses and physical addresses on a multi-page basis. In addition, the wear leveling process may be performed by managing at least one of the write count and erase count on a block-by-block basis.

[0077] By performing the above wear leveling process, the degree of wear in the page or block units of memory 11 is less uneven, and memory 11 can efficiently reuse memory cells to retain data until the wear information reaches a threshold (W / E lifetime).

[0078] <1-5. Regarding the confirmation of fatigue information and the process of changing the writing mode> When checking for wear and tear, the system first determines whether it is necessary to change the write mode based on the wear and tear counter status or other wear and tear information. For example, if the number of writes and erases for the physical address of a page where data write and erase operations are performed is low, it is determined that it is not necessary to change the write mode, and the write operation is performed without changing the write mode. On the other hand, if the number of writes and erases for the physical address of a page where data write and erase operations are performed is close to the threshold (W / E lifetime), the system will change the write mode for the block containing that page. The system changes the write mode based on the update process of the wear and tear counter stored in RAM44.

[0079] The operation of checking fatigue information and changing the write mode will be explained using Figure 6. Figure 6 is a flowchart of the process of checking fatigue information and changing the write mode in an information processing system according to one embodiment.

[0080] As shown in Figure 6, first, the controller 12 determines whether there is a block containing pages whose fatigue information exceeds a predetermined value (step S1). Here, the predetermined value is preferably smaller than, for example, the threshold (W / E lifetime) for fatigue information (at least one of the number of writes and the number of erases) in the current write mode. If the predetermined value is smaller than the threshold (W / E lifetime) for fatigue information in the current write mode, the memory cell can be prevented from becoming unable to store data or the data stored in the memory cell from being lost by the write mode change process. The determination may be made using the fatigue information of each page, or it may be made using the average value of the fatigue information of the pages in the block. Alternatively, the controller 12 may manage fatigue information on a block-by-block basis, and the determination process may be made using the fatigue information of the block. If there is a block containing pages whose fatigue information exceeds a predetermined value (YES in step S1), the write mode change process described later continues, and if there is no block containing pages whose fatigue information exceeds a predetermined value (NO in step S1), the process ends.

[0081] If there is a block containing pages whose exhaustion information exceeds a predetermined value (YES in step S1), the controller 12 determines whether there is free space in the memory cell array 108 that is greater than or equal to a predetermined size of the block size (step S2). If there is free space in the memory cell array 108 that is greater than or equal to a predetermined size of the block size (YES in step S2), the process of changing the write mode described later continues. Specifically, the predetermined size is 1 / 4 of the block size if the block's write mode is QLC, 1 / 3 of the block size if the block's write mode is TLC, and 1 / 2 of the block size if the block's write mode is MLC. Note that if the block's write mode is QLC, the size may be slightly larger than 1 / 4 of the block size; if the block's write mode is TLC, the size may be slightly larger than 1 / 3 of the block size; and if the block's write mode is MLC, the size may be slightly larger than 1 / 2 of the block size. Here, the block size is the size of the data that can be stored in the memory system 2, and is the size capacity of the memory cell array 108.

[0082] If the memory cell array 108 does not have free space equal to or greater than a predetermined size of the block size (NO in step S2), the controller 12 notifies the host device 3 that there is insufficient free space in the memory cell array 108 (step S6). Specifically, the controller 12 requests the host device 3 to ask the user of the host device 3 to delete data. Steps S1 and S2 are repeated at regular intervals until sufficient free space becomes available in the memory cell array 108.

[0083] If there is free space in the memory cell array 108 that exceeds a predetermined size of the block size (YES in step S2), the controller 12 issues a request to the host device 3 to reduce capacity (step S3). In other words, it issues a request to reduce the number of logical addresses. For example, the controller 12 issues a request to the host device 3 to invalidate logical addresses corresponding to a predetermined size of the block size from the end of the logical addresses.

[0084] If valid data is recorded at the logical address to be reduced, before requesting the capacity reduction, the controller 12 issues a request to the host device 3 to move that logical address to another logical address. In accordance with the request to move the logical address, the host device 3 sends write and delete requests to the memory system 2.

[0085] If host device 3 allows the capacity reduction request (YES in step S4), controller 12 continues the write mode change process described later. If host device 3 does not allow the capacity reduction request (NO in step S4), controller 12 repeats steps S1 to S4 at regular intervals (step S7).

[0086] If the host device 3 permits the capacity reduction request (YES in step S4), the controller 12 invalidates logical addresses corresponding to a predetermined size of the block size from the end of the logical address range. No physical addresses are assigned to the invalidated logical addresses. Figure 7 illustrates the assignment of logical addresses in the memory cell array. In this embodiment, by invalidating logical addresses from the end of the logical address range, the capacity of the memory cell array 108 can be reduced without affecting the system data assigned within a predetermined size range from the beginning of the logical address range. In other words, in the memory system 2 when the write mode is QLC at the beginning of use, that is, when the exhaustion information does not exceed a predetermined value, the capacity of the memory cell array 108 can be reduced without affecting the system data, as long as the system data is assigned within a range of 1 / 4 from the beginning of the logical address range.

[0087] After partially invalidating logical addresses, the write mode of blocks containing pages with exhaustion information exceeding a predetermined value is changed to a mode with one less bit (step S5). Specifically, the write mode of a block is changed from QLC to TLC, from TLC to MLC, and from MLC to SLC. For blocks whose write mode has been changed, the new write mode is applied to subsequent write operations.

[0088] In this embodiment, by changing the write mode to a mode with one less bit, the capacity of the memory cell array 108 is reduced, but the write and erase thresholds (W / E lifespan) of the block can be increased.

[0089] By repeating steps S1 to S5 at regular intervals, the memory cell array 108 can retain data for a long period of time until it reaches the write and erase cycle threshold (W / E lifespan) of the SLC.

[0090] Figure 8 illustrates the relationship between the capacity of a memory cell array and the write and erase thresholds (W / E lifespan) of the blocks in question. In this embodiment, the write and erase counts of each block in the memory cell array 108 are made approximately uniform by wear leveling. Therefore, as the write and erase thresholds (W / E lifespan) for each write mode are approached, the write mode is changed simultaneously in each block of the memory cell array 108. As a result, the capacity of the memory cell array 108 decreases in a stepwise manner. However, this is not limited to this; if the write and erase thresholds (W / E lifespan) are not made approximately uniform by wear leveling, the write mode may be changed sequentially in each block of the memory cell array 108, and the capacity of the memory cell array 108 may decrease linearly. In any case, the write and erase thresholds (W / E lifespan) of the memory cell array 108 increase, and the total storage capacity decreases. Ultimately, the memory cell array 108 can retain data for a long period of time until the write and erase thresholds (W / E lifespan) of the SLC are reached.

[0091] In this embodiment, the write mode change process was performed on a block-by-block basis. However, it is not limited to this, and if the number of writes and erases for each block of the memory cell array 108 is made approximately uniform by wear leveling, the write mode change process may be continued for all blocks when step S1 is YES. In this case, for the blocks whose write mode has been changed, a different write mode will be applied from the subsequent write operation.

[0092] Furthermore, in this embodiment, an example was shown in which at least one of the number of writes and the number of erases is used as fatigue information. However, it is not limited to this, and for example, the number of reads may be used as fatigue information, or both the number of writes and the number of reads may be used. If the fatigue caused by reading has little effect, for example, the threshold for the number of reads may be approximately 10 times greater than the threshold for the number of writes.

[0093] <Second Embodiment> The configuration of the memory system according to the second embodiment is the same as that of the memory system according to the first embodiment, so its description will be omitted. In the first embodiment, wear leveling and write mode change processing were performed evenly on all blocks of the memory cell array 108. In the second embodiment, wear leveling and write mode change processing are performed on only some blocks of the memory cell array 108.

[0094] An information processing system including a memory system according to the second embodiment will be described using Figure 9. Figure 9 is a diagram illustrating the relationship between the capacity of a memory cell array and the write and erase thresholds (W / E lifetime) of the block. An example of the first embodiment is shown with a dotted line, and the second embodiment is shown with a solid line.

[0095] Read-only data is stored (or moved from other blocks) in blocks where the number of writes approaches the write and erase threshold (W / E lifetime) for the initial write mode (e.g., QLC). The initial write mode is maintained in the block in question, and wear leveling and write mode change processes are performed only in the other blocks. Read-only data may be indicated when the host device 3 requests a write from the memory system 2. For example, when the host device 3 requests a write from the memory system 2, it may specify that the data to be written is read-only data. Read-only data may also be system data, for example.

[0096] In this embodiment, by performing wear leveling and write mode change processing on only some blocks, the timing of the write mode change processing is accelerated, while the reduction in capacity of the memory cell array 108 can be suppressed. As shown in Figure 9, compared to the first embodiment (dotted line), in the second embodiment (solid line), the timing of the capacity reduction of the memory cell array 108 is accelerated, while the reduction in capacity can be suppressed.

[0097] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0098] 1 Information processing system, 2 Memory system, 3 Host device, 10 Stacked structure, 11 Semiconductor memory, 12 Controller, 22 Core logic section, 31 Host interface, 32 Buffer, 33 Data bus, 34 Memory interface, 35 Buffer, 36 ECC circuit (error correcting code), 41 Control bus, 42 CPU (central processing unit), 43 ROM (read-only memory), 44 RAM (random access memory), 45 Register, 51 Analog circuit, 100 Input / output circuit, 101 Logic control circuit, 102 Status register, 103 Address register, 104 Command register, 105 Sequencer, 106 Busy circuit, 107 Voltage generation circuit, 108 Memory cell array, 130 User area, 131 System area

Claims

1. A non-volatile memory having multiple blocks, each containing multiple memory cells, The system includes a memory controller that manages at least one of the number of writes and erases of the block, The aforementioned memory controller When writing data to the memory cell, N bits of data (where N is an integer of 2 or more) are written to each memory cell. If at least one of the number of writes and erases of the block exceeds the first number, Determine whether there is free space of a predetermined size in the non-volatile memory. A memory system that, if there is available space, invalidates a logical address corresponding to the predetermined size and writes data to the block by writing M bits of data (where M is an integer between 1 and N) per memory cell.

2. The memory system according to claim 1, wherein the predetermined size is 1 / N or larger in size of the plurality of blocks.

3. The memory system according to claim 2, wherein N is 4 and M is 3.

4. The memory system is connectable to the host device, The memory system according to claim 1, wherein, if there is available space, the memory controller sends a request to the host device to reduce the capacity of the logical address.

5. The memory system is connectable to the host device, The memory system according to claim 1, wherein if there is no available space, the memory controller sends a request to the host device for data reduction.

6. The memory system according to claim 1, wherein the first number of writes is smaller than at least one of the threshold number of writes and the threshold number of erases in the N bits.

7. A non-volatile memory having multiple blocks, each having multiple memory cells, The system includes a memory controller that manages at least one of the number of writes and erases of the plurality of blocks, The aforementioned memory controller When writing data to the memory cell, N bits of data (where N is an integer of 2 or more) are written to each memory cell. A memory system in which, when at least one of the write count and erase count of the plurality of blocks exceeds a first count, Read Only data from the data stored in the plurality of blocks is stored in the first block of the plurality of blocks by writing N bits of data per memory cell, and data writing to the second block of the plurality of blocks is performed by writing M bits of data (M is an integer between 1 and N, inclusive) per memory cell.

8. The memory system according to claim 7, wherein the Read Only data is system data.

9. The memory system is connectable to the host device, The memory system according to claim 7, wherein the memory controller performs data writing to the second block in response to receiving a write command from the host device.

10. The memory system according to claim 7, wherein the data written to the second block includes the valid data of the third block and the valid data of the fourth block among the plurality of blocks.

11. The memory system according to claim 7, wherein the memory controller performs wear leveling processing on the plurality of blocks.

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