Semiconductor memory

Abstract

To provide a semiconductor memory device that can shorten processing time. [Solution] The semiconductor memory device according to the embodiment includes a first wiring layer, a second wiring layer, and a plurality of third wiring layers arranged in a first direction spaced apart from each other in this order; a memory pillar extending in the first direction, the portion intersecting with the first wiring layer functions as a first memory cell; and a control circuit that controls the read operation of data stored in the first memory cell. The control circuit performs, during a read operation, a first operation which changes the voltage of the plurality of third wiring layers from a first voltage to a second voltage higher than the first voltage with a first slope; a second operation which changes the voltage of the second wiring layer from a first voltage to a third voltage higher than the second voltage with a second slope greater than the first slope; and a third operation which changes the voltage of the first wiring layer to a fourth voltage corresponding to the read level of the first memory cell.

Description

Technical Field

[0001] Embodiments relate to semiconductor memory devices.

Background Art

[0002] As a semiconductor memory device capable of storing data non-volatilely, a NAND-type flash memory is known. In a NAND-type flash memory, when reading data stored in a certain memory cell transistor, a voltage higher than the read voltage is applied to other memory cell transistors in the same NAND string as the memory cell transistor.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor memory device capable of shortening processing time.

Means for Solving the Problems

[0005] The semiconductor memory device according to the embodiment includes a first wiring layer, a second wiring layer, and a plurality of third wiring layers arranged in a first direction spaced apart from each other in this order; a memory pillar extending in the first direction, the portion of which intersects with the first wiring layer functions as a first memory cell; and a control circuit for controlling the read operation of data stored in the first memory cell. The control circuit performs, during a read operation, a first operation which changes the voltage of the plurality of third wiring layers from a first voltage to a second voltage higher than the first voltage with a first slope; a second operation which changes the voltage of the second wiring layer from a first voltage to a third voltage higher than the second voltage with a second slope greater than the first slope; and a third operation which changes the voltage of the first wiring layer to a fourth voltage corresponding to the read level of the first memory cell. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a block diagram showing an example of the configuration of a memory system according to the first embodiment. [Figure 2] Figure 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 3] Figure 3 is a plan view showing an example of a planar layout of a memory cell array in a semiconductor memory device according to the first embodiment. [Figure 4] Figure 4 is a plan view showing an example of a planar layout in the memory area of ​​a memory cell array in a semiconductor memory device according to the first embodiment. [Figure 5] Figure 5 is a cross-sectional view along the VV line in Figure 4, showing an example of the cross-sectional structure in the memory region of a memory cell array in a semiconductor memory device according to the first embodiment. [Figure 6] Figure 6 is a cross-sectional view along the line VI-VI in Figure 5, showing an example of the cross-sectional structure of a memory pillar in a semiconductor memory device according to the first embodiment. [Figure 7] Figure 7 is a circuit diagram showing an example of the circuit configuration of a low decoder module included in the semiconductor memory device according to the first embodiment. [Figure 8]Figure 8 is a circuit diagram showing an example of the circuit configuration of a driver module included in the semiconductor memory device according to the first embodiment. [Figure 9] Figure 9 shows an example of the threshold distribution, read voltage, and verify voltage of a memory cell transistor in a semiconductor memory device according to the first embodiment. [Figure 10] Figure 10 is a timing chart showing an example of the lower page data read operation in a semiconductor memory device according to the first embodiment. [Figure 11] Figure 11 shows an example of the data writing order in the NAND string of the semiconductor memory device according to the first embodiment. [Figure 12] Figure 12 is a timing chart showing an example of a write operation in a semiconductor memory device according to the first embodiment. [Figure 13] Figure 13 is a timing chart showing an example of the lower page data read operation in a semiconductor memory device according to the second embodiment. [Figure 14] Figure 14 is a circuit diagram showing an example of the circuit configuration of a driver module included in a semiconductor memory device according to the third embodiment. [Figure 15] Figure 15 is a timing chart showing an example of the lower page data read operation in a semiconductor memory device according to the third embodiment. [Figure 16] Figure 16 is a timing chart showing an example of the lower page data read operation in a semiconductor memory device according to the fourth embodiment. [Figure 17] Figure 17 is a circuit diagram showing an example of the circuit configuration of a driver module included in a semiconductor memory device according to the fifth embodiment. [Figure 18] Figure 18 is a timing chart showing an example of the lower page data read operation in a semiconductor memory device according to the fifth embodiment. [Figure 19] Figure 19 is a circuit diagram showing an example of the circuit configuration of a driver module included in a semiconductor memory device according to the sixth embodiment. [Figure 20]FIG. 20 is a timing chart showing an example of a write operation in the semiconductor memory device according to the sixth embodiment. [Figure 21] FIG. 21 is a timing chart showing an example of a write operation in the semiconductor memory device according to the seventh embodiment. [Figure 22] FIG. 22 is a timing chart showing an example of a write operation in the semiconductor memory device according to the eighth embodiment. [Figure 23] FIG. 23 is a timing chart showing an example of a write operation in the semiconductor memory device according to the ninth embodiment. [Figure 24] FIG. 24 is a circuit diagram showing an example of the circuit configuration of a driver module included in the semiconductor memory device according to the tenth embodiment. [Figure 25] FIG. 25 is a timing chart showing an example of a write operation in the semiconductor memory device according to the tenth embodiment.

Embodiments of the Invention

[0007] Embodiments will be described below with reference to the drawings. The drawings are schematic, and the dimensions and ratios in the drawings are not necessarily the same as those in reality. In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. When particularly distinguishing between elements having the same configuration, different characters or numbers may be added to the end of the same reference numeral.

[0008] In the following description, when a first element is "connected to" a second element, it includes that the first element is indirectly connected to the second element through an intermediate element that is always or selectively conductive, or directly connected to the second element without passing through an intermediate element.

[0009] 1. First Embodiment 1.1 Configuration 1.1.1 Memory System A semiconductor memory device according to the first embodiment will now be described. Figure 1 is a block diagram showing an example of the configuration of a memory system according to the first embodiment. Memory system 1 is a memory device configured to be connected to an external host device (not shown). Memory system 1 is, for example, an SD TM The memory is a card-like memory card, UFS (Universal Flash Storage), or SSD (Solid State Drive). The memory system 1 includes a memory controller 2 and a semiconductor storage device 3.

[0010] The memory controller 2 is composed of an integrated circuit, such as a System on a Chip (SoC). The memory controller 2 controls the semiconductor memory device 3 based on requests from an external host device. Specifically, the memory controller 2 writes data requested to be written by the external host device to the semiconductor memory device 3. The memory controller 2 also reads data requested to be read from the semiconductor memory device 3 and outputs it to the external host device.

[0011] The semiconductor memory device 3 is, for example, a memory that stores data either volatilely or non-volatilely. The following description assumes that the semiconductor memory device 3 is a NAND flash memory.

[0012] Communication between the memory controller 2 and the semiconductor storage device 3 conforms to, for example, an SDR (Single Data Rate) interface, a toggle DDR (Double Data Rate) interface, or an ONFI (Open NAND Flash Interface). Signals such as IO<7:0>, CEn, CLE, ALE, WEn, REn, and RBn are exchanged between the memory controller 2 and the semiconductor storage device 3.

[0013] 1.1.2 Semiconductor Memory Devices Next, the internal configuration of the semiconductor memory device 3 according to the first embodiment will be described with reference to the block diagram shown in Figure 1. The semiconductor memory device 3 includes, for example, a memory cell array 10, an input / output circuit 11, a logic control circuit 12, a register 13, a sequencer 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0014] The memory cell array 10 is a collection of memory cell transistors and components connected to the memory cell transistors. The memory cell array 10 includes multiple blocks BLK0 to BLKn (where n is an integer greater than or equal to 1). A block BLK is a collection of multiple memory cell transistors capable of storing data non-volatilely. A block BLK is used, for example, as an erasure unit when erasing data stored by a memory cell transistor. The memory cell array 10 is also provided with multiple bit lines and multiple word lines. Each memory cell transistor is associated, for example, with a combination of one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0015] The input / output circuit 11 is an interface circuit that controls the transmission and reception of signals IO<7:0> between it and the memory controller 2. Signals IO<7:0> are 8-bit signals. Signals IO<7:0> include, for example, data DAT, command CMD, address information ADD, and status information STA. The input / output circuit 11 inputs and outputs data DAT between the sense amplifier module 17 and the memory controller 2, respectively. The input / output circuit 11 outputs command CMD and address information ADD, respectively, transferred from the memory controller 2, to register 13. The input / output circuit 11 outputs status information STA, transferred from register 13, to the memory controller 2.

[0016] The logic control circuit 12 is an interface circuit that receives signals CEn, CLE, ALE, WEn, and REn input from the memory controller 2, and transmits signal RBn to the memory controller 2. Based on the signals CEn, CLE, ALE, WEn, and REn, the logic control circuit 12 controls the input / output circuit 11 and the sequencer 14, respectively. For example, based on the signal CEn, the logic control circuit 12 controls the sequencer 14 to enable the semiconductor memory device 3. Based on the signals CLE and ALE, the logic control circuit 12 notifies the input / output circuit 11 that the input / output signals it has received are command CMD and address information ADD, respectively. Based on the signals WEn and REn, the logic control circuit 12 commands the input / output circuit 11 to input and output signals IO<7:0>, respectively. The logic control circuit 12 also outputs the signal REn to the memory controller 2, indicating whether the semiconductor memory device 3 is in a ready state (ready to accept external commands) or a busy state (not ready to accept external commands).

[0017] Register 13 temporarily stores command CMD, address information ADD, and status information STA. Command CMD includes, for example, instructions to cause the sequencer 14 to perform read operations, write operations, erase operations, etc. Address information ADD includes, for example, block address BA, page address PA, and column address CA. For example, block address BA, page address PA, and column address CA are used to select block BLK, word lines, and bit lines, respectively. Status information STA is used to notify the memory controller 2 whether the operation has been completed successfully or not. Status information STA is updated based on the control of the sequencer 14 and transferred to the input / output circuit 11.

[0018] The sequencer 14 controls the overall operation of the semiconductor memory device 3. For example, the sequencer 14 controls the driver module 15, the row decoder module 16, and the sense amplifier module 17, etc., based on the command CMD stored in register 13. The sequencer 14 also performs read operations, write operations, and erase operations, for example.

[0019] The driver module 15 generates multiple voltages of different magnitudes used in read, write, and erase operations. The driver module 15 supplies the generated voltages to the row decoder module 16 and the sense amplifier module 17, etc. The driver module 15 also applies the generated voltages to the signal lines corresponding to the word lines selected based on the page address PA stored in register 13, for example.

[0020] The row decoder module 16 selects a corresponding block BLK in the memory cell array 10 based, for example, on the block address BA stored in register 13. The row decoder module 16 then transfers, for example, the voltage of the signal line applied by the driver module 15 to the selected word line in the selected block BLK.

[0021] The sense amplifier module 17 includes a sense amplifier unit capable of determining data based on the voltage of the associated bit line, and a latch circuit for temporarily storing data. In a write operation, the sense amplifier module 17 applies a predetermined voltage to each bit line according to the write data DAT received from the input / output circuit 11. In a read operation, the sense amplifier module 17 determines the data stored in the memory cell transistor based on the magnitude of the bit line voltage. Subsequently, the sense amplifier module 17 transfers the determination result as read data DAT to the input / output circuit 11.

[0022] 1.1.3 Circuit configuration of memory cell array Figure 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array in a semiconductor memory device according to the first embodiment. Figure 2 shows block BLK0. Block BLK0 includes, for example, five string units SU0 to SU4.

[0023] Each string unit SU includes multiple NAND strings NS, each associated with a bit line BL0 to BLm (where m is an integer greater than or equal to 1). Each NAND string NS includes, for example, eight memory cell transistors MT0 to MT7 and selection transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage film, and stores data nonvolatilously based on the amount of charge in the charge storage film. Selection transistors ST1 and ST2 are used to select the string unit SU during various operations.

[0024] In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series in this order. The drain of selection transistor ST1 is connected to the associated bit line BL, and the source of selection transistor ST1 is connected to the drain of memory cell transistor MT7. The drain of selection transistor ST2 is connected to the source of memory cell transistor MT0, and the source of selection transistor ST2 is connected to the source line SL.

[0025] Within the same block BLK, the control gates (hereinafter simply referred to as "gates") of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. Within string units SU0 to SU4, the gates of selection transistors ST1 are connected to selection gate lines SGD0 to SGD4, respectively. Within the same block BLK, the gate of selection transistor ST2 is connected to selection gate line SGS.

[0026] Each bit line BL0 to BLm is assigned a different column address CA. Each bit line BL is shared by a NAND string NS, which is assigned the same column address CA across multiple block BLKs. Each word line WL0 to WL7 is provided for each block BLK. The source line SL is shared, for example, across multiple block BLKs.

[0027] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU is called, for example, a cell unit CU. For example, the storage capacity of a cell unit CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data". A cell unit CU may have a storage capacity of 2 pages of data or more, depending on the number of bits of data stored by the memory cell transistors MT. In the following description, we will consider the case where the memory cell transistors MT are TLCs (Triple Level Cells) that store 3 bits of data. That is, each cell unit CU has a storage capacity of 3 pages of data.

[0028] The circuit configuration of the memory cell array 10 in the semiconductor memory device 3 according to the first embodiment is not limited to the above description. For example, the number of string units SU included in each block BLK can be designed to any number. The number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can each be designed to any number.

[0029] 1.1.4 Structure of a memory cell array An example of the structure of the memory cell array 10 provided in the semiconductor memory device 3 according to the first embodiment is described below. In the following description, the extension direction of the word line WL is the X direction. The extension direction of the bit line BL is the Y direction. When viewed from the source line SL side, the direction in which the selected gate lines SGD and SGS, and the stacked wiring corresponding to the word line WL are stacked is the Z direction or upward direction. The opposite direction of upward is downward. In the plan view, hatching is added as appropriate to improve the visibility of the drawing. The hatching added to the plan view is not necessarily related to the material or characteristics of the component to which the hatching is added.

[0030] 1.1.4.1 Overview Figure 3 is a plan view showing an example of a planar layout of a memory cell array in a semiconductor memory device according to the first embodiment. In Figure 3, regions corresponding to four blocks BLK0 to BLK3 are shown. The sequential numbers at the end to distinguish the blocks BLK are assigned in ascending order from the top of the page. In the memory cell array 10, for example, the layout shown in Figure 3 is repeatedly arranged in the Y direction. As shown in Figure 3, the memory cell array 10 includes stacked wiring, which is formed by stacking multiple wiring layers (e.g., word lines WL0 to WL7, and selection gate lines SGS and SGD) spaced apart from each other in the Z direction, multiple members SLT, and multiple members SHE. The planar layout of the memory cell array 10 is divided, for example, in the X direction into a memory area MA and an extraction area HA.

[0031] The memory area MA is an area used for storing data, containing multiple NAND strings NS. The lead area HA is an area used for connecting each wiring layer of the stacked wiring to the row decoder module 16. For example, each wiring layer of the stacked wiring is formed in a stepped manner in the lead area HA so that it can be connected to the row decoder module 16 from the bit line BL side without interfering with other wiring layers.

[0032] Multiple SLT members each extend along the X direction and are aligned in the Y direction. Each SLT member traverses the memory area MA and the extraction area HA in the X direction at the boundary region between adjacent blocks BLK. In other words, each region demarcated by an SLT member corresponds to one block BLK in the memory cell array 10. Each SLT member has a structure in which, for example, an insulator and plate-shaped contacts are embedded. Each SLT member separates adjacent stacked wiring through it.

[0033] Multiple members SHE are arranged in the memory area MA. Each of the multiple members SHE is provided across the memory area MA in the X direction and aligned in the Y direction. The right-hand end of each member SHE is included in the lead-out area HA. ​​For example, in the memory area MA, four members SHE are each arranged between adjacent members SLT in the Y direction. Each region of the memory area MA separated by members SLT and SHE corresponds to one string unit SU in the memory cell array 10. Each member SHE has, for example, a structure with an embedded insulator. Each member SHE separates adjacent selection gate lines SGD through the member SHE.

[0034] The planar layout of the memory cell array 10 in the semiconductor memory device 3 according to the first embodiment is not limited to the layout described above. For example, the number of members SHE arranged between adjacent members SLT can be designed to be any number. The number of string units SU formed between adjacent members SLT can be changed based on the number of members SHE arranged between adjacent members SLT.

[0035] In the semiconductor memory device 3 according to the first embodiment, word lines WL0 to WL7 extend in the X direction, and voltage is applied from the row decoder module 16 via contacts (not shown) connected in the extraction region HA. In this case, the effect of wiring delay may become significant in the portion of word line WL that is far from the extraction region HA included in the memory region MA.

[0036] In this specification, “delay” refers to the length of the RC delay time, which is the time it takes from the time a voltage is applied to a wire until the voltage in that wire rises or falls to the target value. Furthermore, in the following description, the portion of the word line WLk (where k is an integer satisfying 0 ≤ k ≤ 7) contained in the memory area MA that is far from the lead area HA is referred to as the “far end of the word line WLk” and is indicated as “Far” in the drawings. The portion that is close to the lead area HA is referred to as the “near end of the word line WLk” and is indicated as “Near” in the drawings. The timing at which the voltage reaches the target value may differ between the near end and the far end of the word line WLk.

[0037] In the following, when applying voltage to a word line WL, the rate of increase or decrease in voltage at the near end of the word line WL at the start of voltage application will be referred to as the "slope".

[0038] 1.1.4.2 Structure of the memory area (Flat layout) Figure 4 is a plan view showing an example of a planar layout in the memory region of a memory cell array in a semiconductor memory device according to the first embodiment. As shown in Figure 4, in the memory region MA, the memory cell array 10 includes a plurality of memory pillars MP, a plurality of contacts CCV, and a plurality of bit lines BL. In addition, each component SLT includes a contact LI and a spacer SP.

[0039] Each memory pillar MP functions, for example, as a single NAND string NS. Multiple memory pillar MPs are arranged in a staggered pattern, for example, 24 rows in the Y direction, in the region between two adjacent members SLT. In the example shown in Figure 4, one member SHE overlaps each of the 5th, 10th, 15th, and 20th memory pillar MPs, counting from the top of the paper.

[0040] Multiple bit lines BL each extend in the Y direction and are aligned in the X direction. Each bit line BL is positioned to overlap with at least one memory pillar MP for each string unit SU. In the example shown in Figure 4, two bit lines BL are positioned to overlap with one memory pillar MP. If multiple bit lines BL overlap with a memory pillar MP, one bit line BL and the corresponding memory pillar MP are electrically connected via a contact CCV. If only one bit line BL overlaps with a memory pillar MP, that bit line BL and the corresponding memory pillar MP are electrically connected via a contact CCV.

[0041] For example, the contact CCV between a memory pillar MP in contact with a component SHE and the corresponding bit line BL is omitted. In other words, the contact CCV between a memory pillar MP and a bit line BL in contact with two different selection gate lines SGD is omitted. The number and arrangement of memory pillars MP and component SHE between adjacent component SLTs are not limited to the configuration shown in Figure 4 and can be changed as appropriate. For example, the number of bit lines BL overlapping each memory pillar MP can be designed to be any number.

[0042] Contact LI is a conductor extending in the XZ plane. The lower surface of contact LI is in contact with a source wire SL (not shown). Spacer SP is an insulator provided on the side of contact LI. In other words, spacer SP is provided in contact with contact LI so as to sandwich it in the Y direction.

[0043] (Cross-sectional structure) Figure 5 is a cross-sectional view along the VV line in Figure 4, showing an example of the cross-sectional structure in the memory region of a memory cell array in a semiconductor memory device according to the first embodiment. As shown in Figure 5, the memory cell array 10 further includes wiring layers 21-25 and insulating layers 40-46.

[0044] As shown in Figure 5, the insulating layer 40, wiring layer 21, insulating layer 41, wiring layer 22, and insulating layer 42 are stacked in this order. The wiring layer 21 is formed, for example, as a plate stretched along the X direction on the XY plane. The wiring layer 21 is used as a source line SL. The wiring layer 21 contains, for example, phosphorus-doped silicon. The wiring layer 22 is formed, for example, as a plate stretched along the X direction on the XY plane. The wiring layer 22 is used as a selection gate line SGS. The wiring layer 22 contains, for example, tungsten. The insulating layer 40 includes, for example, wiring and pads (not shown) for the semiconductor memory device 3 to connect to external devices.

[0045] Above the insulating layer 42, the wiring layer 23 and the insulating layer 43 are stacked alternately, one layer at a time. In the example shown in Figure 5, eight wiring layers 23 and eight insulating layers 43 are stacked alternately, one layer at a time. Each wiring layer 23 is formed, for example, as a plate stretched along the X direction on the XY plane. Each wiring layer 23 is used as word lines WL0 to WL7, in order from the wiring layer 22 side. Each wiring layer 23 contains, for example, tungsten.

[0046] Above the uppermost insulating layer 43, the wiring layer 24, insulating layer 44, and insulating layer 45 are stacked in this order. The wiring layer 24 is formed, for example, as a plate stretched along the X direction on the XY plane. The wiring layer 24 is used as a selected gate wire SGD. The wiring layer 24 contains, for example, tungsten.

[0047] A wiring layer 25 is laminated above the insulating layer 45. The wiring layer 25 is formed, for example, in a line extending along the Y direction. The wiring layer 25 is used as a bit line BL. In a region not shown, multiple wiring layers 25 are arranged along the X direction. The wiring layer 25 contains, for example, copper.

[0048] An insulating layer 46 is stacked above the wiring layer 25. The insulating layer 46 includes, for example, a plurality of wirings (not shown) for connecting the memory cell array 10 to a low decoder module 16 and a sense amplifier module 17, which are located further above it.

[0049] Each of the memory pillars MP is provided extending along the Z direction. Each of the memory pillars MP penetrates the wiring layers 22-24 and the insulating layers 41-44.

[0050] Each memory pillar MP includes, for example, a core film 30, a semiconductor film 31, and a multilayer film 32. The core film 30 is provided stretched along the Z direction. For example, the upper end of the core film 30 is located within the insulating layer 45, and the lower end of the core film is located within the wiring layer 21. The core film 30 includes, for example, an insulator such as silicon oxide (SiO). The semiconductor film 31 covers the periphery of the core film 30. At the lower end of the memory pillar MP, a portion of the semiconductor film 31 is in contact with the wiring layer 21. The semiconductor film 31 includes, for example, silicon. The multilayer film 32 covers the sides of the semiconductor film 31, except for the portion in contact with the semiconductor film 31 and the wiring layer 21.

[0051] In the structure of the memory pillar MP shown in Figure 5, the portion where the memory pillar MP intersects with the wiring layer 22 functions as a selection transistor ST2. The portions where the memory pillar MP intersects with each wiring layer 23 function as memory cell transistors MT0 to MT7, respectively. The portion where the memory pillar MP intersects with the wiring layer 24 functions as a selection transistor ST1.

[0052] A columnar contact CCV is provided on the upper surface of the semiconductor film 31 within the memory pillar MP. In the region shown in Figure 5, two of the six memory pillar MPs are shown, each with two corresponding contact CCVs. For memory pillar MPs in this region that do not overlap with member SHE and do not have a contact CCV connected to them, another contact CCV is connected in a region not shown.

[0053] One wiring layer 25, i.e., one bit line BL, is in contact with the upper surface of each contact CCV. One contact CCV is connected to each wiring layer 25 in each of the spaces separated by members SLT and SHE. In other words, each wiring layer 25 is electrically connected, for example, to one memory pillar MP in each region between adjacent members SLT and SHE, and to one memory pillar MP in each region between two adjacent members SHE.

[0054] The SLT members are formed, for example, to extend along the XZ plane. Each SLT member divides the wiring layers 22-24 and the insulating layers 41-44 in the Y direction.

[0055] Within the component SLT, the contact LI is provided so as to extend along the XZ plane, and the spacer SP is provided between the contact LI and the wiring layers 22-24 and the insulating layers 41-45. The upper end of the contact LI is located, for example, within the insulating layer 45. The lower end of the contact LI is located, for example, within the wiring layer 21. Note that the contact LI may be omitted depending on the structure of the memory cell array 10.

[0056] Component SHE is formed, for example, as a plate extending along the XZ plane, and divides the wiring layer 24. The upper end of component SHE is located within the insulating layer 45. The lower end of component SHE is located, for example, within the uppermost insulating layer 43. Component SHE includes an insulator such as silicon oxide. The upper end of component SHE and the upper end of component SLT may or may not be aligned. Similarly, the upper end of component SHE and the upper end of the memory pillar MP may or may not be aligned.

[0057] Figure 6 is a cross-sectional view along the line VI-VI in Figure 5, showing an example of the cross-sectional structure of a memory pillar in a semiconductor memory device according to the first embodiment. More specifically, Figure 6 shows the cross-sectional structure of the memory pillar MP in the XY plane including the wiring layer 23. As shown in Figure 6, the laminated film 32 includes, for example, a tunnel insulating film 33, a charge storage film 34, and a block insulating film 35.

[0058] In a cross-section including the wiring layer 23, the core film 30 is provided, for example, in the central part of the memory pillar MP. The semiconductor film 31 surrounds the sides of the core film 30. The tunnel insulating film 33 surrounds the sides of the semiconductor film 31. The charge storage film 34 surrounds the sides of the tunnel insulating film 33. The block insulating film 35 surrounds the sides of the charge storage film 34. The wiring layer 23 surrounds the sides of the block insulating film 35.

[0059] The semiconductor film 31 is used as the channel (current path) for the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2. The tunnel insulating film 33 is used as a potential barrier between the semiconductor film 31 and the charge storage film 34 and includes, for example, silicon oxide. The charge storage film 34 has the function of storing charge and includes, for example, silicon nitride (SiN). The block insulating film 35 suppresses back tunneling of charge from the wiring layer 23 to the memory pillar MP and includes, for example, silicon oxide. With this configuration, each memory pillar MP can function as one NAND string NS.

[0060] 1.1.5 Circuit configuration of the low decoder module Figure 7 is a circuit diagram showing an example of the circuit configuration of a row decoder module provided in a semiconductor memory device according to the first embodiment. As shown in Figure 7, the row decoder module 16 includes, for example, row decoders RD0 to RDn.

[0061] The row decoder RD is used to select block BLK. Row decoders RD0 to RDn are associated with blocks BLK0 to BLKn, respectively.

[0062] The following describes the detailed circuit configuration of the row decoder RD, focusing on row decoder RD0, which corresponds to block BLK0. Row decoders RD1 to RDn have the same configuration as row decoder RD0.

[0063] The low decoder RD includes, for example, a block decoder BD and transistors TR1 to TR14.

[0064] The block decoder BD decodes the block address BA. Based on the decoding result, the block decoder BD applies a predetermined voltage to the transfer gate line TG. The transfer gate line TG is commonly connected to the gates of transistors TR1 to TR14.

[0065] Transistors TR1 to TR14 include, for example, high-voltage N-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) that are durable against the voltage VPRG described later. Transistors TR1 to TR14 are connected between the various signal lines wired from the driver module 15 and the various wirings of the associated block BLK. In the following description, unless the source and drain of a transistor are specified, either the source or the drain of a transistor will be referred to as the "first terminal of the transistor," and either the source or the drain of a transistor will be referred to as the "second terminal of the transistor." The state in which the first and second terminals of a transistor are electrically connected through the transistor is called the "on state," and the state in which they are electrically isolated through the transistor is called the "off state."

[0066] Specifically, the driver module 15 is connected to signal lines SGDD0 to SGDD4, signal lines CG0 to CG7, and signal line SGSD. Signal lines SGDD0 to SGDD4 correspond to select gate lines SGD0 to SGD4, respectively. Signal lines CG0 to CG7 correspond to word lines WL0 to WL7, respectively. Signal line SGSD corresponds to select gate line SGS.

[0067] The first terminal of transistor TR1 is connected to the signal line SGSD. The second terminal of transistor TR1 is connected to the select gate line SGS. The first terminals of transistors TR2 to TR9 are connected to the signal lines CG0 to CG7, respectively. The second terminals of transistors TR2 to TR9 are connected to the word lines WL0 to WL7, respectively. The first terminals of transistors TR10 to TR14 are connected to the signal lines SGDD0 to SGDD4. The second terminals of transistors TR10 to TR14 are connected to the select gate lines SGD0 to SGD4, respectively.

[0068] With the above configuration, the low decoder module 16 can select a block BLK to perform various operations.

[0069] Specifically, during various operations, the block decoder BD corresponding to the selected block BLK applies a "H" level voltage to the transfer gate line TG, while the block decoder BD corresponding to the unselected block BLK applies a "L" level voltage to the transfer gate line. For example, when block BLK0 is selected, transistors TR1 to TR14 in the row decoder RD0 are turned ON, and transistors TR1 to TR14 in the row decoders RD1 to RDn are turned OFF. In this case, a current path is formed between the various wirings provided in block BLK0 and the corresponding signal lines, and the current path between the various wirings provided in blocks BLK1 to BLKn and the corresponding signal lines is interrupted. As a result, the voltage applied to each signal line by the driver module 15 is applied to the various wirings provided in the selected block BLK0 via the row decoder RD0. The row decoder module 16 can operate similarly when other block BLKs are selected.

[0070] 1.1.6 Circuit configuration of the driver module Figure 8 is a circuit diagram showing an example of the circuit configuration of a driver module included in a semiconductor memory device according to the first embodiment. Figure 8 shows a configuration in which voltage is applied to signal lines CG0 to CG7 in the driver module 15. As shown in Figure 8, the driver module 15 includes charge pump circuits 51, 52, and 53, voltage regulator circuits 61, 62, and 63, and CG selection drivers 70-0 to 70-7.

[0071] Charge pump circuits 51, 52, and 53 are circuits that boost the input voltage and output it. Charge pump circuit 51 outputs the voltage VPGMH. Voltage VPGMH is a higher voltage than voltage VPGM, which will be described later. Charge pump circuit 52 outputs the voltage VM. Voltage VM is a higher voltage than voltage VPASS and voltage VREAD, which will be described later. Charge pump circuit 53 outputs the voltage VREADKH. Voltage VREADKH is a higher voltage than voltage VREADK, which will be described later.

[0072] Voltage regulator circuits 61, 62, and 63 are circuits that step down the voltage input from charge pump circuits 51, 52, and 53, respectively, and adjust it to a predetermined voltage value before outputting it. Voltage regulator circuit 61 steps down the voltage VPGMH input from charge pump circuit 51 and outputs the voltage VCGSEL, which is applied to the memory cell transistor MT selected as the target during a read or write operation. Voltage VCGSEL includes the voltage VPGM, read voltages AR, BR, CR, DR, ER, FR, and GR, and verify voltages AV, BV, CV, DV, EV, FV, and GV, which will be described later. In other words, voltage regulator circuit 61 functions as a variable voltage regulator. Voltage regulator circuit 62 steps down the voltage VM input from charge pump circuit 52 and outputs the voltages VPASS, VREAD, VCGM, and VREADE. For example, the voltages VPASS, VREAD, and VCGM may be output from the same output terminal. Voltage VREADE is output from a different output terminal than voltages VPASS, VREAD, and VCGM. That is, voltage regulator circuit 62 functions as a variable voltage regulator. Voltage regulator circuit 63 steps down the voltage VREADKH input from charge pump circuit 53 and outputs voltage VREADK, which will be described later. Note that the voltages output from each voltage regulator circuit 61, 62, and 63 are not limited to those described above.

[0073] Each of the CG selection drivers 70-0 to 70-7 includes multiple transistors (five in the example shown in Figure 8). Each of the transistors included in the multiple transistors TRs is, for example, a high-voltage N-channel MOSFET. Each of the CG selection drivers 70-0 to 70-7, based on the control of the sequencer 14, selects one of the multiple transistors TRs and turns it on, thereby transferring a voltage to the corresponding signal lines CG0 to CG7. The number of multiple transistors TRs varies depending on the type of voltage output from each of the voltage regulator circuits 61, 62, and 63.

[0074] 1.1.7 Threshold distribution of memory cell transistors Figure 9 shows an example of the threshold distribution, read voltage, and verify voltage of memory cell transistors in a semiconductor memory device according to the first embodiment. The vertical axis of Figure 9 corresponds to the number of memory cell transistors (NMTs), and the horizontal axis corresponds to the threshold voltage of the memory cell transistors MT.

[0075] As shown in Figure 9, when a single memory cell transistor MT is a TLC that stores 3 bits of data, the multiple memory cell transistors MT contained in the cell unit CU form eight different threshold voltage distributions. Hereinafter, these eight threshold distributions (write levels) will be denoted as "Er" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level, in order from the lowest threshold voltage.

[0076] When the memory cell transistor MT is in the erase state, the threshold voltage of the memory cell transistor MT falls within the "Er level". When data is written to the memory cell transistor MT, the threshold voltage of the memory cell transistor MT falls within one of the "Er" to "G" levels. Each of the threshold distribution levels "Er" to "G" is assigned a different set of 3 bits of data. It is desirable that the data assignments in each of two adjacent levels differ by only 1 bit of data. The following is an example of data assignment to the threshold distribution.

[0077] “Er” level: “111 (highest bit / middle bit / lowest bit)” data "A" Level: "110" Data "B" Level: "100" data "C" Level: "000" Data "D" Level: "010" Data "E" Level: "011" Data "F" Level: "001" Data “G” Level: “101” Data Each threshold distribution is defined by the read voltage used in the read operation. Specifically, the threshold voltage included in the "Er" level is less than the read voltage AR. The threshold voltage included in the "A" level is greater than or equal to the read voltage AR and less than the read voltage BR. The threshold voltage included in the "B" level is greater than or equal to the read voltage BR and less than the read voltage CR. The threshold voltage included in the "C" level is greater than or equal to the read voltage CR and less than the read voltage DR. The threshold voltage included in the "D" level is greater than or equal to the read voltage DR and less than the read voltage ER. The threshold voltage included in the "E" level is greater than or equal to the read voltage ER and less than the read voltage FR. The threshold voltage included in the "F" level is greater than or equal to the read voltage FR and less than the read voltage GR. The threshold voltage included in the "G" level is greater than or equal to the read voltage AR and less than the voltage VREAD described later.

[0078] Furthermore, the verify voltages AV, BV, CV, DV, EV, FV, and GV are set to higher voltages than the read voltages AR, BR, CR, DR, ER, FR, and GR, respectively. The verify voltages are the voltages used during data writing operations.

[0079] The voltage VREAD is set to a voltage higher than the highest threshold distribution (the maximum threshold voltage at the "G" level). When the voltage VREAD is applied to the gate of the memory cell transistor MT, it turns on regardless of the data being stored.

[0080] During read operations, the semiconductor memory device 3 uses at least one read voltage to determine which threshold distribution the memory cell transistor MT is distributed to. For example, one page of data consisting of the lower bits (lower page data) is determined by read operations using read voltages AR and ER. One page of data consisting of the middle bits (middle page data) is determined by read operations using read voltages BR, DR, and FR. One page of data consisting of the upper bits (upper page data) is determined by read operations using read voltages CR and GR, respectively.

[0081] During the write operation, the semiconductor memory device 3 uses a read operation (hereinafter referred to as "verification operation") with a verify voltage to check whether the threshold voltage of the memory cell transistor MT on which certain data is to be stored exceeds the verify voltage associated with that data. When the sequencer 14 detects that the threshold voltage of the memory cell transistor MT has exceeded the verify voltage associated with that data, it completes the data write operation to the memory cell transistor MT.

[0082] 1.2. Operation The data read and write operations of the semiconductor memory device according to the first embodiment will be described below. In the following description, the case in which a cell unit CU including a memory cell transistor MTk (0≦k≦7) is the target of reading or writing will be described. Hereinafter, the memory cell transistor MTk that is the target of reading or writing will be referred to as the selected memory cell transistor MTk.

[0083] The word line WL connected to the selection memory cell transistor MTk is called the selection word line WLk. The word lines WL(k+1) and WL(k-1) adjacent to the selection word line WLk in the Z direction via the insulating layer are called adjacent word lines WL(k±1). For word line WL0, it is assumed that there is an unillustrated word line WL corresponding to adjacent word line WL(k-1). For word line WL7, it is assumed that there is an unillustrated word line WL corresponding to adjacent word line WL(k+1). The word lines WL that are not adjacent to the selection word line WLk in the Z direction via the insulating layer are called non-adjacent word lines WL(k±i) (i≧2). In the following, WL(k±2) will be described as a representative of the non-adjacent word lines WL(k±i).

[0084] Capacitive interference can occur between two adjacent word lines WL in the Z direction. For example, if the voltage of one word line WL gradually increases and the voltage of the other word line WL gradually decreases, capacitive interference occurs between the two word lines WL, and a coupling current flows through each word line WL. Since the coupling current acts in a direction that inhibits the change in voltage, the rate at which the voltages of both word lines increase or decrease at the far end of each word line WL may decrease. For example, due to the effect of the coupling current, the time required for the far end of each word line WL to rise or fall to a predetermined voltage may be approximately twice as long in some cases.

[0085] Furthermore, for example, if one word line WL is floating and the voltage of the other word line WL is gradually decreasing, capacitive interference occurs between the two word lines WL, causing coupling current to flow through each word line WL. As a result, the voltage of the floating word line WL may decrease.

[0086] A signal line CG connected to the selected word line WLk is called the selected signal line CGk. Signal lines CG(k+1) and CG(k-1) connected to the adjacent word line WL(k±1) are called the adjacent signal lines CG(k±1). Signal lines CG(k+2) and CG(k-2) connected to the non-adjacent word line WL(k±2) are called the non-adjacent signal lines CG(k±2).

[0087] 1.2.1 Read operation An example of a read operation in the semiconductor storage device 3 according to the first embodiment will be described, with the read operation of lower page data being a representative example of a page-level read operation.

[0088] Figure 10 is a timing chart showing an example of the lower page data read operation in a semiconductor memory device according to the first embodiment. Note that for each word line WL, the voltage at the near end is shown with a solid line, and the voltage at the far end is shown with a dashed line.

[0089] As shown in Figure 10, at the start of the read operation, the voltages of the selected word line WLk, the adjacent word line WL(k±1), and the non-adjacent word line WL(k±2) are the voltage VSS. The voltage VSS is, for example, the ground voltage.

[0090] When the lower page data read operation is initiated, the sequencer 14 performs an operation to remove residual electrons in the channel of the selected memory cell transistor MTk, for example, during the period from time t10 to t14. During the period from time t14 to t15, it performs a read operation using the read voltage AR. During the period from time t15 to t16, it performs a read operation using the read voltage ER.

[0091] At time t10, the voltage VREAD is applied to the selected signal line CGk and the non-adjacent signal lines CG(k±2).

[0092] For example, the voltage at the near end of each of the selected word line WLk and the non-adjacent word line WL(k±2) gradually increases, reaching the voltage VREAD at time t12. The voltage at the far end of each of the selected word line WLk and the non-adjacent word line WL(k±2) increases with a delay compared to the near end.

[0093] Meanwhile, at time t10, a voltage VREADK is applied to the adjacent signal line CG(k±1). The voltage VREADK is higher than the voltage VREAD and lower than the voltage VPGM, which will be described later.

[0094] The voltage regulator circuit 63 that generates the voltage VREADK applied to the adjacent signal line CG(k±1) is connected to the charge pump circuit 53. On the other hand, the voltage regulator circuit 62 that generates the voltage VREAD applied to the selection signal line CGk and the non-adjacent signal line CG(k±2) is connected to the charge pump circuit 52. The charge pump circuit 53 supplies current to only two signal lines, the adjacent signal lines CG(k±1), whereas the charge pump circuit 52 supplies current to many signal lines. Therefore, the current supplied to each of the adjacent signal lines CG(k±1) can be greater than the current supplied to each of the non-adjacent signal lines CG(k±2). In other words, the charge pump circuit 53 has a higher current supply capacity per signal line CG than the charge pump circuit 52. As a result, the adjacent word line WL(k±1) experiences a higher rate of voltage increase and a steeper slope than the selection word line WLk and the non-adjacent word line WL(k±2). Therefore, the near end of the adjacent word line WL(k±1) reaches voltage VREADK at time t11, earlier than time t12 when the near ends of the selected word line WLk and the non-adjacent word lines WL(k±2) reach voltage VREAD. The voltage at the far end of the adjacent word line WL(k±1) rises with a delay compared to the near end.

[0095] By setting the voltage of the adjacent word line WL(k±1) to voltage VREADK, the effect of voltage drop due to interference from the low voltage (e.g., read voltage AR) applied to the selected word line WLk during read operation can be suppressed. The gate voltage of the memory cell transistor MT may be affected by interference from the voltage of the word line WL connected to the gate of the adjacent memory cell transistor MT in the Z direction. Specifically, the voltage applied to the gate of each memory cell transistor MT(k±1) may be lower than the voltage of each adjacent word line WL(k±1) due to interference from the low voltage applied to the selected word line WLk. When the voltage of the adjacent word line WL(k±1) is set to voltage VREADK, the voltage drop due to interference to the memory cell transistor MT(k±1) by the low voltage applied to the selected word line WLk is offset by the increase in voltage VREADK from voltage VREAD (VREADK-VREAD). Therefore, when performing the read operation, the voltage drop caused by interference from the low voltage applied to the selected word line WLk can be prevented from causing the voltage of the adjacent word line WL(k±1) to fall below the highest threshold distribution (the maximum threshold voltage at the "G" level).

[0096] After the voltage at the near end (Near) of the selection word line WLk reaches voltage VREAD, at time t12, the voltage applied to the selection signal line CGk is reduced to voltage VSS. Note that the voltage applied to the selection signal line CGk may be reduced to voltage VSS even before the voltage at the far end (Far) of the selection word line WLk and the non-adjacent word lines WL(k±2) reaches voltage VREAD.

[0097] For example, the voltage at the near end (Near) of the selected word line WLk drops sharply to voltage VSS. During the period from time t12 to t13, the voltage at the far end (Far) of the selected word line WLk is affected by the coupling current due to capacitive interference between the selected word line WLk and the adjacent word line WL(k±1), and drops more slowly and with a delay compared to the near end (Near). After time t13, the voltage at the far end (Far) of the selected word line WLk drops to near the readout voltage AR at a faster rate than during the period from time t12 to t13.

[0098] Subsequently, at time t14, the voltage applied to the selection signal line CGk is increased to the readout voltage AR.

[0099] For example, the voltage at the near end (Near) of the selected word line WLk gradually rises to the read voltage AR. The voltage at the far end (Far) of the selected word line WLk continues to decrease and converges to the read voltage AR. Alternatively, the voltage at the far end (Far) of the selected word line WLk may first fall below the read voltage AR, and then rise to the read voltage AR along with the near end (Near).

[0100] Subsequently, the sense amplifier module 17 determines the data stored in the selection memory cell transistor MTk. Specifically, the sense amplifier module 17 determines whether the threshold voltage of the selection memory cell transistor MTk is equal to or greater than the read voltage AR, and stores this information in the latch circuit included in the sense amplifier module 17.

[0101] Next, at time t15, the voltage applied to the selection signal line CGk is increased to the readout voltage ER.

[0102] For example, the voltage at the near end (Near) of the selection word line WLk gradually rises up to the read voltage ER. The voltage at the far end (Far) of the selection word line WLk rises up gradually to the read voltage ER, with a delay compared to the near end.

[0103] Subsequently, the sense amplifier module 17 determines the data stored in the selection memory cell transistor MTk. Specifically, the sense amplifier module 17 determines whether the threshold voltage of the selection memory cell transistor MTk is equal to or greater than the read voltage ER. The sequencer 14 determines the lower page data based on this determination result and the determination result stored in the latch circuit included in the sense amplifier module 17. The determined lower page data is stored, for example, in the latch circuit included in the sense amplifier module 17.

[0104] Finally, at time t16, the voltage VSS is applied to the selected signal line CGk, the adjacent signal line CG(k±1), and the non-adjacent signal line CG(k±2). As a result, the voltages on the selected word line WLk, the adjacent word line WL(k±1), and the non-adjacent word line WL(k±2) drop to the voltage VSS, returning to the state before the read operation.

[0105] As described above, the semiconductor memory device 3 according to the first embodiment can perform a read operation of lower page data. In addition, the semiconductor memory device 3 according to the first embodiment can perform read operations for middle page data and upper page data in the same way as for lower page data. Subsequently, the sense amplifier module 17 performs calculation processing using the determined lower page data, middle page data, and upper page data, and transfers the determination result as read data DAT to the input / output circuit 11.

[0106] 1.2.2 Writing Operation An example of a write operation in the semiconductor storage device 3 according to the first embodiment will be described.

[0107] 1.2.2.1 Write Order Figure 11 shows an example of the data writing order in the NAND string of the semiconductor memory device according to the first embodiment. The data writing order in the NAND string NS will be explained with reference to Figure 11.

[0108] As shown in Figure 11, when a write operation is performed, the memory cell transistors MT on the bit line BL side are selected in order as the target for writing.

[0109] In the example shown in Figure 11, the sequencer 14 first selects memory cell transistor MT7 as the target for writing. Then, the sequencer 14 selects memory cell transistors MT6 to MT1 in order, and finally selects memory cell transistor MT0. In other words, the sequencer 14 first selects word line WL7 as the selected word line, then selects word lines WL6 to WL1 in that order, and finally selects word line WL0.

[0110] The following describes the case where writing is performed sequentially from the memory cell transistor MT on the bit line BL side, as shown in Figure 11. That is, when memory cell transistor MTk is selected, arbitrary data is written to memory cell transistors MT(k+1), MT(k+2), ..., MT7. No data is written to memory cell transistors MT(k-1), MT(k-2), ..., MT0 (they are erased). The selected word line WLk is provided so as to be sandwiched in the Z direction by the adjacent word line WL(k+1) connected to the memory cell transistor MT(k+1) on which data has already been written, and the adjacent word line WL(k-1) connected to the memory cell transistor MT(k-1) on which data has not yet been written, except in the cases of k=0 or k=7. Hereinafter, the adjacent word line WL(k+1) connected to the memory cell transistor MT(k+1) on which data has already been written will be specifically referred to as the already written adjacent word line WL(k+1). An adjacent word line WL(k-1) connected to a memory cell transistor MT(k-1) that has not yet had data written to it is specifically referred to as an unwritten adjacent word line WL(k-1).

[0111] A signal line CGk connected to a selected word line WLk is called a selected signal line CGk. A signal line CG(k+1) connected to an already written adjacent word line WL(k+1) is called an already written adjacent signal line CG(k+1). A signal line CG(k-1) connected to an unwritten adjacent word line WL(k-1) is called an unwritten adjacent signal line CG(k-1). Signal lines CG(k+2) and CG(k-2) connected to non-adjacent word lines WL(k±2) are called non-adjacent signal lines CG(k±2).

[0112] 1.2.2.2 Program Loop The semiconductor memory device 3 repeatedly executes a program loop during a write operation. Each program loop includes a program operation and a verify operation. During the program operation, a voltage VPGM is applied to the selected word line WLk. The voltage VPGM is a high voltage capable of raising the threshold voltage of the selected memory cell transistor MCk. This raises the threshold voltage of the selected memory cell transistor MTk. During the verify operation, it is determined whether the threshold voltage of the selected memory cell transistor MTk exceeds the verify voltage applied to the selected word line WLk. During a write operation, the program loop, which includes the program operation and the verify operation, is repeated multiple times.

[0113] In the following, an example of a write operation in the semiconductor memory device 3 according to the first embodiment will be described, using a program loop in which "A" level and "B" level are set as verification targets in the verification operation as a representative example.

[0114] Figure 12 is a timing chart showing an example of a write operation in a semiconductor memory device according to the first embodiment. Figure 12 shows the write operation in a program loop where the "A" level and "B" level are set as the verification targets in the verification operation. In Figure 12, the voltage at the near end (Near) of each word line WL is shown with a solid line, and the voltage at the far end (Far) is shown with a dashed line.

[0115] As shown in Figure 12, at the start of the program loop, the voltages of the selected word line WLk, the already written adjacent word line WL(k+1), the unwritten adjacent word line WL(k-1), and the non-adjacent word line WL(k±2) are, for example, the voltage VSS.

[0116] When the program loop starts, the sequencer 14 executes the programmed operations, for example, during the period from time t20 to t23. During the period from time t23 to t29, it performs verification operations. In particular, during the period from time t27 to t28, it performs verification using the verification voltage AV. During the period from time t28 to t29, it performs verification using the verification voltage BV. The period from time t23 to t27 is a period for adjusting the voltage levels for performing the verification operations.

[0117] As shown in Figure 12, at the start of the program loop, the voltages of the selected word line WLk, the already written adjacent word line WL(k+1), the unwritten adjacent word line WL(k-1), and the non-adjacent word line WL(k±2) are, for example, the voltage VSS.

[0118] At time t20, the voltage VPASS is applied to the selected signal line CGk, the already written adjacent signal line CG(k+1), the unwritten adjacent signal line CG(k-1), and the non-adjacent signal line CG(k±2). The voltage VPASS is lower than the voltage VPGM and is a voltage that turns on the memory cell transistor MT regardless of the threshold voltage of the memory cell transistor MT.

[0119] For example, the voltage at the near end of each of the selected word line WLk, the already written adjacent word line WL(k+1), the unwritten adjacent word line WL(k-1), and the non-adjacent word line WL(k±2) gradually increases until it reaches voltage VPASS. The voltage at the far end of each of the selected word line WLk, the already written adjacent word line WL(k+1), the unwritten adjacent word line WL(k-1), and the non-adjacent word line WL(k±2) increases with a delay compared to the near end.

[0120] Next, at time t21, the voltage VPGM is applied to the selection signal line CGk.

[0121] For example, the voltage at the near end (Near) of the selected word line WLk gradually increases until it reaches voltage VPGM. The voltage at the far end (Far) of the selected word line WLk increases with a delay compared to the near end (Near).

[0122] During the period from time t21 to t22, when the voltage across the selection word line WLk reaches the voltage VPGM, the potential difference (VPGM-VSS) between the selection word line WLk and the channel (e.g., the voltage VSS applied via the corresponding bit line BL) increases in the selection memory cell transistor MTk being programmed. As a result, electrons are trapped in the charge storage film, and the threshold voltage of the selection memory cell transistor MTk increases. On the other hand, in the selection memory cell transistor MTk that is not programmed, the potential difference between the selection word line WLk and the channel (e.g., the voltage applied via the corresponding bit line BL) is smaller than that of the selection memory cell transistor MTk being programmed. As a result, due to the self-boost effect, electrons are not trapped in the charge storage film, and the threshold voltage of the selection memory cell transistor MTk is maintained.

[0123] Next, at time t22, the voltage VCGM is applied to the selected signal line CGk, the already written adjacent signal line CG(k+1), the unwritten adjacent signal line CG(k-1), and the non-adjacent signal line CG(k±2). The voltage VCGM is higher than the voltage VSS and lower than the voltages VPASS and VREAD.

[0124] For example, the voltage at the near end (Near) of the selected word line WLk drops sharply, reaching a voltage near VCGM at time t23. The voltage at the far end (Far) of the selected word line WLk lags behind the near end (Near) immediately after the voltage is applied, and then drops while being affected by the coupling current due to capacitive interference between it and the adjacent word line WL(k±1).

[0125] The voltages at the near end of each of the already written adjacent word line WL(k+1) and the unwritten adjacent word line WL(k-1) drop sharply and reach voltage VCGM before time t23. The voltages at the far end of each of the already written adjacent word line WL(k+1) and the unwritten adjacent word line WL(k-1) are affected by the coupling current due to capacitive interference with the selected word line WLk and drop sharply, and may take a voltage lower than voltage VCGM.

[0126] The voltage at the near end (Near) of the non-adjacent word line WL(k±2) drops sharply to the voltage VCGM. The voltage at the far end (Far) of the non-adjacent word line WL(k±2) drops with a delay compared to the near end (Near).

[0127] Next, at time t23, the voltage VREAD is applied to the selected signal line CGk and the non-adjacent signal lines CG(k±2). The voltage VREADK is applied to the already written adjacent signal line CG(k+1). The voltage VREADE is applied to the unwritten adjacent signal line CG(k-1). The voltage VREADE is lower than the voltage VREAD and higher than the lowest threshold distribution (the maximum threshold voltage at the "Er" level). When the voltage VREADE is applied to the gate of the memory cell transistor MT, which is in the erase state (no data has been written), it turns ON.

[0128] The voltage regulator circuit 63 that generates the voltage VREADK applied to the already written adjacent signal line CG(k+1) is connected to the charge pump circuit 53. On the other hand, the voltage regulator circuit 62 that generates the voltage VREAD applied to the selection signal line CGk and the non-adjacent signal line CG(k±2), and the voltage VREADE applied to the unwritten adjacent signal line CG(k-1), is connected to the charge pump circuit 52. The charge pump circuit 53 supplies current to only one signal line, the already written adjacent signal line CG(k+1), whereas the charge pump circuit 52 supplies current to many signal lines. Therefore, the current supplied to the already written adjacent signal line CG(k+1) can be greater than the current supplied to each of the selection signal line CGk, the unwritten adjacent signal line CG(k-1), and the non-adjacent signal line CG(k±2). In other words, the charge pump circuit 53 has a higher current supply capacity per signal line CG than the charge pump circuit 52. Therefore, the voltage rise rate of the already written adjacent word line WL(k+1) is higher and the slope is steeper than that of the selected word line WLk, the unwritten adjacent word line WL(k-1), and the non-adjacent word line WL(k±2). Consequently, for example, the voltage at the near end of the already written adjacent word line WL(k+1) reaches voltage VREADK at time t24. The voltage at the far end of the already written adjacent word line WL(k+1) is delayed compared to the near end and rises more slowly due to the coupling current caused by capacitive interference with the selected word line WLk.

[0129] From time t23 onward, the voltage at the near end of the selected word line WLk, the unwritten adjacent word line WL(k-1), and the non-adjacent word line WL(k±2) rises at approximately the same rate (slope). Therefore, the unwritten adjacent word line WL(k-1), which has a lower applied voltage, reaches voltage VREADE first. The far end (Far) of the selected word line WLk, the unwritten adjacent word line WL(k-1), and the non-adjacent word line WL(k±2) rises with a delay compared to the near end (Near). For example, the far end (Far) of the unwritten adjacent word line WL(k-1) reaches voltage VREADE.

[0130] By increasing the voltage of the selection word line WLk, residual electrons in the channel of the selection memory cell transistor MTk are removed, enabling proper verification.

[0131] Subsequently, at time t25, a voltage VSS is applied to the selection signal line CGk.

[0132] From time t25 onward, the voltage at the far end (Far) of the already written adjacent word line WL(k+1) is affected by the coupling current due to capacitive interference with the selected word line WLk, causing the voltage rise to slow down until it reaches the voltage VREADK at time t26.

[0133] The voltage at the near end (Near) of the selected word line WLk drops sharply and reaches voltage VSS. The voltage at the far end (Far) of the selected word line WLk drops slowly during the period from time t25 to t26 due to the coupling current caused by capacitive interference with the already written adjacent word line WL(k+1). After time t26, the effect of the coupling current is small, so the voltage drops more rapidly to near the verify voltage AV.

[0134] By setting the voltage of the already written adjacent word line WL(k+1) to voltage VREADK, the voltage drop caused by interference from the low voltage (e.g., verify voltage AV) applied to the selected word line WLk during the verification operation can be canceled out. The memory cell transistor MT may be affected by the voltage of the word line WL connected to the gate of the adjacent memory cell transistor MT in the Z direction. Specifically, the voltage applied to the gate of each memory cell transistor MT(k+1) may be lower than the voltage of each adjacent word line WL(k+1) due to interference from the low voltage applied to the selected word line WLk. When the voltage of the adjacent word line WL(k+1) is set to voltage VREADK, the voltage drop caused by the voltage drop effect on the memory cell transistor MT(k+1) due to the low voltage applied to the selected word line WLk is canceled out by the increase in voltage VREADK from voltage VREAD (VREADK-VREAD). Therefore, when performing the verification operation, the voltage drop caused by the low voltage applied to the selected word line WLk can prevent the voltage of the already written adjacent word line WL(k+1) from falling below the highest threshold distribution (the maximum threshold voltage at the "G" level).

[0135] Subsequently, at time t27, the verify voltage AV is applied to the selected signal line CGk.

[0136] For example, the voltage at the near end (Near) of the selected word line WLk gradually rises to the verify voltage AV. The voltage at the far end (Far) of the selected word line WLk continues to decrease and converges to the verify voltage AV. Alternatively, the voltage at the far end (Far) of the selected word line WLk may first fall below the verify voltage AV before rising to the verify voltage AV along with the near end (Near).

[0137] Subsequently, the sense amplifier module 17 determines the data stored in the selected memory cell transistor MTk, which is the target of verification. Specifically, the sense amplifier module 17 determines whether the threshold voltage of the selected memory cell transistor MTk is equal to or greater than the verification voltage AV, and stores this information in the latch circuit included in the sense amplifier module 17.

[0138] Next, at time t28, the voltage applied to the selection signal line CGk is increased to the verify voltage BV.

[0139] For example, the voltage at the near end (Near) of the selected word line WLk gradually rises up to the verify voltage BV. The voltage at the far end (Far) of the selected word line WLk rises up gradually to the verify voltage BV, with a delay compared to the near end.

[0140] Subsequently, the sense amplifier module 17 determines the data stored in the selection memory cell transistor MTk. Specifically, the sense amplifier module 17 determines whether the threshold voltage of the selection memory cell transistor MTk is equal to or greater than the verify voltage BV. The sequencer 14 determines the verification result based on this determination result and the determination result stored in the latch circuit included in the sense amplifier module 17. The determined verification result is stored, for example, in the latch circuit included in the sense amplifier module 17.

[0141] Finally, at time t29, the voltage VSS is applied to the selected signal line CGk, the already written adjacent word line WL(k+1), the unwritten adjacent word line WL(k-1), and the non-adjacent signal line CG(k±2). As a result, the voltages on the selected word line WLk, the already written adjacent word line WL(k+1), the unwritten adjacent word line WL(k-1), and the non-adjacent word line WL(k±2) drop down to the voltage VSS, returning to the state at the start of the program loop.

[0142] As described above, the semiconductor memory device 3 according to the first embodiment executes one program loop. After that, based on the verification result, it is decided whether to execute the next program loop. If so, in the next program loop, the selected memory cell transistor MTk to be programmed and the selected memory cell transistor MTk to be disabled for programming are determined. By executing multiple program loops, the semiconductor memory device 3 according to the first embodiment can perform a write operation.

[0143] 1.3. Effects The semiconductor memory device according to this embodiment can reduce the processing time required for reading and writing data to memory cells. This effect will be described in detail below.

[0144] 1.3.1 Effects in read operations During the readout operation, from the time when the voltage of the selected word line WLk begins to drop to voltage VSS (time t12 in Figure 10) to the time when the voltage rise at the far end (Far) of the adjacent word line WL(k±1) ends (time t13 in Figure 10) (t12~t13), the voltage of the adjacent word line WL(k±1) rises and the voltage of the selected word line WLk falls, resulting in a coupling current due to capacitive interference between the two. This coupling current inhibits the rise in the voltage of the adjacent word line WL(k±1) and also inhibits the decrease in the voltage of the selected word line WLk.

[0145] In the read operation of the semiconductor memory device 3 according to the first embodiment, as shown in Figure 10, the rate at which the voltage of the adjacent word line WL(k±1) rises to voltage VREADK is faster than the rate at which the voltages of the selected word line WLk and the non-adjacent word line WL(k±2) rise to voltage VREAD. Therefore, the time at which the voltage at the far end (Far) of the adjacent word line WL(k±1) reaches voltage VREADK can be accelerated. Subsequently, at the time (t12) when voltage VSS is applied to the selected word line WLk, the voltage at the far end (Far) of the adjacent word line WL(k±1) has risen to near voltage VREADK. Therefore, the period (t12~t13) from the time (t12) when the voltage of the selected word line WLk begins to fall to voltage VSS to the time (t13) when the far end (Far) of the adjacent word line WL(k±1) reaches voltage VREADK can be shortened. Therefore, the period during which the coupling current flows can be shortened, and the rate at which the voltage at the far end (Far) of the selected word line WLk decreases can be accelerated.

[0146] As a result, the time at which the voltage at the far end (Far) of the selected word line WLk reaches the read voltage (e.g., read voltage AR) is shortened, allowing the read operation to start earlier and thus reducing the overall time required for the read operation.

[0147] 1.3.2 Effects of writing operations During the writing operation, from the time when the voltage of the selected word line WLk begins to drop to voltage VSS (time t25 in Figure 12) until the time when the voltage rise at the far ends (Far) of both the already written adjacent word line WL(k+1) and the unwritten adjacent word line WL(k-1) ends (time t26 in Figure 12) (t25~t26), the voltages of the already written adjacent word line WL(k+1) and the unwritten adjacent word line WL(k-1) rise, and the voltage of the selected word line WLk falls. As a result, a coupling current is generated due to capacitive interference between the two. This coupling current inhibits the rise in voltage of the already written adjacent word line WL(k+1) and the unwritten adjacent word line WL(k-1), as well as the decrease in voltage of the selected word line WLk.

[0148] In the writing operation of the semiconductor memory device 3 according to the first embodiment, as shown in Figure 12, the rate at which the voltage of the already written adjacent word line WL(k+1) rises to voltage VREADK is faster than the rate at which the voltages of the selected word line WLk and the non-adjacent word lines WL(k±2) rise to voltage VREAD. Therefore, the time at which the voltage at the far end (Far) of the already written adjacent word line WL(k+1) reaches voltage VREADK can be accelerated. Subsequently, at the time when voltage VSS is applied to the selected word line WLk (t25), the voltage at the far end (Far) of the already written adjacent word line WL(k+1) has risen to near voltage VREADK. Therefore, the period (t25~t26) from the time when the voltage of the selected word line WLk begins to fall to voltage VSS (t25) to the time when the far end (Far) of the already written adjacent word line WL(k+1) reaches voltage VREADK (t26) can be shortened. Therefore, the period during which the coupling current flows can be shortened, and the rate at which the voltage at the far end (Far) of the selected word line WLk drops to the voltage VSS can be increased.

[0149] Furthermore, the time it takes for the voltage of the unwritten adjacent word line WL(k-1) to rise to voltage VREADE is shorter than the time it takes for the voltages of the selected word line WLk and the non-adjacent word lines WL(k±2) to rise to voltage VREADE. Therefore, the time at which the voltage at the far end (Far) of the unwritten adjacent word line WL(k-1) reaches voltage VREADE can be accelerated. Subsequently, at the time when voltage VSS is applied to the selected word line WLk (t25), the voltage at the far end (Far) of the unwritten adjacent word line WL(k-1) has risen to near voltage VREADE. Therefore, the period from the time when the voltage of the selected word line WLk begins to fall to voltage VSS to the time when the far end (Far) of the unwritten adjacent word line WL(k-1) reaches voltage VREADE can be shortened. Thus, the period during which coupling current flows can be shortened, and the rate at which the voltage at the far end (Far) of the selected word line WLk falls can be accelerated.

[0150] Furthermore, the memory cell transistor MT(k-1), to which the unwritten adjacent word line WL(k-1) is connected as a gate, has no data written to it (it is in an erased state). Therefore, even if the voltage VREADE is applied instead of the voltage VREAD during verification, the memory cell transistor MT(k-1) will turn ON. Consequently, this does not hinder the verification operation.

[0151] As a result, the time at which the voltage at the far end (Far) of the selected word line WLk reaches the verify voltage (e.g., verify voltage AV) is shortened, allowing the verification operation to start earlier and, consequently, reducing the overall time required for the write operation.

[0152] 2. Second Embodiment Next, a semiconductor memory device according to the second embodiment will be described. The semiconductor memory device 3 according to the second embodiment performs a different operation in read operation compared to the semiconductor memory device 3 according to the first embodiment. In the following description, the same configuration and operation as the first embodiment will be omitted from the description, and the operation that differs from the first embodiment will be mainly described.

[0153] 2.1 Read Operation An example of a read operation in the semiconductor memory device 3 according to the second embodiment will be described, with the read operation of lower page data being a representative example of a page-level read operation.

[0154] Figure 13 is a timing chart showing an example of the lower page data read operation in a semiconductor memory device according to the second embodiment. Note that for each word line WL, the voltage at the near end is shown with a solid line, and the voltage at the far end is shown with a dashed line.

[0155] As shown in Figure 13, at the start of the read operation, the voltages of the selected word line WLk, the adjacent word line WL(k±1), and the non-adjacent word line WL(k±2) are, for example, the voltage VSS.

[0156] At time t30, the voltage VREAD is applied to the non-adjacent signal line CG(k±2).

[0157] For example, the voltage at the near end of the non-adjacent word line WL(k±2) gradually increases, reaching the voltage VREAD at time t32. The voltage at the far end of the non-adjacent word line WL(k±2) increases with a delay compared to the near end.

[0158] Meanwhile, at time t30, the voltage VREADK is applied to the selected signal line CGk and the adjacent signal line CG(k±1).

[0159] The voltage regulator circuit 63, which generates the voltage VREADK applied to the selection signal line CGk and the adjacent signal line CG(k±1), is connected to the charge pump circuit 53. On the other hand, the voltage regulator circuit 62, which generates the voltage VREAD applied to the non-adjacent signal line CG(k±2), is connected to the charge pump circuit 52. The charge pump circuit 53 supplies current to only three signal lines: the selection signal line CGk and the adjacent signal line CG(k±1), whereas the charge pump circuit 52 supplies current to many signal lines. Therefore, the current supplied to each of the adjacent signal lines CG(k±1) can be greater than the current supplied to each of the non-adjacent signal lines CG(k±2). In other words, the charge pump circuit 53 has a higher current supply capacity per signal line CG than the charge pump circuit 52. As a result, the voltage rise rate is higher and the slope is steeper for the selection word line WLk and the adjacent word line WL(k±1) than for the non-adjacent word line WL(k±2). Therefore, at time t31, earlier than time t32, when the near end of the non-adjacent word line WL(k±2) reaches voltage VREAD, the near ends of the selected word line WLk and the adjacent word line WL(k±1) each reach voltage VREADK. The voltages at the far ends of the selected word line WLk and the adjacent word line WL(k±1) each rise with a delay compared to the near ends.

[0160] The operation at times t32 to t36 is the same as the operation at times t12 to t16 in the first embodiment.

[0161] 2.2 Effects The semiconductor memory device 3 according to the second embodiment can shorten the processing time required for reading data to the memory cell, similar to the first embodiment.

[0162] Furthermore, in the semiconductor memory device 3 according to the second embodiment, during a read operation, the selected word line WLk is raised to the voltage VREADK at the same rate as the adjacent word line WL(k±1). This suppresses capacitive interference that may occur between the selected word line WLk and the adjacent word line WL(k±1) when the voltage rises. As a result, the time required for the voltage rise can be shortened, and consequently, the processing time required for the entire read operation can be shortened.

[0163] Furthermore, if there is a difference in potential between adjacent word lines, GIDL (Gate Induced Drain Leakage) may occur. When GIDL occurs, the high-field effect causes hot carrier injection (HCI) into the charge storage film, which can lead to rewriting of data stored by the memory cell transistor MT or deterioration of the circuit characteristics of the memory cell transistor MT. In other words, the occurrence of GIDL leads to a decrease in the reliability of the semiconductor memory device 3.

[0164] In the semiconductor memory device 3 according to the second embodiment, during read operation, the selected word line WLk is raised to the voltage VREADK at the same rate as the adjacent word line WL(k±1). As a result, the potential difference between the selected word line WLk and the adjacent word line WL(k±1) becomes small, which suppresses the occurrence of GIDL near the selected word line WLk and suppresses hot carrier injection. Therefore, the degradation of the reliability of the semiconductor memory device 3 can be suppressed.

[0165] 3. Third Embodiment Next, a semiconductor memory device according to the third embodiment will be described. The semiconductor memory device 3 according to the third embodiment performs a different operation in read operation compared to the semiconductor memory device 3 according to the second embodiment. In the following description, the configuration and operation equivalent to that of the second embodiment will be omitted, and the operation that differs from that of the second embodiment will be described mainly.

[0166] 3.1 Circuit configuration of the driver module Figure 14 is a circuit diagram showing an example of the circuit configuration of a driver module included in a semiconductor memory device according to the third embodiment.

[0167] As shown in Figure 14, in the driver module 15 of the semiconductor memory device 3 according to the third embodiment, the voltage regulator circuit 63 further generates a voltage VOPTK. The voltage VOPTK is higher than the highest threshold distribution (the maximum threshold at the "G" level) and lower than the voltage VREADK. The voltage regulator circuit 63 outputs the voltage VOPTK from the same output terminal as the voltage VREADK, for example. That is, the voltage regulator circuit 63 functions as a variable voltage regulator.

[0168] 3.2 Read Operation An example of a read operation in the semiconductor memory device 3 according to the third embodiment will be described, with the read operation of lower page data as a representative example of a page-level read operation.

[0169] Figure 15 is a timing chart showing an example of the lower page data read operation in a semiconductor memory device according to the third embodiment. Note that for each word line WL, the voltage at the near end is shown with a solid line, and the voltage at the far end is shown with a dashed line.

[0170] As shown in Figure 15, at the start of the read operation, the voltages of the selected word line WLk, the adjacent word line WL(k±1), and the non-adjacent word line WL(k±2) are, for example, voltage VSS.

[0171] At time t40, the voltage VREAD is applied to the non-adjacent signal line CG(k±2).

[0172] For example, the voltage at the near end of the non-adjacent word line WL(k±2) gradually increases, reaching the voltage VREAD at time t43. The voltage at the far end of the non-adjacent word line WL(k±2) increases with a delay compared to the near end.

[0173] Meanwhile, at time t40, the voltage VOPTK is applied to the selected signal line CGk and the adjacent signal line CG(k±1).

[0174] The voltage regulator circuit 63, which generates the voltage VOPTK applied to the selected signal line CGk and the adjacent signal line CG(k±1), is connected to the charge pump circuit 53. On the other hand, the voltage regulator circuit 62, which generates the voltage VREAD applied to the non-adjacent signal line CG(k±2), is connected to the charge pump circuit 52. The charge pump circuit 53 supplies current to only two adjacent signal lines CG(k±1), whereas the charge pump circuit 52 supplies current to non-adjacent signal lines CG(k±i) (where i is an integer greater than or equal to 2), and thus supplies current to a larger number of signal lines CG compared to the charge pump circuit. Therefore, the current supplied to each of the adjacent signal lines CG(k±1) can be greater than the current supplied to each of the non-adjacent signal lines CG(k±2). Thus, the charge pump circuit 53 has a higher current supply capacity per signal line CG than the charge pump circuit 52. Therefore, the voltage rise rate and slope are higher for the selected word line WLk and the adjacent word line WL(k±1) than for the non-adjacent word line WL(k±2). Consequently, the near ends (Near) of the selected word line WLk and the adjacent word line WL(k±1) reach the voltage VOPTK at time t41, earlier than time t43 when the near end (Near) of the non-adjacent word line WL(k±2) reaches the voltage VREAD, and thereafter maintain the voltage VOPTK. The voltage at the far ends (Far) of the selected word line WLk and the adjacent word line WL(k±1) rises with a delay compared to the near ends (Near).

[0175] At time t42, when the voltage at the near end of the non-adjacent word line WL(k±2) rises to a height corresponding to the voltage VOPTK, the voltage VREADK is applied to the selection signal line CGk and the adjacent signal line CG(k±1).

[0176] For example, the voltage at the near end of the selected word line WLk and the adjacent word line WL(k±1) gradually increases to the voltage VREADK. The voltage at the far end of the selected word line WLk and the adjacent word line WL(k±1) increases with a delay compared to the near end. That is, the process of raising the voltage of the selected word line WLk and the adjacent word line WL(k±1) to the voltage VREADK includes a first part that raises the voltage to VOPTK, a second part that maintains the voltage VOPTK, and a third part that raises the voltage to VREADK.

[0177] The operation at times t43 to t47 is the same as the operation at t32 to t36 in the second embodiment.

[0178] 3.3 Effects The semiconductor memory device 3 according to the third embodiment, like the second embodiment, can shorten the processing time required for reading data to the memory cell.

[0179] Furthermore, in the semiconductor memory device 3 according to the third embodiment, during read operation, the voltage of the selected word line WLk and the adjacent word line WL(k±1) is first raised to voltage VOPTK, and then, after the voltage of the non-adjacent word line WL(k±2) reaches voltage VOPTK, it is raised to voltage VREADK. As a result, the potential difference between the selected word line WLk and the adjacent word line WL(k±1) is reduced, thereby suppressing the occurrence of GIDL near the selected word line WLk and suppressing hot carrier injection. In addition, the potential difference during voltage rise can be reduced between the adjacent word line WL(k±1) and the non-adjacent word line adjacent to the adjacent word line WL(k±1) in the Z direction (for example, adjacent word line WL(k+1) and non-adjacent word line WL(k+2)). Specifically, voltage VOPTK is adjusted so that the potential difference between it and the word line WL(k±2) which is rising to voltage VREAD is such that hot carrier injection due to GIDL is unlikely to occur. As a result, hot carrier injection near the adjacent word line WL(k±1) can be suppressed. Therefore, the degradation of the reliability of the semiconductor memory device 3 can be suppressed.

[0180] 4. Fourth Embodiment Next, a semiconductor memory device according to the fourth embodiment will be described. The semiconductor memory device 3 according to the fourth embodiment performs a different operation in read operation compared to the semiconductor memory device 3 according to the third embodiment. In the following description, the configuration and operation equivalent to that of the third embodiment will be omitted, and the operation that differs from that of the third embodiment will be described mainly.

[0181] 4.1 Read Operation An example of a read operation in the semiconductor memory device 3 according to the fourth embodiment will be described, with the read operation of lower page data being a representative example of a page-level read operation.

[0182] Figure 16 is a timing chart showing an example of the lower page data read operation in a semiconductor memory device according to the fourth embodiment. Note that for each word line WL, the voltage at the near end is shown with a solid line, and the voltage at the far end is shown with a dashed line.

[0183] As shown in Figure 16, at the start of the read operation, the voltages of the selected word line WLk, the adjacent word line WL(k±1), and the non-adjacent word line WL(k±2) are, for example, the voltage VSS.

[0184] In t50~t51, the operation in which voltage VREAD is applied to the non-adjacent signal line CG(k±2) and voltage VOPTK is applied to the selected signal line CGk and the adjacent signal line CG(k±1) is the same as the operation in t40~t41 of the third embodiment.

[0185] After a predetermined period T has elapsed from time t50, at time t52, the voltage VSS is applied to the selection signal line CGk. The period T is longer than the time from when the voltage VOPTK is first applied to the selection signal line CGk (t50) until the voltage at the near end of the selection word line WLk reaches the voltage VOPTK (t51), and shorter than the time until the voltage VREADK is applied to the adjacent signal line CG(k±1), as described later (t53). The period T is measured internally by the sequencer 14 using self-timer control or the like.

[0186] For example, the voltage at the near end (Near) of the selected word line WLk drops sharply and reaches voltage VSS. The voltage at the far end (Far) of the selected word line WLk is affected by the coupling current due to capacitive interference between the selected word line WLk and the adjacent word line WL(k±1), and drops more slowly and with a delay compared to the near end (Near).

[0187] When the voltage at the near end of the non-adjacent word line WL(k±2) rises to a height corresponding to the voltage VOPTK, the voltage VREADK is applied to the adjacent signal line CG(k±1) at time t53.

[0188] For example, the voltage at the near end (Near) of the adjacent word line WL(k±1) is affected by the coupling current due to capacitive interference between the selected word line WLk and the adjacent word line WL(k±1), and rises slowly until it reaches the voltage VREADK. The voltage at the far end (Far) of the adjacent word line WL(k±1) rises with a delay compared to the near end (Near), reaching the voltage VREADK at time t54. That is, the process of raising the voltage of the selected word line WLk to the voltage VREADK includes a first part that raises it to the voltage VOPTK, a second part that maintains the voltage VOPTK, and a third part that raises it to the voltage VREADK.

[0189] The operation at times t55 to t57 is the same as the operation at t45 to t47 in the third embodiment.

[0190] 4.2 Effects The semiconductor memory device 3 according to the fourth embodiment, like the third embodiment, can shorten the processing time required for reading data to the memory cell.

[0191] Furthermore, in the semiconductor memory device 3 according to the fourth embodiment, during the read operation, the voltage of the selected word line WLk is only raised to voltage VOPTK. Voltage VOPTK is a voltage large enough to remove residual electrons in the channel in the memory pillar MP, and has the same effect as raising the voltage of the selected word line WLk to voltage VREAD or voltage VREADK. Also, when voltage VSS is applied to the selected word line WLk to lower the voltage, the amount of voltage drop (VOPTK-VSS) can be reduced. Therefore, the time required for the voltage to drop can also be shortened accordingly. Consequently, the time at which the voltage at the far end (Far) of the selected word line WLk reaches the read voltage (e.g., read voltage AR) is shortened, allowing read operation to start earlier and thus shortening the time required for the entire read operation.

[0192] Furthermore, in the semiconductor memory device 3 according to the fourth embodiment, the period T is measured using self-timer control, and the timing of applying voltage VSS to the selected word line WLk is determined, so there is no need to manage the voltage using a separate dedicated power supply. Therefore, the increase in circuit area can be suppressed.

[0193] 5. Fifth Embodiment Next, a semiconductor memory device according to the fifth embodiment will be described. The semiconductor memory device 3 according to the fifth embodiment performs a different operation in read operation compared to the semiconductor memory device 3 according to the third embodiment. In the following description, the configuration and operation equivalent to that of the third embodiment will be omitted, and the operation that differs from that of the third embodiment will be mainly described.

[0194] 5.1 Driver Module Circuit Configuration Figure 17 is a circuit diagram showing an example of the circuit configuration of a driver module included in a semiconductor memory device according to the fifth embodiment.

[0195] As shown in Figure 17, in the driver module 15 of the semiconductor memory device 3 according to the fifth embodiment, the voltage regulator circuit 61 further generates a voltage VOPT. The voltage VOPT is higher than the highest threshold distribution (the maximum threshold at the "G" level) and lower than the voltage VOPTK. It is desirable that the voltage VOPT be as low as possible while satisfying the conditions. For example, the voltage regulator circuit 61 outputs the voltage VOPT from the same output terminal as the voltage VCGSEL.

[0196] 5.2 Read Operation An example of a read operation in the semiconductor storage device 3 according to the fifth embodiment will be described, with the read operation of lower page data being a representative example of a page-level read operation.

[0197] Figure 18 is a timing chart showing an example of the lower page data read operation in a semiconductor memory device according to the fifth embodiment. Note that for each word line WL, the voltage at the near end is shown with a solid line, and the voltage at the far end is shown with a dashed line.

[0198] As shown in Figure 18, at the start of the read operation, the voltages of the selected word line WLk, the adjacent word line WL(k±1), and the non-adjacent word line WL(k±2) are, for example, the voltage VSS.

[0199] At time t60, the voltage VREAD is applied to the non-adjacent signal line CG(k±2).

[0200] For example, the voltage at the near end of the non-adjacent word line WL(k±2) gradually increases, reaching the voltage VREAD at time t63. The voltage at the far end of the non-adjacent word line WL(k±2) increases with a delay compared to the near end.

[0201] At time t60, the voltage VOPT is applied to the selected signal line CGk. Additionally, the voltage VOPTK is applied to the adjacent signal line CG(k±1).

[0202] The voltage regulator circuit 63 that generates the voltage VOPT applied to the selection signal line CGk and the voltage VOPTK applied to the adjacent signal line CG(k±1) is connected to the charge pump circuit 53. On the other hand, the voltage regulator circuit 62 that generates the voltage VREAD applied to the non-adjacent signal line CG(k±2) is connected to the charge pump circuit 52. The signal lines to which the charge pump circuit 53 supplies current are only three, namely the selection signal line CGk and the adjacent signal lines CG(k±1), while there are many signal lines to which the charge pump circuit 52 supplies current. Therefore, the current supplied to each of the selection signal line CGk and the adjacent signal lines CG(k±1) can be larger than the current supplied to each of the non-adjacent signal lines CG(k±2). That is, it can be said that the charge pump circuit 53 has a higher current supply capacity per signal line CG than the charge pump circuit 52. For this reason, the adjacent word lines WL(k±1) have a higher voltage rise rate and a larger slope than the non-adjacent word lines WL(k±2). Therefore, at a time t61 earlier than the time t63 when the near end of the non-adjacent word line WL(k±2) reaches the voltage VREAD, the near end of the adjacent word line WL(k±1) reaches the voltage VOPTK, and then holds the voltage VOPTK. The voltage at the far end of the adjacent word line WL(k±1) rises with a delay compared to the near end. Also, the voltage rise rate of the selected word line WLk is substantially equal to that of the adjacent word line WL(k±1). Since the voltage VOPT is lower than the voltage VOPTK and has a smaller voltage rise width (VOPT - VSS < VOPTK - VSS), the near end of the selected word line WLk reaches the voltage VOPT at a time earlier than the time t61 when the near end of the adjacent word line WL(k±1) reaches the voltage VREADK. The voltage at the far end of the selected word line WLk rises with a delay compared to the near end.

[0203] When the voltage at the near end of the non-adjacent word line WL(k±2) rises to a level corresponding to the voltage VOPTK, at time t62, the voltage VREADK is applied to the adjacent signal line CG(k±1).

[0204] For example, the voltage at the near end (Near) of the adjacent word line WL(k±1) is affected by the coupling current due to capacitive interference between the selected word line WLk and the adjacent word line WL(k±1), and rises slowly until it reaches the voltage VREADK. The voltage at the far end (Far) of the adjacent word line WL(k±1) rises with a delay compared to the near end (Near), and reaches the voltage VREADK at time t64. That is, the process of raising the voltage of the selected word line WLk to the voltage VREADK includes a first part that raises it to the voltage VOPTK, a second part that maintains the voltage VOPTK, and a third part that raises it to the voltage VREADK.

[0205] After the voltage at the near end (Near) of the selection word line WLk reaches voltage VREAD, at time t63, the voltage applied to the selection signal line CGk is reduced to voltage VSS. Note that the voltage applied to the selection signal line CGk may be reduced to voltage VSS even before the voltage at the far end (Far) of the selection word line WLk and the non-adjacent word lines WL(k±2) reaches voltage VREAD.

[0206] For example, the voltage at the near end of the selected word line WLk drops sharply to voltage VSS. During the period from time t63 to t64, the voltage at the far end of the selected word line WLk is affected by the coupling current due to capacitive interference between the selected word line WLk and the adjacent word line WL(k±1), and drops more slowly and with a delay compared to the near end. After time t64, the voltage at the far end of the selected word line WLk drops to near the readout voltage AR at a faster rate than during the period from time t63 to t64.

[0207] The operation at times t65 to t67 is the same as the operation at t55 to t57 in the fourth embodiment.

[0208] 5.3 Effects The semiconductor memory device 3 according to the fifth embodiment, like the third embodiment, can shorten the processing time required for reading data to the memory cell.

[0209] Furthermore, in the semiconductor memory device 3 according to the fifth embodiment, during the read operation, the voltage of the selected word line WLk is only raised to voltage VOPT. Voltage VOPT is a voltage large enough to remove residual electrons in the channel in the memory pillar MP, and has the same effect as raising the voltage of the selected word line WLk to voltage VREAD or voltage VREADK. Also, when voltage VSS is applied to the selected word line WLk to lower the voltage, the amount of voltage drop (VOPT-VSS) can be reduced. Therefore, the time required for the voltage to drop can also be shortened accordingly. Consequently, the time at which the voltage at the far end (Far) of the selected word line WLk reaches the read voltage (e.g., read voltage AR) is shortened, allowing read operation to start earlier and, consequently, shortening the time required for the entire read operation.

[0210] Furthermore, in the semiconductor memory device 3 according to the fifth embodiment, since the voltage VOPT is controlled by the voltage regulator circuit 63, the variability of the voltage value is small, and voltage control is easy. Therefore, the margin for dealing with the variability of the voltage value can be reduced, and the lowest possible voltage VOPT can be generated while satisfying the conditions. Consequently, the voltage drop can be reduced, and the time required for the entire read operation can be shortened.

[0211] 6. Sixth Embodiment Next, a semiconductor memory device according to the sixth embodiment will be described. The semiconductor memory device 3 according to the sixth embodiment performs a different operation in the writing operation compared to the semiconductor memory device 3 according to the first embodiment. In the following description, the same configuration and operation as the first embodiment will be omitted from the description, and the operation that differs from the first embodiment will be described mainly.

[0212] 6.1 Circuit configuration of the driver module Figure 19 is a circuit diagram showing an example of the circuit configuration of a driver module included in a semiconductor memory device according to the sixth embodiment.

[0213] As shown in Figure 19, in the driver module 15 of the semiconductor memory device 3 according to the sixth embodiment, the voltage regulator circuit 62 further generates a voltage VPVD. The voltage VPVD is higher than the lowest threshold distribution (the maximum threshold voltage at the "Er" level) and the voltage VCGM, and lower than the voltage VREADE. When the voltage VPVD is applied to the gate of a memory cell transistor MT that is in an erased state (no data has been written), it turns on. The voltage regulator circuit 62 outputs the voltage VPVD from an output terminal different from the output terminals to which the voltages VPASS, VREAD, and VCGM are output, and the output terminal to which the voltage VREADE is output.

[0214] 6.2 Writing Operation In the verification operation, an example of a write operation in the semiconductor memory device 3 according to the sixth embodiment will be described, using a program loop in which "A" level and "B" level are set as the verification targets as a representative example.

[0215] In the following explanation, word lines WL connected to memory cell transistors MT(k+2), MT(k+3), ..., MT7, which have already had data written to them, are specifically referred to as already written non-adjacent word lines WL(k+i) (where i is an integer greater than or equal to 2). Word lines WL connected to memory cell transistors MT(k-2), MT(k-3), ..., MT0, which have not yet had data written to them, are specifically referred to as unwritten non-adjacent word lines WL(ki).

[0216] In the following explanation, WL(k+2) will be described as a representative of the already written non-adjacent word line WL(k+i). WL(k-2) will be described as a representative of the unwritten non-adjacent word line WL(ki). For word lines WL0 and WL1, it is assumed that there are unillustrated word lines WL corresponding to the adjacent word line WL(k-1) and non-adjacent word line WL(k-2). For word lines WL6 and WL7, it is assumed that there are unillustrated word lines WL corresponding to the adjacent word line WL(k+1) and non-adjacent word line WL(k+2).

[0217] Figure 20 is a timing chart showing an example of a write operation in a semiconductor memory device according to the sixth embodiment. Figure 20 shows the write operation in a program loop where the "A" level and "B" level are set as the verification targets in the verification operation. Note that for the voltage of each word line WL, the voltage at the near end is shown with a solid line, and the voltage at the far end is shown with a dashed line.

[0218] As shown in Figure 20, at the start of the program loop, the voltages of the selected word line WLk, the already written adjacent word line WL(k+1), the unwritten adjacent word line WL(k-1), the already written non-adjacent signal line CG(k+2), and the unwritten non-adjacent signal line CG(k-2) are, for example, the voltage VSS.

[0219] At time t70, the voltage VPASS is applied to the selected signal line CGk, the already written adjacent signal line CG(k+1), the unwritten adjacent signal line CG(k-1), the already written non-adjacent signal line CG(k+2), and the unwritten non-adjacent signal line CG(k-2).

[0220] For example, the voltage at the near end of each of the selected word line WLk, the written adjacent word line WL(k+1), the unwritten adjacent word line WL(k-1), the written non-adjacent word line WL(k+2), and the unwritten non-adjacent word line WL(k-2) gradually increases until it reaches voltage VPASS. The voltage at the far end of each of the selected word line WLk, the written adjacent word line WL(k+1), the unwritten adjacent word line WL(k-1), the written non-adjacent word line WL(k+2), and the unwritten non-adjacent word line WL(k-2) rises with a delay compared to the near end.

[0221] Next, at time t71, the voltage VPGM is applied to the selection signal line CGk. This operation is the same as the operation at time t21 in the first embodiment.

[0222] Next, at time t72, the voltage VCGM is applied to the selected signal line CGk, the already written adjacent signal line CG(k+1), the unwritten adjacent signal line CG(k-1), the already written non-adjacent word line WL(k+2), and the unwritten non-adjacent word line WL(k-2).

[0223] For example, the voltage at the near end (Near) of the selected word line WLk drops sharply, reaching a voltage near VCGM at time t73. The voltage at the far end (Far) of the selected word line WLk lags behind the near end (Near) immediately after the voltage is applied, and then drops while being affected by the coupling current due to capacitive interference between it and the adjacent word line WL(k±1).

[0224] The voltages at the near end of each of the already written adjacent word line WL(k+1) and the unwritten adjacent word line WL(k-1) drop sharply and reach voltage VCGM before time t73. The voltages at the far end of each of the already written adjacent word line WL(k+1) and the unwritten adjacent word line WL(k-1) are affected by the coupling current due to capacitive interference with the selected word line WLk and drop sharply, and may take a voltage lower than voltage VCGM.

[0225] The voltage at the near end of each of the already written non-adjacent word line WL(k+2) and the unwritten non-adjacent word line WL(k-2) drops sharply, reaching voltage VCGM before time t73. The voltage at the far end of each of the already written non-adjacent word line WL(k+2) and the unwritten non-adjacent word line WL(k-2) drops more slowly than at the near end.

[0226] Next, at time t73, the voltage VREAD is applied to the selected signal line CGk and the already written non-adjacent signal line CG(k+2). The voltage VREADK is applied to the already written adjacent signal line CG(k+1). The voltage VREADE is applied to the unwritten adjacent signal line CG(k-1). The voltage VPVD is applied to the unwritten non-adjacent signal line CG(k-2).

[0227] A voltage regulator circuit 63 that generates the voltage VREADK applied to the already written adjacent signal line CG(k+1) is connected to a charge pump circuit 53. On the other hand, a voltage regulator circuit 62 that generates the voltage VREAD applied to the selection signal line CGk and the already written non-adjacent signal line CG(k+2), the voltage VREADE applied to the unwritten adjacent signal line CG(k-1), and the voltage VPVD applied to the unwritten non-adjacent signal line CG(k-2) is connected to a charge pump circuit 52. The charge pump circuit 53 supplies current to only one signal line, the already written adjacent signal line CG(k+1), whereas the charge pump circuit 52 supplies current to many signal lines. Therefore, the current supplied to the already written adjacent signal line CG(k+1) may be greater than the current supplied to each of the selection signal line CGk, the unwritten adjacent signal line CG(k-1), the already written non-adjacent signal line CG(k+2), and the unwritten non-adjacent signal line CG(k-2). In other words, the charge pump circuit 53 has a higher current supply capacity per signal line CG than the charge pump circuit 52. Therefore, the voltage rise rate of the already written adjacent word line WL(k+1) is higher and the slope is steeper than that of the selected word line WLk, the unwritten adjacent word line WL(k-1), the already written non-adjacent word line WL(k+2), and the unwritten non-adjacent word line WL(k-2). Consequently, for example, the voltage at the near end of the already written adjacent word line WL(k+1) reaches voltage VREADK at time t74. The voltage at the far end of the already written adjacent word line WL(k+1) is delayed compared to the near end and rises slowly due to the coupling current caused by capacitive interference with the selected word line WLk.

[0228] From time t73 onward, the voltage at the near end (Near) of the selected word line WLk, the unwritten adjacent word line WL(k-1), the written non-adjacent word line WL(k+2), and the unwritten non-adjacent word line WL(k-2) rises at approximately the same rate (slope). Therefore, the unwritten non-adjacent word line WL(k-2), which has a lower applied voltage, reaches voltage VPVD first. Next, the unwritten adjacent word line WL(k-1) reaches voltage VREADE. The far end (Far) of the selected word line WLk, the unwritten adjacent word line WL(k-1), the written non-adjacent word line WL(k+2), and the unwritten non-adjacent word line WL(k-2) rises with a delay compared to the near end (Near). For example, the far end (Far) of the unwritten adjacent word line WL(k-1) reaches voltage VREADE around time t75.

[0229] Subsequently, at time t75, voltage VSS is applied to the selection signal line CGk.

[0230] From time t75 onward, the voltage at the far end (Far) of the already written adjacent word line WL(k+1) is affected by the coupling current due to capacitive interference with the selected word line WLk, causing the voltage rise to slow down until it reaches the voltage VREADK at time t76.

[0231] The voltage at the near end (Near) of the selected word line WLk drops sharply and reaches voltage VSS. The voltage at the far end (Far) of the selected word line WLk drops slowly during the period from time t75 to t76, due to the coupling current caused by capacitive interference with the already written adjacent word line WL(k+1). After time t76, the effect of the coupling current becomes smaller, so the voltage drops at a faster rate and converges to the verify voltage AV around time t77.

[0232] The verification operation using the verify voltages AV and BV during the period from time t77 to t79 is the same as the operation from time t27 to t29 in the first embodiment.

[0233] Finally, at time t79, the voltage VSS is applied to the selected signal line CGk, the written adjacent word line WL(k+1), the unwritten adjacent word line WL(k-1), the written non-adjacent word line WL(k+2), and the unwritten non-adjacent word line WL(k-2). As a result, the voltages on the selected word line WLk, the written adjacent word line WL(k+1), the unwritten adjacent word line WL(k-1), the written non-adjacent word line WL(k+2), and the unwritten non-adjacent word line WL(k-2) drop down to the voltage VSS, returning to the state at the start of the program loop.

[0234] 6.3 Effects The semiconductor memory device 3 according to the sixth embodiment, like the first embodiment, can shorten the processing time required for writing data to the memory cell.

[0235] Furthermore, in the semiconductor memory device 3 according to the sixth embodiment, during verification operation, the voltage of the unwritten non-adjacent word line WL(k-2) is not raised beyond the voltage VPVD. This reduces the current required to charge the unwritten non-adjacent word line WL(k-2), allowing the current to be redirected to charge other word lines WL. Therefore, the semiconductor memory device 3 can be operated efficiently.

[0236] Furthermore, since the unwritten non-adjacent word line WL(k-2) is connected to the gate of the memory cell transistor MT(k-2), no data has been written to it (it is in an erased state). Therefore, even if the voltage VPVD is applied instead of the voltage VREAD during verification, the memory cell transistor MT(k-2) will turn on. Consequently, the verification operation is not hindered. Also, since the unwritten non-adjacent word line WL(k-2) is not adjacent to the selected word line WLk in the Z direction, the voltage of the unwritten non-adjacent word line WL(k-2) does not interfere with the gate of the selected memory cell transistor MTk, and the selected memory cell transistor MTk will not be turned off.

[0237] Furthermore, when reading data written in the write operation, if the current flowing through the NAND string NS differs between verification and reading, there is a possibility that the data stored in the memory cell transistor MT cannot be read correctly. In the semiconductor memory device 3 according to the sixth embodiment, when verifying the selected memory cell transistor MTk, no data is stored in the memory cell transistor MT(k-2), and the threshold voltage is at the "Er" level. By applying a voltage VPVD lower than the voltage VREAD to the memory cell transistor MT(k-2), the resistance value in the channel of the memory cell transistor MT(k-2) increases compared to when the voltage VREAD is applied. This makes it possible to simulate the resistance value in the channel when, for example, the voltage VREAD is applied to the memory cell transistor MT(k-2), which is at an arbitrary level during reading. Therefore, the current flowing through the NAND string can be made the same during verification and reading, and a decrease in the reliability of the semiconductor memory device 3 can be suppressed.

[0238] 7. Seventh Embodiment Next, a semiconductor memory device according to the seventh embodiment will be described. The semiconductor memory device 3 according to the seventh embodiment performs a different operation in the writing operation compared to the semiconductor memory device 3 according to the sixth embodiment. In the following description, the configuration and operation equivalent to that of the sixth embodiment will be omitted, and the operation that differs from that of the sixth embodiment will be mainly described.

[0239] 7.1 Writing Operation Figure 21 is a timing chart showing an example of a write operation in a semiconductor memory device according to the seventh embodiment. Figure 21 shows the write operation in a program loop where the "A" level and "B" level are set as the verification targets in the verification operation. Note that for the voltage of each word line WL, the voltage at the near end is shown with a solid line, and the voltage at the far end is shown with a dashed line.

[0240] As shown in Figure 21, at the start of the program loop, the voltages of the selected word line WLk, the already written adjacent word line WL(k+1), the unwritten adjacent word line WL(k-1), the already written non-adjacent signal line CG(k+2), and the unwritten non-adjacent signal line CG(k-2) are, for example, voltage VSS.

[0241] The operation during the period from time t80 to t82 is the same as the operation during the period from t70 to t72 in the sixth embodiment.

[0242] At time t82, the voltage VSS is applied to the selection signal line CGk.

[0243] For example, the voltage at the near end (Near) of the selected word line WLk drops sharply. The voltage at the far end (Far) of the selected word line WLk drops more slowly than at the near end (Near) immediately after the voltage is applied.

[0244] On the other hand, at time t82, the voltage VCGM is applied to the already written adjacent signal line CG(k+1), the unwritten adjacent signal line CG(k-1), the already written non-adjacent word line WL(k+2), and the unwritten non-adjacent word line WL(k-2).

[0245] The voltages at the near end of each of the already written adjacent word line WL(k+1) and the unwritten adjacent word line WL(k-1) drop sharply and reach voltage VCGM before time t83. The voltages at the far end of each of the already written adjacent word line WL(k+1) and the unwritten adjacent word line WL(k-1) are affected by the coupling current due to capacitive interference with the selected word line WLk and drop sharply, and may take a voltage lower than voltage VCGM.

[0246] The voltage at the near end of each of the already written non-adjacent word line WL(k+2) and the unwritten non-adjacent word line WL(k-2) drops sharply, reaching voltage VCGM before time t83. The voltage at the far end of each of the already written non-adjacent word line WL(k+2) and the unwritten non-adjacent word line WL(k-2) drops more slowly than at the near end.

[0247] Next, at time t83, the voltage VREADK is applied to the already written adjacent signal line CG(k+1). The voltage VREADE is applied to the unwritten adjacent signal line CG(k-1). The voltage VREAD is applied to the already written non-adjacent signal line CG(k+2). The voltage VPVD is applied to the unwritten non-adjacent signal line CG(k-2).

[0248] For example, the voltage at the near end of the already written adjacent word line WL(k+1) reaches voltage VREADK at time t84. The voltage at the far end of the already written adjacent word line WL(k+1) lags behind the near end and, influenced by the coupling current with the selected word line WLk, rises slowly, reaching voltage VREADK at time t85.

[0249] From time t83 onward, the voltage at the near end (Near) of the selected word line WLk, the unwritten adjacent word line WL(k-1), the written non-adjacent word line WL(k+2), and the unwritten non-adjacent word line WL(k-2) rises at approximately the same rate (slope). Therefore, the unwritten non-adjacent word line WL(k-2), which has a lower applied voltage, reaches voltage VPVD first. Next, the unwritten adjacent word line WL(k-1) reaches voltage VREADE. The far ends (Far) of the selected word line WLk, the unwritten adjacent word line WL(k-1), the written non-adjacent word line WL(k+2), and the unwritten non-adjacent word line WL(k-2) rise with a delay compared to the near ends (Near). In particular, the far end (Far) of the unwritten adjacent word line WL(k-1) is affected by the coupling current between it and the selected word line WLk, and rises slowly to reach voltage VREADE.

[0250] The voltage at the far end (Far) of the selected word line WLk gradually decreases from time t83 onward due to the influence of the coupling current between the already written adjacent word line WL(k+1) and the unwritten adjacent word line WL(k-1). From time t85 onward, the influence of the coupling current decreases, causing the voltage to decrease more rapidly and converge to the verify voltage AV around time t86.

[0251] The verification operation using the verify voltages AV and BV from time t86 onwards, and the operation between program loops, are the same as the operation from time t77 onwards in the sixth embodiment.

[0252] 7.2 Effects The semiconductor memory device 3 according to the seventh embodiment, like the sixth embodiment, can shorten the processing time required for writing data to the memory cell, improve operational efficiency, and suppress a decrease in the reliability of the semiconductor memory device 3.

[0253] Furthermore, in the semiconductor memory device 3 according to the seventh embodiment, when transitioning from program operation to verify operation, the voltage applied to the selection signal line CGk transitions from voltage VPGM to voltage VSS without passing through other voltages. As a result, the voltage rise at the near end (Near) of the selection word line WLk is eliminated, as in the period from time t73 to t74 in the sixth embodiment. This reduces the voltage drop and increases the rate at which the voltage at the far end (Far) of the selection word line WLk decreases. Therefore, the time at which the voltage at the far end (Far) of the selection word line WLk reaches the verify voltage (e.g., verify voltage AV) is shortened, allowing the verify operation to start earlier and, consequently, shortening the time required for the entire write operation.

[0254] In addition, in order to perform the writing operation according to the seventh embodiment, it is necessary that the voltage VPGM is sufficiently high. When the voltage VPGM is sufficiently high, at the time t83 when the verification operation starts, the voltage at the far end of the selected word line WLk takes a voltage value sufficient to remove the residual electrons in the channel of the selected memory cell transistor MTk. Therefore, there is no need to raise the voltage of the selected word line WLk again, and it becomes possible to directly apply the voltage VSS.

[0255] 8. Eighth Embodiment Next, a semiconductor memory device according to the eighth embodiment will be described. The semiconductor memory device 3 according to the eighth embodiment performs an operation different from that of the semiconductor memory device 3 according to the sixth embodiment in the writing operation. In the following description, the description of the configuration and operation equivalent to those of the sixth embodiment will be omitted, and the operation different from that of the sixth embodiment will be mainly described.

[0256] 8.1 Writing Operation FIG. 22 is a timing chart showing an example of a writing operation in a semiconductor memory device according to the eighth embodiment. FIG. 22 shows a writing operation in a program loop in which the "A" level and the "B" level are set as verification targets in the verification operation. Regarding the voltage of each word line WL, the voltage at the near end is indicated by a solid line, and the voltage at the far end is indicated by a broken line.

[0257] As shown in FIG. 22, at the start of the program loop, the voltages of the selected word line WLk, the already-written adjacent word line WL(k + 1), the unwritten adjacent word line WL(k - 1), the already-written non-adjacent signal line CG(k + 2), and the unwritten non-adjacent signal line CG(k - 2) are, for example, the voltage VSS.

[0258] The program operation during the period from time t90 to t93 is the same as the operation during the period from t70 to t73 in the sixth embodiment.

[0259] At time t93, the voltage VREADK is applied to the selected signal line CGk and the already written adjacent signal line CG(k+1). The voltage VREADE is applied to the unwritten adjacent signal line CG(k-1). The voltage VREAD is applied to the already written non-adjacent signal line CG(k+2). The voltage VPVD is applied to the unwritten non-adjacent signal line CG(k-2).

[0260] The voltage regulator circuit 63, which generates the voltage VREADK applied to the selection signal line CGk and the already written adjacent signal line CG(k+1), is connected to the charge pump circuit 53. On the other hand, the voltage regulator circuit 62, which generates the voltage VREADE applied to the unwritten adjacent signal line CG(k-1), the voltage VREAD applied to the already written non-adjacent signal line CG(k+2), and the unwritten non-adjacent signal line CG(k-2), is connected to the charge pump circuit 52. The charge pump circuit 53 supplies current to only two signal lines, the selection signal line CGk and the already written adjacent signal line CG(k+1), whereas the charge pump circuit 52 supplies current to many signal lines. Therefore, the current supplied to the already written adjacent signal line CG(k+1) may be greater than the current supplied to each of the selection signal line CGk, the unwritten adjacent signal line CG(k-1), the already written non-adjacent signal line CG(k+2), and the unwritten non-adjacent signal line CG(k-2). In other words, the charge pump circuit 53 has a higher current supply capacity per signal line CG than the charge pump circuit 52. Therefore, the voltage rise rate is higher and the slope is steeper for the selected word line WLk and the already written adjacent word line WL(k+1) than for the unwritten adjacent word line WL(k-1), the already written non-adjacent word line WL(k+2), and the unwritten non-adjacent word line WL(k-2). Consequently, for example, the voltage at the near end of the selected word line WLk and the already written adjacent word line WL(k+1) reaches voltage VREADK at time t94. The voltage at the far end of the selected word line WLk converges around voltage VREADK. The voltage at the far end of the already written adjacent word line WL(k+1) is delayed compared to the near end and rises slowly due to the coupling current caused by capacitive interference with the selected word line WLk.

[0261] Thereafter, at time t95, a voltage VSS is applied to the selected word line WLk.

[0262] After time t95, the voltage at the far end of the previously written adjacent word line WL(k + 1) is affected by the coupling current due to capacitive interference with the selected word line WLk, and the voltage rise becomes gradual, reaching the voltage VREADK at time t96.

[0263] For example, the voltage at the near end of the selected word line WLk drops rapidly and reaches the voltage VSS. The voltage at the far end of the selected word line WLk is affected by the coupling current due to capacitive interference with the previously written adjacent word line WL(k + 1) during the period from time t95 to t96 and drops gradually. After time t96, since the influence of the coupling current becomes smaller, it drops at a faster speed and converges to the verify voltage AV around time t97.

[0264] After time t93, the voltages at the near ends of the unwritten adjacent word line WL(k - 1), the previously written non - adjacent word line WL(k + 2), and the unwritten non - adjacent word line WL(k - 2) rise at substantially the same speed (slope). Therefore, the unwritten non - adjacent word line WL(k - 2) with the lower applied voltage reaches the voltage VPVD first. Thereafter, the unwritten adjacent word line WL(k - 1) reaches the voltage VREADE. The far ends of the unwritten adjacent word line WL(k - 1), the previously written non - adjacent word line WL(k + 2), and the unwritten non - adjacent word line WL(k - 2) rise with a delay compared to the near ends.

[0265] The verify operation using the verify voltages AV and BV after time t97 and the operation between program loops are the same as the operation after time t77 in the sixth embodiment.

[0266] 8.2 Effects The semiconductor memory device 3 according to the eighth embodiment, like the sixth embodiment, can shorten the processing time required for writing data to the memory cell, improve operational efficiency, and suppress a decrease in the reliability of the semiconductor memory device 3.

[0267] Furthermore, in the semiconductor memory device 3 according to the eighth embodiment, during verification operation, the voltage of the selected word line WLk is raised to VREADK at the same rate as the voltage of the previously written adjacent word line WL(k+1). This suppresses inter-word line capacitance interference that may occur between the selected word line WLk and the previously written adjacent word line WL(k+1) during voltage rise. As a result, the time required for voltage rise can be shortened, and consequently, the processing time required for the entire write operation can be shortened. In addition, the occurrence of GIDL near the selected word line WLk can be suppressed, and hot carrier injection can be suppressed. Therefore, a decrease in the reliability of the semiconductor memory device 3 can be suppressed.

[0268] 9. Ninth Embodiment Next, a semiconductor memory device according to the ninth embodiment will be described. The semiconductor memory device 3 according to the ninth embodiment performs a different operation in the writing operation compared to the semiconductor memory device 3 according to the eighth embodiment. In the following description, the configuration and operation equivalent to that of the eighth embodiment will be omitted from the description, and the operation that differs from that of the eighth embodiment will be described mainly.

[0269] 9.1 Writing Operation Figure 23 is a timing chart showing an example of a write operation in a semiconductor memory device according to the ninth embodiment. Figure 23 shows the write operation in a program loop where the "A" level and "B" level are set as the verification targets in the verification operation. Note that for the voltage of each word line WL, the voltage at the near end is shown with a solid line, and the voltage at the far end is shown with a dashed line.

[0270] As shown in Figure 23, at the start of the program loop, the voltages of the selected word line WLk, the already written adjacent word line WL(k+1), the unwritten adjacent word line WL(k-1), the already written non-adjacent signal line CG(k+2), and the unwritten non-adjacent signal line CG(k-2) are, for example, the voltage VSS.

[0271] The program operation during the period from time t100 to t103 is the same as the operation during the period from t90 to t93 in the eighth embodiment.

[0272] At time t103, the voltage VREADK is applied to the selected signal line CGk and the already written adjacent signal line CG(k+1). The voltage VREADE is applied to the unwritten adjacent signal line CG(k-1). The voltage VREAD is applied to the already written non-adjacent signal line CG(k+2). The voltage VPVD is applied to the unwritten non-adjacent signal line CG(k-2).

[0273] The voltage regulator circuit 63, which generates the voltage VREADK applied to the selection signal line CGk and the already written adjacent signal line CG(k+1), is connected to the charge pump circuit 53. On the other hand, the voltage regulator circuit 62, which generates the voltage VREADE applied to the unwritten adjacent signal line CG(k-1), the voltage VREAD applied to the already written non-adjacent signal line CG(k+2), and the unwritten non-adjacent signal line CG(k-2), is connected to the charge pump circuit 52. The charge pump circuit 53 supplies current to only two signal lines, the selection signal line CGk and the already written adjacent signal line CG(k+1), whereas the charge pump circuit 52 supplies current to many signal lines. Therefore, the current supplied to each of the selection signal line CGk and the already written adjacent signal line CG(k+1) may be greater than the current supplied to each of the unwritten adjacent signal line CG(k-1), the already written non-adjacent signal line CG(k+2), and the unwritten non-adjacent signal line CG(k-2). In other words, the charge pump circuit 53 has a higher current supply capacity per signal line CG than the charge pump circuit 52. As a result, the voltage rise rate is higher and the slope is steeper for the selected word line WLk and the already written adjacent word line WL(k+1) than for the unwritten adjacent word line WL(k-1), the already written non-adjacent word line WL(k+2), and the unwritten non-adjacent word line WL(k-2). Therefore, for example, the voltage at the near end of the already written adjacent word line WL(k+1) reaches voltage VREADK at time t105. The voltage at the far end of the already written adjacent word line WL(k+1) is delayed compared to the near end and rises more slowly due to the coupling current caused by capacitive interference with the selected word line WLk.

[0274] After a predetermined period T has elapsed from time t103, at time t104, the voltage VSS is applied to the selected word line WLk. Period T is shorter than the time from when the voltage VREADK is first applied to the selected signal line CGk (t103) until the voltage at the near end (Near) of the already written adjacent selected word line WL(k+1) reaches the voltage VREADK (t105). During period T, residual electrons in the channel are removed. Period T is measured internally by the sequencer 14 using self-timer control or the like.

[0275] From time t104 onward, the voltage at the far end (Far) of the already written adjacent word line WL(k+1) is affected by the coupling current due to capacitive interference with the selected word line WLk, causing the voltage rise to slow down until it reaches the voltage VREADK at time t106.

[0276] For example, the voltage at the near end (Near) of the selected word line WLk drops sharply and reaches voltage VSS. The voltage at the far end (Far) of the selected word line WLk drops slowly during the period from time t104 to t106, due to the coupling current caused by capacitive interference between the already written adjacent word line WL(k+1) and the unwritten adjacent word line WL(k-1). After time t106, the effect of the coupling current becomes smaller, so the voltage drops at a faster rate and converges to the verify voltage AV around time t107.

[0277] From time t103 onward, the voltage at the near end (Near) of the unwritten adjacent word line WL(k-1), the written non-adjacent signal line CG(k+2), and the unwritten non-adjacent signal line CG(k-2) rises at approximately the same rate (slope). Therefore, the unwritten non-adjacent word line WL(k-2), which has a lower applied voltage, reaches voltage VPVD first. Subsequently, the unwritten adjacent word line WL(k-1) reaches voltage VREADE. The far end (Far) of the unwritten adjacent word line WL(k-1), the written non-adjacent signal line CG(k+2), and the unwritten non-adjacent signal line CG(k-2) rises with a delay compared to the near end (Near). In particular, the voltage at the far end (Far) of the unwritten adjacent word line WL(k-1) is affected by the coupling current due to capacitive interference with the selected word line WLk, causing the voltage rise to be gradual and reaching the voltage VREADE before time t106.

[0278] The verification operation using the verify voltages AV and BV from time t107 onwards, and the operation between program loops, are the same as the operation from time t97 onwards in the sixth embodiment.

[0279] 9.2 Effects The semiconductor memory device 3 according to the ninth embodiment, like the eighth embodiment, can shorten the processing time required for writing data to the memory cell, improve operational efficiency, and suppress a decrease in the reliability of the semiconductor memory device 3.

[0280] Furthermore, in the semiconductor memory device 3 according to the ninth embodiment, during the verify operation, while the voltage of the selected word line WLk is being increased, the voltage VSS is applied. Therefore, the voltage at the near end of the selected word line WLk starts to decrease before reaching the voltage VREADK. Therefore, when the voltage VSS is applied to the selected word line WLk to decrease the voltage, the falling width of the voltage can be reduced. For this reason, the time required for the voltage to drop can also be shortened accordingly. Therefore, since the time when the voltage at the far end of the selected word line WLk reaches the verify voltage (for example, the verify voltage AV) is advanced, verification can be started earlier, and thus the time required for the entire write operation can be shortened.

[0281] Also, in the semiconductor memory device 3 according to the ninth embodiment, since the period T is measured using self-timer control and the timing for applying the voltage VSS to the selected word line WLk is determined, there is no need to separately manage the voltage using a dedicated power supply. Therefore, an increase in the circuit area can be suppressed.

[0282] 10. Tenth Embodiment Next, a semiconductor memory device according to the tenth embodiment will be described. The semiconductor memory device 3 according to the tenth embodiment performs an operation different from that of the semiconductor memory device 3 according to the eighth embodiment in the write operation. In the following description, the description of the configuration and operation equivalent to those of the eighth embodiment will be omitted, and mainly the operation different from that of the eighth embodiment will be described.

[0283] 10.1 Circuit Configuration of Driver Module FIG. 24 is a circuit diagram showing an example of the circuit configuration of a driver module included in the semiconductor memory device according to the tenth embodiment.

[0284] As shown in Figure 24, in the driver module 15 of the semiconductor memory device 3 according to the tenth embodiment, the voltage regulator circuit 61 further generates a voltage VOPT. The voltage VOPT is higher than the highest threshold distribution (the maximum threshold at the "G" level) and lower than the voltage VREAD. It is desirable that the voltage VOPT be as low as possible while satisfying the conditions. For example, the voltage regulator circuit 61 outputs the voltage VOPT from the same output terminal as the voltage VCGSEL.

[0285] 10.2 Writing Operation Figure 25 is a timing chart showing an example of a write operation in a semiconductor memory device according to the 10th embodiment. Figure 25 shows the write operation in a program loop where the "A" level and "B" level are set as the verification targets in the verification operation. Note that for the voltage of each word line WL, the voltage at the near end is shown with a solid line, and the voltage at the far end is shown with a dashed line.

[0286] As shown in Figure 25, at the start of the program loop, the voltages of the selected word line WLk, the already written adjacent word line WL(k+1), the unwritten adjacent word line WL(k-1), the already written non-adjacent signal line CG(k+2), and the unwritten non-adjacent signal line CG(k-2) are, for example, the voltage VSS.

[0287] The program operation during the period from time t110 to t113 is the same as the operation during the period from t90 to t93 in the eighth embodiment.

[0288] At time t113, the voltage VOPT is applied to the selected signal line CGk. The voltage VREADK is applied to the already written adjacent signal line CG(k+1). The voltage VREADE is applied to the unwritten adjacent signal line CG(k-1). The voltage VREAD is applied to the already written non-adjacent signal line CG(k+2). The voltage VPVD is applied to the unwritten non-adjacent signal line CG(k-2).

[0289] Voltage regulator circuit 63, which generates VOPT applied to the selection signal line CGk and the voltage VREADK applied to the already written adjacent signal line CG(k+1), is connected to charge pump circuit 53. On the other hand, voltage regulator circuit 62, which generates the voltage VREADE applied to the unwritten adjacent signal line CG(k-1), the voltage VREAD applied to the already written non-adjacent signal line CG(k+2), and the voltage VREAD for the unwritten non-adjacent signal line CG(k-2), is connected to charge pump circuit 52. Charge pump circuit 53 supplies current to only two signal lines, the selection signal line CGk and the already written adjacent signal line CG(k+1), whereas charge pump circuit 52 supplies current to numerous signal lines. Therefore, the current supplied to each of the selected signal line CGk and the already written adjacent signal line CG(k+1) may be greater than the current supplied to each of the unwritten adjacent signal line CG(k-1), the already written non-adjacent signal line CG(k+2), and the unwritten non-adjacent signal line CG(k-2). In other words, the charge pump circuit 53 has a higher current supply capacity per signal line CG than the charge pump circuit 52. As a result, the voltage rise rate and slope are higher for the selected word line WLk and the already written adjacent word line WL(k+1) than for the unwritten adjacent word line WL(k-1), the already written non-adjacent word line WL(k+2), and the unwritten non-adjacent word line WL(k-2). Therefore, for example, the voltage at the near end of the selected word line WLk reaches voltage VOPT by time t114. The voltage at the near end of the previously written adjacent word line WL(k+1) reaches voltage VREADK at time t114. The voltage at the far end of the selected word line WLk converges near voltage VOPT. The voltage at the far end of the previously written adjacent word line WL(k+1) is delayed compared to the near end and rises slowly due to the coupling current caused by capacitive interference with the selected word line WLk.

[0290] Subsequently, at time t115, a voltage VSS is applied to the selected word line WLk.

[0291] From time t115 onward, the voltage at the far end (Far) of the already written adjacent word line WL(k+1) is affected by the coupling current due to capacitive interference with the selected word line WLk, causing the voltage rise to slow down until it reaches the voltage VREADK at time t116.

[0292] For example, the voltage at the near end (Near) of the selected word line WLk drops sharply and reaches voltage VSS. The voltage at the far end (Far) of the selected word line WLk drops slowly during the period t115-t116 due to the coupling current caused by capacitive interference with the already written adjacent word line WL(k+1). After time t116, the effect of the coupling current becomes smaller, so the voltage drops at a faster rate and converges to the verify voltage AV around time t117.

[0293] From time t113 onward, the voltages of the unwritten adjacent word line WL(k-1), the written non-adjacent signal line CG(k+2), and the unwritten non-adjacent signal line CG(k-2) rise at approximately the same rate (slope). Therefore, the unwritten non-adjacent word line WL(k-2), which has a lower applied voltage, reaches voltage VPVD first. Subsequently, the unwritten adjacent word line WL(k-1) reaches voltage VREADE. The far end (Far) of the unwritten adjacent word line WL(k-1), the written non-adjacent signal line CG(k+2), and the unwritten non-adjacent signal line CG(k-2) rise with a delay compared to the near end (Near).

[0294] The verification operation using the verify voltages AV and BV from time t117 onwards, and the operation between program loops, are the same as the operation from time t97 onwards in the eighth embodiment.

[0295] 10.3 Effects The semiconductor memory device 3 according to the tenth embodiment, like the eighth embodiment, can shorten the processing time required for writing data to the memory cell, improve operational efficiency, and suppress a decrease in the reliability of the semiconductor memory device 3.

[0296] Furthermore, in the semiconductor memory device 3 according to the 10th embodiment, during the verify operation, the voltage of the selected word line WLk is only raised to voltage VOPT. Voltage VOPT is a voltage large enough to remove residual electrons in the channel in the memory pillar MP, and has the same effect as raising the voltage of the selected word line WLk to voltage VREAD or voltage VREADK. Also, when voltage VSS is applied to the selected word line WLk to lower the voltage, the amount of voltage drop (VOPT-VSS) can be reduced. Therefore, the time required for the voltage to drop can also be shortened accordingly. Consequently, the time at which the voltage at the far end (Far) of the selected word line WLk reaches the verify voltage (e.g., verify voltage AV) is shortened, so verification can be started earlier, and consequently the time required for the entire write operation can be shortened.

[0297] Furthermore, in the semiconductor memory device 3 according to the tenth embodiment, the voltage VOPT is controlled by the voltage regulator circuit 63, resulting in less voltage variability and easier voltage control. Therefore, the margin required to accommodate voltage variability can be reduced, and the lowest possible voltage VOPT can be generated while satisfying the conditions. Consequently, the voltage drop can be reduced, shortening the overall time required for the write operation.

[0298] 11. Others In the embodiment described above, the case in which memory cell transistors MT on the bit line BL side are selected sequentially as the writing target during the writing operation was explained. However, the memory cell transistors MT on the source line SL side may also be selected sequentially as the writing target. In this case, word line WL(k-1) becomes an already written adjacent word line, and word line WL(k+1) becomes an unwritten adjacent word line. Similarly, word line WL(ki) becomes an already written non-adjacent word line, and word line WL(k+i) becomes an unwritten non-adjacent word line (i is an integer of 2 or more).

[0299] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0300] 1…Memory system 2…Memory controller 3…Semiconductor memory 10…Memory cell array 11…Input / Output Circuits 12…Logic control circuits 13…Register 14… Sequencer 15…Driver module 16… Raw Decoder Module 17…Sense Amp Module 21, 22, 23, 24, 25...wiring layer 30…Core film 31… Semiconductor film 32… Multilayer film 33...Tunnel insulating film 34...Charge storage film 35…Block Insulating Film 40, 41, 42, 43, 44, 45, 46… Insulating layer 51, 52, 53... Charge pump circuit 61, 62, 63…Voltage regulator circuits 70-0~70-7…CG Selection Driver BD… Block Decoder BL...bit line BLK...block CC, CCV, LI... Contact CG, SGDD, SGSD...Signal line CU... Cell Unit HA…Drawer area MA...Memory area MP...Memory Pillar MT...Memory cell transistor NS...NAND string SGD, SGS... Selectable gate lines SHE, SLT... components SL…Source Line SP...Spacer ST1, ST2…Selection transistor SU... String Unit TG...Transfer Gate Line TR1~TR14, TRs... Transistors WL...Word line

Claims

1. A first wiring layer, a second wiring layer, and a plurality of third wiring layers are arranged in this order, spaced apart from each other in the first direction. A memory pillar extending in the first direction, with a portion intersecting the first wiring layer functioning as a first memory cell, A control circuit that controls the read operation of the data stored in the first memory cell, Equipped with, The control circuit, during the read operation, A first operation in which the voltage of the plurality of third wiring layers is changed from a first voltage to a second voltage higher than the first voltage with a first slope, A second operation in which the voltage of the second wiring layer is changed from the first voltage to a third voltage higher than the second voltage with a second slope greater than the first slope, A third operation which changes the voltage of the first wiring layer to a fourth voltage corresponding to the read level of the first memory cell, Execute Semiconductor memory device.

2. The system further comprises a fourth wiring layer and a plurality of fifth wiring layers, which are arranged in the order and spaced apart from each other in the first direction, on the opposite side of the second wiring layer from the first wiring layer, The first operation includes changing the voltage of the plurality of fifth wiring layers from the first voltage to the second voltage with a first slope, The second operation includes changing the voltage of the fourth wiring layer from the first voltage to the third voltage with the second slope, The semiconductor memory device according to claim 1.

3. The control circuit executes the first operation and the second operation simultaneously during the read operation. The semiconductor memory device according to claim 2.

4. The control circuit, during the read operation, A fourth operation, which changes the voltage of the first wiring layer from a first voltage to a second voltage with a first slope, is performed simultaneously with the first operation. The third operation is performed after the voltages of the first wiring layer and the plurality of third wiring layers reach the second voltage, and the voltage of the second wiring layer reaches the third voltage. The semiconductor memory device according to claim 1.

5. The control circuit, during the read operation, A fifth operation, which changes the voltage of the first wiring layer from the first voltage to the third voltage with the second slope, is performed simultaneously with the second operation. The third operation is performed after the voltages of the plurality of third wiring layers reach the second voltage and the voltages of the first and second wiring layers reach the third voltage. The semiconductor memory device according to claim 1.

6. The second operation is an operation that sequentially performs: a first part that changes the voltage of the second wiring layer from the first voltage to a fifth voltage lower than the third voltage with the second slope; a second part that maintains the voltage of the second wiring layer at the fifth voltage; and a third part that changes the voltage of the second wiring layer from the fifth voltage to the third voltage with the second slope. The fifth operation is an operation that sequentially performs: a fourth part which changes the voltage of the first wiring layer from the first voltage to the fifth voltage with the second slope; a fifth part which maintains the voltage of the first wiring layer at the fifth voltage; and a sixth part which changes the voltage of the first wiring layer from the fifth voltage to the third voltage with the second slope. The third portion of the second operation and the sixth portion of the fifth operation are performed in the first operation after the voltage of the plurality of third wiring layers reaches the fifth voltage. The semiconductor memory device according to claim 5.

7. The second operation is an operation that sequentially performs: a first part that changes the voltage of the second wiring layer from the first voltage to a fifth voltage lower than the third voltage with the second slope; a second part that maintains the voltage of the second wiring layer at the fifth voltage; and a third part that changes the voltage of the second wiring layer from the fifth voltage to the third voltage with the second slope. The third portion of the second operation is performed after the voltages of the plurality of third wiring layers reach the fifth voltage in the first operation. The control circuit, during the read operation, A sixth operation is performed simultaneously with the second operation, in which the voltage of the first wiring layer is changed from the first voltage to the fifth voltage with the second slope. The third operation is performed after a predetermined time has elapsed since the sixth operation was performed. The semiconductor memory device according to claim 1.

8. The second operation is an operation that sequentially performs: a first part that changes the voltage of the second wiring layer from the first voltage to a fifth voltage lower than the third voltage with the second slope; a second part that maintains the voltage of the second wiring layer at the fifth voltage; and a third part that changes the voltage of the second wiring layer from the fifth voltage to the third voltage with the second slope. The third portion of the first operation is performed after the voltages of the plurality of third wiring layers have reached the fifth voltage. The control circuit, during the read operation, A seventh operation is performed simultaneously with the second operation, which changes the voltage of the first wiring layer from the first voltage to a sixth voltage lower than the fifth voltage with the second slope. The third operation is performed after the voltages of the plurality of third wiring layers reach the second voltage, the voltage of the second wiring layer reaches the third voltage, and the voltage of the first wiring layer reaches the sixth voltage. The semiconductor memory device according to claim 1.

9. The system further comprises a fourth wiring layer and a plurality of fifth wiring layers, which are arranged in the order and spaced apart from each other in the first direction, on the opposite side of the second wiring layer from the first wiring layer, The memory pillar functions as a second memory cell, a plurality of third memory cells, a fourth memory cell, and a plurality of fifth memory cells at the points where it intersects with the second wiring layer, the plurality of third wiring layers, the fourth wiring layer, and the plurality of fifth wiring layers, respectively. When reading data stored in the first memory cell, the second memory cell and each of the plurality of third memory cells are in a state of storing data, while the fourth memory cell and each of the plurality of fifth memory cells are in a state of not storing data. The semiconductor memory device according to claim 1.

10. The control circuit, during the readout operation, further performs an eighth operation simultaneously with the second operation, which changes the voltage of the fourth wiring layer from the first voltage to a seventh voltage lower than the second voltage with the first slope. The semiconductor memory device according to claim 9.

11. The control circuit, during the readout operation, further performs a ninth operation simultaneously with the second and eighth operations, which changes the voltage of the fourth wiring layer from the first voltage to an eighth voltage lower than the seventh voltage with the first slope. The semiconductor memory device according to claim 10.

12. The control circuit, during the read operation, A fourth operation is performed simultaneously with the first operation, in which the voltage of the first wiring layer is changed from the first voltage to the second voltage with a first slope. The third operation is performed after the voltages of the first wiring layer and the plurality of third wiring layers reach the second voltage, and the voltage of the second wiring layer reaches the third voltage. The semiconductor memory device according to claim 10 or claim 11.

13. The control circuit, during the read operation, A fifth operation is performed simultaneously with the second operation, in which the voltage of the first wiring layer is changed from the first voltage to the third voltage with the second slope. The third operation is performed after the voltages of the first and second wiring layers reach the third voltage. The semiconductor memory device according to claim 11.

14. The control circuit, during the read operation, A tenth operation, which increases the voltage of the first wiring layer by the second slope, is performed simultaneously with the second operation. The third operation is performed after a predetermined time has elapsed since the ninth operation was performed. The semiconductor memory device according to claim 11.

15. The control circuit, during the read operation, A seventh operation is performed simultaneously with the second operation, which changes the voltage of the first wiring layer from the first voltage to a sixth voltage lower than the second voltage with the second slope. The third operation is performed after the voltage of the second wiring layer reaches the third voltage and the voltage of the first wiring layer reaches the sixth voltage. The semiconductor memory device according to claim 11.

16. The control circuit, during the read operation, An eleventh operation is performed by applying a ninth voltage to the first wiring layer to increase the threshold voltage of the first memory cell, Following the 11th operation, a 12th operation is performed to lower the voltage of the first wiring layer to the first voltage, Further execution, After the 12th operation, the first and second operations are performed. The semiconductor memory device according to claim 1.

17. The control circuit, during the read operation, The third operation is performed simultaneously with the first and second operations. The semiconductor memory device according to claim 16.

18. A first charge pump supplies a current that changes the voltage of the plurality of third wiring layers from the first voltage to the second voltage with the first slope, A second charge pump supplies a current that changes the voltage of the second wiring layer from the first voltage to the third voltage with the second slope, The semiconductor memory device according to claim 1, further comprising the above.

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