Semiconductor memory

Abstract

To provide a semiconductor memory device that is easy to manufacture and capable of high-density recording. [Solution] The memory cell array 110, which is a semiconductor memory device, comprises a first laminated film 41 in which a plurality of first conductive layers 36 and a plurality of first insulating layers 57 are alternately stacked one layer at a time in the Z direction and stretched in the X and Y directions, and a second laminated film 42 in which a plurality of second conductive layers 37 and a plurality of second insulating layers 59 are alternately stacked one layer at a time in the Z direction and stretched in the X and Y directions. Furthermore, the array comprises, in this order, a first core insulating film 90 containing oxide, a second core insulating film 96 containing nitride, a third core insulating film 97 containing oxide, a first channel semiconductor film 91, a first tunnel insulating film 92, a first charge storage film 93, and a first block insulating film, each penetrating the first laminated film in the Z direction, and a fourth core insulating film 80 containing oxide, a second channel semiconductor film 81, a second tunnel insulating film 82, a second charge storage film 83, and a second block insulating film 84, each penetrating the second laminated film in the Z direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device.

Background Art

[0002] Large-capacity non-volatile memories are being developed. Such large-capacity non-volatile memories enable low-voltage and low-current operation, high-speed switching, and miniaturization and high integration of memory cells.

[0003] In a memory cell array included in a large-capacity non-volatile memory, a large number of metal wirings called bit lines and word lines are arranged. A voltage is applied to the bit line and the word line connected to the cell, and data is written into the memory cell corresponding to the bit line and the word line. A semiconductor memory device in which memory cells are three-dimensionally arranged and having a stacked film in which a conductive layer and an insulating layer serving as such word lines are alternately stacked has been proposed.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] An object of the embodiment is to provide a semiconductor memory device that is easy to manufacture and enables high-density recording.

Means for Solving the Problems

[0006] The semiconductor memory device of the embodiment comprises a first laminated film in which a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked one by one in a first direction, and which extends in a second direction intersecting the first direction and a third direction intersecting the first and second directions; a first core insulating film containing oxide that penetrates the first laminated film in a first direction; a second core insulating film containing nitride that is provided around the first core insulating film and penetrates the first laminated film in a first direction; a third core insulating film containing oxide that is provided around the second core insulating film and penetrates the first laminated film in a first direction; a first channel semiconductor film provided around the third core insulating film and penetrates the first laminated film in a first direction; and a first laminated film that is provided around the first channel semiconductor film. The film comprises a first tunnel insulating film penetrating in a first direction, a first charge storage film provided around the first tunnel insulating film and penetrating the first laminated film in a first direction, a second laminated film in which a plurality of second conductive layers and a plurality of second insulating layers are alternately stacked one by one in the first direction and stretched in the second and third directions, a fourth core insulating film containing oxide penetrating the second laminated film in a first direction, a second channel semiconductor film provided around the fourth core insulating film and penetrating the first laminated film in a first direction, a second tunnel insulating film provided around the second channel semiconductor film and penetrating the second laminated film in a first direction, and a second charge storage film provided around the second tunnel insulating film and penetrating the second laminated film in a first direction. [Brief explanation of the drawing]

[0007] [Figure 1] This is a block diagram of a semiconductor memory device according to the first embodiment. [Figure 2] This is an equivalent circuit diagram of the semiconductor memory device according to the first embodiment. [Figure 3] This is a schematic cross-sectional view of the main part of the semiconductor memory device according to the first embodiment. [Figure 4] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 5] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 6] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 7]This is a schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 8] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 10] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 11] This is a schematic cross-sectional view of the main part of the semiconductor memory device according to the second embodiment.

[0008] The embodiments will be described below with reference to the drawings. In the drawings, identical or similar parts are denoted by the same or similar reference numerals.

[0009] In this specification, the upper direction in a drawing is referred to as "up" and the lower direction in a drawing as "down" to indicate the positional relationship of parts, etc. In this specification, the concepts of "up" and "down" do not necessarily refer to a relationship with the direction of gravity.

[0010] (First Embodiment) The semiconductor memory device of the embodiment comprises a first laminated film in which a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked one by one in a first direction, and which extends in a second direction intersecting the first direction and a third direction intersecting the first and second directions; a first core insulating film containing oxide that penetrates the first laminated film in a first direction; a second core insulating film containing nitride that is provided around the first core insulating film and penetrates the first laminated film in a first direction; a third core insulating film containing oxide that is provided around the second core insulating film and penetrates the first laminated film in a first direction; a first channel semiconductor film provided around the third core insulating film and penetrates the first laminated film in a first direction; and a first laminated film that is provided around the first channel semiconductor film. The film comprises a first tunnel insulating film penetrating in a first direction, a first charge storage film provided around the first tunnel insulating film and penetrating the first laminated film in a first direction, a second laminated film in which a plurality of second conductive layers and a plurality of second insulating layers are alternately stacked one by one in the first direction and stretched in the second and third directions, a fourth core insulating film containing oxide penetrating the second laminated film in a first direction, a second channel semiconductor film provided around the fourth core insulating film and penetrating the first laminated film in a first direction, a second tunnel insulating film provided around the second channel semiconductor film and penetrating the second laminated film in a first direction, and a second charge storage film provided around the second tunnel insulating film and penetrating the second laminated film in a first direction.

[0011] The overall configuration of the semiconductor memory device 100 will now be described. The semiconductor memory device 100 according to this embodiment is, for example, a NAND flash memory capable of storing data non-volatilely. Figure 1 is a block diagram of the semiconductor memory device 100 according to this embodiment.

[0012] The semiconductor memory device 100 includes a memory cell array 110, a row decoder 101, a column decoder 108, a sense amplifier 109, an input / output circuit 104, a command register 105, an address register 106, and a sequencer (control circuit) 107, among others.

[0013] The memory cell array 110 includes j blocks BLK0 to BLK(j - 1). j is an integer greater than or equal to 1. Each of the plurality of blocks BLK includes a plurality of memory cell transistors. The memory cell transistors include electrically rewritable memory cells. The memory cell array 110 includes a plurality of bit lines, a plurality of word lines, a source line, etc. for controlling the voltage applied to the memory cell transistors. The specific configuration of the block BLK will be described later.

[0014] The row decoder 101 receives a row address from the address register 106 and decodes this row address. The row decoder 101 performs a selection operation such as a word line based on the decoded row address. Then, the row decoder 101 transfers a plurality of voltages necessary for a write operation, a read operation, and an erase operation to the memory cell array 110.

[0015] The column decoder 108 receives a column address from the address register 106 and decodes this column address. The column decoder 108 performs a selection operation of a bit line based on the decoded column address.

[0016] The sense amplifier 109 detects and amplifies the data read from the memory cell transistor to the bit line during a read operation. Also, the sense amplifier 109 transfers the write data to the bit line during a write operation.

[0017] The input / output circuit 104 is connected to an external device (host device) via a plurality of input / output lines (DQ lines). The input / output circuit 104 receives a command CMD and an address ADD from the external device. The command CMD received by the input / output circuit 104 is sent to the command register 105. The address ADD received by the input / output circuit 104 is sent to the address register 106. Also, the input / output circuit 104 performs transmission and reception of data DAT with the external device.

[0018] Sequencer 107 receives a control signal CNT from an external device. The control signal CNT includes a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, and the like. The "n" appended to the signal name indicates active-low. The sequencer 107 controls the operation of the entire semiconductor memory device 100 based on the command CMD held in the command register 105 and the control signal CNT.

[0019] Next, the electrical configuration of the memory cell array 110 will be described.

[0020] FIG. 2 is a diagram showing an equivalent circuit of a part of the memory cell array 110. FIG. 2 shows one block BLK included in the memory cell array 10 extracted. The block BLK includes a plurality (for example, four) of string units SU0 to SU3.

[0021] Each of the string units SU0 to SU3 is an aggregate of a plurality of NAND strings NS. One end of each NAND string NS is connected to any one of bit lines BL0 to BLm (m is an integer of 1 or more). The other end of the NAND string NS is connected to a source line SL. Each NAND string NS includes a plurality of memory cell transistors MT0 to MTn (n is an integer of 1 or more), a first selection transistor S1, and a second selection transistor S2.

[0022] The plurality of memory cell transistors MT0 to MTn are electrically connected in series to each other. The memory cell transistor MT includes a control gate and a memory film (for example, a charge storage film), and stores data non-volatilely. The memory cell transistor MT changes the state of the memory film according to the voltage applied to the control gate. For example, charges are stored in the charge storage film. The control gate of the memory cell transistor MT is connected to any one of the corresponding word lines WL0 to WLn. The memory cell transistor MT is electrically connected to the row decoder 11 via the word line WL.

[0023] In each NAND string NS, the first selection transistor S1 is connected between a plurality of memory cell transistors MT0 to MTn and one of the bit lines BL0 to BLm. The drain of the first selection transistor S1 is connected to one of the bit lines BL0 to BLm. The source of the first selection transistor S1 is connected to the memory cell transistor MTn. The control gate of the first selection transistor S1 in each NAND string NS is connected to one of the first selection gate lines SGD0 to SGD3. The first selection transistor S1 is electrically connected to the row decoder 11 via the first selection gate line SGD. The first selection transistor S1 connects the NAND string NS and the bit line BL when a predetermined voltage is applied to one of the first selection gate lines SGD0 to SGD3.

[0024] In each NAND string NS, the second selection transistor S2 is connected between the multiple memory cell transistors MT0 to MTn and the source line SL. The drain of the second selection transistor S2 is connected to the memory cell transistor MT0. The source of the second selection transistor S2 is connected to the source line SL. The control gate of the second selection transistor S2 is connected to the second selection gate line SGS. The second selection transistor S2 is electrically connected to the row decoder 11 via the second selection gate line SGS. The second selection transistor S2 connects the NAND string NS and the source line SL when a predetermined voltage is applied to the second selection gate line SGS.

[0025] The memory cell array 110 may have other circuit configurations besides those described above. For example, the number of string units SU included in each block BLK, the number of memory cell transistors MT included in each NAND string NS, and the number of selection transistors STD and STS may be changed. Also, block BLK may include a first subblock containing memory cell transistors MT0 to MTk, and a second subblock containing multiple memory cell transistors MTk+1 to MTn. The erase operation may be performed on a block BLK basis, or it may be divided and performed between the first subblock and the second subblock. Also, the NAND string NS may include one or more dummy transistors that are not used to store valid data.

[0026] Next, the structure of the memory cell array 110 will be described using Figure 3. Figure 3 is an example of the cross-sectional structure of the memory cell array 110 of the semiconductor memory device 1 according to this embodiment.

[0027] In the drawings referenced below, the X direction (an example of the first direction) corresponds to the extension direction of the bit line BL, and the Y direction (an example of the second direction) corresponds to the extension direction of the word line WL. The Z direction (an example of the third direction) corresponds to the direction from the insulating layer 54 of the semiconductor memory device 1 toward the bit line BL. In the following explanation, the surface and end of a component on the insulating layer 54 side will be referred to as the first surface and first end, respectively. The surface and end of a component on the bit line BL side will be referred to as the second surface and second end, respectively.

[0028] The memory cell array 110 includes conductive layers 30A, 31, 33, 34, and 35, a plurality of first conductive layers 36, a plurality of second conductive layers 37, insulating layers 50, 53, and 58, a plurality of first insulating layers 57, a plurality of second insulating layers 59, and a plurality of memory pillars MP. Figure 3 shows four of the memory pillars MP. Figure 3 also shows a case where the plurality of first conductive layers 36 and plurality of second conductive layers 37 include four first conductive layers 36 and four second conductive layers 37. Furthermore, Figure 3 shows a case where the plurality of first insulating layers 57 and plurality of second insulating layers 59 include four first insulating layers 57 and four second insulating layers 59.

[0029] The conductive layer 30A is formed, for example, in the shape of a plate extending along the XY plane. The conductive layer 30A is used as the source wire SL. The conductive layer 30A is composed of a conductive material. The conductive material is, for example, an N-type semiconductor with impurities added, or a metallic material.

[0030] An insulating layer 50 is provided on the second surface of the conductive layer 30A. A conductive layer 31 is provided on the second surface of the insulating layer 50. The conductive layer 31 has a plate-like shape that is stretched in the X and Y directions and extends along the XY plane. The conductive layer 31 is used as a second selected gate line SGS. The conductive layer 31 includes, for example, tungsten and a barrier metal film around the tungsten.

[0031] On the second surface of the conductive layer 31, the first insulating layer 57 and the first conductive layer 36 are laminated alternately in the Z direction, one layer at a time, in the order of first insulating layer 57, first conductive layer 36, ..., first insulating layer 57, first conductive layer 36. The first conductive layer 36 and the first insulating layer 57 are, for example, stretched in the X and Y directions and have a plate-like shape that spreads along the XY plane. The four layers of the first conductive layer 36 are used as word lines WL0 to WL3, respectively, in order from the conductive layer 31 side along the Z direction. The first conductive layer 36 includes, for example, tungsten and a barrier metal film around the tungsten.

[0032] The insulating layer 58, for example, is stretched in the X and Y directions and has a plate-like shape that extends along the XY plane.

[0033] An insulating layer 58 is laminated on the second surface of the first conductive layer 36, which is used as word line WL3. On the second surface of the insulating layer 58, the second conductive layer 37 and the second insulating layer 59 are laminated alternately one layer at a time in the Z direction, in the order of second conductive layer 37, second insulating layer 59, ..., second conductive layer 37, second insulating layer 59. The second conductive layer 37 and the second insulating layer 59 have a plate-like shape that is stretched in the X and Y directions and spread along the XY plane. The four layers of the second conductive layer 37 are used as word lines WL4 to WL7, respectively, in order from the conductive layer 31 side along the Z direction. The second conductive layer 37 includes, for example, tungsten and a barrier metal film around the tungsten.

[0034] The first laminated film 41 has a plurality of first conductive layers 36 and a plurality of first insulating layers 57.

[0035] The second laminated film 42 has a plurality of second conductive layers 37 and a plurality of second insulating layers 59.

[0036] A conductive layer 33 is laminated on the second surface of the second conductive layer 37, which is used as the word line WL7, via a second insulating layer 59. The conductive layer 33 is formed in a plate shape that extends along the XY plane, for example, by being stretched in the X and Y directions. The conductive layer 33 is used as the first selected gate line SGD. The conductive layer 33 includes, for example, tungsten and a barrier metal film around the tungsten. The conductive layer 33 is electrically insulated for each string unit SU by, for example, multiple members SHE.

[0037] An insulating layer 53 is laminated on the second surface of the conductive layer 33. A conductive layer 34 is laminated on the second surface of the insulating layer 53. The conductive layer 34 is provided extending along the X direction. The conductive layer 34 functions as a bit line BL.

[0038] The laminated structure, which includes conductive layers 30A, 31, 33, and 34, a first conductive layer 36, a second conductive layer 37, insulating layers 50, 53, and 58, a first insulating layer 57, and a second insulating layer 59, is provided so as to be surrounded by insulating layers. Figure 3 shows the insulating layer 54 in contact with the first surface of the conductive layer 30A, and the insulating layer 55 in contact with the second surface of the conductive layer 34.

[0039] Multiple memory pillars MP are provided, extending along the Z direction. The multiple memory pillars MP penetrate the conductive layer 31, the first conductive layer 36, the second conductive layer 37, the conductive layer 33, the insulating layer 50, the first insulating layer 57, the insulating layer 58, and the second insulating layer 59. Each of the multiple memory pillars MP functions as a single NAND string NS.

[0040] Each memory pillar MP comprises a lower memory pillar LMP, an upper memory pillar UMP, and a joint JT provided between the lower memory pillar LMP and the upper memory pillar UMP to join (connect) the lower memory pillar LMP and the upper memory pillar UMP.

[0041] The lower memory pillar LMP has a portion whose diameter or cross-sectional area increases toward the insulating layer 55 from the insulating layer 54, or toward the Z direction. The upper memory pillar UMP has a portion whose diameter or cross-sectional area increases toward the insulating layer 55 from the insulating layer 54, or toward the Z direction.

[0042] Each of the lower memory pillars (LMPs) includes a first core insulating film 90, a second core insulating film 96, a third core insulating film 97, a first channel semiconductor film 91, a first tunnel insulating film 92, a first charge storage film 93, and a first block insulating film 94.

[0043] The first core insulating film 90 penetrates the first laminated film 41 in the Z direction. The first core insulating film 90 contains an oxide, where the oxide is, for example, a compound containing silicon and oxygen.

[0044] The second core insulating film 96 is provided around the first core insulating film 90. The second core insulating film 96 penetrates the first laminated film 41 in the Z direction. The second core insulating film 96 contains a nitride, where the nitride is, for example, a compound containing silicon and nitrogen.

[0045] The third core insulating film 97 is provided around the second core insulating film 96. The third core insulating film 97 penetrates the first laminated film 41 in the Z direction. The third core insulating film 97 contains an oxide, where the oxide is, for example, a compound containing silicon and oxygen.

[0046] The first channel semiconductor film 91 is provided around the third core insulating film 97. The first channel semiconductor film 91 penetrates the first stacked film 41 in the Z direction. The first channel semiconductor film 91 functions as a current path (channel) for the lower memory pillar LMP. The first channel semiconductor film 91 includes, for example, a semiconductor material such as polysilicon.

[0047] The first tunnel insulating film 92 is provided around the first channel semiconductor film 91. The first tunnel insulating film 92 is an insulating film that conducts current when a predetermined voltage is applied. The first tunnel insulating film 92 includes, for example, an oxide. Here, the oxide is, for example, a compound containing silicon and oxygen.

[0048] The first charge storage film 93 is provided around the first tunnel insulating film 92. The first charge storage film 93 is a film containing a material capable of storing charge. The first charge storage film 93 contains, for example, a nitride. Here, the nitride is, for example, a compound containing silicon and nitrogen.

[0049] The first block insulating film 94 is provided around the first charge storage film 93. The first block insulating film 94 is a film that suppresses the flow of charge between the first charge storage film 93 and the plurality of first conductive layers 36. The first block insulating film 94 includes, for example, an oxide. Here, the oxide is, for example, a compound of silicon and oxygen.

[0050] The portions where each lower memory pillar LMP intersects with the conductive layer 31 function as selection transistors ST2. The portions where each lower memory pillar LMP intersects with each first conductive layer 36 function as memory cell transistors MT.

[0051] Each of the upper memory pillars UMP includes a fourth core insulating film 80, a second channel semiconductor film 81, a second tunnel insulating film 82, a second charge storage film 83, and a second block insulating film 84.

[0052] The fourth core insulating film 80 penetrates the second laminated film 42 in the Z direction. The fourth core insulating film 80 contains an oxide, where the oxide is, for example, a compound of silicon and oxygen.

[0053] The second channel semiconductor film 81 is provided around the fourth core insulating film 80. The second channel semiconductor film 81 penetrates the second stacked film 42 in the Z direction. The second channel semiconductor film 81 functions as a current path (channel) for the upper memory pillar UMP. The second channel semiconductor film 81 includes, for example, a semiconductor material such as polysilicon.

[0054] The second tunnel insulating film 82 is provided around the second channel semiconductor film 81. The second tunnel insulating film 82 is an insulating film that conducts current when a predetermined voltage is applied. The second tunnel insulating film 82 contains, for example, an oxide. Here, the oxide is, for example, a compound of silicon and oxygen.

[0055] The second charge storage film 83 is provided around the second tunnel insulating film 82. The second charge storage film 83 is a film containing a material capable of storing charge. The second charge storage film 83 contains, for example, a nitride, where the nitride is, for example, a compound of silicon and nitrogen.

[0056] The second block insulating film 84 is provided around the second charge storage film 83. The second block insulating film 84 is a film that suppresses the flow of charge between the second charge storage film 83 and the plurality of second conductive layers 37. The second block insulating film 84 includes, for example, an oxide. Here, the oxide is, for example, a compound of silicon and oxygen.

[0057] The portions where each upper memory pillar UMP intersects with each second conductive layer 37 function as memory cell transistors MT. The portions where each upper memory pillar UMP intersects with the conductive layer 33 function as selection transistors ST1.

[0058] The conductive member 76 is provided on the fourth core insulating film 80 of the upper memory pillar UMP.

[0059] The joint JT is provided within the insulating layer 58 and has a conductive member 75. The conductive member 75 is electrically connected to the second channel semiconductor film 81. The conductive member 75 includes, for example, polysilicon.

[0060] The conductive layer 34 and the conductive member 75 are electrically connected by the conductive member 35. The conductive member 35 includes, for example, polysilicon.

[0061] The insulating layers 50, 51, 53, 58, 60, the multiple first insulating layers 57, and the multiple second insulating layers 59 contain, for example, an oxide. Here, the oxide contains an insulator such as a silicon-oxygen compound.

[0062] Furthermore, the lower memory pillar LMP may be positioned on the second surface side and the upper memory pillar UMP on the first surface side. In other words, the memory pillar MP having the second core insulating film 96 and the third core insulating film 97 may be positioned on the second surface side, and the memory pillar MP without the second core insulating film 96 and the third core insulating film 97 may be positioned on the first surface side.

[0063] Figures 4 to 10 are schematic cross-sectional views illustrating the method for manufacturing a semiconductor memory device according to this embodiment.

[0064] For example, using the Chemical Vapor Deposition (CVD) method, an insulating layer 50 containing oxide and a sacrificial layer 61 containing nitride are sequentially formed on the second surface side of the conductive layer 30A. Next, on the second surface side of the sacrificial layer 61, a plurality of first insulating layers 57 containing oxide and a plurality of sacrificial layers 66 containing nitride are alternately laminated one layer at a time. Next, an insulating layer 58 containing oxide is formed on the second surface side of the sacrificial layer 66.

[0065] Next, for example, using the RIE (Reactive Ion Etching) method, an opening H1 (through-hole) is formed that penetrates the insulating layer 50, the first insulating layer 57, the insulating layer 58, the sacrificial layer 61, and the sacrificial layer 66 in the Z direction, extends in the Z direction, and reaches the conductive layer 30A (Figure 4).

[0066] Next, a first block insulating film 94, a first charge storage film 93, and a first tunnel insulating film 92 are formed sequentially within the opening H1, for example by the ALD (Atomic Layer Deposition) method. Next, a hole is formed at the bottom of the opening H1, penetrating the first tunnel insulating film 92, the first charge storage film 93, and the first block insulating film 94, for example by the RIE method. Next, a first channel semiconductor film 91 is formed inside this hole and on the second surface side of the first tunnel insulating film 92, for example by the ALD method. Next, a third core insulating film 97, a second core insulating film 96, and a first core insulating film 90 are formed sequentially on the second surface side of the first channel semiconductor film 91, for example by the ALD method (Figure 5).

[0067] Next, using a photoresist (not shown) as a mask, a portion of the first block insulating film 94, first charge storage film 93, first tunnel insulating film 92, first channel semiconductor film 91, third core insulating film 97, second core insulating film 96, and first core insulating film 90 on the second surface side is removed, for example by RIE. Next, a conductive member 75 is formed in the portion where the first block insulating film 94, first charge storage film 93, first tunnel insulating film 92, first channel semiconductor film 91, third core insulating film 97, second core insulating film 96, and first core insulating film 90 were removed, for example by CVD. Next, a photoresist (not shown) is removed (Figure 6).

[0068] Next, an insulating layer is formed on the second surface side of the insulating layer 58 and the conductive member 75, for example by CVD, to increase the thickness of the insulating layer 58 in the Z direction and to place the conductive member 75 inside the insulating layer 58. Next, a plurality of sacrificial layers 67 containing nitrides and a plurality of second insulating layers 59 containing oxides are alternately laminated one layer at a time on the second surface side of the insulating layer 58. Next, a sacrificial layer 63 and an insulating layer 53 are sequentially formed on the second surface side of the sacrificial layer 67.

[0069] Next, for example, by the RIE method, an opening H2 (through-hole) is formed that penetrates the insulating layer 58, the multiple sacrificial layers 67, the second insulating layer 59, the sacrificial layer 63, and the insulating layer 53 in the Z direction, extends in the Z direction, and reaches the conductive member 75 (Figure 7).

[0070] Next, a second tunnel insulating film 82, a second charge storage film 83, a second block insulating film 84, and a protective film 89 are sequentially formed within the opening H2, for example, by the ALD method. Here, the protective film 89 contains, for example, amorphous silicon (Figure 8).

[0071] Next, for example, by the RIE method, an opening H3 (through-hole) is formed below the opening H2, penetrating the second tunnel insulating film 82, the second charge storage film 83, the second block insulating film 84, and the protective film 89, and reaching the conductive member 75. Next, the protective film 89 is removed, for example, by wet etching (Figure 9).

[0072] Next, a second channel semiconductor film 81 is formed in the opening H2, for example by the ALD method. Next, a fourth core insulating film 80 is formed in the opening H2, for example by the CVD method. Next, a conductive member 75 is formed on the fourth core insulating film 80, for example by the CVD method (Figure 10).

[0073] Next, the sacrificial layer 61 is replaced with the conductive layer 31, the sacrificial layer 66 with the first conductive layer 36, the sacrificial layer 67 with the second conductive layer 37, and the sacrificial layer 63 with the conductive layer 33. For example, the sacrificial layers 61, 66, 67, and 63 are removed by wet etching using phosphoric acid (H3PO4) through an opening (not shown). Next, the conductive layer 31, the first conductive layer 36, the second conductive layer 37, and the conductive layer 33, each having tungsten (W) and a barrier metal film around the tungsten, are formed, for example, by a CVD method.

[0074] Next, the insulating layer 53, member SHE, conductive member 35, conductive layer 34, and insulating layer 55 are formed as appropriate to obtain the semiconductor memory device 100 of this embodiment.

[0075] Next, the effects and benefits of the semiconductor memory device of this embodiment will be described.

[0076] The storage capacity of semiconductor memory devices is being increased by performing multi-level recording in memory cell transistors (MTs). To enable the storage of more information in a single memory cell transistor (MT), it is preferable to enable the storage of more electrons in the charge storage film of the memory cell transistor (MT), thereby enabling the setting of a higher threshold voltage (Vt).

[0077] For example, consider the TLC (Triple Level Cell) method, where the threshold voltage distribution of the memory cell transistor MT is divided into 8 levels, and the QLC (Quad Level Cell) method, where it is divided into 16 levels. In this case, the threshold voltage Vt at the "S15" level, which has the highest threshold voltage Vt in the QLC method, is higher than the threshold voltage Vt at the "G" level, which has the highest threshold voltage Vt in the TLC method. As a result, the QLC method allows for setting more threshold voltages Vt than the TLC method, thereby increasing the memory capacity of the semiconductor memory device.

[0078] However, when attempting to inject more electrons into the charge storage film, there was a problem that the injected electrons could not be stored in the charge storage film and would leak out. Furthermore, if the thickness of the charge storage film and tunnel insulating film were to be made different for each memory cell transistor MT by setting a threshold voltage Vt in order to suppress electron leakage from the charge storage film, it would be difficult to manufacture because setting the process conditions for the semiconductor memory device would be time-consuming.

[0079] Therefore, the semiconductor memory device of this embodiment comprises a first core insulating film that penetrates the first stacked film in a first direction and contains an oxide, a second core insulating film that is provided around the first core insulating film, penetrates the first stacked film in a first direction and contains a nitride, and a third core insulating film that is provided around the second core insulating film, penetrates the first stacked film in a first direction and contains an oxide.

[0080] During the erase operation, electrons that move from the charge storage film to the channel semiconductor film are trapped within the second core insulating film containing nitride. This allows, for example, in the QLC method, if the threshold voltage Vt is lower than the ground voltage only at the "S0" level, trapping electrons within the second core insulating film containing nitride makes it possible to achieve a threshold voltage distribution where the threshold voltage Vt is lower than the ground voltage not only at the "S0" level but also at the "S1" level. In other words, the neutral threshold voltage Vt can be moved from, for example, between the "S0" and "S1" levels to between the "S1" and "S2" levels. As a result, the amount of electrons injected into the charge storage film can be reduced at the "S15" level, where the threshold voltage is highest. This allows, for example, the threshold voltage Vt at the "S15" level in the QLC method to be brought closer to the threshold voltage Vt at the "G" level in the TLC method.

[0081] Consequently, within a semiconductor memory device having a charge storage layer manufactured under the same process conditions, a memory pillar without a second core insulating film and a third core insulating film can be used as a TLC-type memory cell transistor MT and memory cell (an example of a second memory cell capable of storing second data with fewer bits than the first data), while a memory pillar MP having a second core insulating film and a third core insulating film can be used as a QLC-type memory cell transistor MT and memory cell (an example of a first memory cell capable of storing first data).

[0082] This allows for setting a wide range of threshold voltages Vt, even when the amount of electrons stored in the electrostatic storage film is small.

[0083] The semiconductor memory device manufacturing method of this embodiment makes it possible to provide a semiconductor memory device that is easy to manufacture and capable of high-density recording.

[0084] (Second Embodiment) The semiconductor memory device of this embodiment differs from the semiconductor memory device of the first embodiment in that the first and second stacked films are arranged side by side in the second direction. Here, descriptions that overlap with those of the first embodiment are omitted.

[0085] Figure 11 is a schematic cross-sectional view of the semiconductor memory device of this embodiment. Memory pillars and laminates having a second core insulating film and a third core insulating film, and memory pillars and laminates without the second core insulating film and the third core insulating film, are arranged in the X direction. Alternatively, the memory pillars and laminates having the second core insulating film and the third core insulating film, and the memory pillars and laminates without the second core insulating film and the third core insulating film, may be arranged in the Y direction.

[0086] The semiconductor memory device manufacturing method of this embodiment also makes it possible to provide a semiconductor memory device that is easy to manufacture and capable of high-density recording.

[0087] While several embodiments and examples of the present invention have been described, these embodiments and examples are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0088] 1: Semiconductor memory 10: Memory cell array 11: Raw Decoder 30A: Conductive layer 31: Conductive layer 33: Conductive layer 34: Conductive layer 35: Conductive material 36: First conductive layer 37: Second conductive layer 41: First layer 42: Second layer film 50: Insulating layer 51: Insulating layer 53: Insulating layer 54: Insulating layer 55: Insulating layer 57: First insulating layer 58: Insulating layer 59: Second insulating layer 60: Insulating layer 61: Sacrificial Layer 63: Sacrificial Layer 66: Sacrificial layer 67: Sacrificial layer 75: Conductive material 76: Conductive material 80: Fourth core insulating film 81: Second channel semiconductor film 82: Second tunnel insulating film 83:Second charge storage film 84: Second block insulating film 89:Protective film 90: First core insulating film 91: First channel semiconductor film 92: First tunnel insulating film 93:First charge storage film 94: First block insulating film 96: Second core insulating film 97: Third core insulating film 100: Semiconductor memory 110: Memory cell array ADD: address ALE: Address latch enable signal BL: Bit line BL0: Bit line BLK: Block BLK0: Block CEn: Chip Enable Signal CLE: Command latch enable signal CMD: Command CNT: Control signal DAT: Data H1: Opening H2: Opening H3: Opening JT:Joint LMP: Lower memory pillar MP: Memory Pillar MT: Memory cell transistor NS: NAND string REn: Read-enabled signal S1: First selected transistor S2: Second Select Transistor SGD: First Selection Gate Line SGS: Second choice gate line SHE: Components SL: Source line ST: Select Transistor SU: String Unit UMP: Upper memory pillar Vt: Threshold voltage WEn: Write Enable Signal WL: Word line

Claims

1. A first laminated film is formed in which multiple first conductive layers and multiple first insulating layers are alternately stacked one by one in a first direction, and which extends in a second direction intersecting the first direction and in a third direction intersecting the first and second directions. The first laminated film penetrates in the first direction, and a first core insulating film containing an oxide is provided, A second core insulating film is provided around the first core insulating film, penetrates the first laminated film in the first direction, and contains a nitride. A third core insulating film containing an oxide is provided around the second core insulating film, penetrates the first laminated film in the first direction, and is located around the second core insulating film. A first channel semiconductor film is provided around the third core insulating film and penetrates the first laminated film in a first direction, A first tunnel insulating film is provided around the first channel semiconductor film and penetrates the first stacked film in a first direction, A first charge storage film is provided around the first tunnel insulating film and penetrates the first laminated film in a first direction, A second laminated film is formed by alternately stacking multiple second conductive layers and multiple second insulating layers one by one in the first direction, and extending in the second and third directions. A fourth core insulating film containing an oxide penetrates the second laminated film in the first direction, A second channel semiconductor film is provided around the fourth core insulating film and penetrates the first laminated film in the first direction, A second tunnel insulating film is provided around the second channel semiconductor film and penetrates the second laminated film in the first direction, A second charge storage film is provided around the second tunnel insulating film and penetrates the second laminate in the first direction, A semiconductor memory device equipped with the following features.

2. The first laminated film and the second laminated film are arranged side by side in the first direction, The first channel semiconductor film is electrically connected to the second channel semiconductor film. The semiconductor memory device according to claim 1.

3. The first laminated film and the second laminated film are arranged side by side in the second direction. The semiconductor memory device according to claim 1.

4. The portion of the first charge storage film provided between the first conductive layer and the first channel semiconductor film functions as a first memory cell capable of storing first data. The portion of the second charge storage film provided between the second conductive layer and the second channel semiconductor film functions as a second memory cell capable of storing second data having fewer bits than the first data. The semiconductor memory device according to claim 1.

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