Detection device

Abstract

To provide a detection device with high long-term reliability. [Solution] The detection device includes a photoelectric conversion element electrically connected to a first node, a first transistor including a first oxide semiconductor layer electrically connected between the first node and the second node, a second transistor provided in the same layer as the first oxide semiconductor layer and including a second oxide semiconductor layer connected between the second node and a reset potential line to which a constant voltage is supplied, a first capacitive element including a first conductive layer laminated below the same layer and electrically connected to a power line that supplies a power supply voltage, an electrode layer laminated on the same layer and electrically connected to the second node, and a second conductive layer laminated on the electrode layer and electrically connected to a power line.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a detection device. [Background technology]

[0002] In recent years, detection devices for non-destructive inspection of objects have become widespread. Examples of such devices include X-ray detection devices and fingerprint detection devices, which are used in fields such as medical technology and transportation technology.

[0003] For example, Patent Document 1 discloses a detection device capable of suppressing variations in output signals. The detection device disclosed in Patent Document 1 includes a plurality of detection elements (e.g., pixels), each of which includes a photoelectric conversion element, a plurality of transistors, and a capacitive element. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2021-100081 [Overview of the project] [Problems that the invention aims to solve]

[0005] One of the objectives of the present invention is to provide a detection device with high long-term reliability. [Means for solving the problem]

[0006] A detection device according to one embodiment of the present invention includes a photoelectric conversion element electrically connected to a first node, a first transistor including a first oxide semiconductor layer electrically connected between the first node and a second node, a second transistor provided in the same layer as the first oxide semiconductor layer and including a second oxide semiconductor layer connected between the second node and a reset potential line to which a constant voltage is supplied, and a first capacitive element including a first conductive layer laminated below the same layer and electrically connected to a power line to supply a power supply voltage, an electrode layer laminated on the same layer and electrically connected to the second node, and a second conductive layer laminated on the electrode layer and electrically connected to the power line.

[0007] A detection device according to one embodiment of the present invention includes a photoelectric conversion element electrically connected to a first node, a first transistor including a first oxide semiconductor layer electrically connected between the first node and a second node, a second transistor provided in the same layer as the first oxide semiconductor layer and including a second oxide semiconductor layer connected between the second node and a reset potential line to which a constant voltage is supplied, and a first capacitive element including a first conductive layer laminated below the same layer and electrically connected to a power line to supply a power supply voltage, a third oxide semiconductor layer arranged in the same layer and electrically connected to the second node, and a second conductive layer laminated on the third oxide semiconductor layer and electrically connected to the power line.

[0008] A detection device according to one embodiment of the present invention includes: a photoelectric conversion element electrically connected to a first node; a first transistor including a first oxide semiconductor layer electrically connected between the first node and a second node; a second transistor including a second oxide semiconductor layer provided in the same layer as the first oxide semiconductor layer and connected between the second node and a reset potential line to which a constant voltage is supplied; a first capacitive element including a first conductive layer laminated on the same layer and electrically connected to the power line, and a second conductive layer laminated on the first conductive layer and electrically connected to the second node; and a second capacitive element including a third conductive layer disposed on the second conductive layer and electrically connected to a reference potential line to which a reference voltage is supplied. [Brief explanation of the drawing]

[0009] [Figure 1] This is a plan view showing the configuration of a detection device according to the first embodiment of the present invention. [Figure 2] This is a plan view showing the configuration of a detection device according to the first embodiment of the present invention. [Figure 3] This is a circuit diagram showing a pixel circuit according to the first embodiment of the present invention. [Figure 4] This is an end view showing an example of a pixel end structure according to the first embodiment of the present invention. [Figure 5] This is a plan view showing the layout of a portion of the pixels according to the first embodiment of the present invention. [Figure 6] This is a plan view showing the layout of a portion of the pixels according to the first embodiment of the present invention. [Figure 7] This is a plan view showing the layout of a portion of the pixels according to the first embodiment of the present invention. [Figure 8] This is a plan view showing the layout of a portion of the pixels according to the first embodiment of the present invention. [Figure 9] This is a plan view showing the layout of a portion of the pixels according to the first embodiment of the present invention. [Figure 10] Figure 5 is an end view showing an example of an end face structure cut along A1-A2 in a partial pixel layout. [Figure 11] It is an end view showing an example of an end face structure cut along B1 - B2 in the layout of a part of the pixels shown in FIG. 5. [Figure 12] It is a plan view showing the layout of a part of the pixels according to the second embodiment of the present invention. [Figure 13] It is a plan view showing the layout of a part of the pixels according to the second embodiment of the present invention. [Figure 14] It is a plan view showing the layout of a part of the pixels according to the second embodiment of the present invention. [Figure 15] It is a plan view showing the layout of a part of the pixels according to the second embodiment of the present invention. [Figure 16] It is a plan view showing the layout of a part of the pixels according to the second embodiment of the present invention. [Figure 17] It is an end view showing an example of an end face structure cut along C1 - C2 in the layout of a part of the pixels shown in FIG. 12. [Figure 18] It is an end view showing an example of an end face structure cut along E1 - E2 in the layout of a part of the pixels shown in FIG. 12. [Figure 19] It is a circuit diagram showing a pixel circuit according to the third embodiment of the present invention. [Figure 20] It is a plan view showing the layout of a part of the pixels according to the third embodiment of the present invention. [Figure 21] It is a plan view showing the layout of a part of the pixels according to the third embodiment of the present invention. [Figure 22] It is a plan view showing the layout of a part of the pixels according to the third embodiment of the present invention. [Figure 23] It is a plan view showing the layout of a part of the pixels according to the third embodiment of the present invention. [Figure 24] It is a plan view showing the layout of a part of the pixels according to the third embodiment of the present invention. [Figure 25] It is a plan view showing the layout of a part of the pixels according to the third embodiment of the present invention. [Figure 26]This is a plan view showing the layout of a portion of the pixels according to the third embodiment of the present invention. [Figure 27] This is a plan view showing the layout of a portion of the pixels according to the third embodiment of the present invention. [Figure 28] This is a plan view showing the layout of a portion of the pixels according to the third embodiment of the present invention. [Figure 29] This is an end view showing an example of an end face structure cut along F1-F2 in a partial pixel layout shown in Figure 20. [Figure 30] Figure 20 is an end view showing an example of an end face structure cut along G1-G2 in a partial pixel layout. [Figure 31] This is an end view showing an example of an end face structure cut along H1-H2 in a partial pixel layout shown in Figure 21. [Modes for carrying out the invention]

[0010] The embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different ways, and should not be interpreted as being limited to the embodiments described below. In addition, the drawings may schematically represent the width, thickness, shape, and configuration of each part compared to the actual embodiments in order to make the explanation clearer, but these are merely examples and should not limit the interpretation of the present invention. The letters "1st" and "2nd" attached to each element are convenient indicators used to distinguish each element and have no further meaning unless specifically explained.

[0011] Furthermore, in the specification of this application, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude the case where α includes multiple combinations of A to C unless otherwise specified. Moreover, these expressions do not exclude the case where α includes other elements.

[0012] In the specification of this application, the first direction D1 intersects the second direction D2, and the third direction D3 intersects the first direction D1 and the second direction D2 (the D1D2 plane). For example, the first direction D1, the second direction D2, and the third direction D3 correspond to the X direction, the Y direction, and the Z direction. The first direction D1 may be perpendicular to the second direction D2, the first direction D1 may be perpendicular to the third direction D3, and the second direction D2 may be perpendicular to the third direction D3.

[0013] In the specification of this application, when the terms parallel, identical, and coincident are used, these terms may include errors within the scope of the design.

[0014] For example, a detection device according to one embodiment of the present invention includes a device for detecting biological information such as fingerprints, a device for detecting X-rays, or a solid-state imaging device. For example, a solid-state imaging device is a CMOS (Complementary Metal Oxide Semiconductor) image sensor, a CCD (Charge Coupled Device) image sensor, etc. For example, a solid-state imaging device according to one embodiment of the present invention is a CMOS image sensor. As an example, one embodiment of the present invention is a solid-state imaging device, but the content of the present invention is not limited to solid-state imaging devices and is naturally applicable to detection devices for detecting biological information such as fingerprint sensors and detection devices for detecting X-rays. Furthermore, the imaging data described later may be referred to as detection data.

[0015] [Background of the Invention] For example, development is underway to provide solid-state imaging devices with high long-term reliability.

[0016] Generally, a solid-state imaging device includes multiple pixels, each of which includes a photoelectric converter, multiple transistors, and a capacitive element. As will be described in detail later, the data transfer transistor T1 (see Figure 3) conducts between node N1 (see Figure 3) and node N2 (see Figure 3), and has the function of supplying a current based on the photovoltaic force generated by the light received by the photoelectric converter 110 (see Figures 1 and 2) upon exposure of pixel 502 (see Figures 1 and 2) from node N1 (see Figure 3) to node N2 (see Figure 3). The photoelectric converter 110 is electrically connected to node N1, and the capacitive element SC2 is electrically connected to node N2. For example, in order to efficiently transfer the current based on the photovoltaic force generated by the light received by the photoelectric converter 110 upon exposure of pixel 502 from node N1 to node N2, it is important to reduce the influence of parasitic capacitance between each element (each node). For example, to reduce the effects of parasitic capacitance, it is important to increase the capacitance value of the capacitive element SC2 electrically connected to node N2, and to reduce the parasitic capacitance caused by the coupling between node N1 and node N2.

[0017] For example, as shown in Figure 3 or Figure 5, a solid-state imaging device, which is one embodiment of the present invention, includes a photoelectric conversion element 110 electrically connected to node N1, a data transfer transistor T1 including an oxide semiconductor layer 122B electrically connected between node N1 and node N2, a reset transistor T2 including an oxide semiconductor layer 122D provided in the same layer as the oxide semiconductor layer 122B and connected between node N2 and a reset potential line SVR to which a reset potential VRES is supplied, a conductive layer 120D laminated below the same layer and electrically connected to a drive power line PVDD that supplies a drive voltage VPP, a gate electrode 127C laminated on the same layer and electrically connected to node N2, and a first capacitive element including a conductive layer 132F laminated on the gate electrode 127C and electrically connected to the drive power line PVDD.

[0018] As a result, in one embodiment of the present invention, the solid-state imaging device can suppress the influence of parasitic capacitance between each element (each node) by increasing the capacitance value of the capacitive element SC2 electrically connected to node N2 and reducing parasitic capacitance due to coupling between node N1 and node N2. By suppressing the influence of parasitic capacitance between each element (each node), the long-term reliability of the solid-state imaging device is improved.

[0019] In the following embodiments, a solid-state imaging device, which is one embodiment of the present invention, will be described in detail.

[0020] [1. First Embodiment] [1-1. Configuration of the Solid State Imaging Device 100] The outline of the solid-state imaging device 100 will be described with reference to Figures 1 and 2. Figures 1 and 2 are plan views showing the configuration of the solid-state imaging device 100.

[0021] As shown in Figure 1, the solid-state imaging device 100 includes a power supply circuit 200, a drive timing control circuit 300, a row selection circuit 400, a pixel unit 504, a readout circuit 600, and a signal processing circuit 700. The pixel unit 504 includes a plurality of pixels 502 that image the subject.

[0022] Multiple pixels 502 are arranged in a matrix in a first direction D1 (row direction) and a second direction D2 (column direction) intersecting the first direction D1. As will be described in detail later, each of the multiple pixels 502 includes multiple transistors (Figure 3), multiple capacitive elements (Figure 3), and a light-receiving element (Figure 3) that constitute the pixel circuit 60. For example, the light-receiving element according to one embodiment of the present invention is a photoelectric conversion element 110 (see Figure 3) that generates photovoltaic power. More specifically, the photoelectric conversion element 110 is a photodiode.

[0023] The power supply circuit 200 is electrically connected to the drive timing control circuit 300, the signal processing circuit 700, the readout circuit 600, and the row selection circuit 400. The power supply circuit 200 includes logic circuits (not shown) and voltage generation circuits (not shown). The power supply circuit 200 generates signals or power supply voltages using the logic circuits and voltage generation circuits, and supplies the generated signals, power supply voltages, or power to the drive timing control circuit 300, the signal processing circuit 700, the readout circuit 600, and the row selection circuit 400.

[0024] The drive timing control circuit 300 is electrically connected to the signal processing circuit 700, the readout circuit 600, and the row selection circuit 400. For example, the drive timing control circuit 300 generates the timing signals necessary for signal processing in each circuit and supplies the generated timing signals to each circuit. For example, the timing control signals are the clock signal and start pulse that control row selection in the row selection circuit 400.

[0025] For example, the row selection circuit 400 is positioned adjacent to the pixel section 504 in the first direction D1. For example, the row selection circuit 400 has a data transfer signal line 412 (see Figure 3), a reset signal line 414 (see Figure 3), and a read signal line 410 (see Figure 3). The read signal line 410 is connected to multiple pixels 502 arranged in the same row.

[0026] The readout circuit 600 is connected to the signal processing circuit 700. For example, the readout circuit 600 is positioned adjacent to the pixel 504 in the second direction D2. Multiple output signal lines 420 (see Figure 3) are connected to the readout circuit 600. The output signal lines 420 are connected to multiple pixels 502 arranged in the same row.

[0027] For example, the readout circuit 600 includes an AD converter (not shown) and a horizontal transfer scanning circuit (not shown). An output signal OUT(n) (see Figure 3) is supplied to the output signal line 420, and the output signal OUT(n) (see Figure 3) is converted into a digital signal by the AD converter. The digital signal is transferred to the horizontal transfer scanning circuit. The horizontal transfer scanning circuit reads the digital signal column by column. The horizontal transfer scanning circuit can read out the output signal OUT(n) corresponding to each of the multiple pixels 502 connected to the row selected using the row selection circuit 400 as a digital signal. The output signal OUT(n) is input to the readout circuit 600, and the readout circuit 600 outputs a digital signal.

[0028] The signal processing circuit 700 includes an image processing circuit (not shown). For example, the image processing circuit 720 performs image processing such as gamma correction and noise reduction on multiple digital signals output from the readout circuit 600 to generate image data. For example, the image data is the image data of the captured subject. Although not shown, the signal processing circuit 700 and the image processing circuit 720 each include an arithmetic processing circuit and a memory circuit. For example, the arithmetic processing circuit in one embodiment of the present invention is a processor, CPU, etc., and the memory circuit in one embodiment of the present invention is a volatile memory, non-volatile memory.

[0029] As shown in Figure 2, the row selection circuit 400 supplies a common reset signal RS(n), a readout signal RD(n), and a data transfer signal PD(n) to each of the multiple pixels 502 (pixel circuits 60) located in the nth row of the pixel unit 504. The power supply circuit 200 supplies a reference voltage VSS, a drive voltage VPP, and a reset voltage VRES to each of the pixel circuits 60 of the multiple pixels 502 located in the mth column of the pixel unit 504. For example, the multiple pixels 502 are arranged in m rows along the first direction D1 and n rows along the second direction D2. The numerical values ​​m and n are natural numbers. For example, pixels 502 arranged in a 3x5 grid are called the 3x5 pixel 502 or the pixel 502 at coordinates (3, 5).

[0030] Each of the multiple pixels 502 may contain multiple subpixels. For example, one pixel 502 may have three subpixels, and each of the three subpixels may contain a pixel circuit 60. The three subpixels may contain color filters that exhibit different colors from each other. For example, of the three pixels, the first subpixel may contain a color filter that exhibits red, the second subpixel may contain a color filter that exhibits green, and the third subpixel may contain a color filter that exhibits blue. Alternatively, for example, one pixel 502 may contain subpixels that include four or more color filters that exhibit different colors from each other. For example, by providing pixels or subpixels that include four or more color filters that exhibit different colors from each other, the solid-state imaging device 100 can generate imaging data with high color reproducibility of the subject.

[0031] Furthermore, for example, the arrangement of the multiple pixels 502 of the solid-state imaging device 100 is a stripe arrangement. There are no restrictions on the configuration of the multiple pixels 502, and they can be appropriately selected based on the application or specifications of the solid-state imaging device 100.

[0032] Furthermore, the signals, power supplies, voltages, and powers that form the basis of each signal, power supply, voltage, and power may be supplied from an external circuit (not shown) to the power supply circuit 200, the drive timing control circuit 300, and the signal processing circuit 700. Based on the supplied signals, power supplies, voltages, and powers, the power supply circuit 200, the drive timing control circuit 300, and the signal processing circuit 700 may generate and supply desired signals, desired power supplies, desired voltages, and desired powers to the row selection circuit 400, the pixel unit 504, and the readout circuit 600.

[0033] [1-2. Circuit configuration of pixel 502] Referring to Figure 3, the pixel circuit 60 included in the pixel 502 will be described. Figure 3 is a circuit diagram showing the pixel circuit 60. Each of the multiple pixels 502 has multiple transistors, a capacitive element, and a photoelectric conversion element that constitute the pixel circuit 60. Figure 3 shows the components that constitute the pixel circuit 60 of the n x m pixel 502 shown in Figure 2. The configuration of the pixel circuit 60 shown in Figure 3 is an example, and the configuration of the pixel circuit 60 is not limited to the configuration shown in Figure 3. Configurations identical or similar to those in Figures 1 and 2 will be described as necessary.

[0034] As shown in Figure 3, the pixel circuit 60 includes a data transfer transistor T1 (first transistor), a reset transistor T2 (second transistor), a drive transistor T3 (third transistor), a selection transistor T4 (fourth transistor), a photoelectric conversion element 110, a capacitive element SC1, and a capacitive element SC2. Each transistor includes a gate electrode and a pair of electrodes consisting of a source electrode and a drain electrode (a pair of electrodes consisting of a first electrode and a second electrode). Each capacitive element includes a pair of electrodes (a first electrode and a second electrode). Note that the function of each electrode as a source and drain may be reversed depending on the voltage applied to the source electrode and the drain electrode.

[0035] As a power source for driving the pixel 502, the drive voltage VPP is supplied to the drive power line PVDD, and the reference voltage VSS is supplied to the reference potential line PVSS. In addition, the reset voltage VRES is supplied to the reset potential line SVR. The reset voltage VRES is a constant voltage capable of resetting or initializing the pixel 502, and is supplied to node N2 by controlling the reset transistor T2. The reset voltage VRES may be a constant voltage or a variable voltage depending on time. For example, the reset voltage VRES of the solid-state imaging device 100 is a constant voltage.

[0036] The data transfer transistor T1 has the function of supplying a current based on the photovoltaic force generated by the light received by the photoelectric conversion element 110 in conjunction with the exposure of the pixel 502, by conducting node N1 to node N2. In other words, the data transfer transistor T1 has the function of transferring the current (data signal) generated by the photoelectric conversion element 110 from node N1 to node N2. The data transfer transistor T1 includes a gate electrode 612, a first electrode 614, and a second electrode 616. The gate electrode 612 is electrically connected to the data transfer signal line 412. The first electrode 614 is electrically connected to node N1, the second electrode 24 of the capacitive element SC1, and the second electrode 14 of the photoelectric conversion element 110. The second electrode 616 is electrically connected to node N2, the first electrode 624 of the reset transistor T2, the gate electrode 632 of the drive transistor T3, and the second electrode 34 of the capacitive element CS2. The data transfer signal PD(n) is supplied to the data transfer signal line 412. The switching of the data transfer transistor T1 is controlled using the data transfer signal PD(n). In other words, the conduction state (on state) and non-conduction state (off state) of the data transfer transistor T1 are controlled by the data transfer signal PD(n). When the signal supplied to the data transfer signal PD(n) is at a LO level, the data transfer transistor T1 is in a non-conducting state. When the signal supplied to the data transfer signal PD(n) is at a HI level, the data transfer transistor T1 is in a conduction state.

[0037] The reset transistor T2 has the function of supplying a reset voltage VRES to node N2 and putting pixel 502 into a reset or initialized state. The reset transistor T2 includes a gate electrode 622, a first electrode 624, and a second electrode 626. The gate electrode 622 is electrically connected to the reset signal line 414. The second electrode 626 is electrically connected to the reset potential line SVR. The reset signal RS(n) is supplied to the reset signal line 414. The switching of the reset transistor T2 is controlled using the reset signal RS(n). In other words, the conduction state (on state) and non-conduction state (off state) of the reset transistor T2 are controlled by the reset signal RS(n). When the signal supplied to the reset signal RS(n) is at the LO level, the reset transistor T2 is in the non-conduction state. When the signal supplied to the reset signal RS(n) is at the HI level, the reset transistor T2 is in the conduction state.

[0038] The drive transistor T3 adjusts the current flowing to node N3 in the reset or initialization state based on the reset voltage VREF supplied to the gate electrode 632. The drive transistor T3 also adjusts the current flowing to node N3 according to the current based on the photovoltaic current generated by the light received by the photoelectric conversion element 110 upon exposure of pixel 502. In one embodiment of the present invention, exposure of pixel 502 may be rephrased as light reception by pixel 502 or exposure of pixel 502, and light reception by photoelectric conversion element 110 may be rephrased as exposure of photoelectric conversion element 110 or exposure of photoelectric conversion element 110. The drive transistor T3 includes a gate electrode 632, a first electrode 634, and a second electrode 636. The first electrode 634 is electrically connected to node N3 and the second electrode 646 of the selection transistor T4. The second electrode 636 is electrically connected to the drive power line PVDD. For example, the threshold voltage of the drive transistor T3 is the threshold voltage VTH. The drive transistor T3 controls the amount of current flowing to the light-emitting element at node N3 according to the potential difference Vgs between the voltage supplied to node N2 and the voltage supplied to the first electrode 634, and the potential difference Vds between the voltage supplied to the second electrode 636 and the voltage supplied to the first electrode 634. For example, if the potential difference Vgs is less than the threshold voltage VTH, the second transistor T2 becomes non-conductive, and no current flows to node N3. For example, if the potential difference Vgs is greater than or equal to the threshold voltage VTH and the potential difference Vds is greater than 0V, the drive transistor T3 becomes conductive, and current flows to node N3.

[0039] The selection transistor T4 has the function of connecting node N3 to the output signal line 420 and supplying a current (data signal) flowing through node N3 to the output signal line 420 in accordance with the current based on the photovoltaic current generated by the light received by the photoelectric conversion element 110 when the pixel 502 is exposed. In other words, the selection transistor T4 has the function of supplying a current flowing through node N3 to the output signal line 420 based on the current (data signal) generated by the photoelectric conversion element 110. The selection transistor T4 includes a gate electrode 642, a first electrode 644, and a second electrode 646. The gate electrode 642 is electrically connected to the read signal line 410. The first electrode 644 is electrically connected to the output signal line 420. A read signal RD(n) is supplied to the read signal line 410. The switching of the selection transistor T4 is controlled using the read signal RD(n). In other words, the selector transistor T4 is controlled by the readout signal RD(n) to be either conducting (on) or not conducting (off). When the signal supplied to the readout signal RD(n) is at a LO level, the selector transistor T4 is in a non-conducting state. When the signal supplied to the readout signal RD(n) is at a HI level, the selector transistor T4 is in a conducting state.

[0040] Capacitive element SC1 has the function of holding a charge equivalent to the photovoltaic power generated based on the light received by the photoelectric conversion element 110, which is supplied to node N1. Capacitive element SC1 is provided between node N1 and the reference potential line PVSS. Capacitive element SC1 includes a first electrode 22 and a second electrode 24. The second electrode 24 is electrically connected to the reference potential line PVSS. The capacitance value of capacitive element SC1 is a capacitance value Cdiode.

[0041] The capacitive element SC2 has the function of holding a charge equivalent to the photovoltaic force generated based on the light received by the photoelectric conversion element 110 supplied to node N2. The capacitive element SC2 also has the function of holding a charge equivalent to the drive voltage VPP supplied to node N2. The capacitive element SC2 is provided between node N2 and the drive power line PVDD. The capacitive element SC2 includes a first electrode 32 and a second electrode 34. The first electrode 32 is electrically connected to the drive power line PVDD, and the second electrode 34 is electrically connected to node N2. The capacitance value of the capacitive element SC2 is the capacitance value Css. By having the capacitive element SC2, the solid-state imaging device 100 can suppress the discharge of charge equivalent to the drive voltage VPP and maintain the reset or initialization state of the pixel 502. Furthermore, by having the capacitive element SC2, the solid-state imaging device 100 can suppress the discharge of charge equivalent to the photovoltaic force and maintain the exposure state of the pixel 502. As a result, the solid-state imaging device 100 can maintain constant voltages in the reset state, initialization state, and exposure state, making it a highly reliable device over the long term.

[0042] The photoelectric conversion element 110 has the function of generating a photovoltaic force from the light received when the pixel 502 is exposed. The photoelectric conversion element 110 also has the function of supplying a charge corresponding to the current based on the generated photovoltaic force to node N1 and capacitive element SC1. The photoelectric conversion element 110 includes a first electrode 12 and a second electrode 14.

[0043] In the solid-state imaging device 100, a conductive state is defined as a state where the source electrode and drain electrode of a transistor are conducting, indicating that the transistor is ON. Conversely, a non-conductive state in the solid-state imaging device 100 is defined as a state where the source electrode and drain electrode of a transistor are not conducting, indicating that the transistor is OFF. Note that in each transistor, the source electrode and drain electrode may be swapped depending on the voltage of each electrode. Furthermore, it is easily understood by those skilled in the art that even when a transistor is OFF, a small current may flow, such as leakage current.

[0044] [1-3. An example of the end face structure and layout of pixel 502] Referring to Figures 4 to 11, an example of the end face structure and layout of pixel 502 will be described. Figure 4 is an end view showing an example of the end face structure of pixel 502. Figures 5 to 9 show an example of the layout of pixel 502. Figure 10 is an end view showing the end face of the capacitive element CS2 cut along A1-A2 in the planar layout of pixel 502 shown in Figure 5. Figure 11 is an end view showing the end face of the capacitive element CS2 cut along B1-B2 in the planar layout of pixel 502 shown in Figure 5. The configuration of pixel 502 shown in Figures 4 to 11 is an example, and the configuration of pixel 502 is not limited to the example shown in Figures 4 to 11. Configurations identical or similar to those in Figures 1 to 3 will be described as necessary.

[0045] [1-3-1. End-face structure of pixel 502] First, referring to Figure 4, the outline of the end face structure of the pixel 502 will be explained using the configuration of the data transfer transistor T1, the selection transistor T4, and the photoelectric conversion element 110 as examples. As shown in Figures 4, 10, and 11, the substrate SUB includes a first surface 101A and a second surface 101B opposite to the first surface 101A along the third direction D3. Each layer included in the solid-state imaging device 100 (pixel 502) is located above the substrate SUB (on the first surface 101A side) along the third direction D3.

[0046] As shown in Figure 4, the data transfer transistor T1 includes an oxide semiconductor layer 122B, a gate insulating layer 125, and a gate electrode 127B. The oxide semiconductor layer 122B is electrically connected between node N1 and node N2. The gate electrode 127B faces the oxide semiconductor layer 122B. The gate insulating layer 125 is provided between the oxide semiconductor layer 122B and the gate electrode 127B. The oxide semiconductor layer 122B is provided on the first surface 101A side of the gate electrode 127B, and the data transfer transistor T1 is a so-called top-gate type transistor. As an example, each transistor constituting the solid-state imaging device 100 is a top-gate type transistor, but each transistor constituting the solid-state imaging device 100 may be a bottom-gate type transistor in which the gate electrode 127B is provided on the first surface 101A side of the oxide semiconductor layer 122B, and the positional relationship between the oxide semiconductor layer 122B and the gate electrode 127B is reversed compared to a top-gate type transistor.

[0047] In a plan view, the oxide semiconductor layer 122B in the region overlapping with the gate electrode 127B (gate electrode 612) functions as a semiconductor layer (channel) of the data transfer transistor T1 and switches between a conductive state and a non-conductive state depending on the voltage supplied to the gate electrode 127B. In other words, in a plan view, the oxide semiconductor layer 122B in the region not overlapping with the gate electrode 127B functions as a conductive layer of the data transfer transistor T1 and is the first electrode 614 and the second electrode 616. That is, the oxide semiconductor layer 122B functions as both a semiconductor layer and a conductive layer.

[0048] Along the third direction D3, in order from the first surface 101A, an oxide semiconductor layer 122B is provided on the insulating layer 121, a gate insulating layer 125 is provided on the oxide semiconductor layer 122B, a gate electrode 127B is provided on the gate insulating layer 125, an insulating layer 128 is provided on the gate electrode 127B, conductive layers 132D, 132E, and 132J are provided on the insulating layer 128, and an insulating layer 131 is provided on the conductive layers 132D, 132E, and 132J. The conductive layers 132D and 132E are connected to the oxide semiconductor layer 122B via openings 135D and 135E provided in the insulating layer 128 and the gate insulating layer 125. For example, the conductive layer 132 is supplied (transmitted) with current (data signal) generated by the photoelectric conversion element 110.

[0049] Furthermore, the data transfer transistor T1 includes a conductive layer 120B. The conductive layer 120B is provided between the oxide semiconductor layer 122B and the substrate SUB. In a plan view, the conductive layer 120B is provided in the region where the gate electrode 127B and the oxide semiconductor layer 122B overlap. The conductive layer 132J is connected to the conductive layer 120B via an opening 135F provided in the insulating layer 128, the gate insulating layer 125, and the insulating layer 121. For example, a constant voltage is supplied to the conductive layer 120B via the conductive layer 132J to suppress light incident from the substrate SUB side from reaching the oxide semiconductor layer 122B. Also, similar to the gate electrode 127B, the conductive layer 120B may have a voltage applied to it to control the current flowing through the oxide semiconductor layer 122B. In this case, the conductive layer 120B may be connected to the gate electrode 127B in the peripheral region of the pixel circuit 60.

[0050] Furthermore, as will be described in more detail later, along the third direction D3, in order from the first surface 101A, an insulating layer 136 is provided on top of the insulating layer 131, an insulating layer 141 is provided on top of the insulating layer 136, an insulating layer 151 is provided on top of the insulating layer 141, an insulating layer 152 is provided on top of the insulating layer 151, and an insulating layer 153 is provided on top of the insulating layer 152.

[0051] Furthermore, as will be described in detail later, the conductive layer 139 may be provided between the insulating layer 141 and the insulating layer 136, and the conductive layer 139, n-type semiconductor layer 142, semiconductor layer 143, p-type semiconductor layer 144 and conductive layer 145 may be stacked in this order from the side closest to the first surface 101A along the third direction D3, and the conductive layer 139 may be provided between the insulating layer 141 and the insulating layer 136. The conductive layer 139 may be provided so as to overlap with the data transfer transistor T1, and the conductive layer 139, n-type semiconductor layer 142, semiconductor layer 143, p-type semiconductor layer 144 and conductive layer 145 may be provided so as to overlap with the data transfer transistor T1.

[0052] As shown in Figure 4, the selection transistor T4 has a similar configuration to the data transfer transistor T1. For example, the selection transistor T4 includes a conductive layer 120A, an oxide semiconductor layer 122A, a gate insulating layer 125, a gate electrode 127A, and conductive layers 132A, 132B, and 132C. Conductive layer 120A is formed in the same layer as conductive layer 120B, oxide semiconductor layer 122A is formed in the same layer as oxide semiconductor layer 122B, gate electrode 127A is formed in the same layer as gate electrode 127B, and conductive layers 132A, 132B, and 132C are formed in the same layers as conductive layers 132D, 132E, and 132F.

[0053] In a plan view, the oxide semiconductor layer 122A in the region overlapping with the gate electrode 127A (gate electrode 642) functions as a semiconductor layer (channel) of the data transfer transistor T1 and is switched between a conductive state and a non-conductive state depending on the voltage supplied to the gate electrode 127A. In other words, the oxide semiconductor layer 122A in the region not overlapping with the gate electrode 127A in a plan view functions as a conductive layer of the data transfer transistor T1 and is the first electrode 644 and the second electrode 646. That is, the oxide semiconductor layer 122B functions as both a semiconductor layer and a conductive layer. Furthermore, the conductive layer 132C is connected to the conductive layer 120A via openings 135C provided in the insulating layer 128, the gate insulating layer 125, and the insulating layer 121.

[0054] Furthermore, the reset transistor T2 and the drive transistor T3, as well as each transistor included in the solid-state imaging device 100, have the same configuration as the data transfer transistor T1 and the selection transistor T4, and are formed in the same manner.

[0055] As shown in Figure 4, the photoelectric conversion element 110 includes a conductive layer 139, an n-type semiconductor layer 142, a semiconductor layer 143, a p-type semiconductor layer 144, and a conductive layer 145.

[0056] A conductive layer 139 is provided on an insulating layer 136, an n-type semiconductor layer 142 is provided on the conductive layer 139 so as to be in contact with the conductive layer 139, a semiconductor layer 143 is provided on the n-type semiconductor layer 142 so as to be in contact with the n-type semiconductor layer 142, a p-type semiconductor layer 144 is provided on the semiconductor layer 143 so as to be in contact with the semiconductor layer 143, and a conductive layer 145 is provided on the p-type semiconductor layer 144 so as to be in contact with the p-type semiconductor layer 144.

[0057] The conductive layer 139 is connected to the conductive layer 132D via an opening 137 in the insulating layer 131 and an opening 138 in the insulating layer 136. That is, the conductive layer 139 is in contact with the conductive layer 132D at the bottom of the opening 138, and the conductive layer 139 is electrically connected to the data transfer transistor T1. The conductive layer 139 functions as the lower electrode of the photoelectric conversion element 110. In addition, for example, a part of the conductive layer 139 functions as the second electrode 14 of the photoelectric conversion element 110 and as the second electrode 24 of the capacitive element SC1.

[0058] Furthermore, for example, the n-type semiconductor layer 142, semiconductor layer 143, and p-type semiconductor layer 144 constitute the light-emitting diode 150 and function as a light-emitting diode. The conductive layer 145 functions as the upper electrode constituting the photoelectric conversion element 110. Also, for example, a part of the conductive layer 145 functions as the first electrode 12 of the photoelectric conversion element 110 and functions as the first electrode 22 of the capacitive element SC1.

[0059] Furthermore, an insulating layer 141 is provided on the upper and side surfaces of the conductive layer 145, the upper and side surfaces of the p-type semiconductor layer 144 that is not in contact with the conductive layer 145, the side surfaces of the semiconductor layer 143, the side surfaces of the n-type semiconductor layer 142, the upper and side surfaces of the conductive layer 139 that is not in contact with the n-type semiconductor layer 142, and the upper surface of the insulating layer 136 that is not in contact with the conductive layer 139.

[0060] A conductive layer 148 is provided on top of an insulating layer 151. A conductive layer 149 covers the top and sides of the conductive layer 148, and is also provided on the top and sides of the insulating layer 151 where the conductive layer 148 is not provided (opened by opening 147), the top and sides of the insulating layer 141 where the conductive layer 148 is opened (opened by opening 146), and the conductive layer 145 exposed from the insulating layer 141. That is, the conductive layer 149 is electrically connected to the conductive layer 148, and is also electrically connected to the conductive layer 145 exposed from the insulating layer 141 via opening 147 which opens the insulating layer 151 and opening 146 which opens the insulating layer 141. For example, the conductive layer 149 and the conductive layer 148 function as a reference potential line PVSS.

[0061] An insulating layer 152 is provided on the upper and side surfaces of the conductive layer 149, and on the insulating layer 151 where the conductive layer 149 is not provided, and an insulating layer 153 is provided on the insulating layer 152.

[0062] When distinguishing between conductive layers 120, they are represented by numbers and letters, such as conductive layer 120A, 120B, etc. Similarly, the oxide semiconductor layer 122, gate electrode 127, conductive layer 132, opening 135, opening 138, conductive layer 139, light-emitting diode 150, conductive layer 145, conductive layer 148, conductive layer 149, opening 146, and opening 147 are also represented by numbers followed by letters when distinguishing between them, similar to conductive layer 120. Furthermore, when distinguishing between each layer and each opening, they may be represented by numbers followed by letters, such as conductive layer 132F1, 132F2, etc.

[0063] [1-3-2. Layout of 502 pixels] Next, with reference to Figures 5-9, an overview of the layout of pixel 502 will be described. Configurations identical or similar to those in Figures 1-4 will be described as necessary.

[0064] For example, the layout of pixel 502 shown in Figure 5 includes a conductive layer 120, an oxide semiconductor layer 122, a gate electrode 127B, a conductive layer 132, openings 135, 138A, and 137. In Figure 5, layers above conductive layer 139 are omitted from the third direction, starting from the side closer to the first surface 101A.

[0065] To make each layer easier to understand, Figure 6 shows the layout of the conductive layer 120, Figure 7 shows the layout of the oxide semiconductor layer 122, Figure 8 shows the layout of the gate electrode 127, and Figure 9 shows the layout in which the conductive layer 120, oxide semiconductor layer 122, conductive layer 132, gate electrode 127, and opening 135 are superimposed.

[0066] As shown in Figures 5 and 6, the conductive layer 120 includes conductive layers 120A, 120B, 120C, 120D, and 120E. Conductive layers 120A, 120B, 120C, 120D, and 120E are provided on the same layer. Conductive layers 120A, 120B, 120C, 120D, and 120E are spaced apart from each other. Conductive layer 120A functions as a read signal line 410, conductive layer 120B functions as a data transfer signal line 412, conductive layer 120C functions as a reset signal line 414, conductive layer 120D functions as the first electrode 32 of the capacitive element SC2, and conductive layer 120E functions as a light-shielding layer or gate electrode of the drive transistor T3. Furthermore, conductive layers 120A, 120B, and 120C, like conductive layer 120E, are superimposed on the corresponding transistors and function as light-shielding layers or gate electrodes for those transistors. Conductive layer 120 is sometimes referred to as the lower gate electrode.

[0067] As shown in Figures 5 and 7, the oxide semiconductor layer 122 includes oxide semiconductor layers 122A, 122B, 122C, and 122D. The oxide semiconductor layers 122A, 122B, 122C, and 122D are provided in the same layer. The oxide semiconductor layers 122A, 122B, 122C, and 122D are spaced apart from each other. Also, as shown in Figures 5 and 8, the gate electrode 127 includes gate electrodes 127A, 127B, 127C, and 127D. The gate electrodes 127A, 127B, 127C, and 127D are provided in the same layer. The gate electrodes 127A, 127B, 127C, and 127D are spaced apart from each other.

[0068] In a plan view, the oxide semiconductor layer 122C in the region overlapping with the gate electrode 127C (gate electrode 632) functions as a semiconductor layer (channel) of the drive transistor T3 and switches between a conductive state and a non-conductive state depending on the voltage supplied to the gate electrode 127C. In other words, in a plan view, the oxide semiconductor layer 122C in the region not overlapping with the gate electrode 127C functions as a conductive layer of the drive transistor T3 and is the first electrode 634 and the second electrode 636. That is, the oxide semiconductor layer 122C functions as both a semiconductor layer and a conductive layer.

[0069] As shown in Figures 5 and 9, the opening 135 includes openings 135A to 135T. The opening 135 may penetrate the insulating layer 128, the insulating layer 128 and the gate insulating layer 125, and the insulating layer 128, the gate insulating layer 125 and the insulating layer 121. Also, as shown in Figure 5, the conductive layer 132 includes conductive layers 132A to 132J. The conductive layers 132A to 132J are provided in the same layer. The conductive layers 132A to 132J are arranged spaced apart from each other.

[0070] For example, the opening 135G exposes the conductive layer 120B (data transfer signal line 412). The conductive layer 132J electrically connects the conductive layer 120B and the gate electrode 127B (gate electrode 612) via the openings 135F and 135G. In a plan view, the oxide semiconductor layer 122B is sandwiched between the conductive layer 120B and the gate electrode 127B, and the oxide semiconductor layer 122B, the conductive layer 120B, and the gate electrode 127B face each other and overlap, forming a part of the data transfer transistor T1.

[0071] The conductive layer 132G electrically connects the conductive layer 120C (reset signal line 414) and the gate electrode 127D (gate electrode 622) through openings 135N and 135M. In a plan view, the oxide semiconductor layer 122D is sandwiched between the conductive layer 120C and the gate electrode 127D. The oxide semiconductor layer 122D, the conductive layer 120C, and the gate electrode 127D face each other and overlap, forming a part of the reset transistor T2.

[0072] The conductive layer 132I electrically connects the conductive layer 120E and the gate electrode 127C (gate electrode 632) through openings 135S and 135T. In a plan view, the oxide semiconductor layer 122C is sandwiched between the conductive layer 120E and the gate electrode 127C, and the oxide semiconductor layer 122C, the conductive layer 120E, and the gate electrode 127C face each other and overlap, forming a part of the drive transistor T3.

[0073] The conductive layer 132E electrically connects the oxide semiconductor layer 122B and the gate electrode 127C (gate electrode 632) through openings 135H and 135E. Furthermore, the first electrode 624 of the reset transistor T2, the gate electrode 632 of the drive transistor T3, the second electrode 616 of the data transfer transistor T1, and the second electrode 34 of the capacitive element SC2 are electrically connected. The connected region is node N2.

[0074] The conductive layer 132F (drive power line PVDD) is electrically connected to the oxide semiconductor layer 122C via the opening 135R and to the conductive layer 120D (first electrode 32) via the opening 135I. In other words, the conductive layer 132F (drive power line PVDD) is electrically connected to the drive transistor T3 and the capacitive element SC2.

[0075] The conductive layer 132A (output signal line 420) is electrically connected to the oxide semiconductor layer 122A via the opening 135A. That is, the conductive layer 132A (output signal line 420) is electrically connected to the selection transistor T4.

[0076] Although a detailed explanation is omitted, the other openings 135 also expose the corresponding insulating layer, conductive layer, gate electrode, or oxide semiconductor layer, thereby creating electrical connections between conductive layers, conductive layers and gate electrodes, or conductive layers and oxide semiconductor layers.

[0077] [1-3-3. Configuration of the capacitive element CS2 and reset transistor T2 of pixel 502] Next, the configurations of the capacitive element CS2 and the reset transistor T2 will be described with reference to Figures 5 to 11. Configurations identical or similar to those in Figures 1 to 4 will be described as necessary.

[0078] The end face of pixel 502 shown in Figure 10 is an example of the end face of the capacitive element CS2 and reset transistor T2, and is the end face along conductive layer 132A (output signal line 420), conductive layer 132F (drive power line PVDD), gate electrode 127C (gate electrode 632), conductive layer 120D, opening 135K, conductive layer 132H, opening 135J, oxide semiconductor layer 122D, conductive layer 120C, gate electrode 127D (gate electrode 622), conductive layer 132F (drive power line PVDD), opening 135L, and conductive layer 132I (reset potential line SVR). Conductive layer 132A (output signal line 420), conductive layer 132F (drive power line PVDD), conductive layer 120D, conductive layer 132H, and conductive layer 132I (reset potential line SVR) are arranged on the same layer, spaced apart from each other.

[0079] The end face of pixel 502 shown in Figure 11 is the end face of the region obtained by translating the end face shown in Figure 10 along the first direction D1, and is the end face along the conductive layer 132A (output signal line 420), conductive layer 132F (drive power line PVDD), gate electrode 127C (gate electrode 632), conductive layer 120D, opening 135I, and conductive layer 132I (reset potential line SVR).

[0080] The gate electrode 127C (gate electrode 632) includes a gate electrode 127C1 that functions as the gate electrode of the drive transistor T3, a gate electrode 127C3 superimposed on the conductive layers 120D and 132F that constitute the capacitive element CS2, having a larger area than conductive layer 120D and a smaller area than conductive layer 132F, and a gate electrode 127C2 that extends in the first direction D1 and electrically connects gate electrode 127C1 and gate electrode 127C3. The conductive layer 132F also includes a conductive layer 132F1 that extends in the first direction D1, a conductive layer 132F3 superimposed on the conductive layers 120D and 127C that constitute the capacitive element CS2, having a larger area than conductive layer 120D and gate electrode 127C, and a conductive layer 132F2 that electrically connects conductive layer 132F1 and conductive layer 132F3.

[0081] As shown in Figure 5, the capacitive element CS2 has a configuration in which the conductive layer 120D, gate electrode 127C, and conductive layer 132F are superimposed on each other in a plan view. Also, as shown in Figures 10 and 11, the insulating layer 121 and gate insulating layer 125 are sandwiched between the conductive layer 120D and the gate electrode 127C, and the insulating layer 128 is sandwiched between the gate electrode 127C and the conductive layer 132F. Furthermore, as shown in Figure 11, the conductive layer 132F is electrically connected to the conductive layer 120D through an opening 135I that penetrates the insulating layer 121 and the gate insulating layer 125 to expose the conductive layer 120D. In other words, the capacitive element CS2 is composed of a capacitance formed by the conductive layer 120D and gate electrode 127C with the insulating layer 121 and gate insulating layer 125 sandwiched between them, and a capacitance formed by the gate electrode 127C and conductive layer 132F with the insulating layer 128 sandwiched between them. Furthermore, the capacitive element CS2 does not necessarily have to have a conductive layer 120D, in which case the pixel 502 does not have an opening 135I.

[0082] As shown in Figures 5, 7, or 10, the reset transistor T2 includes an oxide semiconductor layer 122D, a gate insulating layer 125, and a gate electrode 127D. The oxide semiconductor layer 122D is electrically connected between node N2 and the reset potential line SVR to which the reset voltage VREF is supplied. The gate electrode 127D faces the oxide semiconductor layer 122D. The gate insulating layer 125 is provided between the oxide semiconductor layer 122D and the gate electrode 127D. The oxide semiconductor layer 122D is provided on the first surface 101A side of the gate electrode 127D. The oxide semiconductor layer 122D also faces the conductive layer 120D, which is located on the first surface 101A, with an insulating layer 121 in between.

[0083] Furthermore, as shown in Figures 5 and 10, the conductive layer 132H electrically connects the gate electrode 127C (gate electrode 632) and the oxide semiconductor layer 122D through an opening 135K that penetrates the insulating layer 128 and exposes the gate electrode 127C (gate electrode 632), and an opening 135L that penetrates the insulating layer 128 and the gate insulating layer 125 and exposes the oxide semiconductor layer 122D. The conductive layer 132I (reset potential line SVR) is electrically connected to the oxide semiconductor layer 122D through an opening 135L that penetrates the insulating layer 128 and the gate insulating layer 125 and exposes the oxide semiconductor layer 122D. For example, the oxide semiconductor layer 122D exposed by the opening 135L is the first electrode 624, and the oxide semiconductor layer 122D exposed by the opening 135L is the second electrode 626. In other words, the gate electrode 127C (gate electrode 632) and the conductive layer 132I (reset potential line SVR) are electrically connected to the reset transistor T2.

[0084] In a plan view, the oxide semiconductor layer 122B in the region overlapping with the gate electrode 127D (gate electrode 622) functions as a semiconductor layer (channel) of the reset transistor T2 and is switched between a conductive state and a non-conductive state depending on the voltage supplied to the gate electrode 127D. In other words, in a plan view, the oxide semiconductor layer 122D in the region not overlapping with the gate electrode 127D functions as a conductive layer of the reset transistor T2 and is the first electrode 624 and the second electrode 626. That is, the oxide semiconductor layer 122D functions as both a semiconductor layer and a conductive layer.

[0085] For example, in a conventional solid-state imaging device, the pixels of the device are electrically connected to a conductive layer 132F1 and a gate electrode 127C3 via an opening 135 between the conductive layer 132F1 and the gate electrode 127C3. The region formed by the conductive layer 132F1, the gate electrode 127C3, and the conductive layer 132 corresponds to the first electrode 614 and node N2 of the data transfer transistor T1. The first electrode 614 of the data transfer transistor T1 corresponds to node N1. Furthermore, a conductive layer 139 (lower electrode of the photoelectric conversion element 110) is provided above along the third direction D3, and the conductive layer 139 (lower electrode of the photoelectric conversion element 110) overlaps with nodes N2 and N1. Parasitic capacitance due to the overlap between node N2 and the lower electrode of the photoelectric conversion element 110 is added to node N2, and this parasitic capacitance has a significant impact on node N2. In addition, parasitic capacitance due to coupling with node N1 is added to node N2, and this parasitic capacitance has a significant impact on node N2. As a result, the parasitic capacitance of node N2 increases, and the noise caused by the increased parasitic capacitance has a greater impact on node N2. Furthermore, the conductive layer 132I (reset potential line SVR) is electrically connected to the reset transistor T2 via the opening 135, the gate electrode 127, the conductive layer 132, and the multiple openings 135. Since the multiple openings 135 are arranged along the second direction D2 between the conductive layer 132I (reset potential line SVR) and the conductive layer 132 corresponding to the first electrode of the capacitive element SC2, it is difficult to increase the capacitance value of the capacitive element SC2.

[0086] On the other hand, the gate electrode 127C in the pixel of the solid-state imaging device 100 has gate electrodes 127C1, 127C2, and 127C3 integrated together, and the conductive layer 132F in the pixel of the solid-state imaging device 100 has conductive layers 132F1, 132F2, and 132F3 integrated together. Furthermore, the gate electrode 127C3, which is part of node N2, is superimposed on the conductive layer 132F3. The conductive layer 132F3 is the first electrode 32 of the capacitive element SC2, and a constant voltage drive voltage PVDD is supplied to the conductive layer 132F3. Therefore, because the conductive layer 132F3 is positioned between node N2 and the lower electrode of the photoelectric conversion element 110, the conductive layer 132F3 can cover the gate electrode 127C3, which is part of node N2, and shield the lower electrode of the photoelectric conversion element 110 from the gate electrode 127C3. Furthermore, since the gate electrode 127C is not formed in the conductive layer 132, the gate electrode 127C can suppress parasitic capacitance due to coupling with node N1 formed by the conductive layer 132D. As a result, the capacitance value between the conductive layer 132F (drive power line PVDD) and node N2 can be increased, and the parasitic capacitance between node N2 and node N1 can be reduced.

[0087] Furthermore, the conductive layer 132I (reset potential line SVR) is electrically connected to the oxide semiconductor layer 122D (second electrode 626 of the reset transistor T2) via the opening 135L. As a result, the number of openings 135 provided between the conductive layer 132I (reset potential line SVR) and the conductive layer 132F3 constituting the capacitive element SC2 can be reduced. Therefore, the area of ​​the conductive layer 132F3, the area of ​​the conductive layer 120D, and the area of ​​the gate electrode 127C3 constituting the capacitive element SC2 can be increased. As a result, the capacitance value between the conductive layer 132F (drive power line PVDD) and node N2 can be increased.

[0088] For example, as shown in Table 1, in a conventional solid-state imaging device, the proportion of capacitance value added to node N2 is approximately 14% attributable to node N1 and approximately 68% attributable to the drive voltage line PVDD. Also, as shown in Table 1, in the solid-state imaging device 100 of the present invention, the proportion of capacitance value added to node N2 is approximately 5% attributable to node N1 and approximately 82% attributable to the drive voltage line PVDD. Therefore, the configuration of the capacitive element SC2 of the solid-state imaging device 100 has a capacitance value attributable to node N1 that is smaller than that of the capacitive element SC2 of a conventional solid-state imaging device, and a capacitance value attributable to the drive voltage line PVDD that is larger than that of the capacitive element SC2 of a conventional solid-state imaging device. As a result, the solid-state imaging device 100 has a configuration that can reduce parasitic capacitance due to coupling and has a configuration that can increase the ratio of capacitance value to power supply voltage, thereby suppressing the effects of coupling and noise.

[0089] [Table 1]

[0090] [1-3-4. Materials of each component of the solid-state imaging device 100] As the substrate SUB, a rigid substrate that is translucent and inflexible, such as a glass substrate, quartz substrate, or sapphire substrate, can be used. If the substrate SUB needs to be flexible, a flexible substrate containing resin, such as a polyimide substrate, acrylic substrate, siloxane substrate, or fluororesin substrate, can be used. Impurities may be introduced into the resin to improve the heat resistance of the substrate SUB.

[0091] As the conductive layer 120, gate electrode 127, conductive layer 132, conductive layer 139, and conductive layer 148, a metal material can be used. For example, as the metal material, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), or silver (Ag), or an alloy or compound thereof can be used. As the members such as the above electrodes, the above metal material may be used as a single layer or in a laminated form.

[0092] As the insulating layer 121, gate insulating layer 125, insulating layers 128, 131 and 141, and insulating layers 136, 151 and 153, general insulating materials can be used. For example, as the insulating layer 121, gate insulating layer 125, insulating layers 128, 131 and 141, silicon oxide (SiO y , x , x , x , y , y , y , x , x , x , x , x , x , x , y ,

[0093] , , ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ), aluminum oxynitride (AlN x O y ), or aluminum nitride (AlN x ) and other inorganic insulating layers can be used. As these insulating layers, insulating layers with few defects can be used. As the insulating layers 136, 151 and 153, organic insulating materials such as polyimide resin, acrylic resin, epoxy resin, silicone resin, fluororesin, or siloxane resin can be used. In addition, as the insulating layer 121, gate insulating layer 125, insulating layers 128, 131 and 141, the above organic insulating materials may be used. As the members such as the above insulating layers, the above insulating materials may be used as a single layer or in a laminated form.

[0093] SiO x N y and AlO x Ny These are silicon compounds and aluminum compounds that contain nitrogen (N) in a smaller proportion (x>y) than oxygen (O). x O y and AlN x O y These are silicon compounds and aluminum compounds that contain oxygen in a smaller proportion (x > y) than nitrogen.

[0094] As the oxide semiconductor layer 122, an oxide semiconductor having semiconductor properties can be used. The oxide semiconductor layer 122 is translucent. For example, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) can be used.

[0095] For example, the leakage current of a transistor having an oxide semiconductor with semiconductor properties is extremely small. Therefore, when using a transistor having an oxide semiconductor with semiconductor properties, the charge corresponding to the data signal transferred to the capacitive element is less likely to escape from the capacitive element. As a result, by using a transistor having an oxide semiconductor with semiconductor properties, changes in the potential of the data signal transferred to the capacitive element can be suppressed. For example, when using a data transfer transistor T1, the charge corresponding to the data signal transferred to the capacitive element SC2 is less likely to escape from the capacitive element SC2, and changes in the potential of the data signal transferred to the capacitive element SC2 (gate electrode 632, node N2) are suppressed. In addition, since changes in the potential of the gate electrode 632 of the drive transistor T3 are suppressed, the current that the drive transistor T3 sends from the drive power line PVDD to node N3 in response to the data signal input to the gate electrode 632 becomes stable. As a result, the current flowing through the output signal line 420 is stable, so the output signal OUT(m) contains data with high reproducibility of the subject, and the solid-state imaging device 100 can provide the user with images with high reproducibility of the subject.

[0096] Transparent conductive layers are used as conductive layers 145 and 149. For example, a mixture of indium oxide and tin oxide (ITO) or a mixture of indium oxide and zinc oxide (IZO) can be used as the transparent conductive layer. Other materials may also be used as the transparent conductive layer.

[0097] The conductive layer 120, insulating layer 121, oxide semiconductor layer 122, gate insulating layer 125, gate electrode 127B, insulating layer 128, opening 135, conductive layer 132, insulating layer 131, insulating layer 136, and conductive layer 139 are sometimes collectively referred to as the array section 170.

[0098] [2. Second Embodiment] Referring to Figures 12 to 18, an overview of the solid-state imaging apparatus according to the second embodiment will be described. Figures 12 to 16 show an example of the layout of the pixel 502 of the solid-state imaging apparatus according to the second embodiment. Figure 17 is an end view showing the end face of the capacitive element CS2 cut along C1-C2 in the planar layout of the pixel 502 shown in Figure 12. Figure 18 is an end view showing the end face of the capacitive element CS2 cut along E1-E2 in the planar layout of the pixel 502 shown in Figure 12. The configuration of the pixel 502 of the solid-state imaging apparatus according to the second embodiment shown in Figures 12 to 18 is an example and is not limited to the example shown in Figures 12 to 18. Configurations identical or similar to those in Figures 1 to 18 will be described as necessary.

[0099] The pixel 502 of the solid-state imaging device according to the second embodiment includes the configurations shown in (1) to (5) below. The configurations shown in (1) to (5) mainly differ from the configuration of the pixel 502 of the solid-state imaging device 100 according to the first embodiment. (1) The first electrode 32 of the capacitive element SC2 changes from a conductive layer 120D to a conductive layer 120D + conductive layer 120F, and the area of ​​the first electrode 32 of the capacitive element SC2 increases. (2) The oxide semiconductor layer 122E is connected to the oxide semiconductor layers 122D and 122B, and the oxide semiconductor layers are integrated, so the pixel 502 of the solid-state imaging device according to the second embodiment does not contain the openings 135K and 135J. (3) The portion corresponding to the gate electrode 127C3 is replaced by the oxide semiconductor layer 122E. That is, the pixel 502 of the solid-state imaging device according to the second embodiment does not include the gate electrode 127C3. The oxide semiconductor layer 122E is connected to the oxide semiconductor layers 122D and 122B, and the oxide semiconductor layers are integrated. For example, the oxide semiconductor layer 122E functions as part of the second electrode 34 of the capacitive element SC2. (4) A portion of the second electrode 34 of the capacitive element SC2 changes from the conductive layer 132F to the conductive layer 132F + conductive layer 132K, and the area of ​​the second electrode 34 of the capacitive element SC2 increases. (5) Due to the increase in the area of ​​the first electrode 32 of the capacitive element SC2 and the increase in the area of ​​the second electrode 34 of the capacitive element SC2, the position where the opening 135I is located is shifted toward the conductive layer 132F1 side.

[0100] The configurations of the pixel 502 of the solid-state imaging device according to the second embodiment, as shown in (1) to (5), and configurations other than those related to the configurations shown in (1) to (5) of the pixel 502 of the solid-state imaging device according to the second embodiment, are the same as those of the pixel 502 of the solid-state imaging device 100 according to the first embodiment. Therefore, this section will mainly describe the differences from the pixel 502 of the solid-state imaging device 100 according to the first embodiment. When describing the configuration and function of the pixel 502 of the solid-state imaging device according to the second embodiment, configurations and functions similar to those of the pixel 502 of the solid-state imaging device 100 according to the first embodiment will be described as necessary. In addition, configurations identical or similar to those in Figures 1 to 18 will be described as necessary.

[0101] [2-1. Layout of 502 pixels] Next, with reference to Figures 12 to 16, an overview of the layout of the pixels 502 of the solid-state imaging apparatus according to the second embodiment will be described. Configurations identical or similar to those in Figures 1 to 11 will be described as necessary.

[0102] For example, the layout of pixel 502 shown in Figure 12 is similar to the layout of pixel 502 shown in Figure 5, showing a conductive layer 120, an oxide semiconductor layer 122, a gate electrode 127B, a conductive layer 132, an opening 135, an opening 138A, and an opening 137, with layers above conductive layer 139 omitted from the side closer to the first surface 101A along the third direction.

[0103] To make each layer easier to understand, Figure 13 shows the layout of the conductive layer 120, Figure 14 shows the layout of the oxide semiconductor layer 122, Figure 15 shows the layout of the gate electrode 127, and Figure 16 shows the layout in which the conductive layer 120, oxide semiconductor layer 122, conductive layer 132, gate electrode 127, and opening 135 are superimposed.

[0104] As shown in Figures 12 and 13, the conductive layer 120 includes conductive layers 120A, 120B, 120C, 120D, 120E, and 120F. Conductive layers 120A, 120B, 120C, 120D, 120E, and 120F are provided in the same layer. Conductive layers 120A, 120B, 120C, and 120D are arranged spaced apart from each other. Conductive layers 120D and 120F function as the first electrode 32 of the capacitive element SC2.

[0105] As shown in Figures 12 and 14, the oxide semiconductor layer 122 includes oxide semiconductor layers 122A, 122B, 122C, 122D, and 122E. The oxide semiconductor layers 122A, 122B, 122C, 122D, and 122E are provided in the same layer. The oxide semiconductor layers 122A, 122B, 122C, and 122D are arranged spaced apart from each other.

[0106] Furthermore, as shown in Figures 12 and 15, the gate electrode 127 includes gate electrodes 127A, 127B, 127C, and 127D. The gate electrodes 127A, 127B, 127C, and 127D are provided on the same layer. The gate electrodes 127A, 127B, 127C, and 127D are arranged spaced apart from each other.

[0107] As shown in Figures 12 and 16, the opening 135 includes openings 135A to 135I and 135L to 135T. The opening 135 may penetrate the insulating layer 128, the insulating layer 128 and the gate insulating layer 125, and the insulating layer 128, the gate insulating layer 125 and the insulating layer 121. Also, as shown in Figure 12, the conductive layer 132 includes conductive layers 132A to 132K. The conductive layers 132A to 132K are provided in the same layer. The conductive layers 132A to 132K are arranged spaced apart from each other.

[0108] [2-2. Configuration of the capacitive element CS2 and reset transistor T2 of pixel 502] Next, the configurations of the capacitive element CS2 and the reset transistor T2 will be described with reference to Figures 12 to 18. Configurations identical or similar to those in Figures 1 to 11 will be described as necessary.

[0109] The end face of pixel 502 shown in Figure 17 is an example of the end face of the capacitive element CS2 and reset transistor T2, and is the end face along the conductive layer 132A (output signal line 420), conductive layer 132F (drive power line PVDD), oxide semiconductor layer 122E, conductive layer 120D, conductive layer 120C, gate electrode 127D (gate electrode 622), conductive layer 132F (drive power line PVDD), opening 135L, and conductive layer 132I (reset potential line SVR).

[0110] The end face of pixel 502 shown in Figure 18 is the end face of the region obtained by translating the end face shown in Figure 17 along the first direction D1, and is the end face along the conductive layer 132A (output signal line 420), conductive layer 132F (drive power line PVDD), conductive layer 132K (drive power line PVDD), oxide semiconductor layer 122E, conductive layer 120D, opening 135I, and conductive layer 132I (reset potential line SVR).

[0111] The gate electrode 127C (gate electrode 632) includes a gate electrode 127C1 that functions as the gate electrode of the drive transistor T3, and a gate electrode 127C2 that extends in the first direction D1 and is electrically connected to the gate electrode 127C1. The conductive layer 132F also includes a conductive layer 132F1 that extends in the first direction D1, a conductive layer 132F3+132K that is superimposed on the conductive layer 120D+120F and oxide semiconductor layer 122E that constitute the capacitive element CS2 and has a larger area than the conductive layer 120D+120F and oxide semiconductor layer 122E, and a conductive layer 132F2 that electrically connects the conductive layer 132F1 and the conductive layer 132F3+132K.

[0112] As shown in Figure 12, the capacitive element CS2 has a configuration in which the conductive layer 120D+120F, the oxide semiconductor layer 122E, and the conductive layer 132F3+132K are superimposed on each other in a plan view. Also, as shown in Figures 17 and 18, the insulating layer 121 is sandwiched between the conductive layer 120D+120F and the oxide semiconductor layer 122E, and the insulating layer 128 and the gate insulating layer 125 are sandwiched between the oxide semiconductor layer 122E and the conductive layer 132F3+132K. Furthermore, as shown in Figure 18, the conductive layer 132F+132K is electrically connected to the conductive layer 120D+120F through an opening 135I that penetrates the insulating layer 121, the gate insulating layer 125, and the insulating layer 128 to expose the conductive layer 120D. In other words, the capacitive element CS2 consists of a capacitance formed by a conductive layer 120D+120F and an oxide semiconductor layer 122E with an insulating layer 121 in between, and a capacitance formed by an oxide semiconductor layer 122E and a conductive layer 132F3+132K with an insulating layer 128 and a gate insulating layer 125 in between.

[0113] As shown in Figures 12, 14, or 17, the reset transistor T2 includes an oxide semiconductor layer 122D, a gate insulating layer 125, and a gate electrode 127D. The gate electrode 127D faces the oxide semiconductor layer 122D. The gate insulating layer 125 is provided between the oxide semiconductor layer 122D and the gate electrode 127D. The oxide semiconductor layer 122D is provided on the first surface 101A side of the gate electrode 127D. The oxide semiconductor layer 122D also faces the conductive layer 120D, which is located on the first surface 101A with an insulating layer 121 in between.

[0114] In a plan view, the oxide semiconductor layer 122B in the region overlapping with the gate electrode 127D (gate electrode 622) functions as a semiconductor layer (channel) of the reset transistor T2 and switches between a conductive state and a non-conductive state depending on the voltage supplied to the gate electrode 127D. In other words, in a plan view, the oxide semiconductor layer 122D in the region not overlapping with the gate electrode 127D functions as a conductive layer of the reset transistor T2 and is the first electrode 624 and the second electrode 626. Also, in a plan view, the oxide semiconductor layer 122E in the region not overlapping with the gate electrode 127D functions as the second electrode 34 of the capacitive element SC2. The oxide semiconductor layer 122D is electrically connected to the oxide semiconductor layer 122E. That is, the oxide semiconductor layer 122D + 122E functions as both a semiconductor layer and a conductive layer of the reset transistor T2, as well as the second electrode 34 of the capacitive element SC2.

[0115] In the second embodiment of the solid-state imaging device, the oxide semiconductor layers 122D, 122E, and 122B in the pixel 502 are integrated, and the conductive layer 132F+132K in the pixel 502 of the solid-state imaging device in the second embodiment is an integrated conductive layer 132F1, conductive layer 132F2, conductive layer 132F3, and 132K. Furthermore, the oxide semiconductor layer 122E, which is part of node N2, is superimposed on the conductive layer 132F3. The conductive layer 132F3 is the first electrode 32 of the capacitive element SC2, and a constant voltage drive voltage PVDD is supplied to the conductive layer 132F3. Therefore, because the conductive layer 132F3 is positioned between node N2 (oxide semiconductor layer 122E) and the lower electrode of the photoelectric conversion element 110, the conductive layer 132F3 can cover the oxide semiconductor layer 122E, which is part of node N2, and shield the lower electrode of the photoelectric conversion element 110 from the oxide semiconductor layer 122E. Furthermore, since the oxide semiconductor layer 122E is not formed on the conductive layer 132, the oxide semiconductor layer 122E can suppress parasitic capacitance due to coupling with node N1 formed by the conductive layer 132D. As a result, the capacitance value between the conductive layer 132F (drive power line PVDD) and node N2 can be increased, and the parasitic capacitance between node N2 and node N1 can be reduced.

[0116] Furthermore, by integrating the oxide semiconductor layers 122D, 122E, and 122B, the number of openings 135 between the conductive layer 132 and the oxide semiconductor layer 122, and the number of openings 135 between the conductive layer 132 and the oxide semiconductor layer 122 can be reduced. Therefore, the area of ​​the conductive layer 132F3, the area of ​​the conductive layer 120D, and the area of ​​the oxide semiconductor layer 122 constituting the capacitive element SC2 can be increased. As a result, the capacitance value between the conductive layer 132F (drive power line PVDD) and node N2 can be increased.

[0117] As a result, similar to the solid-state imaging device 100 according to the first embodiment, the solid-state imaging device according to the second embodiment has a configuration that can reduce parasitic capacitance due to coupling and has a configuration that can increase the ratio of capacitance value to power supply voltage, thereby suppressing the effects of coupling and noise. Therefore, similar to the solid-state imaging device 100 according to the first embodiment, the solid-state imaging device according to the second embodiment has a configuration that is highly reliable over the long term.

[0118] [3. Third Embodiment] Referring to Figures 19 to 31, an overview of the solid-state imaging device according to the third embodiment will be described. Figure 19 is a circuit diagram showing the pixel circuit of pixel 502 of the solid-state imaging device according to the third embodiment. Figures 20 to 28 are diagrams showing an example of the layout of pixel 502 of the solid-state imaging device according to the third embodiment. Figure 29 is an end view showing the end face of the capacitive element CS2 cut along F1-F2 in the planar layout of pixel 502 shown in Figure 20. Figure 30 is an end view showing the end face of the capacitive element CS2 cut along G1-G2 in the planar layout of pixel 502 shown in Figure 20. Figure 31 is an end view showing the end face of the capacitive element CS3 cut along H1-H2 in the planar layout of pixel 502 shown in Figure 21. The configuration of pixel 502 of the solid-state imaging device according to the third embodiment shown in Figures 19 to 31 is an example and is not limited to the example shown in Figures 19 to 31. Configurations identical or similar to those in Figures 1 to 18 will be described as necessary.

[0119] The pixel 502 of the solid-state imaging device according to the third embodiment includes the configurations shown in (6) to (15) below. The configurations shown in (6) to (15) mainly differ from the configuration of the pixel 502 of the solid-state imaging device 100 according to the first embodiment. (6) Includes a capacitive element SC3 electrically connected between node N2 and reference potential line PVSS. The capacitive element SC3 includes a first electrode 42 and a second electrode 44. The first electrode 42 is electrically connected to the reference potential line PVSS, and the second electrode 44 is electrically connected to node N2. (7) Includes an opening 138B, conductive layers 139A and 139B, a light-emitting diode 150A, a conductive layer 145A, a conductive layer 148A, a conductive layer 149A, openings 147A and 147B, and openings 146A and 146B. (8) The conductive layer 132F3 in the solid-state imaging device 100 according to the first embodiment is reduced in size and includes a conductive layer 132L in which conductive layers 132I, 132F3, 132E and 132H are integrated. (9) The position of the reset transistor T2 is changed to the side that moves away from the conductive layer 132F along the second direction D2, and the positions of the openings 135N and 135M are changed to opening 135N and opening 135M in order of proximity to the conductive layer 132F. (10) The conductive layer 132I is electrically connected to the conductive layer 120F via the opening 135L, and the conductive layer 120F is electrically connected to the oxide semiconductor layer 122D via the opening 135V, the conductive layer 132K, and the opening 135U. The oxide semiconductor layer 122D is supplied with a reset voltage VRES via the conductive layer 132I, the opening 135L, the conductive layer 120F, the opening 135V, the conductive layer 132K, and the opening 135U. (11) The oxide semiconductor layer 122D is electrically connected to the conductive layer 132L via the opening 135J, without the gate electrodes 127C3 and 127C2, and the opening 135K. (12) The oxide semiconductor layer 122B is electrically connected to the conductive layer 132K via the opening 135E, without the opening 135H. (13) The capacitive element SC2 is composed of a conductive layer 132L, a gate electrode 127E, and an insulating layer 128 between the conductive layer 132L and the gate electrode 127E. The conductive layer 132L is the second electrode 34, and the gate electrode 127E is the first electrode 32. (14) The gate electrode 127E is electrically connected to the conductive layer 132F (drive power line PVDD) through the opening 135W, and the gate electrode 127E is supplied with the drive voltage VPP. (15) Conductive layers 148A and 149A are electrically connected to conductive layer 139A via openings 147A and 146A. Conductive layer 132L corresponds to the second electrode 44, and conductive layers 148A, 149A and 139A correspond to the first electrode 42.

[0120] The configurations of the pixel 502 of the solid-state imaging device according to the third embodiment, as shown in (6) to (15), and configurations other than those related to the configurations shown in (6) to (15) of the pixel 502 of the solid-state imaging device according to the third embodiment, are the same as those of the pixel 502 of the solid-state imaging device 100 according to the first embodiment. Therefore, here we will mainly describe the differences from the pixel 502 of the solid-state imaging device 100 according to the first embodiment. When describing the configuration and function of the pixel 502 of the solid-state imaging device according to the third embodiment, configurations and functions similar to those of the pixel 502 of the solid-state imaging device 100 according to the first embodiment will be described as necessary. In addition, configurations that are the same as or similar to those in Figures 1 to 27 will be described as necessary.

[0121] [3-1. Circuit configuration of pixel 502] Referring to Figure 19, the pixel circuit included in pixel 502 of the solid-state imaging device of the third embodiment will be described.

[0122] As explained in (6) above, the pixel 502 of the solid-state imaging device of the third embodiment includes a capacitive element SC3. The capacitance value of capacitive element SC1 is denoted by Cdiode, the capacitance value of capacitive element SC2 is denoted by Css, and the capacitance value of capacitive element SC3 is denoted by Cst.

[0123] [3-2. Layout of 502 pixels] Next, with reference to Figures 19 to 25, an overview of the layout of the pixels 502 of the solid-state imaging apparatus according to the third embodiment will be described. Configurations identical or similar to those in Figures 1 to 18 will be described as necessary.

[0124] The layout of pixel 502 shown in Figure 20 is similar to the layout of pixel 502 shown in Figure 5, showing a conductive layer 120, an oxide semiconductor layer 122, a gate electrode 127B, a conductive layer 132, openings 135, 138A, and 137, with layers above conductive layer 139 omitted from the side closer to the first surface 101A along the third direction.

[0125] The layout of pixel 502 shown in Figure 21 includes openings 138A and 137, 138B as described in (7) above, conductive layers 139A and 139B, light-emitting diode 150A, conductive layer 145A, conductive layer 148A, conductive layer 149A, openings 147A and 147B, and openings 146A and 146B. Along the third direction, layers below conductive layer 139 are omitted from the side closer to the first surface 101A. In addition, to clearly show that conductive layer 139A is superimposed on conductive layer 132L, and conductive layer 139B is superimposed on and electrically connected to conductive layer 132D, conductive layers 132L and 132D, which are layers below conductive layer 139A, are shown in Figure 21 along the third direction D3.

[0126] To make each layer easier to understand, Figure 22 shows the layout of the conductive layer 120, Figure 23 shows the layout of the oxide semiconductor layer 122, Figure 24 shows the layout of the gate electrode 127, Figure 25 shows the layout in which the conductive layer 120, oxide semiconductor layer 122, conductive layer 132, gate electrode 127 and opening 135 are superimposed, and Figure 26 shows the superimposed conductive layer 132L, openings 138A and 138B, opening 137, conductive layers 139A and 139B are superimposed. Figure 27 shows a superimposed layout of conductive layer 132L, openings 138A and 138B, opening 137, conductive layers 139A and 139B, and light-emitting diode 150A. Figure 28 shows a superimposed layout of conductive layer 132L, openings 138A and 138B, opening 137, conductive layers 139A and 139B, light-emitting diode 150A, openings 146A and 146B, and openings 147A and 147B.

[0127] As shown in Figures 20 and 22, the conductive layer 120 includes conductive layers 120A (read signal line 410), 120B (data transfer signal line 412), 120C (reset signal line 414), 120E, and 120F. Conductive layers 120A, 120B, 120C, 120E, and 120F are provided on the same layer. Conductive layers 120A, 120B, 120C, 120E, and 120F are arranged spaced apart from each other. The pixel according to the third embodiment, compared to the pixel 502 according to the first embodiment, does not include conductive layer 120D but includes conductive layer 120F.

[0128] As shown in Figures 20 and 23, the oxide semiconductor layer 122 includes oxide semiconductor layers 122A, 122B, 122C, and 122D, similar to the oxide semiconductor layer 122 of the pixel 502 according to the first embodiment. The oxide semiconductor layers 122A, 122B, 122C, and 122D are provided in the same layer. The oxide semiconductor layers 122A, 122B, 122C, and 122D are arranged spaced apart from each other.

[0129] As shown in Figures 20 and 24, the gate electrode 127 includes gate electrodes 127A (gate electrode 642), 127B (gate electrode 612), 127C, 127D (gate electrode 622), and 127E. As described in (13) above, gate electrode 127E functions as the first electrode 32 and is supplied with a drive voltage VPP. The gate electrodes 127A, 127B, 127C, 127D, and 127E are provided in the same layer. The gate electrodes 127A, 127B, 127C, 127D, and 127E are spaced apart from each other.

[0130] As shown in Figures 20 and 25, the opening 135 includes openings 135A to 135G, 135J, and 135L to 135V. The opening 135 does not include openings 135H and 135I. The opening 135 may penetrate the insulating layer 128, the insulating layer 128 and the gate insulating layer 125, and the insulating layer 128, the gate insulating layer 125, and the insulating layer 121. Also, as shown in Figure 20, the conductive layer 132 includes conductive layers 132A to 132G and 132I to 132L. The conductive layers 132A to 132G and 132I to 132L are provided in the same layer. The conductive layers 132A to 132G and 132I to 132L are arranged spaced apart from each other.

[0131] As shown in Figures 21 and 26, the opening 138 includes openings 138A and 138B. After the insulating layer 131 is formed, the opening 137 penetrates the insulating layer 131 to expose the conductive layer 132D. After the opening 137 exposes the conductive layer 132D, the insulating layer 136 is formed. The opening 138A penetrates the insulating layer 136 to expose the conductive layer 132D. The opening 138B penetrates the insulating layer 136 to expose the insulating layer 131. The conductive layer 139 includes conductive layers 139A and 139B. The conductive layers 139A and 139B are provided in the same layer, and the conductive layers 139A and 139B are arranged spaced apart from each other. The insulating layer 131 sandwiched between the conductive layer 139A and the conductive layer 132L, the conductive layer 139A, and the conductive layer 132L form a capacitive element SC3. The conductive layer 139B is electrically connected to the conductive layer 132D through openings 137 and 138A.

[0132] As shown in Figures 21 and 27, the light-emitting diode 150 includes a light-emitting diode 150A. As shown in Figures 21 and 28, the opening 146 includes openings 146A and 146B, and the opening 147 includes openings 147A and 147B. The opening 146 penetrates the insulating layer 141, and the opening 147 penetrates the insulating layer 151. Also, as shown in Figure 21, the conductive layer 149 includes a conductive layer 149A, and the conductive layer 148 includes a conductive layer 148A. The conductive layer 149 is in contact with and covers the conductive layer 148.

[0133] [3-3. Configuration of the capacitive element CS2 and reset transistor T2 of pixel 502] Next, the configuration of the capacitive element CS2 and reset transistor T2 according to the third embodiment will be described with reference to Figures 20, 22-25, 29, and 30. Configurations identical or similar to those in Figures 1-19 will be described as necessary.

[0134] The end face of the pixel 502 according to the third embodiment shown in Figure 29 is an example of the end face of the capacitive element CS2 and the reset transistor T2, and is an end face along the conductive layer 132A (output signal line 420), conductive layer 132L, gate electrode 127E, opening 135J, oxide semiconductor layer 122D, conductive layer 120C, gate electrode 127D (gate electrode 622), conductive layer 132K, opening 135U, opening 135V, conductive layer 120F, conductive layer 132F (drive power line PVDD), opening 135L, and conductive layer 132I (reset potential line SVR).

[0135] The end face of the pixel 502 according to the third embodiment shown in Figure 30 is the end face of a region obtained by translating the end face shown in Figure 29 along the first direction D1, and is the end face along the conductive layer 132A (output signal line 420), conductive layer 132L, gate electrode 127E, conductive layer 132F (drive power line PVDD), opening 135W, and conductive layer 132I (reset potential line SVR).

[0136] As shown in Figure 20, the capacitive element CS2 according to the third embodiment has a configuration in which the gate electrode 127E and the conductive layer 132L are superimposed in a plan view. Also, as shown in Figures 29 and 30, an insulating layer 128 is sandwiched between the gate electrode 127E and the conductive layer 132L. Furthermore, as shown in Figure 29, the conductive layer 132L is electrically connected to the oxide semiconductor layer 122D through an opening 135J that penetrates the insulating layer 128 and the gate insulating layer 125 to expose the oxide semiconductor layer 122D. Furthermore, as shown in Figure 30, the conductive layer 132F (drive power line PVDD) is electrically connected to the gate electrode 127E through an opening 135J that penetrates the insulating layer 128 to expose the gate electrode 127E. In other words, the capacitive element CS2 consists of a capacitance formed by a conductive layer 120D+120F and an oxide semiconductor layer 122E with an insulating layer 128 in between, and a capacitance formed by a gate electrode 127E and a conductive layer 132L with an insulating layer 128 in between. At this time, the gate electrode 127E is electrically connected to the conductive layer 132F (drive power line PVDD), and the gate electrode 127E is supplied with drive power VPP from the conductive layer 132F (drive power line PVDD).

[0137] As shown in Figures 20, 23, or 29, the reset transistor T2 according to the third embodiment includes a configuration similar to that of the reset transistor T2 according to the first embodiment. For example, the oxide semiconductor layer 122B in the region that overlaps with the gate electrode 127D (gate electrode 622) in a plan view functions as a semiconductor layer (channel) of the reset transistor T2 and is switched between a conductive state and a non-conductive state depending on the voltage supplied to the gate electrode 127D. In other words, the oxide semiconductor layer 122D in the region that does not overlap with the gate electrode 127D in a plan view functions as a conductive layer of the reset transistor T2 and is the first electrode 624 and the second electrode 626. Furthermore, in the reset transistor T2 according to the third embodiment, the portion of the oxide semiconductor layer 122D in the region that does not overlap with the gate electrode 127D in a plan view that functions as the second electrode 34 of the capacitive element SC2 is electrically connected to the conductive layer 132L via an opening 135J. On the other hand, in the reset transistor T2 according to the third embodiment, the portion of the oxide semiconductor layer 122D that does not overlap with the gate electrode 127D in a plan view, which functions as the first electrode 32 of the capacitive element SC2, is electrically connected to the conductive layer 132I (reset potential line SVR) via an opening 135U that exposes the oxide semiconductor layer 122D, an opening 135K that exposes the conductive layer 120F, the conductive layer 120F, and an opening 135L that exposes the conductive layer 120F.

[0138] [3-4. Configuration of the capacitive element CS3 and photoelectric conversion element 110 of pixel 502] Next, the configuration of the capacitive element CS3 and the photoelectric conversion element 110 according to the third embodiment will be described with reference to Figures 20, 26-28, and 31. Configurations identical or similar to those in Figures 1-30 will be described as necessary.

[0139] The end face of the pixel 502 according to the third embodiment shown in Figure 31 is an example of the end face of the capacitive element CS3 and the photoelectric conversion element 110, and is an end face along conductive layer 149A, conductive layer 148A, conductive layer 139A, conductive layer 132L, opening 138A, conductive layer 139B, light-emitting diode 150A, conductive layer 145A, conductive layer 149A, and conductive layer 148A.

[0140] As shown in Figure 21, the capacitive element CS3 according to the third embodiment has a configuration in which, in a plan view, the conductive layer 139A covers the conductive layer 132L, and the conductive layer 139A is superimposed on the conductive layer 132L. That is, the area of ​​the conductive layer 139A is larger than the area of ​​the conductive layer 132L. Also, as shown in Figure 31, the insulating layer 131 is sandwiched between the conductive layer 132L and the conductive layer 139A. The conductive layer 132L is electrically connected to the oxide semiconductor layer 122D, which functions as the second electrode 44 of the capacitive element SC3, and when the reset transistor T2 becomes conductive, the reset voltage VRES is supplied to the conductive layer 132L. The conductive layer 139A is also electrically connected to the conductive layer 132L through an opening 146A that penetrates the insulating layer 141 and exposes the conductive layer 132L, and an opening 147A that penetrates the insulating layer 151. The conductive layer 139A functions as the first electrode 42 of the capacitive element SC3. As shown in Figure 19, the first electrode 42 is electrically connected to the reference potential line PVSS and supplied with the reference voltage VSS. That is, the conductive layer 139A is electrically connected to the reference potential line PVSS and supplied with the reference voltage VSS.

[0141] As shown in Figures 21, 26-28, or 31, the photoelectric conversion element 110 according to the third embodiment includes the same configuration as the photoelectric conversion element 110 according to the first embodiment. For example, in a plan view, the conductive layer 145A is superimposed on the light-emitting diode 150A, the light-emitting diode 150A is superimposed on the conductive layer 139B, the area of ​​the conductive layer 139B is larger than the area of ​​the light-emitting diode 150A, and the area of ​​the light-emitting diode 150A is larger than the area of ​​the conductive layer 145A. Also, the conductive layer 149A covers the conductive layer 148A, and the conductive layer 149A is superimposed on the conductive layer 148A. That is, the area of ​​the conductive layer 149A is larger than the area of ​​the conductive layer 148A. Furthermore, the conductive layer 149A is electrically connected to the conductive layer 145A through an opening 146B that penetrates the insulating layer 141 and exposes the conductive layer 145A, and through an opening 147B that penetrates the insulating layer 151.

[0142] Furthermore, referring to Figures 5, 19, 20, or 21, the conductive layer 139B is electrically connected to the conductive layer 132D via openings 147A and 138A. The conductive layer 139B corresponds to the second electrode 14 of the photoelectric conversion element 110, and the conductive layer 139B is electrically connected to node N1, the first electrode 614 of the data transfer transistor T1, and the second electrode 24 of the capacitive element SC1.

[0143] Referring to Figure 20 or Figure 21, in the third embodiment of the solid-state imaging apparatus, the region in which the conductive layer 132L in pixel 502 overlaps with the conductive layer 139B (lower electrode) of the photoelectric conversion element 110 is a small peripheral region including the region in which the conductive layer 132L overlaps with the openings 135S and 135T. Furthermore, although the conductive layer 139B (lower electrode) overlaps with node N1, as described above, the region in which the conductive layer 139B (lower electrode) overlaps with node N2 is small. Therefore, almost no parasitic capacitance due to coupling with node N1 is added to node N2.

[0144] Therefore, the pixel 502 of the solid-state imaging device according to the third embodiment includes a configuration that can suppress the addition of parasitic capacitance to node N2 due to the superposition of node N2 and the conductive layer 139B, and also includes a configuration that can suppress parasitic capacitance due to coupling with node N1. Furthermore, since the pixel 502 of the solid-state imaging device according to the third embodiment includes a capacitive element SC3, the capacitance value can be increased from CSss to CSss+CSst. As a result, the capacitance value Css between the gate electrode 127E to which the conductive layer 132F (drive power line PVDD) is connected and node N2 can be increased, and the parasitic capacitance between node N2 and node N1 can be reduced.

[0145] For example, as shown in Table 2, in a conventional solid-state imaging device, the proportion of capacitance value added to node N2 is approximately 14% attributable to node N1 and approximately 68% attributable to the drive voltage line PVDD and reference potential line PVSS. Also, as shown in Table 2, in the solid-state imaging device 100 of the present invention, the proportion of capacitance value added to node N2 is approximately 2% attributable to node N1 and approximately 92% attributable to the drive voltage line PVDD and reference potential line PVSS. Therefore, the configuration of the capacitive elements SC2 and SC3 of the solid-state imaging device 100 has a capacitance value attributable to node N1 that is smaller than that of the capacitive element SC2 of a conventional solid-state imaging device, and a capacitance value attributable to the drive voltage line PVDD and reference potential line PVSS that is larger than that of the capacitive element SC2 of a conventional solid-state imaging device.

[0146] [Table 2]

[0147] As a result, similar to the solid-state imaging device 100 according to the first embodiment, the solid-state imaging device according to the third embodiment has a configuration that can reduce parasitic capacitance due to coupling and has a configuration that can increase the ratio of capacitance value to power supply voltage, thereby suppressing the effects of coupling and noise. Therefore, similar to the solid-state imaging device 100 according to the first embodiment, the solid-state imaging device according to the third embodiment has a configuration that is highly reliable over the long term.

[0148] The various configurations of the detection device (solid-state imaging device) illustrated as one embodiment of the present invention can be combined as appropriate, as long as they do not contradict each other. Furthermore, the various configurations of the detection device (solid-state imaging device) illustrated as one embodiment of the present invention can be replaced as appropriate, as long as they do not contradict each other. Based on the detection device (solid-state imaging device) disclosed in this specification and drawings, any additions, deletions, or design changes made by those skilled in the art, or additions, omissions, or changes in processes, are also included within the scope of the present invention, as long as they retain the gist of the present invention.

[0149] Any effects or benefits other than those brought about by the embodiments disclosed herein are to be understood to be brought about by the present invention if they are clear from the description herein or can be easily predicted by a person skilled in the art. [Explanation of Symbols]

[0150] 12: First electrode, 14: Second electrode, 22: First electrode, 24: Second electrode, 32: First electrode, 34: Second electrode, 42: First electrode, 44: Second electrode, 60: Pixel circuit, 100: Solid-state imaging device, 101A: First surface, 101B: Second surface, 110: Photoelectric conversion element, 120: Conductive layer, 120A: Conductive layer, 120B: Conductive layer, 120C: Conductive layer, 120D: Conductive layer, 120E: Conductive layer, 120F: Conductive layer, 121: Insulating layer, 122: Oxide semiconductor layer, 122A: Oxide semiconductor layer, 122B: Oxide semiconductor layer, 122C: Oxide semiconductor layer, 122D: Oxide Semiconductor layer, 122E: Oxide semiconductor layer, 125: Gate insulating layer, 127: Gate gate, 127A: Gate gate, 127B: Gate gate, 127C: Gate gate, 127C1: Gate gate, 127C2: Gate gate, 127C3: Gate gate, 127D: Gate gate, 127E: Gate gate, 128: Insulating layer, 131: Insulating layer, 132: Conductive layer, 132A: Conductive layer, 132B: Conductive layer, 132C: Conductive layer, 132D: Conductive layer, 132E: Conductive layer, 132F: Conductive layer, 132F1: Conductive layer, 132F2: Conductive layer, 132F3: Conductive layer, 132G: Conductive layer, 132 H: conductive layer, 132I: conductive layer, 132J: conductive layer, 132K: conductive layer, 132L: conductive layer, 135: opening, 135A: opening, 135B: Open hole, 135C: Open hole, 135D: Open hole, 135E: Open hole, 135F: Open hole, 135G: Open hole, 135H: Open hole, 135I: Open hole, 135 J: Open hole, 135K: Open hole, 135L: Open hole, 135M: Open hole, 135N: Open hole, 135O: Open hole, 135P: Open hole, 135Q: Open hole, 1 35R: Open hole, 135S: Open hole, 135T: Open hole, 135U: Open hole, 135V: Open hole, 135W: Open hole, 136: Insulating layer, 137: Open hole: 1 38: Opening, 138A: Opening, 138B: Opening, 139: Conductive layer, 139A: Conductive layer, 139B: Conductive layer, 141: Insulating layer, 142: n-type semiconductor layer, 143: Semiconductor layer, 144: p-type semiconductor layer, 145: Conductive layer, 145A: Conductive layer, 146: Opening, 146A: Opening, 146B: Opening, 147: Opening, 147A: Opening, 147B: Opening, 147D: Opening, 148: Conductive layer, 148A: Conductive layer, 149: Conductive layer, 149A: Conductive layer, 150: Light-emitting diode, 150A: Light-emitting diode, 151: Insulating layer, 152: Insulating layer, 153: Insulating layer, 170: Array section,200: Power supply circuit, 300: Drive timing control circuit, 400: Row selection circuit, 410: Signal line, 412: Data transfer signal line, 414: Reset signal line, 420: Output signal line, 502: Pixel, 504: Pixel section, 600: Circuit, 612: Gate electrode, 614: First electrode, 616: Second electrode, 622: Gate electrode, 624: First electrode, 626: Second electrode, 632: Gate electrode, 634: First electrode, 636: Second electrode, 642: Gate electrode, 644: First electrode, 646: Second electrode, 700: Signal processing circuit,

Claims

1. A photoelectric conversion element electrically connected to the first node, A first transistor comprising a first oxide semiconductor layer electrically connected between the first node and the second node, A second transistor comprising a second oxide semiconductor layer provided in the same layer as the first oxide semiconductor layer and connected between the second node and a reset potential line to which a constant voltage is supplied, A first capacitive element comprising: a first conductive layer laminated beneath the same layer and electrically connected to a power line supplying a power voltage; an electrode layer laminated on top of the same layer and electrically connected to the second node; and a second conductive layer laminated on top of the electrode layer and electrically connected to the power line; A detection device that includes [this].

2. The detection device according to claim 1, wherein, in a plan view, the second conductive layer is superimposed on the electrode layer, and the electrode layer is superimposed on the first conductive layer.

3. The second conductive layer is provided in the same layer as the power line and the reset potential line. The detection device according to claim 1, wherein the second conductive layer, the power line, and the reset potential line are arranged to be spaced apart from each other.

4. The first transistor includes a gate electrode and a lower gate electrode, In an end-face view, the first oxide semiconductor layer is provided between the lower gate electrode and the gate electrode, the lower gate electrode is arranged in the same layer as the first conductive layer, and the gate electrode is laminated on the lower gate electrode and arranged in the same layer as the electrode layer. In a plan view, the first oxide semiconductor layer, the gate electrode, and the lower gate electrode are superimposed. The first oxide semiconductor layer superimposed on the gate electrode is a channel, and the first oxide semiconductor layer, apart from the channel, includes a first electrode and a second electrode of the first oxide semiconductor layer. The detection device according to claim 1, wherein the first electrode is electrically connected to the electrode layer, and the second electrode is electrically connected to the first node.

5. The second transistor includes a gate electrode and a lower gate electrode, In an end-face view, the second oxide semiconductor layer is provided between the lower gate electrode and the gate electrode, the lower gate electrode is arranged in the same layer as the first conductive layer, and the gate electrode is laminated on the lower gate electrode and arranged in the same layer as the electrode layer. In a plan view, the second oxide semiconductor layer, the gate electrode, and the lower gate electrode are superimposed. The second oxide semiconductor layer superimposed on the gate electrode is a channel, and the second oxide semiconductor layer, apart from the channel, includes the first electrode and the second electrode of the second oxide semiconductor layer. The detection device according to claim 1, wherein the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the reset potential line.

6. It further includes a third transistor, The third transistor includes a third oxide semiconductor layer, a gate electrode, and a lower gate electrode. The third oxide semiconductor layer is arranged in the same layer. In an end-face view, the third oxide semiconductor layer is provided between the lower gate electrode of the third transistor and the gate electrode of the third transistor, and the lower gate electrode of the third transistor is located in the same layer as the first conductive layer. The gate electrode of the third transistor is disposed on the second conductive layer as the same conductive layer that also serves as the electrode layer. In a plan view, the third oxide semiconductor layer, the gate electrode of the third transistor, and the lower gate electrode of the third transistor are superimposed. The third oxide semiconductor layer superimposed on the gate electrode of the third transistor is a channel, and the third oxide semiconductor layer, apart from the channel, includes the first electrode and the second electrode of the third transistor. The detection device according to claim 1, wherein the gate electrode of the third transistor is electrically connected to the second node, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the power line.

7. It further includes a fourth transistor, The fourth transistor includes a fourth oxide semiconductor layer, a gate electrode, and a lower gate electrode. The fourth oxide semiconductor layer is arranged in the same layer. In an end-face view, the fourth oxide semiconductor layer is provided between the lower gate electrode of the fourth transistor and the gate electrode of the fourth transistor, and the lower gate electrode of the fourth transistor is located in the same layer as the first conductive layer. The gate electrode of the fourth transistor is located in the same layer as the electrode layer. In a plan view, the fourth oxide semiconductor layer, the gate electrode of the fourth transistor, and the lower gate electrode of the fourth transistor are superimposed. The fourth oxide semiconductor layer superimposed on the gate electrode of the fourth transistor is a channel, and the fourth oxide semiconductor layer, apart from the channel, includes the first electrode and the second electrode of the fourth transistor. The detection device according to claim 6, wherein the gate electrode of the fourth transistor is electrically connected to a control signal line that controls the on and off states of the fourth transistor, the second electrode of the fourth transistor is electrically connected to the third node, and the first electrode of the fourth transistor is electrically connected to an output signal line for outputting a data signal detected by the detection device.

8. A photoelectric conversion element electrically connected to the first node, A first transistor comprising a first oxide semiconductor layer electrically connected between the first node and the second node, A second transistor comprising a second oxide semiconductor layer provided in the same layer as the first oxide semiconductor layer and connected between the second node and a reset potential line to which a constant voltage is supplied, A first capacitive element comprising: a first conductive layer laminated beneath the same layer and electrically connected to a power line supplying a power voltage; a third oxide semiconductor layer disposed on the same layer and electrically connected to the second node; and a second conductive layer laminated on the third oxide semiconductor layer and electrically connected to the power line; A detection device that includes [this].

9. The detection device according to claim 8, wherein, in a plan view, the second conductive layer is superimposed on the third oxide semiconductor layer, and the third oxide semiconductor layer is superimposed on the first conductive layer.

10. The second conductive layer is provided in the same layer as the power line and the reset potential line. The detection device according to claim 8, wherein the second conductive layer, the power line, and the reset potential line are arranged to be spaced apart from each other.

11. The first transistor includes a gate electrode and a lower gate electrode, In an end-face view, the first oxide semiconductor layer is provided between the lower gate electrode and the gate electrode, the lower gate electrode is arranged in the same layer as the first conductive layer, and the gate electrode is laminated on top of the lower gate electrode. In a plan view, the first oxide semiconductor layer, the gate electrode, and the lower gate electrode are superimposed. The detection device according to claim 8, wherein the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer are arranged on the first conductive layer as a single component.

12. The second transistor includes a gate electrode and a lower gate electrode, In an end-face view, the second oxide semiconductor layer is provided between the lower gate electrode and the gate electrode, the lower gate electrode is arranged in the same layer as the first conductive layer, and the gate electrode is laminated on top of the lower gate electrode. In a plan view, the second oxide semiconductor layer, the gate electrode, and the lower gate electrode are superimposed. The detection device according to claim 8, wherein the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer are arranged on the first conductive layer as a single component.

13. It further includes a third transistor, The third transistor includes a fourth oxide semiconductor layer, a gate electrode, and a lower gate electrode. The fourth oxide semiconductor layer is arranged in the same layer as the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer. In an end-face view, the fourth oxide semiconductor layer is provided between the lower gate electrode of the third transistor and the gate electrode of the third transistor, and the lower gate electrode of the third transistor is located in the same layer as the first conductive layer. The gate electrode of the third transistor is electrically connected to the second node and the second oxide semiconductor layer, and is disposed on the second oxide semiconductor layer. In a plan view, the fourth oxide semiconductor layer, the gate electrode of the third transistor, and the lower gate electrode of the third transistor are superimposed. The fourth oxide semiconductor layer superimposed on the gate electrode of the third transistor is a channel, and the fourth oxide semiconductor layer, apart from the channel, includes the first electrode and the second electrode of the third transistor. The first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the power line. The detection device according to claim 8, wherein the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer are arranged on the first conductive layer as a single component.

14. It further includes a fourth transistor, The fourth transistor includes a fifth oxide semiconductor layer, a gate electrode, and a lower gate electrode. The fifth oxide semiconductor layer is arranged in the same layer as the first oxide semiconductor layer, the second oxide semiconductor layer, the third oxide semiconductor layer, and the fourth oxide semiconductor layer. In an end-face view, the fourth oxide semiconductor layer is provided between the lower gate electrode of the fourth transistor and the gate electrode of the fourth transistor, and the lower gate electrode of the fourth transistor is located in the same layer as the first conductive layer. The gate electrode of the fourth transistor is located on the same layer as the gate electrode of the third transistor. In a plan view, the fifth oxide semiconductor layer, the gate electrode of the fourth transistor, and the lower gate electrode of the fourth transistor are superimposed. The fifth oxide semiconductor layer superimposed on the gate electrode of the fourth transistor is a channel, and the fifth oxide semiconductor layer, apart from the channel, includes the first electrode and the second electrode of the fourth transistor. The detection device according to claim 13, wherein the gate electrode of the fourth transistor is electrically connected to a control signal line that controls the on and off states of the fourth transistor, the second electrode of the fourth transistor is electrically connected to the third node, and the first electrode of the fourth transistor is electrically connected to an output signal line for outputting a data signal detected by the detection device.

15. A photoelectric conversion element electrically connected to the first node, A first transistor comprising a first oxide semiconductor layer electrically connected between the first node and the second node, A second transistor comprising a second oxide semiconductor layer provided in the same layer as the first oxide semiconductor layer and connected between the second node and a reset potential line to which a constant voltage is supplied, A first capacitive element comprising a first conductive layer laminated on the same layer and electrically connected to a power line to which a power supply voltage is supplied, and a second conductive layer laminated on the first conductive layer and electrically connected to the second node, A second capacitive element comprising a third conductive layer disposed on the second conductive layer and electrically connected to a reference potential line to which a reference voltage is supplied, A detection device that includes [this].

16. The first capacitive element includes a first electrode and a second electrode, The second capacitive element includes a first electrode and a second electrode, The photoelectric conversion element includes a first electrode and a second electrode provided below the first electrode. The first electrode of the first capacitive element is the first conductive layer, the first electrode of the second capacitive element is the third conductive layer, and the second conductive layer serves as both the second electrode of the first capacitive element and the second electrode of the second capacitive element. In a plan view, the third conductive layer is superimposed on the second conductive layer, the second conductive layer is superimposed on the first conductive layer, the first electrode of the photoelectric conversion element is superimposed on the second electrode of the photoelectric conversion element, and the first and second electrodes of the photoelectric conversion element are arranged apart from the third and second conductive layers. In an end view, the second conductive layer is provided in the same layer as the power line and the reset potential line, the second conductive layer, the power line and the reset potential line are spaced apart from each other, the second electrode of the photoelectric conversion element is provided in the same layer as the third conductive layer, and the second electrode of the photoelectric conversion element and the third conductive layer are spaced apart from each other, as described in claim 15.

17. The first transistor described above includes a gate electrode, In an end-face view, the gate electrode is provided on the first oxide semiconductor layer, and the gate electrode is arranged in the same layer as the first conductive layer. In a plan view, the first oxide semiconductor layer and the gate electrode are superimposed. The first oxide semiconductor layer superimposed on the gate electrode is a channel, and the first oxide semiconductor layer, apart from the channel, includes a first electrode and a second electrode of the first oxide semiconductor layer. The detection device according to claim 15, wherein the first electrode is electrically connected to the second conductive layer, and the second electrode is electrically connected to the first node.

18. The second transistor includes a gate electrode and a lower gate electrode, In an end-face view, the gate electrode is provided on the second oxide semiconductor layer, and the gate electrode is arranged in the same layer as the first conductive layer. In a plan view, the second oxide semiconductor layer and the gate electrode are superimposed. The second oxide semiconductor layer superimposed on the gate electrode is a channel, and the second oxide semiconductor layer, apart from the channel, includes the first electrode and the second electrode of the second oxide semiconductor layer. The detection device according to claim 15, wherein the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the reset potential line.

19. It further includes a third transistor, The third transistor includes a third oxide semiconductor layer and a gate electrode. The third oxide semiconductor layer is arranged in the same layer. In an end-view, the gate electrode is provided on the third oxide semiconductor layer, The gate electrode of the third transistor is electrically connected to the second conductive layer. In a plan view, the third oxide semiconductor layer and the gate electrode of the third transistor are superimposed. The third oxide semiconductor layer superimposed on the gate electrode of the third transistor is a channel, and the third oxide semiconductor layer, apart from the channel, includes the first electrode and the second electrode of the third transistor. The detection device according to claim 15, wherein the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the power line.

20. It further includes a fourth transistor, The fourth transistor includes a fourth oxide semiconductor layer and a gate electrode. The fourth oxide semiconductor layer is arranged in the same layer. In an end-view, the gate electrode is provided on the fourth oxide semiconductor layer, The gate electrode of the fourth transistor is located on the same layer as the gate electrode of the third transistor. In a plan view, the fourth oxide semiconductor layer and the gate electrode of the fourth transistor are superimposed. The fourth oxide semiconductor layer superimposed on the gate electrode of the fourth transistor is a channel, and the fourth oxide semiconductor layer, apart from the channel, includes the first electrode and the second electrode of the fourth transistor. The detection device according to claim 19, wherein the gate electrode of the fourth transistor is electrically connected to a control signal line that controls the on and off states of the fourth transistor, the second electrode of the fourth transistor is electrically connected to the third node, and the first electrode of the fourth transistor is electrically connected to an output signal line for outputting a data signal detected by the detection device.

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