Semiconductor memory device and control method for semiconductor memory device

Abstract

Even when determining whether a fuse element can be written to or not using a function, the determination is made reliably in the so-called gray area. [Solution] The semiconductor memory device of the embodiment includes a data latch circuit that holds inverted data of the expected read value data of a memory cell under test during memory cell testing, and a test reference potential setting circuit that shifts a reference potential for determining the logical level of data read from the memory cell under test to the side that makes the normal determination of the potential corresponding to the expected read value data stricter, and determines the logical level of data read from the memory cell under test based on the shifted reference potential.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device and a control method for a semiconductor memory device.

Background Art

[0002] Conventionally, the determination of whether a fuse element can be written before / after writing has been made by measuring the cell current and checking the fuse resistance value. By the way, in order to measure the cell current, a waiting time for the current to stabilize is required, so the test time is long (400 to 500 msec), and the test cost is high.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Therefore, it has been attempted to reduce the test cost by adding a function to determine whether a fuse element can be written before / after writing in the function operation. However, in the prior art, in a so-called gray zone where the determination result may be inverted due to voltage fluctuations or the like, it has not been possible to make a reliable determination.

[0005] The present invention has been made in view of the above, and provides a semiconductor memory device and a control method for a semiconductor memory device that can reliably make a determination even in a so-called gray zone when determining whether a fuse element can be written before / after writing in a function operation.

Means for Solving the Problems

[0006] The semiconductor memory device of the embodiment includes a data latch circuit that holds inverted data of the expected read value data of a memory cell under test during memory cell testing, and a test reference potential setting circuit that shifts a reference potential for determining the logical level of data read from the memory cell under test to the side that makes the normal determination of the potential corresponding to the expected read value data stricter, and determines the logical level of data read from the memory cell under test based on the shifted reference potential. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a schematic block diagram of the semiconductor memory device according to the embodiment. [Figure 2] Figure 2 is a detailed circuit diagram illustrating the one-shot pulse generation unit, sense amplifier control unit, and data latch / output unit. [Figure 3] Figure 3 is an explanatory diagram illustrating an example of the configuration of a fuse test control unit. [Figure 4] Figure 4 is an explanatory diagram illustrating an example of the configuration of the reference voltage generation unit. [Figure 5] Figure 5 is an explanatory diagram illustrating a specific example of a reference voltage. [Figure 6] Figure 6 is an operation timing chart of the embodiment. [Modes for carrying out the invention]

[0008] Preferred embodiments will be described below with reference to the drawings. Figure 1 is a schematic block diagram of the semiconductor memory device according to the embodiment. In Figure 1, for ease of understanding, the circuit configuration related to one fuse cell FC is shown within a fuse cell array in which multiple fuse cells FC are arranged in an array.

[0009] The semiconductor memory device 10 includes a one-shot pulse generation unit 11, a fuse test control unit 12, a reference voltage generation unit 13, a sense amplifier 14, a sense amplifier control unit 15, and a data latch / output unit 16.

[0010] The one-shot pulse generation unit 11 outputs a first reset pulse signal RST_0 and a second reset pulse signal RST_1 to the output data latch unit 16 based on the timing of the input, in synchronization with the internal clock pulse ICKp.

[0011] Here, the first reset pulse signal RST_0 is a signal to set the data held by the data latch / output unit 16 to the "L" level when the expected output value of the fuse cell FC is at the "H" level. The second reset pulse signal RST_1 is a signal to set the data held by the data latch / output unit 16 to the "H" level when the expected output value of the fuse cell FC is at the "L" level.

[0012] The fuse test control unit 12 generates first setting data TDT and second setting data TDB for setting the reference voltage Ref based on the input test enable signal TEN and read expectation value data TDI, and outputs them to the reference voltage generation unit 13.

[0013] The reference voltage generation unit 13 generates a reference voltage Ref based on the input first setting data TDT and second setting data TDB, and outputs it to one of the input terminals of the sense amplifier 14.

[0014] In this case, the reference voltage Ref is set to either Ref_N, the normal mode reference voltage used for normal data reading; Ref_H, the reference voltage used in the "H" verify readout mode when the expected output value is at the "H" level during fuse testing; or Ref_L, the reference voltage used in the "L" verify readout mode when the expected output value is at the "L" level during fuse testing.

[0015] In the aforementioned "H" verify readout mode, the reference voltage Ref_H is set higher than the reference voltage Ref_N in normal mode. In other words, the reference voltage Ref_H in “H” verify readout mode is: Ref_H > Ref_N + α (α > 0) Therefore, it is determined as the "H" level only when a voltage that is surely determined as the "H" level is input.

[0016] Similarly, the reference voltage Ref_L in the above-described "L" verify read mode is set lower than the reference voltage Ref_N in the normal mode. That is, the reference voltage Ref_L in the "L" verify read mode is Ref_L < Ref_N - β (β > 0) Therefore, it is determined as the "L" level only when a voltage that is surely determined as the "L" level is input.

[0017] The sense amplifier 14 compares the voltage of the signal RD read from the fuse cell FC with the reference voltage Ref at the timing based on the inverted sense amplifier enable signal / SAEN, and outputs it to the data latch / output section 16 as the output data OUTPUT0.

[0018] The sense amplifier control section 15 inverts the input sense amplifier enable signal and outputs the inverted sense amplifier enable signal / SAEN to the sense amplifier 14, and outputs the first sense amplifier signal SA1 and the second sense amplifier signal SA2 for controlling the data latch / output section 16 to the data latch / output section 16. The data latch / output section 16 latches and holds the output data OUTPUT0 based on the first reset pulse signal RST_0 and the second reset pulse signal RST_1 output by the one-shot pulse generation section 11, and the first sense amplifier signal SA1 and the second sense amplifier signal SA2 output by the sense amplifier control section 15.

[0019] FIG. 2 is a detailed circuit explanatory diagram of the one-shot pulse generation section, the sense amplifier control section, and the data latch / output section.

[0020] The one-shot pulse generation unit 11 includes a buffer circuit 11A to which an internal clock pulse ICKp is input, a delay circuit 11B that delays the output of the buffer circuit 11A, a first reset pulse signal generation circuit 11C which generates a first reset pulse signal RST_0 when first setting data TDT is input to one input terminal and the output of the delay circuit 11B is input to the other input terminal, and a second reset pulse signal generation circuit 11D which generates a second reset pulse signal RST_1 when second setting data TDB is input to one input terminal and the output of the delay circuit 11B is input to the other input terminal.

[0021] The sense amplifier control unit 15 receives the sense amplifier enable signal SAEN as input, outputs an inverted sense amplifier enable signal / SAEN, which is the inverted signal of the sense amplifier enable signal SAEN, to the enable terminal of the sense amplifier 14, outputs the sense amplifier enable signal SAEN as the first sense amplifier signal SA1 to the data latch / output unit 16, and outputs the inverted sense amplifier enable signal / SAEN as the second sense amplifier signal SA2 to the data latch / output unit 16.

[0022] The data latch / output unit 16 latches and holds the output data from the sense amplifier 14 during normal read mode. In addition, during "H" verify mode and "L" verify mode, the data latch / output unit 16 outputs the first reset pulse signal RST_0 or the second reset pulse signal RST_1 output by the one-shot pulse generation unit 11.

[0023] When a one-shot pulse is input as the first reset pulse signal RST_0, the data latch / output unit 16 sets itself to "H" verify read mode and holds "L" data as inverted data of the expected value data. Furthermore, when a one-shot pulse is input as the second reset pulse signal RST_1, the data latch / output unit 16 sets itself to "L" verify read mode and holds "H" data as inverted expected value data.

[0024] Next, the fuse test control unit 12 will be described in detail. Figure 3 is an explanatory diagram illustrating an example of the configuration of a fuse test control unit. The fuse test control unit 12 includes a first hold latch circuit 14A that receives and holds a test enable signal TEN from the memory controller MC, a second hold latch circuit 14B that receives and holds read expectation value data TDI from the memory controller MC, and a setting data generation unit 14C that, when the test enable signal TEN is at the "L" level, i.e., in non-test mode, sets both the first setting data TDT and the second setting data TDB to the "H" level or both to the "L" level, and when the test enable signal TEN is at the "H" level, i.e., in test mode, sets one of them to the "H" level and the other to the "L" level based on the read expectation value data TDI.

[0025] Next, the reference voltage generation unit 13 will be explained in detail. In the following explanation, the read enable signal EN is assumed to be an "L" active signal. That is, data can be read from the fuse cell FC when the read enable signal EN is at the "L" level.

[0026] Figure 4 is an explanatory diagram illustrating an example of the configuration of the reference voltage generation unit. The reference voltage generation unit 13 comprises, broadly speaking, a first voltage divider resistor R11, a voltage divider resistor selection circuit 13A equipped with a plurality of second voltage divider resistors R21 to R24, a logic circuit 13B, and a first voltage divider resistor connection circuit 13C.

[0027] The first voltage divider resistor connection circuit 13C electrically disconnects the first voltage divider resistor R11 from the high-potential power supply and the voltage divider resistor selection circuit 13A when the read-out enable signal EN is at the "H" level, and connects the first voltage divider resistor R11 to the high-potential power supply and the voltage divider resistor selection circuit 13A when the read-out enable signal EN is at the "L" level.

[0028] Based on the first setting data TDT and the second setting data TDB, the logic circuit 13B outputs a first voltage divider select signal RSL1 and a second voltage divider select signal RSL2 to select the second voltage divider resistors R21 to R24 connected to the first voltage divider resistor in the voltage divider resistor select circuit 13A.

[0029] Then, based on the first setting data TDT and the second setting data TDB, the logic circuit 13B outputs a first voltage divider selection signal RSL1 and a second voltage divider selection signal RSL2 such that, when the expected read value data TDI is at the "L" level, the combined resistance value of the second voltage divider selected by the voltage divider selection circuit 13A becomes lower than the resistance value of the second voltage divider when the operating mode is normal read mode.

[0030] More specifically, if we assume that the resistance values ​​of the second voltage divider resistors R21 to R24 are all equal, then in normal read mode, the second voltage divider resistor selection signal RSL1 is set to the "H" level and the second voltage divider resistor selection signal RSL2 is set to the "L" level, thereby connecting the second voltage divider resistors R21 and R24 to the first voltage divider resistor R11.

[0031] In this case, for example, by setting the first voltage divider selection signal RSL1 to the "H" level and the second voltage divider selection signal RSL2 to the "H" level, all of the second voltage divider resistors R21 to R24 are connected to the first voltage divider resistor R11, or by setting the first voltage divider selection signal RSL1 to the "L" level and the second voltage divider selection signal RSL2 to the "H" level, the second voltage divider resistors R22 to R24 are connected to the first voltage divider resistor R11, thereby increasing the number of parallel connections of the second voltage divider resistors compared to the normal readout mode, and thus lowering the combined resistance value of the second voltage divider resistors.

[0032] Also, when the read expected value data TDI is at the "H" level, based on the first setting data TDT and the second setting data TDB, the logic circuit 13B outputs the voltage division resistor selection signals RSL1 and RSL2 such that the combined resistance value of the second voltage division resistor selected in the voltage division resistor selection circuit 13A is higher than the resistance value of the second voltage division resistor in the case where the operation mode is the normal read mode.

[0033] In this case, for example, by setting the first voltage division resistor selection signal RSL1 = "L" level and the second voltage division resistor selection signal RSL2 = "L" level, only the second voltage division resistor R24 is connected to the first voltage division resistor R11, and the number of parallel second voltage division resistors is reduced compared to the normal read mode, so that the combined resistance value of the second voltage division resistor becomes higher.

[0034] FIG. 5 is an explanatory diagram of a specific example of the reference voltage. As shown in FIG. 5, when the reference voltage Ref = Ref_N in the normal read mode, when the read expected value data TDI is at the "H" level, the reference voltage Ref = Ref_H>Ref_N is set.

[0035] As a result, the potential of the data read from the fuse cell FC is not determined to be at the "H" level unless it is higher than that in the normal read mode. Therefore, it can be determined that the data read from the fuse cell FC has a higher potential level and is surely at the "H" level.

[0036] On the other hand, when the read expected value data TDI is at the "L" level, the reference voltage Ref = Ref_L<Ref_N is set. As a result, the potential of the data read from the fuse cell FC is not determined to be at the "L" level unless it is lower than that in the normal read mode. Therefore, it can be determined that the data read from the fuse cell FC has a lower potential level and is surely at the "L" level.

[0037] As a result, even with fluctuations in potential levels caused by noise, etc., it is possible to more reliably determine between "H" and "L" levels, and to reliably determine the read data even in the so-called gray area where fluctuations in potential levels may cause the determination result to be reversed.

[0038] Next, an example of the operation of the embodiment will be described. Figure 6 is an operation timing chart of the embodiment. In this embodiment, as described above, there are three modes: normal read mode, "H" verify read mode, and "L" verify read mode.

[0039] First, let's explain how it works in normal read mode. In normal readout mode, the test enable signal TEN is at the "L" level. Therefore, even if the internal clock pulse ICKp transitions to the "H" level at time t1, the first reset pulse RST_0 remains at the "L" level.

[0040] Subsequently, at time t2, when the sense amplifier enable signal SAEN transitions to "L", the sense amplifier 14 reads the data from the fuse cell FC, and the data stored in the fuse cell FC ("H" level or "L" level) is output as output data OUTPUT.

[0041] Next, we will explain the operation in "H" verify read mode. First, assuming that the test enable signal TEN transitions to "H" as shown at time t3, the read mode becomes either "H" verify read mode or "L" verify read mode. In this case, at time t3, the expected read value data TDI = "H", so the data in fuse cell FC after writing should be at the "H" level, and the system will switch to "H" verify read mode.

[0042] Therefore, the logic circuit 13B of the reference voltage generation unit 13 outputs a first voltage divider select signal RSL1 and a second voltage divider select signal RSL2 to select the second voltage divider resistors R21 to R24 connected to the first voltage divider resistor in the voltage divider resistor selection circuit 13A, based on the first setting data TDT and the second setting data TDB.

[0043] More specifically, logic circuit 13B outputs voltage divider selection signals RSL1 and RSL2 such that the combined resistance value of the second voltage divider selected by voltage divider selection circuit 13A is higher than the resistance value of the second voltage divider when the operating mode is normal read mode, since the read expected value data TDI is at the "H" level.

[0044] In this case, for example, by setting the first voltage divider resistor selection signal RSL1 to the "L" level and the second voltage divider resistor selection signal RSL2 to the "L" level, only the second voltage divider resistor R24 ​​is connected to the first voltage divider resistor R11, thereby reducing the number of parallel second voltage divider resistors compared to the normal readout mode and increasing the combined resistance value of the second voltage divider resistors.

[0045] As a result, the reference voltage Ref = Ref_H > Ref_N is set, so it can be reliably determined that the potential of the data read from the fuse cell FC is at the "H" level. Therefore, even if there are fluctuations in the potential level due to noise, etc., it is possible to more reliably determine that it is at the "H" level, and to reliably determine the read data even in the so-called gray area where there is a risk that the determination result will be reversed due to fluctuations in the potential level.

[0046] Then, assuming that the internal clock pulse ICKp transitions to the "H" level at time t4, the first reset pulse RST_0 transitions to the "H" level at time t5. As a result, at time t6, the data latch / output unit 16 latches data at the "L" level, which is the inverse signal of the expected read value data TDI, because TDI is at the "H" level. As a result, the output data OUTPUT will be at the "L" level.

[0047] Subsequently, at time t7, when the sense amplifier enable signal SAEN transitions to "L", the sense amplifier 14 reads the data from the fuse cell FC, and the data stored in the fuse cell FC ("H" level or "L" level) is output as output data OUTPUT.

[0048] Next, we will explain the operation in "L" verify read mode. First, as shown in the case at time t8, the test enable signal TEN remains "H", and at time t8, the expected read value data TDI = "L". Therefore, the data in fuse cell FC after writing should be at the "L" level, and the system transitions to "L" verify read mode.

[0049] Therefore, the logic circuit 13B of the reference voltage generation unit 13 outputs a first voltage divider select signal RSL1 and a second voltage divider select signal RSL2 to select the second voltage divider resistors R21 to R24 connected to the first voltage divider resistor in the voltage divider resistor selection circuit 13A, based on the first setting data TDT and the second setting data TDB.

[0050] More specifically, logic circuit 13B outputs voltage divider selection signals RSL1 and RSL2 such that the combined resistance value of the second voltage divider selected by voltage divider selection circuit 13A is lower than the resistance value of the second voltage divider when the operating mode is normal read mode, since the read expected value data TDI is at the "L" level.

[0051] More specifically, for example, by setting the first voltage dividing resistor selection signal RSL1 = "H" level and the second voltage dividing resistor selection signal RSL2 = "H" level, all of the second voltage dividing resistors R21 to R24 are connected to the first voltage dividing resistor R11, or by setting the first voltage dividing resistor selection signal RSL1 = "L" level and the second voltage dividing resistor selection signal RSL2 = "H" level, the second voltage dividing resistors R22 to R24 are connected to the first voltage dividing resistor R11. By increasing the number of parallel second voltage dividing resistors compared to the normal read mode, the combined resistance value of the second voltage dividing resistors can be made lower.

[0052] As a result, since the reference voltage Ref = Ref_L < Ref_N is set, it can be determined that the potential of the data read from the fuse cell FC is surely at the "L" level. Therefore, even if there are fluctuations in the potential level due to noise or the like, it can be more surely determined as the "H" level, and the determination of the read data can be surely performed even in the so-called gray area where there is a possibility that the determination result may be reversed due to fluctuations in the potential level.

[0053] Assuming that the internal clock pulse ICKp transitions to the "H" level at time t9, at time t10, the second reset pulse RST_1 transitions to the "L" level. As a result, at time t11, since the read expected value data TDI at the data latch / output unit 16 is at the "L" level, the "H" level data, which is the inverted signal thereof, is latched.

[0054] Thereby, the output data OUTPUT becomes the "H" level. After that, when the sense amplifier enable signal SAEN = "L" transitions at time t12, the data of the fuse cell FC is read by the sense amplifier 14, and the data ("H" level or "L" level) stored in the fuse cell FC is output as the output data OUTPUT.

[0055] In other words, according to the embodiment, based on the operating mode, the logic level of the data held by the output data latch circuit and the logic level of the memory cell under test are sequentially output via the output line from which the output data OUTPUT is output.

[0056] As described above, according to the embodiment, even when determining whether a fuse element can be written to or not using a function operation, a reliable determination can be made even in the so-called gray area. Furthermore, even in cases of previous value retention due to insufficient operating margin in the read circuit, i.e., when data writing is not performed correctly, it can be determined based on the data in the output data latch section (inverted data of the expected read value).

[0057] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0058] 10 Semiconductor memory devices 11 One-shot pulse generation unit 11A Buffer Circuit 11B Delay Circuit 11C First Reset Pulse Signal Generation Circuit 11D Second reset pulse signal generation circuit 12 Fuse Test Control Unit 13. Reference voltage generation unit 13A Voltage Divider Resistor Selection Circuit 13B Logic Circuit 13C First voltage divider resistor connection circuit 14 SenseAmp 14A First Hold Latch Circuit 14B Second Hold Latch Circuit 14C Configuration Data Generation Unit 15 Sense Amplifier Control Unit 16 Output data latch section R11 First voltage divider resistor R21~R24 Second voltage divider resistors EN Read-out enable signal FC fuse cell ICKp Internal Clock Pulse MC Memory Controller OUTPUT Output data OUTPUT0 Output data RD signal RST_0 First reset pulse signal RST_1 Second reset pulse signal Reference voltage Ref_N Reference voltage in normal mode Ref_H “H” Reference voltage in verify readout mode Ref_L “L” Reference voltage in verify readout mode RSL1 First voltage divider resistor selection signal RSL2 Second voltage divider resistor selection signal SA1 First Sense Amplifier Signal SA2 Second Sense Amplifier Signal SLR1 Second voltage divider resistor selection signal SAEN Sense Amplifier Enable Signal TDB 2nd Configuration Data TDI Readout Expected Value Data TDT 1st setting data TEN Test Enable Signal

Claims

1. A data latch circuit that holds inverted data of the expected read value of the memory cell under test during memory cell testing, The system includes a test reference potential setting circuit that shifts the reference potential for determining the logical level of the data read from the memory cell under test to a side that makes the normal determination of the potential corresponding to the expected read value data stricter, The logical level of the data read from the memory cell under test is determined based on the shifted reference potential. Semiconductor memory device.

2. The system includes a latch data generation circuit that generates inverted data based on a test enable signal to initiate the memory cell test and the read expectation data, and outputs it to the data latch circuit. The semiconductor memory device according to claim 1.

3. The latch data generation circuit includes a one-shot pulse generation circuit that generates inverted data of the read expected value data using a one-shot pulse corresponding to the read expected value data. The semiconductor memory device according to claim 2.

4. The pre-one-shot pulse generation circuit generates a first reset pulse that resets the data held by the data latch circuit to the "L" level when the read expected value data is at the "H" level. If the expected read-out data is at the "L" level, a second reset pulse is generated to reset the data held by the data latch circuit to the "H" level. The semiconductor memory device according to claim 3.

5. The system includes a sense amplifier that determines the logical level of the stored data in the memory cell under test based on the reference potential and outputs it as output data. The semiconductor memory device according to claim 1.

6. Based on the operating mode, the logic level of the data held by the data latch circuit and the logic level of the memory cell under test are sequentially output via the output line. The semiconductor memory device according to claim 5.

7. The process of storing inverted data of the expected read value of the memory cell under test during memory cell testing, A process of shifting the reference potential for determining the logical level of the data read from the memory cell under test to the side that makes the normal determination of the potential corresponding to the expected read value data stricter, A process for determining the logical level of data read from the memory cell under test based on the shifted reference potential, A control method for a semiconductor memory device equipped with the following features.

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