Wiring board, semiconductor device, and method for manufacturing a wiring board

Abstract

To provide a wiring board that can reduce manufacturing costs. [Solution] The wiring board 10 has an insulating layer 31, N-layer insulating layers 32, 33, 34 including an insulating layer 32 laminated on the upper surface of the insulating layer 31, and a cavity 40 formed in the insulating layers 32, 33, 34 and formed so as to expose a part of the upper surface of the insulating layer 31. The wiring board 10 has an electronic component 50 placed in the cavity 40 and an insulating layer 35 that fills the cavity 40 and covers the electronic component 50. The wiring board 10 has a via wiring V4 that penetrates the insulating layer 31 in the thickness direction and is connected to the first electrode 52, and a wiring layer 21B that is laminated on the lower surface of the insulating layer 31 and is electrically connected to the first electrode 52 via the via wiring V4. The cavity 40 is formed so that the opening width decreases as it approaches the insulating layer 31. The via wiring V4 is formed so that its diameter decreases as it approaches the electronic component 50.

Description

Technical Field

[0001] The present invention relates to a wiring board, a semiconductor device, and a method for manufacturing a wiring board.

Background Art

[0002] [[ID=II]] [[ID=I2]]Conventionally, a wiring board incorporating electronic components has been known (see, for example, Patent Document I). As this type of wiring board, there has been proposed one in which an electronic component is mounted on a conductive pad exposed at the bottom of a cavity formed in a plurality of insulating layers, and a filling insulating layer is formed to fill the cavity so as to cover the electronic component. Such a wiring board is manufactured, for example, by the following manufacturing method. First, a conductive pad is formed, and after forming a protective material covering the conductor pad, a plurality of insulating layers covering the conductive pad and the protective material are laminated. Subsequently, after forming a cavity that exposes the protective material by removing a predetermined region of the plurality of insulating layers, the protective material is removed to expose the conductive pad. Next, after mounting an electronic component on the conductive pad, a filling insulating layer is formed to fill the cavity and cover the electronic component. [[ID=I3]] [[ID=I4]]

Prior Art Documents

Patent Documents

[0003]

Patent Document I

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in the above - mentioned wiring board, reduction of manufacturing cost is desired.

Means for Solving the Problems

[0005] According to one aspect of the present invention, a wiring substrate having the form of a coreless substrate comprises: a first insulating layer; a first wiring layer laminated on the first insulating layer; an N-layer insulating layer (where N is a natural number of 1 or more) including a second insulating layer laminated on the first surface of the first insulating layer and formed to cover the first wiring layer; a cavity formed in the N-layer insulating layer and formed to expose a part of the first surface of the first insulating layer; an electronic component disposed in the cavity and having a first electrode covered by the first insulating layer; a filling insulating layer that fills the cavity and covers the electronic component; a first via wiring that penetrates the first insulating layer in the thickness direction and is connected to the first electrode; and a second wiring layer laminated on the second surface of the first insulating layer opposite to the first surface and electrically connected to the first electrode via the first via wiring, wherein the cavity is formed such that its opening width decreases towards the first insulating layer, and the first via wiring is formed such that its diameter decreases towards the electronic component. [Effects of the Invention]

[0006] According to one aspect of the present invention, it has the effect of reducing manufacturing costs. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a schematic cross-sectional view showing a wiring board of the first embodiment. [Figure 2] Figure 2 is a schematic cross-sectional view showing an enlarged portion of the wiring board of the first embodiment. [Figure 3] Figure 3 is a schematic cross-sectional view showing a semiconductor device of the first embodiment. [Figure 4] Figure 4 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 5] Figure 5 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 6] Figure 6 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 7]Figure 7 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 8] Figure 8 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 9] Figure 9 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 10] Figure 10 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 11] Figure 11 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 12] Figure 12 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 13] Figure 13 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 14] Figure 14 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 15] Figure 15 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 16] Figure 16 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 17] Figure 17 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 18] Figure 18 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 19] Figure 19 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 20] Figure 20 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 21] Figure 21 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 22] Figure 22 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 23] Figure 23 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 24]FIG. 24 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the first embodiment. [Figure 25] FIG. 25 is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to the first embodiment. [Figure 26] FIG. 26 is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to the first embodiment. [Figure 27] FIG. 27 is a schematic cross-sectional view showing a wiring board according to the second embodiment. [Figure 28] FIG. 28 is a schematic cross-sectional view showing a partially enlarged view of the wiring board according to the second embodiment. [Figure 29] FIG. 29 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the second embodiment. [Figure 30] FIG. 30 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the second embodiment. [Figure 31] FIG. 31 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the second embodiment. [Figure 32] FIG. 32 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the second embodiment. [Figure 33] FIG. 33 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the second embodiment. [Figure 34] FIG. 34 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the second embodiment. [Figure 35] FIG. 35 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the second embodiment. [Figure 36] FIG. 36 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the second embodiment. [Figure 37] FIG. 37 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the second embodiment. [Figure 38] FIG. 38 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the second embodiment. [Figure 39] FIG. 39 is a schematic cross-sectional view showing a method of manufacturing a wiring board according to the second embodiment. [Figure 40] FIG. 40 is a schematic cross-sectional view showing a wiring board according to the third embodiment. [Figure 41]Figure 41 is a schematic cross-sectional view showing a manufacturing method for a wiring board according to the third embodiment. [Figure 42] Figure 42 is a schematic cross-sectional view showing a manufacturing method for a wiring board according to the third embodiment. [Figure 43] Figure 43 is a schematic cross-sectional view showing a manufacturing method for a wiring board according to the third embodiment. [Figure 44] Figure 44 is a schematic cross-sectional view showing a manufacturing method for a wiring board according to the third embodiment. [Figure 45] Figure 45 is a schematic cross-sectional view showing a manufacturing method for a wiring board according to the third embodiment. [Modes for carrying out the invention]

[0008] The embodiments will be described below with reference to the attached drawings. Note that, for convenience, the attached drawings may show enlarged versions of characteristic parts to make the features easier to understand, and the dimensional ratios of each component may differ in each drawing. Furthermore, in the cross-sectional views, to make the cross-sectional structure of each member easier to understand, the hatching of some members has been replaced with a textured pattern, and the hatching of some members has been omitted. In this specification, "plan view" refers to viewing the object from the vertical direction (up and down direction in the drawing) as shown in Figure 1, etc., and "planar shape" refers to the shape of the object as viewed from the vertical direction (up and down direction in the drawing) as shown in Figure 1, etc. Also, in this specification, "up and down direction" and "left and right direction" refer to the direction in which the symbols indicating each member in each drawing are correctly readable. In this specification, "diameter" refers to the distance between the two furthest apart points in a cross-section along the horizontal direction (left and right direction in each drawing) of the object. That is, for example, if the cross-sectional shape is circular, it refers to the diameter; if the cross-sectional shape is polygonal, it refers to the length of the longest diagonal; and if the cross-sectional shape is elliptical, it refers to the major axis. Furthermore, in this specification, "facing" means that two surfaces or members are in a position facing each other, and includes not only cases where they are completely facing each other, but also cases where they are partially facing each other. In this specification, "facing" also includes cases where two members are in contact with each other, as well as cases where two members are separated from each other.

[0009] (First Embodiment) The first embodiment will be described below with reference to Figures 1 to 26. (Overall configuration of the wiring board 10) As shown in Figure 1, the wiring board 10 has a wiring structure 11, one or more (two in this embodiment) cavities 40 formed in the wiring structure 11, and one or more (two in this embodiment) electronic components 50 arranged in the cavities 40. The wiring board 10 is a wiring board with built-in electronic components 50.

[0010] (Structure of electronic component 50) As shown in Figure 2, the electronic component 50 has a main body 51, a first electrode 52 provided at the bottom of the electronic component 50, a second electrode 53 provided at the top of the electronic component 50, and a through electrode 54. The electronic component 50 in this embodiment has a plurality of first electrodes 52, a plurality of second electrodes 53, and a plurality of through electrodes 54.

[0011] Examples of electronic components 50 include semiconductor elements, crystal oscillators, chip components, and silicon bridges. Examples of chip components include chip capacitors, chip resistors, and chip inductors. The electronic components 50 embedded in the wiring board 10 are not limited to one type, but may include multiple types of electronic components 50.

[0012] The main body 51 is formed, for example, in the shape of a rectangular parallelepiped. The thickness of the main body 51 can be, for example, about 50 μm to 200 μm. The main body 51 is formed from, for example, silicon (Si) or silicon carbide (SiC).

[0013] For the materials of the first electrode 52, the second electrode 53, and the through electrode 54, for example, metals such as aluminum (Al) and copper (Cu), or alloys containing at least one metal selected from these metals can be used.

[0014] Each first electrode 52 is formed to be embedded in the main body 51, for example. The lower surface of each first electrode 52 is formed to be exposed from the lower surface of the main body 51. The lower surface of each first electrode 52 is formed to be flush with the lower surface of the main body 51, for example. The thickness of the first electrode 52 can be, for example, about 2 μm to 20 μm. Each first electrode 52 may also be formed to protrude downward from the lower surface of the main body 51.

[0015] Each second electrode 53 is provided on the opposite side of the first electrode 52. Each second electrode 53 is formed to protrude upward from, for example, the upper surface of the main body 51. The thickness of the second electrode 53 can be, for example, about 2 μm to 20 μm. Each second electrode 53 may also be formed to be embedded in the main body 51.

[0016] Each through electrode 54 is formed to penetrate the main body 51 in the thickness direction. Each through electrode 54 extends linearly along the thickness direction of the main body 51, for example. Each through electrode 54 electrically connects the first electrode 52 and the second electrode 53 to each other.

[0017] (Structure of wiring structure 11) The wiring structure 11 has a structure in which a wiring layer 20, a solder resist layer 30, a wiring layer 21, an insulating layer 31, a wiring layer 22, an insulating layer 32, a wiring layer 23, an insulating layer 33, a wiring layer 24, an insulating layer 34, an insulating layer 35, a wiring layer 25, an insulating layer 36, a wiring layer 26, an insulating layer 37, a wiring layer 27, and a solder resist layer 38 are sequentially stacked. Unlike wiring substrates manufactured using a general build-up method, that is, those in which the required number of build-up layers are sequentially formed and stacked on both sides or one side of a core substrate as a support substrate, the wiring substrate 10 of this embodiment has the form of a so-called coreless substrate that does not include a support substrate. For convenience, in this embodiment, the solder resist layer 30 side of the wiring substrate 10 in Figure 2 is referred to as the lower side or one side, and the solder resist layer 38 side is referred to as the upper side or the other side. Furthermore, in this embodiment, for convenience, the side of each portion facing the solder resist layer 30 will be referred to as one side or the bottom side, and the side facing the solder resist layer 38 will be referred to as the other side or the top side. However, the wiring board 10 can be used upside down or positioned at any angle.

[0018] For example, copper or copper alloys can be used as the material for wiring layers 20, 21, 22, 23, 24, 25, 26, and 27. The thickness of each wiring layer 20, 21, 22, 23, 24, 25, 26, and 27 can be, for example, about 1 μm to 35 μm. The line / space (L / S) of wiring layers 20, 21, and 22 is smaller than the line / space of wiring layers 23, 24, 25, 26, and 27. The line / space of wiring layers 20, 21, and 22 can be, for example, about 2 μm / 2 μm to 3 μm / 3 μm. The line / space (L / S) of wiring layers 23, 24, 25, 26, and 27 can be, for example, about 3 μm / 3 μm to 50 μm / 50 μm. Here, in line / space, "line" represents the wiring width, and "space" represents the distance between adjacent wirings (wiring spacing). For example, if line / space is specified as 10μm / 10μm~50μm / 50μm, it means that the wiring width is 10μm or more and 50μm or less, and the wiring spacing between adjacent wirings is 10μm or more and 50μm or less. Note that the wiring width and wiring spacing do not necessarily have to be equal.

[0019] The insulating layers 31, 32, 33, 34, 35, 36, and 37 are insulating layers mainly composed of, for example, a non-photosensitive resin. The insulating layers 31, 32, 33, 34, 35, 36, and 37 can be mainly composed of, for example, thermosetting non-photosensitive resins such as epoxy resins, imide resins, phenolic resins, and cyanate resins. The solder resist layers 30 and 38 are insulating layers mainly composed of, for example, a photosensitive insulating resin mainly composed of phenolic resins or polyimide resins can be used as the material for the solder resist layers 30 and 38.

[0020] The wiring layer 20 is laminated on the underside of the solder resist layer 30. The wiring layer 20 is formed to protrude downward from the underside of the solder resist layer 30. The wiring layer 20 is, for example, the outermost (in this case, the bottommost) wiring layer of the wiring substrate 10. The wiring layer 20 functions, for example, as a chip mounting pad for electrically connecting to a semiconductor chip 110 (see Figure 3). That is, the side on which the wiring layer 20 is formed is the chip mounting surface.

[0021] The wiring layer 20 comprises a wiring layer 20A and a wiring layer 20B. Wiring layer 20A is electrically connected to wiring layer 21 via via wiring V1 that penetrates the solder resist layer 30 in the thickness direction. Wiring layer 20A is formed integrally with, for example, the via wiring V1. Wiring layer 20A and via wiring V1 are provided in a position that does not overlap with the electronic component 50 in a plan view. Wiring layer 20B is electrically connected to wiring layer 21 via via wiring V2 that penetrates the solder resist layer 30 in the thickness direction. Wiring layer 20B is formed integrally with, for example, the via wiring V2. Wiring layer 20B and via wiring V2 are provided in a position that overlaps with the electronic component 50 in a plan view.

[0022] The diameter of via wiring V2 is smaller than the diameter of via wiring V1. The diameter of via wiring V1 can be, for example, about 20 μm to 100 μm. The diameter of via wiring V2 can be, for example, about 3 μm to 30 μm.

[0023] Furthermore, if necessary, a surface treatment layer may be formed on the surface (bottom and side surfaces, or bottom surface only) of the wiring layer 20. Examples of surface treatment layers include an Au layer, a Ni / Au layer (a metal layer formed by stacking a Ni layer and an Au layer in that order), or a Ni / Pd / Au layer (a metal layer formed by stacking a Ni layer, a Pd layer, and an Au layer in that order). Other examples of surface treatment layers include a Ni / Sn layer (a metal layer formed by stacking a Ni layer and an Sn layer in that order), a Ni / Sn / In layer (a metal layer formed by stacking a Ni layer, a Sn layer, and an In layer in that order), or a Bi layer. Here, the Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or a Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy. Also, the Sn layer is a metal layer made of Sn or an Sn alloy, the In layer is a metal layer made of In or an In alloy, and the Bi layer is a metal layer made of Bi or a Bi alloy. These Au, Ni, Pd, Sn, In, and Bi layers can be, for example, metal layers formed by electroless plating (electroless plated metal layers) or metal layers formed by electroplating (electroplated metal layers). Furthermore, as the surface treatment layer, an OSP (Organic Solderability Preservative) film formed by applying an anti-oxidation treatment such as OSP treatment to the surface of the wiring layer 20 can be used. As the OSP film, for example, an organic film such as an azole compound or an imidazole compound can be used.

[0024] An external connection terminal 60 is provided on the underside of the wiring layer 20. For example, a solder ball can be used as the external connection terminal 60. For example, Sn-Ag, Sn-Cu, or Sn-Ag-Cu lead-free solder can be used as the material for the solder ball. The external connection terminal 60 has an external connection terminal 60A provided on the underside of the wiring layer 20A and an external connection terminal 60B provided on the underside of the wiring layer 20B. The external connection terminal 60B is formed to be smaller in diameter than the external connection terminal 60A. The pitch of the external connection terminal 60B is smaller than the pitch of the external connection terminal 60A. The pitch of the external connection terminal 60A can be, for example, about 60 μm to 150 μm. The pitch of the external connection terminal 60B can be, for example, about 10 μm to 100 μm.

[0025] The solder resist layer 30 is formed on the lower surface of the insulating layer 31 so as to cover the wiring layer 21. The solder resist layer 30 is formed so as to cover the lower surface and sides of the wiring layer 21. The solder resist layer 30 is formed so as to cover the upper surface of the wiring layer 20. The thickness from the lower surface of the wiring layer 21 to the lower surface of the solder resist layer 30 can be, for example, about 12 μm to 50 μm.

[0026] The wiring layer 21 is laminated on the lower surface (second surface) of the insulating layer 31. The wiring layer 21 has a wiring layer 21A and a wiring layer 21B. The wiring layer 21A is electrically connected to the wiring layer 22 via a via wiring V3 that penetrates the insulating layer 31 in the thickness direction. The wiring layer 21A is formed integrally with the via wiring V3, for example. The wiring layer 21A is electrically connected to the wiring layer 20A via a via wiring V1. The wiring layer 21A and the via wiring V3 are provided in positions that do not overlap with the electronic component 50 in a plan view, for example. The wiring layer 21B is electrically connected to the first electrode 52 of the electronic component 50 via a via wiring V4 that penetrates the insulating layer 31 in the thickness direction. The wiring layer 21B is formed integrally with the via wiring V4, for example. The wiring layer 21B is electrically connected to the wiring layer 20B via a via wiring V2. The wiring layer 21B and via wiring V4 are provided, for example, in a position that overlaps with the electronic component 50 in a plan view.

[0027] Via wiring V4 is formed with a smaller diameter than via wiring V3. The diameter of via wiring V3 can be, for example, about 20 μm to 100 μm. The diameter of via wiring V4 can be, for example, about 3 μm to 30 μm.

[0028] Here, via wirings V1, V2, V3, and V4 are formed in a tapered shape, for example, in Figure 2, where the diameter decreases from the bottom side (solder resist layer 30 side) to the top side (wiring layer 22 side or first electrode 52 side). Via wirings V1, V2, V3, and V4 are formed in a frustoconical shape, where the diameter of the upper surface is smaller than the diameter of the lower surface.

[0029] The insulating layer 31 is formed on the lower surface of the insulating layer 32 so as to cover the wiring layer 22. The insulating layer 31 is formed so as to cover the lower surface of the wiring layer 22. The insulating layer 31 is formed on the upper surface of the solder resist layer 30 so as to cover the upper surface of the wiring layer 21. The insulating layer 31 has a protrusion 31A that protrudes from the upper surface of the insulating layer 31 toward the cavity 40. The insulating layer 31 is a single layer. The protrusion 31A is provided inside the cavity 40. The protrusion 31A is provided so as to overlap with the electronic component 50 in a plan view. The protrusion 31A is formed so as to cover the lower surface of the electronic component 50. The protrusion 31A is formed so as to cover the lower surface of the main body 51 and the lower surface of the first electrode 52. The thickness of the protrusion 31A can be, for example, about 0.1 μm to 25 μm. The thickness from the bottom surface of the wiring layer 22 to the bottom surface of the insulating layer 31 can be, for example, about 5 μm to 40 μm.

[0030] The wiring layer 22 is laminated on the upper surface (first surface) of the insulating layer 31. The lower surface of the wiring layer 22 is exposed from the lower surface of the insulating layer 32. The lower surface of the wiring layer 22 is formed flush with, for example, the lower surface of the insulating layer 32.

[0031] The insulating layer 32 is formed on the upper surface (first surface) of the insulating layer 31 so as to cover the wiring layer 22. The insulating layer 32 is formed so as to cover the upper surface and side surfaces of the wiring layer 22. The thickness from the upper surface of the wiring layer 22 to the upper surface of the insulating layer 32 can be, for example, about 15 μm to 60 μm.

[0032] The wiring layer 23 is laminated on the upper surface of the insulating layer 32. The wiring layer 23 is electrically connected to the wiring layer 22 via via wiring V5 that penetrates the insulating layer 32 in the thickness direction. The wiring layer 23 is formed integrally with, for example, the via wiring V5. The wiring layer 23 is positioned so as not to overlap with the cavity 40 in a plan view.

[0033] The insulating layer 33 is formed on the upper surface of the insulating layer 32 so as to cover the wiring layer 23. The insulating layer 33 is formed so as to cover the upper and side surfaces of the wiring layer 23. The thickness from the upper surface of the wiring layer 23 to the upper surface of the insulating layer 33 can be, for example, about 15 μm to 60 μm.

[0034] The wiring layer 24 is laminated on the upper surface of the insulating layer 33. The wiring layer 24 is electrically connected to the insulating layer 33 via via wiring V6 that penetrates the insulating layer 33 in the thickness direction. The wiring layer 24 is formed integrally with, for example, the via wiring V6. The wiring layer 24 is positioned so as not to overlap with the cavity 40 in a plan view.

[0035] The insulating layer 34 is formed on the upper surface of the insulating layer 33 so as to cover the wiring layer 24. The insulating layer 34 is formed so as to cover the upper and side surfaces of the wiring layer 24. The thickness from the upper surface of the wiring layer 24 to the upper surface of the insulating layer 34 can be, for example, about 10 μm to 40 μm.

[0036] Each cavity 40 is formed in the insulating layers 32, 33, and 34. Each cavity 40 is formed to be recessed downward from the upper surface of the insulating layer 34. Each cavity 40 is formed to penetrate the insulating layers 32, 33, and 34 in the thickness direction. Each cavity 40 is formed to expose, for example, a portion of the upper surface of the insulating layer 31. Each cavity 40 is formed to correspond to the embedded electronic component 50. That is, each cavity 40 is formed at the mounting position of the electronic component 50.

[0037] The cavity 40 is formed in a tapered shape, for example, in Figure 2, where the opening width decreases from the top (top surface of the insulating layer 34) to the bottom (side of the insulating layer 31). That is, the cavity 40 is formed so that the upper opening widens relative to the lower opening. The space enclosed by the inner wall surface of the cavity 40, the upper surface of the insulating layer 31 exposed from the cavity 40, and the upper surface of the protrusion 31A, i.e., the internal space of the cavity 40, becomes a housing space for accommodating the electronic component 50. Thus, in the wiring board 10 of this example, the three insulating layers 32, 33, and 34 serve as insulating layers for cavity formation.

[0038] The insulating layer 35 is a filling insulating layer that fills the cavity 40. The insulating layer 35 is formed to cover the upper surface of the insulating layer 34 and to fill the cavity 40 and cover the electronic component 50. The insulating layer 35 is formed to cover the entire inner wall surface of the cavity 40. The insulating layer 35 is formed to cover the electronic component 50 as a whole, for example. For example, the insulating layer 35 is formed to cover the upper and side surfaces of the main body 51. The insulating layer 35 is formed to cover the upper and side surfaces of the second electrode 53, for example.

[0039] A recess 35X is provided on the lower surface of the insulating layer 35 in the portion filled in the cavity 40. The recess 35X is formed to recess upward from the lower surface of the insulating layer 35. The recess 35X is formed to expose the lower surface of the electronic component 50. The recess 35X is located in a position that overlaps with the electronic component 50 in a plan view. The recess 35X is filled with, for example, a protruding portion 31A of the insulating layer 31.

[0040] The insulating layer 35 is formed, for example, to cover the entire upper surface of the insulating layer 34. The thickness from the upper surface of the insulating layer 34 to the upper surface of the insulating layer 35 can be, for example, about 5 μm to 30 μm.

[0041] The wiring layer 25 is formed on the upper surface of the insulating layer 35. The wiring layer 25 has a wiring layer that is electrically connected to the wiring layer 24 via a via wiring V7 that penetrates the insulating layers 34 and 35 in the thickness direction. The wiring layer 25 has a wiring layer that is electrically connected to the second electrode 53 of the electronic component 50 via a via wiring V8 that penetrates the insulating layer 35 in the thickness direction. The wiring layer 25 is formed integrally with, for example, the via wiring V7 or the via wiring V8. The wiring layer 25 may be routed in a planar direction on the upper surface of the insulating layer 35 (specifically, in a direction perpendicular to the stacking direction of the wiring board 10). Furthermore, the wiring layer 25 routed in a planar direction in this way may electrically connect the wiring layer 25 connected to the wiring layer 24 and the wiring layer 25 connected to the second electrode 53 to each other.

[0042] The insulating layer 36 is formed on the upper surface of the insulating layer 35 so as to cover the wiring layer 25. The insulating layer 36 is formed so as to cover the upper and side surfaces of the wiring layer 25. The thickness from the upper surface of the wiring layer 25 to the upper surface of the insulating layer 36 can be, for example, about 15 μm to 60 μm.

[0043] The wiring layer 26 is laminated on the upper surface of the insulating layer 36. The wiring layer 26 is electrically connected to the wiring layer 25 via via wiring V9 that penetrates the insulating layer 36 in the thickness direction. The wiring layer 26 is formed integrally with, for example, the via wiring V9.

[0044] The insulating layer 37 is formed on the upper surface of the insulating layer 36 so as to cover the wiring layer 26. The insulating layer 37 is formed so as to cover the upper and side surfaces of the wiring layer 26. The thickness from the upper surface of the wiring layer 26 to the upper surface of the insulating layer 37 can be, for example, about 15 μm to 60 μm.

[0045] The wiring layer 27 is laminated on the upper surface of the insulating layer 37. The wiring layer 27 is electrically connected to the wiring layer 26 via via wiring V10 that penetrates the insulating layer 37 in the thickness direction. The wiring layer 27 is formed integrally with, for example, the via wiring V10. The wiring layer 27 is, for example, the outermost (in this case, the topmost) wiring layer of the wiring board 10.

[0046] Here, vias V5, V6, V7, V8, V9, V10 are formed in a tapered shape, for example, in Figure 2, where the diameter decreases from the upper side (solder resist layer 38 side) to the lower side (underside of insulating layer 32). Vias V5, V6, V7, V8, V9, V10 are formed in an inverted frustoconical shape where the diameter of the upper surface is larger than the diameter of the lower surface. Thus, vias V5, V6, V7, V8, V9, V10 formed above the wiring layer 22 are formed in an inverted frustoconical shape where the diameter decreases toward the wiring layer 22. On the other hand, vias V1, V2, V3, V4 formed below the wiring layer 22 are formed in a frustoconical shape where the diameter decreases toward the wiring layer 22. In other words, the structures of vias V1, V2, V3, V4 and vias V5, V6, V7, V8, V9, V10 are different from each other with respect to the wiring layer 22. Furthermore, in the wiring structure 11, the laminated structure of the wiring layer and the insulating layer differs between the upper and lower sides of the wiring layer 22. Note that via wirings V2 and V4 are formed with a smaller diameter than via wirings V1, V3, V5, V6, V7, V8, V9, and V10.

[0047] The solder resist layer 38 is formed on the upper surface of the insulating layer 37 so as to cover the wiring layer 27. The solder resist layer 38 is formed so as to cover the upper and side surfaces of the wiring layer 27. The solder resist layer 38 is the outermost insulating layer provided on the outermost layer (in this case, the top layer) of the wiring substrate 10. The thickness from the upper surface of the wiring layer 27 to the upper surface of the solder resist layer 38 can be, for example, about 12 μm to 50 μm.

[0048] The solder resist layer 38 has openings 38X formed in it to expose a portion of the upper surface of the top wiring layer 27 as a connecting pad. A surface treatment layer 61 is formed on the wiring layer 27 exposed through the openings 38X, if necessary. As the surface treatment layer 61, metal layers such as an Au layer, Ni layer / Au layer, Ni layer / Pd layer / Au layer, or an OSP film can be used.

[0049] (Structure of semiconductor device 1) Next, the structure of the semiconductor device 1 will be described according to Figure 3. The semiconductor device 1 comprises a substrate 70, a wiring board 10 mounted on the substrate 70, an underfill resin 100, one or more (four in this embodiment) semiconductor chips 110 mounted on the wiring board 10, and an underfill resin 120. Note that in Figure 3, the wiring board 10 shown in Figures 1 and 2 is shown rotated by 180°.

[0050] (Configuration of circuit board 70) The substrate 70 has a core substrate 71. As the core substrate 71, for example, a so-called glass epoxy substrate can be used, which is made by impregnating glass cloth with a thermosetting insulating resin such as epoxy resin. As the core substrate 71, for example, a substrate may be used in which woven or nonwoven fabrics such as glass fibers, carbon fibers, or aramid fibers are impregnated with a thermosetting insulating resin such as epoxy resin. Note that the illustration of glass cloth, etc. is omitted in each figure.

[0051] The core substrate 71 has a plurality of through holes 72 that penetrate the core substrate 71 in the thickness direction. Through electrodes 73 that penetrate the core substrate 71 in the thickness direction are formed on the inner wall surface of the through holes 72. The center of the through holes 72, specifically the through holes 72 inside the through electrodes 73, is filled with a resin portion 74. For example, copper or a copper alloy can be used as the material for the through electrodes 73. For example, an insulating resin such as epoxy resin can be used as the material for the resin portion 74.

[0052] The core substrate 71 has one or more (two in this embodiment) openings 75 that penetrate the core substrate 71 in the thickness direction. Electronic components 76 are housed inside the openings 75. The openings 75 are filled with a resin portion 77 so as to cover the electronic components 76. The resin portion 77 is formed to cover, for example, the bottom and sides of the electronic components 76. Examples of electronic components 76 include semiconductor elements, crystal oscillators, chip components, and silicon bridges. Examples of chip components include chip capacitors, chip resistors, and chip inductors. Note that the electronic components 76 embedded in the substrate 70 are not limited to one type, but may be multiple types of electronic components 76. As the material for the resin portion 77, for example, an insulating resin such as epoxy resin can be used.

[0053] The substrate 70 has a wiring structure on the lower surface of the core substrate 71 in which a wiring layer 81, an insulating layer 82, a wiring layer 83, an insulating layer 84, a wiring layer 85, an insulating layer 86, a wiring layer 87, and a solder resist layer 88 are sequentially stacked. The substrate 70 also has a wiring structure on the upper surface of the core substrate 71 in which a wiring layer 91, an insulating layer 92, a wiring layer 93, an insulating layer 94, a wiring layer 95, an insulating layer 96, a wiring layer 97, and a solder resist layer 98 are sequentially stacked.

[0054] For the wiring layers 81, 83, 85, 87, 91, 93, 95, and 97, for example, copper or copper alloys can be used as materials. The thickness of each wiring layer 81, 83, 85, 87, 91, 93, 95, and 97 can be, for example, about 8 μm to 40 μm. The insulating layers 82, 84, 86, 92, 94, and 96 are insulating layers mainly composed of non-photosensitive resins. The insulating layers 82, 84, 86, 92, 94, and 96 can be mainly composed of thermosetting non-photosensitive resins such as epoxy resins, imide resins, phenolic resins, and cyanate resins. The thickness of each insulating layer 82, 84, 86, 92, 94, and 96 can be, for example, about 15 μm to 100 μm. The solder resist layers 88 and 98 are insulating layers mainly composed of photosensitive resins. For example, a photosensitive insulating resin mainly composed of phenolic resin or polyimide resin can be used as the material for the solder resist layers 88 and 98. The thickness of the solder resist layers 88 and 98 can be, for example, about 12 μm to 50 μm.

[0055] The wiring layer 81 is laminated on the lower surface of the core substrate 71. The wiring layer 81 is electrically connected to the through-electrode 73. The insulating layer 82 is formed on the lower surface of the core substrate 71 to cover the wiring layer 81. The wiring layer 83 is laminated on the lower surface of the insulating layer 82. The wiring layer 83 is electrically connected to the wiring layer 81 via via wiring that penetrates the insulating layer 82 in the thickness direction. The insulating layer 84 is formed on the lower surface of the insulating layer 82 to cover the wiring layer 83. The wiring layer 85 is laminated on the lower surface of the insulating layer 84. The wiring layer 85 is electrically connected to the wiring layer 83 via via wiring that penetrates the insulating layer 84 in the thickness direction. The insulating layer 86 is formed on the lower surface of the insulating layer 84 to cover the wiring layer 85. The wiring layer 87 is laminated on the lower surface of the insulating layer 86. The wiring layer 87 is electrically connected to the wiring layer 85 via via wiring that penetrates the insulating layer 86 in the thickness direction.

[0056] The solder resist layer 88 is formed on the underside of the insulating layer 86 so as to cover the wiring layer 87. The solder resist layer 88 has an opening 88X formed therein to expose a portion of the underside of the bottommost wiring layer 87 as an external connection pad. An external connection terminal 89 is provided on the underside of the wiring layer 87 exposed through the opening 88X. For example, a solder ball can be used as the external connection terminal 89.

[0057] The wiring layer 91 is laminated on the upper surface of the core substrate 71. The wiring layer 91 is electrically connected to the wiring layer 81 via through electrodes 73. Some of the wiring layers 91 are electrically connected to electronic components 76. The insulating layer 92 is formed on the upper surface of the core substrate 71 to cover the wiring layer 91. The wiring layer 93 is laminated on the upper surface of the insulating layer 92. The wiring layer 93 is electrically connected to the wiring layer 91 via via wiring that penetrates the insulating layer 92 in the thickness direction. The insulating layer 94 is formed on the upper surface of the insulating layer 92 to cover the wiring layer 93. The wiring layer 95 is laminated on the upper surface of the insulating layer 94. The wiring layer 95 is electrically connected to the wiring layer 93 via via wiring that penetrates the insulating layer 94 in the thickness direction. The insulating layer 96 is formed on the upper surface of the insulating layer 94 to cover the wiring layer 95. The wiring layer 97 is laminated on the upper surface of the insulating layer 96. The wiring layer 97 is electrically connected to the wiring layer 95 via via wiring that penetrates the insulating layer 96 in the thickness direction.

[0058] The solder resist layer 98 is formed on the upper surface of the insulating layer 96 so as to cover the wiring layer 97. The solder resist layer 98 has an opening 98X formed therein to expose a portion of the upper surface of the topmost wiring layer 97 as a connection pad. The opening 98X is provided so as to overlap in a plan view with the opening 38X of the solder resist layer 38 of the wiring board 10.

[0059] (Structure of the wiring board 10) The wiring board 10 is mounted on the upper surface of the substrate 70. The wiring board 10 is mounted on the upper surface of the substrate 70 with the wiring layer 27 and the solder resist layer 38 facing the upper surface of the substrate 70. More specifically, the wiring layer 27 exposed through the opening 38X of the solder resist layer 38 and the wiring layer 97 exposed through the opening 98X of the solder resist layer 98 are joined to each other by a joining member 99. The joining member 99 is joined to the wiring layer 27 (specifically, the surface treatment layer 61) exposed through the opening 38X and to the wiring layer 97 exposed through the opening 98X. For example, a solder layer can be used as the joining member 99. For example, Sn-Ag, Sn-Cu, or Sn-Ag-Cu Pb-free solder can be used as the material for the solder layer. Alternatively, for example, a Cu-Ni-Sn electroplated metal layer or a copper-based ink paste can be used as the joining member 99.

[0060] In this way, the substrate 70 and the wiring board 10 are laminated and bonded via a bonding member 99 to form a semiconductor device 1 with a POP (Package on Package) structure. Here, the electronic components 76 embedded in the substrate 70 may be electrically connected to the electronic components 50 embedded in the wiring board 10 through wiring layers 91, 93, 95, 97, 27, 25, etc.

[0061] (Structure of underfill resin 100) The underfill resin 100 is provided to fill the gap between the substrate 70 and the wiring board 10. The underfill resin 100 is provided, for example, to fill the gap between the solder resist layer 98 and the solder resist layer 38. As the material for the underfill resin 100, an insulating resin such as epoxy resin can be used.

[0062] (Structure of semiconductor chip 110) Each semiconductor chip 110 is flip-chip mounted on the wiring layer 20 of the wiring board 10. Each semiconductor chip 110 is electrically connected to the wiring layer 20 of the wiring board 10 via an external connection terminal 60.

[0063] As the semiconductor chip 110, for example, logic chips such as CPU (Central Processing Unit) chips and GPU (Graphics Processing Unit) chips can be used. In addition, as the semiconductor chip 110, memory chips such as DRAM (Dynamic Random Access Memory) chips, SRAM (Static Random Access Memory) chips and flash memory chips can be used. When mounting multiple semiconductor chips 110 on the wiring board 10, logic chips and memory chips may be combined and mounted on the wiring board 10.

[0064] (Structure of underfill resin 120) The underfill resin 120 is provided to fill the gap between the wiring board 10 and the semiconductor chip 110. For example, the underfill resin 120 is provided to fill the gap between multiple semiconductor chips 110. As the material for the underfill resin 120, an insulating resin such as epoxy resin can be used.

[0065] In this embodiment, insulating layer 31 is an example of a first insulating layer, wiring layer 22 is an example of a first wiring layer, insulating layer 32 is an example of a second insulating layer, insulating layers 32, 33, and 34 are examples of N-layer insulating layers, and insulating layer 35 is an example of a filled insulating layer. Via wiring V4 is an example of a first via wiring, wiring layer 21B is an example of a second wiring layer, protrusion 31A is an example of a first protrusion, via wiring V3 is an example of a second via wiring, wiring layer 21A is an example of a third wiring layer, via wiring V2 is an example of a third via wiring, and wiring layer 20B is an example of a fourth wiring layer. Via wiring V5 is an example of a fourth via wiring, wiring layer 23 is an example of a fifth wiring layer, via wiring V8 is an example of a fifth via wiring, wiring layer 25 is an example of a sixth wiring layer, electronic component 50 is an example of a first electronic component, and electronic component 76 is an example of a second electronic component.

[0066] (Manufacturing method for wiring board 10) Next, the manufacturing method of the wiring board 10 will be described. For the sake of clarity, the parts that will ultimately become components of the wiring board 10 will be denoted by their final component reference numerals.

[0067] First, in the process shown in Figure 4, a support 200 is prepared. The support 200 has a structure in which a metal foil 202 and a metal film 203 are sequentially laminated on both the upper and lower surfaces of a substrate 201. The substrate 201 is a prepreg made by impregnating a reinforcing material such as glass, aramid, or LCP fiber woven or nonwoven fabric with a thermosetting resin such as epoxy resin or polyimide resin. The metal foil 202 is, for example, copper foil. The metal film 203 is, for example, a nickel (Ni) plated film. Note that the material of the metal foil 202 is not limited to copper, and may be a metal other than copper. Also, the material of the metal film 203 may be a metal other than nickel, as long as it is a conductive material that can be selectively etched away from the wiring layer 22 (see Figure 2) formed in a later process.

[0068] In this embodiment, although structures corresponding to a part of the wiring board 10 are formed on both the upper and lower surfaces of the support 200, for the sake of simplicity, only the structure formed on the upper surface of the support 200 will be illustrated and described.

[0069] Next, in the process shown in Figure 5, a resist layer 210 having an opening pattern 210X is formed on the upper surface of the metal film 203 of the support 200. The opening pattern 210X is formed so as to expose the upper surface of the metal film 203 in the area corresponding to the formation region of the wiring layer 22. As the material of the resist layer 210, for example, a material that is resistant to plating in the next plating process can be used. As the material of the resist layer 210, for example, a photosensitive dry film resist or a liquid photoresist (for example, a dry film resist or liquid resist such as a novolac resin or acrylic resin) can be used. When using a photosensitive dry film resist, the dry film is laminated to the upper surface of the metal film 203 by thermocompression bonding, and the dry film is patterned by photolithography to form a resist layer 210 having an opening pattern 210X. Note that when using a liquid photoresist, the resist layer 210 can also be formed by a similar process.

[0070] Next, using the resist layer 210 as a plating mask, an electrolytic plating method is applied to the metal film 203, utilizing the metal film 203 as the plating power supply layer. Specifically, an electrolytic plating method, in this case an electrolytic Cu plating method, is applied to the upper surface of the metal film 203 exposed through the opening pattern 210X of the resist layer 210. Through this process, a wiring layer 22 is formed on the upper surface of the metal film 203 exposed through the opening pattern 210X.

[0071] Next, in the process shown in Figure 6, the resist layer 210 shown in Figure 5 is removed using an alkaline stripping solution (for example, an organic amine-based stripping solution, caustic soda, acetone, or ethanol).

[0072] Next, in the process shown in Figure 7, an insulating layer 32 covering the wiring layer 22 is formed on the upper surface of the metal film 203. When a resin film is used as the insulating layer 32, for example, the resin film is laminated onto the upper surface of the metal film 203. Then, the insulating layer 32 can be formed by heat-treating the resin film at a temperature above the curing temperature (for example, around 130°C to 200°C) while pressing it down and curing it. As the resin film, for example, a thermosetting resin film mainly composed of epoxy resin can be used. Alternatively, when a liquid or paste-like insulating resin is used as the insulating layer 32, the liquid or paste-like insulating resin is applied to the upper surface of the metal film 203 by a spin-coating method or the like. Then, the insulating layer 32 can be formed by heat-treating the applied insulating resin at a temperature above the curing temperature and curing it. As the liquid or paste-like insulating resin, for example, a thermosetting resin mainly composed of epoxy resin can be used.

[0073] Next, through-holes VH5 are formed at predetermined locations in the insulating layer 32 so that a portion of the upper surface of the wiring layer 22 is exposed. The through-holes VH5 can be formed by laser processing, for example, using a CO2 laser or a UV-YAG laser.

[0074] Next, if the through-hole VH5 is formed by laser processing, a desmear treatment is performed to remove the resin smear adhering to the exposed surface of the wiring layer 22 exposed at the bottom of the through-hole VH5. Examples of desmear treatments in this step include wet desmear treatment using a potassium permanganate solution or the like.

[0075] Next, in the process shown in Figure 8, a seed layer (not shown) is formed so as to cover the entire upper surface of the insulating layer 32 and the entire inner surface of the through-hole VH5. The seed layer can be formed, for example, by sputtering or electroless plating. Subsequently, a resist layer 211 having an opening pattern 211X at a predetermined location is formed on the seed layer by performing the same process as shown in Figure 5. The opening pattern 211X is formed so as to expose the upper surface of the seed layer in the area corresponding to the formation region of the wiring layer 23. Next, using the resist layer 211 as a plating mask, an electroplating method is applied to the seed layer, using the seed layer as a plating power supply layer. As a result, via wiring V5 that fills the through-hole VH5 is formed, and the wiring layer 23 is formed within the opening pattern 211X.

[0076] Next, in the process shown in Figure 9, the resist layer 211 shown in Figure 8 is removed using an alkaline stripping solution (for example, an organic amine-based stripping solution, caustic soda, acetone, or ethanol). After that, the unnecessary seed layer is removed by etching.

[0077] Next, in the process shown in Figure 10, the insulating layer 33 and the wiring layer 24 are laminated on the upper surface of the insulating layer 32 by performing the same process as in Figures 7 to 9. Furthermore, an insulating layer 34 covering the wiring layer 24 is laminated on the upper surface of the insulating layer 33. At this time, the insulating layer 34 is formed to cover the entire upper surface and the entire side surface of the wiring layer 24.

[0078] Next, in the process shown in Figure 11, a cavity 40 is formed that is recessed from the upper surface of the insulating layer 34 toward the support 200, such that a portion of the upper surface of the metal film 203 is exposed. The cavity 40 is formed so as to penetrate the insulating layers 34, 33, and 32 in the thickness direction. The cavity 40 can be formed by laser processing, for example, using a CO2 laser or a UV-YAG laser.

[0079] Subsequently, if the cavity 40 is formed by laser processing, desmear treatment is performed to remove the resin smear adhering to the exposed surface of the metal film 203 exposed at the bottom of the cavity 40.

[0080] Next, in the process shown in Figure 12, an electronic component 50 having a main body 51, a first electrode 52, a second electrode 53, and a through electrode 54 is prepared. Subsequently, using a mounter, the electronic component 50 is fixed to the upper surface of the metal film 203 exposed from the cavity 40 via an adhesive insulating resin 55. As the insulating resin 55, for example, an adhesive can be used in which a filler is mixed into a base resin such as an epoxy resin. The thickness of the insulating resin 55 can be, for example, about 1 μm to 25 μm.

[0081] Next, in the process shown in Figure 13, an insulating layer 35 is formed to cover the upper surface of the insulating layer 34 and fill the cavity 40 by performing the same process as in Figure 7. The insulating layer 35 is formed to cover the sides of the insulating resin 55 and to cover the entire surface of the electronic component 50 exposed from the insulating resin 55. The insulating layer 35 is formed to cover the entire upper surface of the metal film 203 exposed from the insulating resin 55.

[0082] Next, in the process shown in Figure 14, through-holes VH7 are formed at predetermined locations in the insulating layers 34 and 35, penetrating the insulating layers 34 and 35 in the thickness direction and exposing a portion of the upper surface of the wiring layer 24. The through-holes VH7 can be formed, for example, by a laser processing method using a CO2 laser. In addition, through-holes VH8 are formed at predetermined locations in the insulating layer 35, penetrating the insulating layer 35 in the thickness direction and exposing a portion of the upper surface of the second electrode 53. The through-holes VH8 can be formed, for example, by a laser processing method using a CO2 laser. The through-holes VH8 may be formed in the same process as the through-holes VH7, or in a separate process from the through-holes VH7.

[0083] Next, in the process shown in Figure 15, a via wiring V7 that fills the through hole VH7 is formed by performing the same process as in Figures 8 and 9, and a wiring layer 25 that is electrically connected to the wiring layer 24 via the via wiring V7 is laminated on the upper surface of the insulating layer 35. In addition, a via wiring V8 that fills the through hole VH8 is formed, and a wiring layer 25 that is electrically connected to the second electrode 53 via the via wiring V8 is laminated on the upper surface of the insulating layer 35.

[0084] Next, in the process shown in Figure 16, the same process as in Figures 7 to 9 is performed to sequentially laminate the insulating layer 36, wiring layer 26, insulating layer 37, and wiring layer 27 on the upper surface of the insulating layer 35.

[0085] Next, in the process shown in Figure 17, a solder resist layer 38 is formed on the upper surface of the insulating layer 37, having an opening 38X to expose a portion of the upper surface of the wiring layer 27 as an external connection pad. The solder resist layer 38 can be formed, for example, by laminating a photosensitive solder resist film or by applying a liquid solder resist and patterning the resist into the required shape.

[0086] Subsequently, a surface treatment layer 61 is formed on the upper surface of the wiring layer 27 exposed through the opening 38X. The surface treatment layer 61 can be formed, for example, by electroless plating. Next, in the process shown in Figure 18, the substrate 201 of the support 200 is removed. For example, the substrate 201 is mechanically peeled off from the metal foil 202.

[0087] Next, the metal foil 202 is removed. For example, the metal foil 202 is mechanically peeled off from the metal film 203. For example, the metal foil 202 is selectively etched off from the metal film 203. As a result, the lower surface of the metal film 203 is exposed to the outside, as shown in Figure 19.

[0088] Next, the metal film 203 is removed. For example, the metal film 203 is removed by etching. The metal film 203 is selectively etched off with respect to the wiring layer 22, for example. As a result, the lower surfaces of the wiring layer 22 and the insulating layer 32 are exposed to the outside, as shown in Figure 20. At this time, the lower surfaces of the wiring layer 22 and the insulating layer 32, which were in contact with the upper surface of the metal film 203 (see Figure 19), are formed in a shape that follows the upper surface of the metal film 203 (in this case, the flat surface). Therefore, the lower surfaces of the wiring layer 22 and the insulating layer 32 are formed flush with each other.

[0089] Next, the insulating resin 55 shown in Figure 19 is removed. This exposes the lower surfaces of the electronic components 50, specifically the lower surfaces of the main body 51 and the first electrode 52, to the outside. At this time, a recess 35X is formed on the lower surface of the insulating layer 35.

[0090] Next, in the process shown in Figure 21, an insulating layer 31 is formed on the lower surface of the insulating layer 32, covering the lower surface of the wiring layer 22, by performing the same process as in Figure 7. The insulating layer 31 is formed to fill the recess 35X. This forms an insulating layer 31 having protrusions 31A that fill the recess 35X.

[0091] Next, a through-hole VH3 is formed at a predetermined location in the insulating layer 31, penetrating the insulating layer 31 in the thickness direction and exposing a portion of the lower surface of the wiring layer 22. The through-hole VH3 can be formed, for example, by a laser processing method using a CO2 laser. Furthermore, a through-hole VH4 is formed at a predetermined location in the insulating layer 31, penetrating the insulating layer 31 in the thickness direction and exposing a portion of the lower surface of the first electrode 52. The through-hole VH4 is formed so as to penetrate the insulating layer 31, including the protruding portion 31A, in the thickness direction. The through-hole VH4 can be formed, for example, by a laser processing method using a UV laser or excimer laser suitable for microfabrication. The through-hole VH4 may be formed in the same process as the through-hole VH3, or in a separate process from the through-hole VH4.

[0092] Here, the through-hole VH4 is formed to be smaller in diameter than the through-hole VH3. In this case, since the insulating layer 31 is formed on the lower surface of the insulating layer 32 and the lower surface of the wiring layer 22, which are formed on a flat surface, the lower surface of the insulating layer 31 is formed on a flat surface. For example, the lower surface of the insulating layer 31 can be formed to be flatter than the upper surface of the insulating layer 35, which covers the upper surface of the insulating layer 34 and fills the cavity 40. As a result, the thickness of the insulating layer 31 can be formed uniformly, and thus a small-diameter through-hole VH4 can be suitably formed in the insulating layer 31.

[0093] Next, in the process shown in Figure 22, a via wiring V3 that fills the through hole VH3 is formed by performing the same process as in Figures 8 and 9, and a wiring layer 21A that is electrically connected to the wiring layer 22 via the via wiring V3 is laminated on the lower surface of the insulating layer 31. In addition, a via wiring V4 that fills the through hole VH4 is formed, and a wiring layer 21B that is electrically connected to the first electrode 52 via the via wiring V4 is laminated on the lower surface of the insulating layer 31. Through this process, a wiring layer 21 having wiring layer 21A and wiring layer 21B can be formed on the lower surface of the insulating layer 31.

[0094] Next, in the process shown in Figure 23, a solder resist layer 30 having through holes VH1 and VH2 that expose a portion of the lower surface of the wiring layers 21A and 21B is formed by performing the same process as in Figure 17.

[0095] Next, in the process shown in Figure 24, via wiring V1 is formed to fill the through-hole VH1, and wiring layer 20A, which is electrically connected to wiring layer 21A via via wiring V1, is laminated on the lower surface of solder resist layer 30. In addition, via wiring V2 is formed to fill the through-hole VH2, and wiring layer 20B, which is electrically connected to wiring layer 21B via via wiring V2, is laminated on the lower surface of solder resist layer 30. Through this process, wiring layer 20 having wiring layer 20A and wiring layer 20B can be formed on the lower surface of solder resist layer 30. After that, external connection terminals 60 are formed on the lower surface of wiring layer 20. Specifically, external connection terminals 60A are formed on the lower surface of wiring layer 20A, and external connection terminals 60B are formed on the lower surface of wiring layer 20B.

[0096] The wiring board 10 of this embodiment can be manufactured through the above manufacturing process. (Method of manufacturing semiconductor device 1) Next, the manufacturing method of the semiconductor device 1 will be described with reference to Figures 25 and 26. Note that in Figures 25 and 26, the wiring board 10 shown in Figure 24 is shown rotated by 180°.

[0097] First, in the process shown in Figure 25, a substrate 70 containing electronic components 76 is manufactured. Since the substrate 70 can be manufactured by known manufacturing methods, a detailed explanation is omitted here. A bonding member 99 is formed on the wiring layer 97 exposed through the opening 98X of the solder resist layer 98 of the substrate 70.

[0098] Next, the wiring board 10 is placed above the substrate 70. At this time, the wiring board 10 is positioned so that the solder resist layer 38 faces the solder resist layer 98 of the substrate 70. Also, the wiring board 10 is positioned so that each surface treatment layer 61 faces each bonding member 99.

[0099] Next, in the process shown in Figure 26, the wiring board 10 is mounted on the substrate 70. More specifically, the surface treatment layer 61 of the wiring board 10 is bonded to the bonding member 99 of the substrate 70. As a result, the wiring layer 27 of the wiring board 10 and the wiring layer 97 of the substrate 70 are electrically connected to each other via the surface treatment layer 61 and the bonding member 99.

[0100] Next, underfill resin 100 is filled into the gap between the bonded substrate 70 and the wiring board 10, and the underfill resin 100 is cured. Subsequently, as shown in Figure 3, the semiconductor chip 110 is flip-chip mounted onto the wiring layer 20 of the wiring board 10. This electrically connects the semiconductor chip 110 to the wiring layer 20 of the wiring board 10 via the external connection terminal 60. Next, underfill resin 120 is filled into the gap between the semiconductor chip 110 and the wiring board 10, and the underfill resin 120 is cured.

[0101] By following the above manufacturing process, the semiconductor device 1 shown in Figure 3 can be manufactured. (Effects of the first embodiment) Next, the effects of the first embodiment will be explained.

[0102] (1-1) The process includes the steps of forming a wiring layer 22 on a support 200 and forming N-layer (3 layers in this embodiment) insulating layers 32, 33, 34, including an insulating layer 32 laminated on the support 200 so as to cover the wiring layer 22. The process includes the steps of forming a cavity 40 in the N-layer insulating layers 32, 33, 34 that exposes a part of the upper surface of the support 200 and fixing an electronic component 50 on the support 200 that is exposed from the cavity 40. The process includes the steps of filling the cavity 40 to form an insulating layer 35 that covers the electronic component 50, removing the support 200 and laminating an insulating layer 31 on the surface of the insulating layer 32 that was in contact with the support 200. The process includes the steps of forming a via wiring V4 that penetrates the insulating layer 31 in the thickness direction and is connected to the first electrode 52 of the electronic component 50, and a wiring layer 21B that is laminated on the lower surface of the insulating layer 31 and is electrically connected to the first electrode 52 via the via wiring V4.

[0103] In this configuration, instead of mounting the electronic component 50 on a conductive pad exposed from the cavity, as in the conventional technology, the electronic component 50 is mounted on a support 200 exposed from the cavity 40. Therefore, the formation of a protective material to cover the conductive pad can be omitted. Furthermore, compared to the conventional technology, the manufacturing process for mounting the electronic component 50 inside the cavity 40 can be simplified.

[0104] In more detail, when mounting an electronic component 50 on a conductive pad exposed from a cavity, as in the conventional technology, for example, a solder layer for connecting to the conductive pad and a film made of a thermosetting resin such as NCF (Non-Conductive Film) are provided on the underside of the electronic component 50. Then, the electronic component 50 and the conductive pad are joined by the TCB (Thermal Compression Bonding) method. Specifically, the solder layer joined to the underside of the first electrode 52 of the electronic component 50 is joined to the conductive pad by heat and pressure. More specifically, the electronic component 50 is heated with a heater while being pressed towards the conductive pad at a predetermined pressure. As a result, the solder layer melts and is joined to the conductive pad. Because specialized equipment is required to join the electronic component 50 to the conductive pad using such a TCB method, manufacturing costs increase.

[0105] In contrast, according to the manufacturing method of this embodiment, the electronic component 50 is not mounted on a conductive pad, but rather mounted on the metal film 203 of the support 200. Therefore, when mounting the electronic component 50 in the cavity 40, it is not necessary to electrically connect the first electrode 52 of the electronic component 50 to the support 200. As a result, when mounting the electronic component 50, it is not necessary to provide a solder layer on the electronic component 50 for bonding with the conductive pad, and furthermore, there is no need for a process to melt the solder layer. In other words, the electronic component 50 can be fixed on the metal film 203 without using the TCB method. Therefore, dedicated equipment for performing the TCB method is not required, and manufacturing costs can be reduced compared to the conventional technology.

[0106] (1-2) An insulating layer 31 is laminated on the lower surface of the insulating layer 32 that was in contact with the support 200, and via wiring V4 is formed that penetrates the insulating layer 31 in the thickness direction and is connected to the first electrode 52 of the electronic component 50. At this time, the lower surface of the insulating layer 32 that was in contact with the support 200 is formed as a flat surface along the upper surface of the support 200. For example, the lower surface of the insulating layer 31 can be formed as flat as the upper surface of the insulating layer 35 that fills the cavity 40. As a result, the thickness of the insulating layer 31 can be formed uniformly. Therefore, small diameter through holes VH4 can be suitably formed in the insulating layer 31, and small diameter via wiring V4 that fills the through holes VH4 can be suitably formed.

[0107] (1-3) The wiring board 10 has a solder resist layer 30 formed on the lower surface of the insulating layer 31 so as to cover the wiring layer 21B, and via wiring V2 that penetrates the solder resist layer 30 in the thickness direction and is connected to the wiring layer 21B. The wiring board 10 has a wiring layer 20B that is laminated on the lower surface of the solder resist layer 30 and is electrically connected to the wiring layer 21B via via wiring V2. With this configuration, since the solder resist layer 30 is formed on the lower surface of the insulating layer 31 which is formed on a flat surface, the lower surface of the solder resist layer 30 can be suitably formed flat. As a result, the thickness of the solder resist layer 30 can be uniformly formed. Therefore, small diameter through holes VH2 can be suitably formed in the solder resist layer 30, and small diameter via wiring V2 that fills the through holes VH2 can be suitably formed. As a result, the pitch of the external connection terminals 60B provided on the lower surface of the wiring layer 20B that are connected to the via wiring V2 can be suitably narrowed.

[0108] (1-4) The insulating layer 31 has a projection 31A that protrudes from the upper surface of the insulating layer 31 toward the cavity 40. The projection 31A is positioned within the cavity 40 and is formed to cover the first electrode 52 of the electronic component 50. The insulating layer 31 having the projection 31A is a single layer. With this configuration, via wiring V4 can be formed so as to penetrate the single-layer insulating layer 31 in the thickness direction.

[0109] (Second Embodiment) The second embodiment will be described below with reference to Figures 27 to 39. The following description will focus on the differences from the first embodiment. Components identical to those shown in Figures 1 to 26 will be denoted by the same reference numerals, and detailed explanations of each of these elements will be omitted.

[0110] (Structure of wiring board 10A) As shown in Figure 27, the wiring board 10A has a wiring structure 11A, one or more (two in this embodiment) cavities 40 formed in the wiring structure 11A, and one or more (two in this embodiment) electronic components 50 arranged in the cavities 40. The wiring board 10A is a wiring board with built-in electronic components 50.

[0111] (Wiring structure 11A structure) As shown in Figure 28, the insulating layer 32 is formed to cover the upper and side surfaces of the wiring layer 22. The insulating layer 32 has a recess 32X that is recessed upward from the lower surface of the insulating layer 32. The recess 32X is provided so as to overlap with the wiring layer 22 in a plan view. The recess 32X is formed so as to expose the lower surface of the wiring layer 22.

[0112] The insulating layer 31 has a projection 31B that protrudes upward from the upper surface of the insulating layer 31. The projection 31B is formed to fill the recess 32X. The projection 31B is formed to cover the lower surface of the wiring layer 22. In other words, the wiring layer 22 is formed on the projection 31B. Therefore, the lower surface of the wiring layer 22 is located above the lower surface of the insulating layer 32. The insulating layer 32 is formed to cover the side surface of the projection 31B.

[0113] The insulating layer 31 of this embodiment does not have a protruding portion 31A (see Figure 2) that fills the recess 35X. An insulating resin 56 is formed in the recess 35X of this embodiment. The insulating resin 56 is formed to fill the recess 35X. The insulating resin 56 is an insulating layer mainly composed of a non-photosensitive resin, for example. The insulating resin 56 can be mainly composed of a thermosetting non-photosensitive resin such as an epoxy resin, imide resin, phenolic resin, or cyanate resin. It is preferable that the material of the insulating resin 56 is the same type of material as the material that constitutes the insulating layer 31. In this embodiment, the first insulating layer is composed of a two-layer structure of the insulating layer 31 and the insulating resin 56.

[0114] Here, the electronic component 50 is fixed to the upper surface of the insulating layer 31 exposed from the cavity 40 via an insulating resin 56. In other words, the electronic component 50 is mounted on the insulating resin 56 provided on the upper surface of the insulating layer 31.

[0115] Via wiring V3 is formed to penetrate the insulating layer 31, including the protrusion 31B, in the thickness direction and connect to the wiring layer 22. Via wiring V4 is formed to penetrate the insulating layer 31 and the insulating resin 56 in the thickness direction and connect to the first electrode 52. The diameter of via wiring V4 is formed to be smaller than the diameter of via wiring V3.

[0116] In the wiring structure 11A, an insulating layer 37A and an insulating layer 37B are sequentially laminated on the upper surface of the insulating layer 36, covering the wiring layer 26. The insulating layer 37A is formed to cover the upper and side surfaces of the wiring layer 26. The insulating layer 37B is formed to cover the entire upper surface of the insulating layer 37A. The via wiring V10 is formed to penetrate the insulating layers 37A and 37B in the thickness direction and connect to the wiring layer 26. The insulating layers 37A and 37B are, for example, insulating layers mainly composed of a non-photosensitive resin. The insulating layers 37A and 37B can be mainly composed of thermosetting non-photosensitive resins such as epoxy resins, imide resins, phenolic resins, or cyanate resins.

[0117] In this embodiment, the insulating layer 31 and insulating resin 56 are examples of the first insulating layer, the insulating layer 31 is an example of the first insulating resin, the insulating resin 56 is an example of the second insulating resin, and the protruding portion 31B is an example of the second protruding portion.

[0118] (Manufacturing method for wiring board 10A) Next, the manufacturing method of the wiring board 10A will be described. For the sake of clarity, the parts that will ultimately become components of the wiring board 10A will be labeled with their final component reference numerals.

[0119] First, in the process shown in Figure 29, a support 230 is prepared. The support 230 has a structure in which a metal film 232 and a metal film 233 are sequentially laminated on both the upper and lower surfaces of a substrate 231. The substrate 231 is a prepreg made by impregnating a reinforcing material such as glass, aramid, or LCP fiber woven or nonwoven fabric with a thermosetting resin such as epoxy resin or polyimide resin. The metal film 232 is, for example, a Cu film. The metal film 233 is formed to cover the side surface of the metal film 232. The metal film 233 is formed to cover the upper or lower surface of the substrate 231 that is exposed from the metal film 232. The metal film 233 is, for example, a Cu plating film. Note that the material of the metal film 232 is not limited to copper, and may be a metal other than copper. The material of the metal film 233 is not limited to copper, and may be a metal other than copper.

[0120] In this embodiment, although structures corresponding to a part of the wiring board 10A are formed on both the upper and lower surfaces of the support 230, for the sake of simplicity, only the structure formed on the upper surface of the support 230 will be illustrated and described.

[0121] Next, in the process shown in Figure 30, a resist layer 210 having an opening pattern 210X is formed on the upper surface of the metal film 233 of the support 230. The opening pattern 210X is formed to expose the upper surface of the metal film 233 in the portion corresponding to the area where the wiring layer 22 is formed.

[0122] Next, using the resist layer 210 as a plating mask, an electroplating method is applied to the metal film 233, utilizing the metal film 233 as the plating power supply layer. More specifically, first, an electroplating method, in this case an electrolytic nickel plating method, is applied to the upper surface of the metal film 233 exposed through the opening pattern 210X of the resist layer 210. This forms a metal layer 240 on the upper surface of the metal film 233 exposed through the opening pattern 210X. The material of the metal layer 240 may be a conductive material other than nickel, as long as it can be selectively etched away from the wiring layer 22 formed in a later process. Next, an electroplating method, in this case an electrolytic copper plating method, is applied to the metal layer 240, utilizing the metal film 233 as the plating power supply layer. This forms a wiring layer 22 on the metal layer 240.

[0123] Next, in the step shown in Figure 31, the resist layer 210 shown in Figure 30 is removed using an alkaline stripping solution (for example, an organic amine-based stripping solution, caustic soda, acetone, or ethanol).

[0124] Next, in the process shown in Figure 32, the same process as in Figures 7 to 9 is performed to sequentially laminate the insulating layer 32, the wiring layer 23, the insulating layer 33, the wiring layer 24, and the insulating layer 34 on the upper surface of the metal film 233. The insulating layer 32 is formed to cover the entire side surface of the metal layer 240 and the entire side surface of the wiring layer 22.

[0125] Next, by performing the same process as shown in Figure 11, a cavity 40 is formed that is recessed from the upper surface of the insulating layer 34 toward the support 230, such that a portion of the upper surface of the metal film 233 is exposed. The cavity 40 is formed so as to penetrate the insulating layers 34, 33, and 32 in the thickness direction.

[0126] Next, in the process shown in Figure 33, the same process as in Figure 12 is performed to fix the electronic component 50 to the upper surface of the metal film 233 exposed from the cavity 40 via an adhesive insulating resin 56 using a mounter.

[0127] Next, in the process shown in Figure 34, the same process as in Figure 7 is performed to cover the upper surface of the insulating layer 34 and to form an insulating layer 35 that fills the cavity 40.

[0128] Next, in the process shown in Figure 35, the same process as in Figures 7 to 9 is performed to sequentially laminate the wiring layer 25, the insulating layer 36, the wiring layer 26, and the insulating layer 37A on the upper surface of the insulating layer 35. At this time, the insulating layer 37A is formed to cover the entire upper surface and the entire side surface of the wiring layer 26.

[0129] Next, the outer periphery of the support 230 is cut using a slicer or similar tool. The outer periphery of the support 230 is the portion that protrudes outward from the outer surfaces of the insulating layers 32, 33, 34, 35, 36, and 37A.

[0130] Next, in the process shown in Figure 36, the cut support 230 shown in Figure 35 is removed by performing the same process as in Figures 18 to 20. The metal film 233 (see Figure 35), which is a Cu plating film, is selectively etched off from the metal layer 240, which is a Ni layer. At this time, since the surface of the wiring layer 26 is covered with the insulating layer 37A, the etching off of the wiring layer 26 can be suitably suppressed.

[0131] In this process, the lower surfaces of the insulating layer 32, the metal layer 240, and the insulating resin 56 are exposed to the outside. At this time, the lower surfaces of the insulating layer 32, the metal layer 240, and the insulating resin 56, which were in contact with the upper surface of the metal film 233 (see Figure 35), are formed in a shape that follows the upper surface of the metal film 233 (in this case, the flat surface). As a result, the lower surfaces of the insulating layer 32, the metal layer 240, and the insulating resin 56 are formed flush with each other.

[0132] Next, the metal layer 240 is removed. The metal layer 240 is selectively etched away from, for example, the wiring layer 22. As a result, the lower surface of the wiring layer 22 is exposed to the outside, as shown in Figure 37. At this time, a recess 32X is formed on the lower surface of the insulating layer 32.

[0133] Next, in the process shown in Figure 38, an insulating layer 31 is formed on the lower surface of the insulating layer 32, covering the lower surface of the wiring layer 22 and the lower surface of the insulating resin 56, by performing the same process as in Figure 7. The insulating layer 31 is formed to fill the recess 32X. This forms an insulating layer 31 having protrusions 31B that fill the recess 32X. In addition, an insulating layer 37B is formed on the upper surface of the insulating layer 37A, covering the entire upper surface of the insulating layer 37A.

[0134] Next, in the process shown in Figure 39, the same process as in Figures 8 and 9 is performed to laminate the wiring layer 21 on the lower surface of the insulating layer 31 and the wiring layer 27 on the upper surface of the insulating layer 37B. Subsequently, the same process as in Figure 17 is performed to form a solder resist layer 30 on the lower surface of the insulating layer 31 and a solder resist layer 38 on the upper surface of the insulating layer 37B. Then, the wiring layer 20 is laminated on the lower surface of the solder resist layer 30. After that, an external connection terminal 60 is formed on the lower surface of the wiring layer 20.

[0135] The wiring board 10A of this embodiment can be manufactured through the above manufacturing process. (Effects of the second embodiment) According to the second embodiment described above, in addition to the effects (1-1) to (1-3) of the first embodiment, the following effects can be achieved.

[0136] (2-1) The insulating layer 31 is formed such that a recess 32X is provided on the lower surface of the insulating layer 32, and a protrusion 31B fills the recess 32X. The insulating layer 32 is formed to cover the side surface of the protrusion 31B. This increases the contact area between the insulating layer 31 and the insulating layer 32, and improves the adhesion between the insulating layer 31 and the insulating layer 32.

[0137] (2-2) The insulating resin 56 used to fix the electronic component 50 onto the support 230 exposed from the cavity 40 is not removed, and an insulating layer 31 is laminated on the underside of the insulating resin 56. This eliminates the need to remove the insulating resin 56.

[0138] (Third embodiment) The third embodiment will be described below with reference to Figures 40 to 45. The following description will focus on the differences from the second embodiment. Components identical to those shown in Figures 1 to 39 will be denoted by the same reference numerals, and detailed explanations of each of these elements will be omitted.

[0139] As shown in Figure 40, the wiring board 10B has a wiring structure 11B, one or more (two in this embodiment) cavities 40 formed in the wiring structure 11B, an electronic component 50 disposed within the cavity 40, and an electronic component 50A disposed within the cavity 40. The wiring board 10 is a wiring board that incorporates the electronic components 50 and 50A.

[0140] (Structure of electronic component 50A) The electronic component 50A has a main body 57 and a first electrode 58 provided at the lower part of the electronic component 50A. The electronic component 50A in this embodiment has a plurality of first electrodes 58.

[0141] Examples of electronic components 50A include semiconductor elements, crystal oscillators, chip components, and silicon bridges without through-holes. Examples of chip components include chip capacitors, chip resistors, and chip inductors.

[0142] The main body 57 is formed, for example, in the shape of a rectangular parallelepiped. The thickness of the main body 57 can be, for example, about 50 μm to 100 μm. The main body 57 is formed from, for example, silicon (Si) or silicon carbide (SiC).

[0143] As the material for the first electrode 58, for example, a metal such as aluminum (Al) or copper (Cu), or an alloy containing at least one metal selected from these metals can be used.

[0144] Each first electrode 58 is formed to be embedded in the main body 57, for example. The lower surface of each first electrode 58 is formed to be exposed from the lower surface of the main body 57. The lower surface of each first electrode 58 is formed to be flush with the lower surface of the main body 57, for example. The thickness of the first electrode 58 can be, for example, about 2 μm to 20 μm. Each first electrode 58 may also be formed to protrude downward from the lower surface of the main body 57.

[0145] The electronic component 50A does not have electrodes on its upper surface. Furthermore, the electronic component 50A does not have through electrodes that penetrate the main body 57 in the thickness direction. The wiring layer 21 of this embodiment has wiring patterns 21C and 21D that are routed in a planar direction on the lower surface of the insulating layer 31. Wiring pattern 21C electrically connects, for example, a wiring layer 21 connected to wiring layer 22 and a wiring layer 21 connected to the first electrode 52 of the electronic component 50. Wiring pattern 21D electrically connects, for example, a wiring layer 21 connected to wiring layer 22 and a wiring layer 21 connected to the first electrode 58 of the electronic component 50A.

[0146] Here, the electronic component 50A is fixed to the upper surface of the insulating layer 31 exposed from the cavity 40 via an insulating resin 56. In other words, the electronic component 50A is mounted on the insulating resin 56 provided on the upper surface of the insulating layer 31.

[0147] The wiring layer 23 of this embodiment has a wiring pattern 23A that is routed in a planar direction on the upper surface of the insulating layer 32. The wiring pattern 23A is connected, for example, to a wiring layer 22 that is electrically connected to a wiring pattern 21C via via wiring V5, and also to a wiring layer 22 that is electrically connected to a wiring pattern 21D via via wiring V5.

[0148] Electronic component 50 and electronic component 50A are electrically connected to each other, for example, through wiring layers 21, 22, 23, etc. More specifically, electronic component 50 and electronic component 50A are electrically connected to each other through wiring patterns 21C, 21D, wiring layer 22, and wiring pattern 23A, etc.

[0149] (Manufacturing method for wiring board 10B) Next, the manufacturing method of the wiring board 10B will be described. For the sake of clarity, the parts that will ultimately become components of the wiring board 10B will be labeled with their final component reference numerals.

[0150] First, the structure shown in Figure 41 is manufactured by performing the same process as shown in Figures 29 to 35. Here, the wiring layer 23 is formed to have a wiring pattern 23A. The electronic component 50A is fixed to the upper surface of the metal film 233 exposed from the cavity 40 via an insulating resin 56, similar to the electronic component 50. At this time, the electronic component 50A is fixed in a position where the first electrode 58 faces the insulating resin 56.

[0151] Next, the outer periphery of the support 230 is cut by performing the same process as shown in Figure 35. Next, in the process shown in Figure 42, the support 230 after cutting shown in Figure 41 is removed by performing the same process as in Figure 36. This exposes the lower surface of the insulating layer 32, the lower surface of the metal layer 240, and the lower surface of the insulating resin 56 to the outside.

[0152] Next, the metal layer 240 is removed. The metal layer 240 is selectively etched away, for example, from the wiring layer 22. As a result, the lower surface of the wiring layer 22 is exposed to the outside, as shown in Figure 43. At this time, a recess 32X is formed on the lower surface of the insulating layer 32.

[0153] Next, in the process shown in Figure 44, an insulating layer 31 is formed on the lower surface of the insulating layer 32, covering the lower surface of the wiring layer 22 and the lower surface of the insulating resin 56, by performing the same process as in Figure 38. The insulating layer 31 is formed to fill the recess 32X. In addition, an insulating layer 37B is formed on the upper surface of the insulating layer 37A, covering the entire upper surface of the insulating layer 37A.

[0154] Next, by performing the same steps as shown in Figures 8 and 9, a wiring layer 21 is laminated on the lower surface of the insulating layer 31, and a wiring layer 27 is laminated on the upper surface of the insulating layer 37B. At this time, the wiring layer 21 is formed to have wiring patterns 21C and 21D. This allows the electronic component 50 and the electronic component 50A to be electrically connected to each other through the wiring patterns 21C and 21D, the wiring layer 22, and the wiring pattern 23A, etc.

[0155] Next, in the process shown in Figure 45, a solder resist layer 30 is formed on the lower surface of the insulating layer 31 and a solder resist layer 38 is formed on the upper surface of the insulating layer 37B by performing the same process as in Figure 17. Then, a wiring layer 20 is laminated on the lower surface of the solder resist layer 30. After that, an external connection terminal 60 is formed on the lower surface of the wiring layer 20.

[0156] The wiring board 10B of this embodiment can be manufactured through the above manufacturing process. (Effects of the third embodiment) According to the third embodiment described above, the same effects and benefits as those of (1-1) to (1-3) of the first embodiment and (2-1) and (2-2) of the second embodiment can be achieved.

[0157] (Example of change) Each of the above embodiments can be implemented with the following modifications. Each of the above embodiments and the following modifications can be combined with each other to the extent that they do not contradict each other technically.

[0158] The structures of the wiring boards 10, 10A, and 10B in each of the above embodiments can be modified as appropriate. In the wiring boards 10, 10A, and 10B of the above embodiments, the number of wiring layers and insulating layers laminated on the lower surface of the insulating layer 32 is not particularly limited. For example, only one insulating layer 31 and one wiring layer 21 may be laminated on the lower surface of the insulating layer 32. That is, the solder resist layer 30 and the wiring layer 20 may be omitted. In this case, for example, an external connection terminal 60 is provided on the lower surface of the wiring layer 21.

[0159] The insulating layer 31 in each of the above embodiments may be modified to have a structure that includes both the protruding portion 31A and the protruding portion 31B. The insulating layer 31 in each of the above embodiments may be modified to have a structure that does not have both the protruding portion 31A and the protruding portion 31B.

[0160] In the wiring boards 10, 10A, and 10B of the above embodiments, the number of wiring layers and insulating layers laminated on the upper surface of the insulating layer 35 for cavity filling is not particularly limited. The solder resist layer 38 in each of the above embodiments may be omitted.

[0161] In the wiring structures 11, 11A, and 11B of the above embodiments, the insulating layer for cavity formation is composed of three insulating layers 32, 33, and 34. However, the insulating layer for cavity formation may be composed of one insulating layer, two insulating layers, or four or more insulating layers.

[0162] In the wiring boards 10, 10A, and 10B of each of the above embodiments, the structure may be changed to one that incorporates only the electronic component 50A. The number of electronic components 50, 50A to be incorporated into the wiring boards 10, 10A, 10B of each of the above embodiments is not limited. For example, only one electronic component 50 may be incorporated into the wiring boards 10, 10A, 10B. For example, three or more electronic components 50 may be incorporated into the wiring boards 10, 10A, 10B.

[0163] In the wiring boards 10, 10A, and 10B of the above embodiments, one electronic component 50, 50A is placed in each cavity 40, but this is not limited to this. For example, multiple electronic components 50, 50A may be placed in each cavity 40.

[0164] In the above embodiment, the electronic component 50 having a through electrode 54 is embedded in the wiring boards 10, 10A, and 10B, but the embodiment is not limited to this. For example, an electronic component without a through electrode 54 may be embedded in the wiring boards 10, 10A, and 10B.

[0165] In the embodiments described above, an electronic component 50 having two types of electrodes, namely a first electrode 52 and a second electrode 53, is incorporated into the wiring boards 10, 10A, and 10B, but the invention is not limited to this. For example, an electronic component having three or more types of electrodes may be incorporated into the wiring boards 10, 10A, and 10B.

[0166] The structure of the substrate 70 in each of the above embodiments can be modified as appropriate. In the substrate 70 of each of the above embodiments, the number of wiring layers and insulating layers laminated on the upper surface of the core substrate 71 is not particularly limited.

[0167] In the substrate 70 of each of the above embodiments, the number of wiring layers and insulating layers laminated on the lower surface of the core substrate 71 is not particularly limited. The number of electronic components 76 to be embedded in the substrate 70 of each of the above embodiments is not limited. For example, only one electronic component 76 may be embedded in the substrate 70. For example, three or more electronic components 76 may be embedded in the substrate 70.

[0168] The number of semiconductor chips 110 mounted on the wiring board 10 in each of the above embodiments of the semiconductor device 1 is not limited. In the above embodiments, structures corresponding to parts of the wiring boards 10, 10A, and 10B are formed on both the upper and lower surfaces of the support bodies 200 and 230, but the invention is not limited to this. For example, structures corresponding to parts of the wiring boards 10, 10A, and 10B may be formed on only one side of the support bodies 200 and 230. [Explanation of symbols]

[0169] 1 Semiconductor device 10, 10A, 10B Wiring Board 11,11A,11B wiring structure 20A wiring layer 20B wiring layer 21A wiring layer 21B wiring layer 22 wiring layer 23,24,25,26,27 wiring layer 30 solder resist layers 31 Insulating layer 31A Protrusion 31B Projection 32 Insulating layer 32X recess 33,34 Insulating layer 35 Insulating layer 35X recess 36, 37, 37A, 37B Insulating layer 38 Solder Resist Layers 40 Cavity 50,50A Electronic Components 51, 57 Main body 52,58 1st electrode 53 2nd electrode 54 Through electrode 56 Insulating resin 60, 60A, 60B External connection terminals 70 circuit boards 76 Electronic Components 110 semiconductor chips 200,230 Support V1, V2, V3, V4 via wiring V5, V6, V7, V8, V9, V10 via wiring

Claims

1. A wiring board having the form of a coreless substrate, The first insulating layer and A first wiring layer laminated on the first insulating layer, An insulating layer comprising N layers (where N is a natural number of 1 or more), including a second insulating layer that is laminated on the first surface of the first insulating layer and formed to cover the first wiring layer, A cavity formed in the insulating layer of the N layer and formed so as to expose a part of the first surface of the first insulating layer, An electronic component having a first electrode disposed within the cavity and covered with the first insulating layer, A filling insulating layer that fills the cavity and covers the electronic component, A first via wiring that penetrates the first insulating layer in the thickness direction and is connected to the first electrode, The first insulating layer is laminated on the second surface opposite to the first surface of the first insulating layer and is electrically connected to the first electrode via a first via wiring, The cavity is formed such that its opening width decreases as it approaches the first insulating layer. The first via wiring is formed such that its diameter decreases as it approaches the electronic component, on a wiring board.

2. The first insulating layer has a first projection that protrudes from the first surface of the first insulating layer toward the cavity, The first protrusion is positioned within the cavity and is formed to cover the first electrode. The wiring board according to claim 1, wherein the first insulating layer is a single layer.

3. The first insulating layer is A first insulating resin having the first surface, The first insulating resin is provided on the first surface of the first insulating resin and also provided in the cavity, The wiring board according to claim 1, wherein the first via wiring is formed to penetrate the first insulating resin and the second insulating resin in the thickness direction.

4. The first insulating layer has a second projection that protrudes from the first surface of the first insulating layer toward the insulating layer of the N layer, The first wiring layer is provided on the second protrusion, The wiring board according to claim 1, wherein the second insulating layer is formed to cover the side surface of the second protrusion.

5. A second via wiring that penetrates the first insulating layer in the thickness direction and is connected to the first wiring layer, The first insulating layer is laminated on the second surface of the first insulating layer and has a third wiring layer electrically connected to the first wiring layer via the second via wiring, The second via wiring and the third wiring layer are provided in positions that do not overlap with the cavity in a plan view. The second via wiring is formed such that its diameter decreases as it approaches the first wiring layer. The wiring board according to claim 1, wherein the diameter of the first via wiring is smaller than the diameter of the second via wiring.

6. A solder resist layer is formed on the second surface of the first insulating layer so as to cover the second wiring layer, A third via wiring penetrates the solder resist layer in the thickness direction and is connected to the second wiring layer, The solder resist layer is laminated on the side opposite to the side in contact with the first insulating layer, and has a fourth wiring layer that is electrically connected to the second wiring layer via the third via wiring, The wiring board according to claim 1, wherein the third via wiring is formed such that its diameter decreases as it approaches the second wiring layer.

7. A fourth via wiring that penetrates the second insulating layer in the thickness direction and is connected to the first wiring layer, The wiring comprises a fifth wiring layer laminated on the second insulating layer and electrically connected to the first wiring layer via the fourth via wiring, The wiring board according to claim 1, wherein the fourth via wiring is formed such that its diameter decreases as it approaches the first wiring layer.

8. The electronic component has a second electrode provided on the opposite side of the first electrode, The aforementioned wiring board is A fifth via wiring penetrates the aforementioned filling insulating layer in the thickness direction and is connected to the second electrode, It has a sixth wiring layer laminated on the filling insulating layer and electrically connected to the second electrode via the fifth via wiring, The fifth via wiring is formed such that its diameter decreases as it approaches the second electrode. The wiring board according to claim 1, wherein the diameter of the first via wiring is smaller than the diameter of the fifth via wiring.

9. A wiring board according to any one of claims 1 to 8, A circuit board on which the aforementioned wiring board is mounted, The wiring board includes a semiconductor chip mounted on the second wiring layer side, which is located on the side opposite to the board, A semiconductor device in which, when the aforementioned electronic component is designated as the first electronic component, the substrate incorporates a second electronic component electrically connected to the first electronic component.

10. The process of preparing the support, The steps include forming a first wiring layer on the support, A step of forming an N-layer (N is a natural number of 1 or more) insulating layer, which includes a second insulating layer laminated on the support so as to cover the first wiring layer, A step of forming a cavity in the insulating layer of the N layer that exposes a part of the support, A step of fixing an electronic component onto the support exposed from the cavity, A step of filling the cavity to form a filling insulating layer that covers the electronic component, The step of removing the support, A step of laminating the first insulating layer onto the surface of the second insulating layer that was in contact with the support, A step of forming a first via wiring that penetrates the first insulating layer in the thickness direction and is connected to a first electrode of the electronic component, and a second wiring layer that is laminated on a second surface of the first insulating layer opposite to the first surface in contact with the second insulating layer and is electrically connected to the first electrode via the first via wiring, A method for manufacturing a wiring board.

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