Semiconductor manufacturing equipment and semiconductor device manufacturing method

Abstract

To improve the value of semiconductor devices. [Solution] The semiconductor manufacturing apparatus of the embodiment includes an inspection unit 110 for inspecting a first wafer obtained from an ingot, an estimation unit 120 for estimating the location of defects in a second wafer obtained from the ingot based on the inspection results of defects in the first wafer, and an evaluation unit 130 for evaluating the first and second wafers based on the location of the defects in the first wafer and the location of the defects in the second wafer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor manufacturing apparatus and a method for manufacturing a semiconductor device.

Background Art

[0002] It is known that a wafer cut from a single crystal ingot contains various through dislocations such as through screw dislocations. Through dislocations may have an adverse effect on semiconductor devices formed on the wafer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Non-Patent Documents

[0007] [Figure 1] A block diagram showing an example configuration of a semiconductor manufacturing apparatus according to an embodiment. [Figure 2] A block diagram showing an example configuration of a defect inspection device for semiconductor manufacturing equipment according to the embodiment. [Figure 3] A block diagram showing an example of the computer configuration of a semiconductor manufacturing apparatus according to an embodiment. [Figure 4] A block diagram showing an example of the database configuration for a semiconductor manufacturing apparatus according to an embodiment. [Figure 5] A schematic diagram showing an example of an ingot. [Figure 6] A schematic diagram showing an example of a wafer. [Figure 7] A cross-sectional view showing an example of a semiconductor device. [Figure 8] A block diagram showing an example configuration of a semiconductor manufacturing apparatus according to an embodiment. [Figure 9] A flowchart illustrating an example of the operation of the semiconductor manufacturing apparatus according to the embodiment. [Figure 10] A flowchart showing a modified example of the operation of the semiconductor manufacturing apparatus according to the embodiment. [Figure 11] A flowchart showing a modified example of the operation of the semiconductor manufacturing apparatus according to the embodiment. [Modes for carrying out the invention]

[0008] Referring to FIGS. 1 to 11, a semiconductor manufacturing apparatus and a method for manufacturing a semiconductor device according to an embodiment will be described. In the following description, elements having the same function and configuration are denoted by the same reference numerals. Also, in each of the following embodiments, when components (for example, circuits, wirings, various voltages and signals, etc.) with reference numerals accompanied by numbers / letters for differentiation at the end do not need to be distinguished from each other, descriptions (reference numerals) with the numbers / letters at the end omitted are used.

[0009] (Embodiment) Referring to FIGS. 1 to 11, a semiconductor manufacturing apparatus and a method for manufacturing a semiconductor device according to an embodiment will be described.

[0010] (1) Configuration Example Referring to FIGS. 1 to 8, a configuration example of a semiconductor manufacturing apparatus according to an embodiment will be described.

[0011] FIG. 1 is a block diagram showing a configuration example of the semiconductor manufacturing apparatus of the present embodiment.

[0012] As shown in FIG. 1, the semiconductor manufacturing apparatus 100 of the present embodiment includes a defect inspection apparatus 1, a computer 2, and a database 3.

[0013] The defect inspection apparatus (also called a wafer inspection apparatus) 1 inspects the wafer 9. The defect inspection apparatus 1 detects defects in the wafer 9 by non-destructive inspection. The wafer 9 is, for example, a silicon carbide (SiC) wafer. However, the wafer 9 may be a gallium nitride (GaN) or diamond (C) wafer. Furthermore, the wafer 9 may be a silicon (Si) wafer.

[0014] The computer 2 analyzes the inspection results of the defect inspection apparatus 1 and executes various calculation processes based on the inspection results. The computer 2 uses various information in the database 3 to analyze the inspection results. The computer 2 can control the defect inspection apparatus 1 and the database 3.

[0015] Database 3 stores various types of information. For example, database 3 can store data from inspection results performed by defect inspection device 1. Database 3 is accessed by computer 2 for analysis and calculations. Database 3 is, for example, external storage for computer 2. Database 3 may also be provided from a server.

[0016] Figure 2 is a schematic diagram showing an example of the configuration of the defect inspection device 1 in the semiconductor manufacturing apparatus 100 of this embodiment.

[0017] In this embodiment, the defect inspection device 1 is an X-ray topography (XRT) device.

[0018] As shown in Figure 2, the defect inspection apparatus 1 includes an X-ray source 10, a sensor 12, a slit 15, a sample stage 17, and a control unit 19.

[0019] The wafer 9 is held on the sample stage 17.

[0020] The slit 15 is located between the X-ray source 10 and the sample stage 17. The slit 15 focuses the X-rays from the X-ray source 10 into a sheet-like shape.

[0021] The X-ray source 10 irradiates the wafer 9 on the sample stage 17 with X-rays through the slit 15. The X-rays are incident on the wafer 9 at the Bragg diffraction angle. The X-rays are diffracted in the wafer 9 to satisfy the Bragg diffraction conditions.

[0022] Sensor 12 detects diffracted X-rays from wafer 9.

[0023] The control unit 19 controls the X-ray source 10, the sensor 12, the slit 15, and the sample stage 17. The control unit 19 scans the entire area of ​​the wafer 9 or a representative area within the wafer 9 by controlling each component. The control unit 19 can generate an X-ray topography image of the wafer 9 obtained by the scan. The X-ray topography image shows the results of the defect inspection. Alternatively, the X-ray topography image may be generated by the computer 2, which receives the detection results from the defect inspection device 1.

[0024] The defect inspection device 1 detects through-dislocations contained in the SiC wafer 9 based on an X-ray topography image. Through-dislocations include various types of defects such as through-helical dislocations and through-edge dislocations.

[0025] Furthermore, the defect inspection device 1 may inspect the wafer 9 by destructive testing if it is capable of detecting defects in the wafer 9 (e.g., through-dislocations). For example, the defect inspection device 1 may detect through-dislocations in the wafer 9 by various analytical methods such as etch pitting, polarized light microscopy, scanning electron microscopy, photoluminescence, cathodoluminescence, or Raman spectroscopy.

[0026] Figure 3 is a block diagram showing an example configuration of the computer 2 in the semiconductor manufacturing apparatus 100 of this embodiment.

[0027] As shown in Figure 3, computer 2 includes a processor 21, ROM (Read Only Memory) 22, RAM (Random Access Memory) 23, storage 24, and an interface (I / F) 25.

[0028] The processor 21 is a processing circuit capable of executing various programs (software, applications). The processor 21 performs computational processing using various information, various data, various signals, and various parameters. The processor 21 controls the operation of the ROM 22, RAM 23, storage 24, and interface 25. The processor 21 includes, for example, a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit).

[0029] ROM22 is a non-volatile semiconductor memory. ROM22 stores programs and control data for controlling computer 2.

[0030] RAM23 is a volatile semiconductor memory. RAM23 is used as a workspace for processor 21. RAM23 temporarily stores various data and parameters used in the processing of processor 21.

[0031] The storage device 24 is a non-volatile storage device such as an HDD (Hard Disk Drive), SSD (Solid State), or memory card. The storage device 24 stores various types of information, data, and parameters. The storage device 24 has a database composed of a collection of certain types of data. Program and control data may be stored in the storage device 24. For example, the storage device 24 stores a program PG relating to the manufacturing method (inspection method) of the semiconductor device of this embodiment. The program PG may be stored in the ROM 22.

[0032] Interface 25 includes various connectors, various ports, signal processing circuits, and communication modules. Interface 25 connects computer 2 to defect inspection device 1 and database 3. Interface 25 sends control signals from processor 21 to defect inspection device 1 and database 3. Interface 25 sends information (inspection results) from defect inspection device 1 and information from database 3 to processor 21.

[0033] Figure 4 shows an example of the configuration of the database 3 in the semiconductor manufacturing apparatus 100 of this embodiment.

[0034] As shown in Figure 4, database 3 includes chip layout information 31, pattern layout information 32, process information 33, and distance information 34.

[0035] The chip layout information 31 is information regarding the layout of chip areas within the wafer 9. A chip area is a region within the wafer 9 that corresponds to chips that are individualized by dicing the wafer 9.

[0036] The pattern layout information 32 includes information about the layout (coordinates) of various patterns arranged within the chip area on the wafer 9. For example, the pattern layout information 32 includes information about the layout of active regions (e.g., diffusion layer patterns or impurity semiconductor region patterns), information about the layout of gate patterns, and information about the layout of wiring patterns.

[0037] Process information 33 includes information on manufacturing processes such as ion implantation, film deposition, and etching. The various manufacturing process information included in the process information is linked to the pattern layout included in the pattern layout information.

[0038] Distance information 34 is information regarding the distance from the seed crystal side end of the ingot to the target wafer 9 in the growth plane direction of the ingot. For example, the distance from the end of the ingot to the target wafer 9 is determined based on the thickness of the wafer 9 and the position of the wafer 9 within the ingot.

[0039] Database 3 may also be stored in the internal storage 24 of computer 2.

[0040] Figure 5 is a schematic diagram illustrating the wafer 9 and the ingot.

[0041] As shown in Figure 5, the ingot 900 is formed by growing a semiconductor crystal 90 on a seed crystal 99.

[0042] For example, ingot 900 is a SiC ingot. However, ingot 900 may also be a GaN or C (diamond) ingot. Ingot 900 may also be a Si ingot.

[0043] The ingot 900 contains multiple threading dislocations 999. The threading dislocations 999 in the ingot 900 originate from defects in the seed crystal 99. As the semiconductor crystal 90 grows, the threading dislocations 999 extend substantially linearly from the side of the seed crystal 99 toward the growth end of the ingot 900, at a certain angle with respect to the surface of the seed crystal 99, depending on the size of the diameter of the ingot 900 (the diameter of the wafer). For example, the direction of extension of the threading dislocations 999 in the ingot 900 (the growth direction of the threading dislocations 999) can be predicted based on information regarding the manufacturing history of past ingots using the same seed crystal 99.

[0044] Multiple wafers 9 (9A, 9B) are cut from the ingot 900 through slicing.

[0045] For example, wafer 9 has an identification number corresponding to its distance from the seed crystal 99 in order to determine its position within the ingot 900. For example, wafer 9A has an identification number ID <m>Wafer 9B has an identification number ID <n>It has the following properties: m and n are integers greater than or equal to 1, where m has a value different from n.

[0046] Identification number ID <m>Wafer 9A and another identification number ID <n>Wafer 9B is used for inspection of through-dislocations 999 within the wafer.

[0047] In this embodiment, within the ingot 900 from which multiple wafers 9 are cut, a certain identification number ID <m>Wafer 9A and identification number ID <n>Other wafers besides wafer 9B do not need to be used for defect inspection. Identification number ID in ingot 900 <m>Corresponding location and identification number ID <n>The portion 910 other than the corresponding location is called the uninspected region 910. Wafers 9 cut from the uninspected region 910 are excluded from defect inspection. Defects in wafers 9 within the uninspected region 910 (e.g., penetrating dislocations 999) are calculated by simulation based on the measured inspection results of wafers 9A and 9B, for example, by simulation using distance information 34 from database 3.

[0048] Thus, if the positional information of dislocations on wafer 9A on the seed crystal 99 side and the positional information of dislocations on wafer 9B on the growth end side of ingot 900 are obtained, the direction of extension of the penetrating dislocations 999 within ingot 900 can be predicted.

[0049] Figure 6 is a schematic diagram illustrating wafer 9. In Figure 6, the top surface (XY plane) of wafer 9 is shown as viewed from the growth direction (Z direction) of the ingot (wafer). In Figure 6, the chip area 950 based on the chip layout information 31 is virtually shown.

[0050] As shown in Figure 6, the wafer 9 contains multiple chip areas 950. Dicing areas 959 are provided within the wafer 9 so as to surround the chip areas 950. By dicing the wafer 9 along the dicing areas 959, the chip areas 950 become independent as individual semiconductor chips (semiconductor devices).

[0051] The wafer 9 contains multiple defects (e.g., through-dislocations 999) depending on the defects that occurred during the manufacturing of the ingot 900. The through-dislocations 999 may be present in the chip area 950 and the dicing area 959.

[0052] Figure 7 is a schematic diagram illustrating the chip area 950 of wafer 9 (see Non-Patent Document 1).

[0053] Figure 7 shows a chip area 950 on which an example semiconductor device 7 is formed.

[0054] The chip area (semiconductor chip) 950 includes a semiconductor substrate (SiC substrate) as part of the wafer 9.

[0055] The semiconductor device 7 is a power device 7. The power device 7 is, for example, a vertical power MOS (Metal-Oxide-Semiconductor) transistor. The semiconductor device 7 formed on the wafer 9 may also be an IGBT (Insulated Gate Bipolar Transistor).

[0056] The power MOS transistor 7 includes a gate electrode 72, a gate insulating film 73, a source electrode 74, a well region 75, a source region 76, a substrate 77, a drain electrode 78, and a drift layer 70.

[0057] The gate electrode 72 is provided on the surface of the substrate 77 (wafer 9). The gate insulating film (e.g., gate oxide film) 73 is provided between the drift layer 70 and the gate electrode 72. The gate insulating film 73 covers the gate electrode 72. The gate electrode 72 is stacked on the gate insulating film 73 in the Z direction.

[0058] The source electrode 74 is positioned above the surface of the substrate 77 so as to cover the gate electrode 72. A gate insulating film 73 is provided between the source electrode 74 and the gate electrode 72. The gate insulating film 73 insulates the source electrode 74 from the gate electrode 72.

[0059] Two p-type well regions 75 are provided within (on top of) the drift layer 70. The well regions 75 are semiconductor regions (semiconductor layers). The well regions 75 are aligned in the X direction. + A source region (diffusion layer) 76 of a specific type is provided within the well region 75. The source region 76 is a semiconductor region (semiconductor layer). The well region 75 and the source region 76 are connected to the source electrode 74. The channel of the transistor 7 is formed within the well region 75.

[0060] n + The substrate 77 of the mold is spaced apart from the well region 75.

[0061] The drain electrode (drain region) 78 is provided on the back side of the substrate 77.

[0062] n - A drift layer 70 of a specific type is provided in the region between the substrate 77 and the gate electrode 72. The drift layer 70 is a semiconductor layer formed on the substrate 77. The drift layer 70 is in contact with the well region 75. The drift layer 70 faces the gate electrode 72 via the gate insulating film 73. The drift layer 70 is designed according to the withstand voltage of the device.

[0063] When the power MOS transistor 7 is driven, current flows between the source electrode 74 and the drain electrode 78 via the channel region and drift layer 70 of the transistor 7.

[0064] The patterns of the gate electrode 72, source electrode 74, and drain electrode 78 are set as electrode patterns in the pattern layout information 32. The patterns of the drift layer 70, well region 75, source region 76, and substrate 77 are set as impurity region patterns (implantation patterns) in the pattern layout information 32.

[0065] The components 70, 72, 73, 74, 75, 76, 77, and 78 of the power MOS transistor 7 are formed at predetermined positions within the chip area 950 under predetermined process conditions, based on pattern layout information 32 and process information 33.

[0066] Through-dislocations 999 in the substrate 77 directly beneath or near the active region (e.g., semiconductor layers 70, 75, 76) where the power device 7 is formed pose a high risk of causing power device failure. Through-dislocations 999 in regions within the substrate 77 (wafer 9) that do not contribute to the characteristics of the power device 7 (e.g., element isolation region or dicing area 959) pose a low risk of causing power device failure.

[0067] The semiconductor manufacturing apparatus 100 of this embodiment evaluates the defect risk for the semiconductor device 7 formed in the chip area 950 according to the location of defects (e.g., through-dislocations 999) within the chip area 950. Based on the defect risk evaluation results, the semiconductor manufacturing apparatus 100 of this embodiment classifies the quality of the semiconductor device 7.

[0068] Figure 8 is a block diagram showing the functional blocks of the semiconductor manufacturing apparatus 100 according to this embodiment.

[0069] As shown in Figure 8, the semiconductor manufacturing apparatus 100 of this embodiment includes a defect inspection unit 110, a defect estimation unit 120, a defect risk assessment unit 130, and a quality classification unit 140. The functions of each functional block (software configuration) 110, 120, 130, and 140 of the semiconductor manufacturing apparatus 100 are realized by the hardware configuration of the semiconductor manufacturing apparatus 100, such as the defect inspection unit 1 and the computer 2. For example, the processor 21 of the computer 2 is configured to execute the functions and processing of each unit 110, 120, 130, and 140.

[0070] The defect inspection unit (also called the wafer inspection unit) 110 controls the defect inspection apparatus 1 to inspect through-dislocations 999 in one or more wafers 9 obtained from the ingot 900. For example, the defect inspection unit 110 inspects through-dislocations 999 in the first wafer 9A and the second wafer 9B. The defect inspection unit 110 acquires actual data showing the inspection results for the first and second wafers 9A and 9B, respectively. The defect inspection unit 110 stores (retains) or stores in the database 3 information regarding the location of the through-dislocations 999 shown in the inspection results.

[0071] The defect estimation unit 120 incorporates the measured data of wafers 9A and 9B into the chip layout information of wafers 9A and 9B. This allows the coordinates of the penetration dislocations 999 in wafers 9A and 9B to be detected. Based on the inspection results (measured data) of wafers 9A and 9B by the defect inspection unit 110, the coordinates of the penetration dislocations 999 (and the coordinates of defects in the seed crystal) within wafers 9A and 9B, and distance information 34 indicating the position of wafer 9 within the ingot 900, the defect estimation unit 120 estimates the defects (penetration dislocations 999) and the location of the defects in one or more wafers 9 cut from the uninspected region 910 of the ingot 900 through simulation by the computer 2. Based on the identification numbers of the inspected wafers 9A and 9B and the identification numbers of wafer 9 in the uninspected region 910, the defect estimation unit 120 can calculate the location of the penetration dislocations 999 in wafer 9 within the uninspected region 910. The defect estimation unit 120 stores (retains) or stores in the database 3 information regarding the location of the penetrating dislocation 999 estimated by the simulation results.

[0072] As illustrated with Figure 5, the penetrating dislocation 999 extends substantially in a straight line within the ingot 900. The penetrating dislocation 999 originates from a defect in the seed crystal 99. The position of wafer 9 within the ingot 900 is calculated using distance information 34 and the identification number of wafer 9 associated with its position within the ingot 900.

[0073] The defect estimation unit 120 verifies the identity (or continuity) between the penetrating dislocation 999 of wafer 9A and the penetrating dislocation 999 of wafer 9B based on the positions of wafers 9A and 9B within the ingot 900, and the amount of coordinate displacement of the corresponding penetrating dislocations 999 of the inspected wafers 9A and 9B.

[0074] This allows the defect estimation unit 120 to determine whether a penetrating dislocation 999 at a certain coordinate on wafer 9A is continuous with (or exists on the same straight line with) a penetrating dislocation 999 at a certain coordinate on wafer 9B.

[0075] As a result, the defect estimation unit 120 calculates the number of penetrating dislocations 999 formed within the ingot 900.

[0076] The defect estimation unit 120 estimates which wafer 9 in the ingot 900 the calculated penetration dislocation 999 will pass through, based on various information such as the calculated penetration dislocation 999 and distance information 34.

[0077] Thus, defects (through-dislocations 999) of the wafer 9 obtained from the uninspected region 910 can be detected without being performed by the defect inspection device 1.

[0078] The defect risk assessment unit 130 evaluates the defect risk for each wafer 9 and the defect risk for multiple chip areas (semiconductor chips) 950 on each wafer 9, based on various information.

[0079] For example, the defect risk assessment unit 130 sets the risk score of a through-dislocation 999 that spans both wafers 9A and 9B to be inspected to a higher value than the risk score of a through-dislocation 999 that forms on only one of the two wafers 9A and 9B. This score setting is because a through-dislocation 999 that spans both wafers 9A and 9B also spans the uninspected region of wafer 9 between the two wafers 9A and 9B.

[0080] The defect risk evaluation unit 130 evaluates the risk of defects in the chip area 950 on which the semiconductor device 7 is formed, based on various information such as chip layout information 31, pattern layout information 32, and process information 33. The defect risk evaluation unit 130 sets the score of through-dislocations 999 at locations overlapping with the active region of the chip area 950 (e.g., semiconductor layers 70, 75, 76) to a higher value than the score of through-dislocations 999 at locations overlapping with regions that do not contribute to the characteristics of the power device 7 (e.g., element isolation region or dicing area 959). This score setting is because through-dislocations 999 at locations overlapping with the active region are likely to adversely affect the operation of the semiconductor device 7.

[0081] In this way, the defect risk assessment unit 130 assesses the risk of through-dislocations 999 for each wafer 9 or each chip area 950.

[0082] The quality classification unit 140 ranks the quality of the wafer 9 and chip area 950 based on the evaluation results of the defect risk of the wafer 9 and chip area 950.

[0083] For example, the quality classification unit 140 classifies a chip area (or semiconductor chip on which a semiconductor device is formed) as a best product if the defect risk score of a certain chip area is less than a first threshold. For example, the quality classification unit 140 classifies a chip area 950 as a good product if the defect risk score of a certain chip area is greater than or equal to a first threshold but less than a second threshold. For example, the quality classification unit 140 classifies a chip area 950 as a defective product if the defect risk score of a certain chip area 950 is greater than or equal to a second threshold.

[0084] With the above configuration, the semiconductor manufacturing apparatus 100 of this embodiment can reduce the number of wafers to be inspected. Furthermore, the semiconductor manufacturing apparatus 100 of this embodiment can improve the quality of the semiconductor chips shipped.

[0085] (2) Example of operation Figure 9 is a schematic diagram illustrating an example of the operation of the semiconductor manufacturing apparatus of this embodiment. The example of the operation of the semiconductor manufacturing apparatus of this embodiment relates to a method for manufacturing a semiconductor device according to the embodiment.

[0086] Figure 9 is a flowchart showing an example of the operation of the semiconductor manufacturing apparatus according to this embodiment.

[0087] In the computer 2 of the semiconductor manufacturing equipment 100, the processor 21 executes the following multiple processes S1, S2, S3, and S4 based on the program PG in the storage 24.

[0088] <s1> The semiconductor manufacturing equipment 100 obtains a certain identification number ID from a certain ingot 900 using the XRT method with the defect inspection equipment 1. <m>The first wafer 9A is inspected. This allows the semiconductor manufacturing equipment 100 to acquire measured data of the XRT image of the first wafer 9A. The semiconductor manufacturing equipment 100 then uses the XRT method with the defect inspection device 1 to obtain another identification number ID obtained from the same ingot 900 as the first wafer 9A. <n>The second wafer 9B is then inspected. This allows the semiconductor manufacturing equipment 100 to acquire measured data of the XRT image of the second wafer 9B.

[0089] Furthermore, the semiconductor manufacturing apparatus 100 may inspect three or more wafers 9 cut from the same ingot 900.

[0090] <s2> Based on the inspection results of the inspected wafers 9A and 9B and the chip layout information 31, the semiconductor manufacturing apparatus 100 estimates the location of defects (e.g., through-dislocations 999) in each of the multiple wafers 9 included in the uninspected region 910 of the ingot 900, and calculates the location of the through-dislocations 999 for each chip area 950 of the wafer 9 within the uninspected region 910.

[0091] For example, the semiconductor manufacturing apparatus 100 reflects the locations of the through-dislocations 999 included in the measured data of multiple wafers 9A and 9B into the chip layout information 31 of wafers 9A and 9B. As a result, the coordinates of the through-dislocations 999 within the chip area 950 are detected for the inspected wafers 9A and 9B.

[0092] By considering the amount of displacement of a specific penetration dislocation 999 between wafers 9A and 9B, and comparing the position (coordinates) of the penetration dislocation 999 in the first wafer 9A with the position of the penetration dislocation 999 in the second wafer 9B, and using distance information 34, the positions of multiple penetration dislocations 999 that may occur in the uninspected area 910 are estimated.

[0093] Furthermore, by superimposing the estimated locations of the penetrating dislocations 999 on the wafer 9 with the chip layout information 31, the locations of the penetrating dislocations 999 in each chip area 950 within the wafer 9 are calculated.

[0094] As a result, information regarding the location of through-dislocations 999 in the wafer 9 and chip area 950 for multiple wafers 9 within the uninspected region 910 is obtained without actual measurement inspection by the defect inspection device 1. Consequently, the number of inspections required for multiple wafers 9 is reduced.

[0095] <s3> The semiconductor manufacturing equipment 100 evaluates the defect risk of each of the multiple chip areas 950 on each wafer 9 based on pattern layout information 32 and process information 33. The semiconductor manufacturing equipment 100 assigns a score to each chip 950 according to the location of the through-dislocation 999 within the chip area 950.

[0096] <s4> The semiconductor manufacturing equipment 100 classifies each chip area 950 into one of several ranks based on the quality corresponding to the defect risk assessment results for each chip area 950. As a result, the semiconductor manufacturing equipment 100 can improve the quality of the semiconductor devices shipped.

[0097] <s5> After inspection and evaluation of the wafer, semiconductor devices 7 are formed on each of the chip areas 950 of the wafer 9. Through a dicing process, each wafer 9 is divided into individual chips. This process results in the manufacture of multiple semiconductor devices 7.

[0098] <s6> Multiple chips 950 (semiconductor devices 7) are either shipped to the market or discarded based on their classified quality rank.

[0099] The above process completes the processing flow for the manufacturing method of the semiconductor device according to this embodiment.

[0100] (3) Variant Referring to Figures 10 and 11, a modified example of the operation of the semiconductor manufacturing apparatus of the embodiment (method for manufacturing a semiconductor device) will be described.

[0101] Figure 10 is a flowchart illustrating the operation of a semiconductor manufacturing apparatus in a modified form.

[0102] In the example described above, the risk of defects (e.g., through-dislocations 999) for multiple wafers 9 is evaluated in units of chip area 950.

[0103] As shown in Figure 10 for S2A, S3A, S4A, and S6A, defect risk and quality may be evaluated on a wafer-by-wafer basis.

[0104] When defect risk is evaluated on a wafer-by-wafer basis, the semiconductor manufacturing equipment 100 evaluates the defect risk of the wafer based on the location of the through-dislocations 999 within the wafer 9 and the number of through-dislocations 999 in the wafer 9.

[0105] Figure 11 is a flowchart illustrating the operation of another modified semiconductor manufacturing apparatus.

[0106] In the example described above, the locations of multiple penetrating dislocations 999 in wafers 9 of the uninspected region 910 are estimated and calculated using two wafers 9A and 9B cut from ingot 900.

[0107] As described above, the penetrating dislocations 999 in the ingot 900 originate from dislocations (defects) in the seed crystal 99. If the positional information of the dislocations on the wafer 9 on the seed crystal 99 side of the ingot 900 (for example, preferably the positional information of two or more dislocations) is obtained, the direction of extension of the penetrating dislocations 999 can be predicted.

[0108] Therefore, as shown in S1B and S2B of Figure 11, based on one inspected wafer 9 (and seed crystal 99), the locations of the through-dislocations 999 in multiple wafers 9 in the uninspected region 910 can be estimated and calculated.

[0109] (4) Summary Defects such as through-dislocation 999 in wafers cut from SiC ingots raise concerns about potential device failures in semiconductor chips.

[0110] In the semiconductor manufacturing apparatus and semiconductor device manufacturing method of this embodiment, defects (e.g., through-dislocations 999) in multiple wafers cut from an uninspected region of a certain ingot are estimated based on the actual inspection results of a specific wafer cut from the ingot. Therefore, this embodiment can reduce the number of wafers that are actually inspected.

[0111] As a result, this embodiment can suppress the increase in costs incurred by inspections and the increase in capital investment for inspection equipment.

[0112] In this embodiment, chips are classified according to their quality based on the risk of chip defects.

[0113] This embodiment enables the provision of high-quality chips in a large number of chips distributed in the market. As the quality of the chips improves, this embodiment can add high value to the chips and increase the selling price of the chips.

[0114] As described above, the semiconductor manufacturing apparatus and semiconductor device manufacturing method of this embodiment can improve the value of semiconductor devices.

[0115] (5) Others While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0116] 1: Defect inspection equipment, 2: Computer, 3: Database, 100: Semiconductor manufacturing equipment, 110: Defect inspection department, 120: Defect estimation department, 130: Defect risk assessment department, 140: Quality classification department. < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / m>

Claims

1. An inspection unit that inspects the first wafer obtained from the ingot, An estimation unit that estimates the location of defects in a second wafer obtained from an ingot based on the inspection results of defects in the first wafer, An evaluation unit that evaluates the first and second wafers based on the location of the defects in the first wafer and the location of the defects in the second wafer, A semiconductor manufacturing apparatus equipped with the following features.

2. Based on the evaluation results of the first and second wafers, a classification unit is provided to classify the quality of semiconductor devices manufactured from each of the first and second wafers. The semiconductor manufacturing apparatus according to claim 1, further comprising the present invention.

3. The first and second wafers include a plurality of chip areas, The evaluation unit evaluates the defects in each of the plurality of chip areas, The classification unit classifies the quality of each of the multiple chip areas based on the evaluation results of the defects in each of the multiple chip areas. The semiconductor manufacturing apparatus according to claim 2.

4. The estimation unit estimates the location of the defect in the second wafer based on the location of the defect in the seed crystal for manufacturing the ingot and the location of the defect in the first wafer. The semiconductor manufacturing apparatus according to claim 1.

5. The inspection unit inspects a third wafer that is different from the first wafer. The estimation unit estimates the location of the defect on the second wafer, obtained from the region between the first wafer and the third wafer in the ingot, based on the location of the defect on the first wafer and the location of the defect on the third wafer. The semiconductor manufacturing apparatus according to claim 1.

6. The defect in the second wafer is estimated by a calculation process based on the position of the first wafer in the ingot, the position of the third wafer in the ingot, the position of the defect in the first wafer, and the position of the defect in the third wafer. The semiconductor manufacturing apparatus according to claim 5.

7. The inspection unit inspects the first wafer using a method capable of detecting dislocations on the wafer. The semiconductor manufacturing apparatus according to claim 1.

8. The ingot comprises one of silicon carbide, gallium nitride, and diamond. The semiconductor manufacturing apparatus according to claim 1.

9. The inspection unit detects a first penetration dislocation among the defects of the first wafer and retains information regarding the location of the first penetration dislocation. The estimation unit estimates the location of the second penetration dislocation among the defects of the second wafer based on information regarding the distance in the growth plane direction of the ingot, and retains information regarding the location of the second penetration dislocation. The evaluation unit evaluates the first and second wafers based on the information relating to the position of the first penetration dislocation, the information relating to the position of the second penetration dislocation, the information relating to the distance in the growth surface direction of the ingot, information relating to the layout of the chip areas of the first and second wafers, information relating to the patterns arranged within the chip areas, and information relating to the process for forming elements within the chip areas. The semiconductor manufacturing apparatus according to claim 1.

10. Inspecting the first wafer obtained from the ingot, Based on the inspection results of the defects in the first wafer, the location of the defects in the second wafer obtained from the ingot is estimated, Evaluating the first and second wafers based on the location of the defect in the first wafer and the location of the defect in the second wafer, A method for manufacturing a semiconductor device comprising the above.

11. A first penetration dislocation is detected among the defects of the first wafer, and information regarding the location of the first penetration dislocation is retained. Based on information regarding the distance in the growth plane direction of the ingot, the location of the second penetration dislocation among the defects of the second wafer is estimated, and information regarding the location of the second penetration dislocation is retained. The first and second wafers are evaluated based on the information relating to the position of the first penetration dislocation, the information relating to the position of the second penetration dislocation, the information relating to the distance in the growth plane direction of the ingot, information relating to the layout of the chip areas of the first and second wafers, information relating to the patterns arranged within the chip areas, and information relating to the process for forming elements within the chip areas. A method for manufacturing a semiconductor device according to claim 10.

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