Liquid ejection device and print head drive circuit

Abstract

To provide a liquid dispensing device capable of driving many drive elements at a high frequency. [Solution] A liquid dispensing device in which a first transistor included in an amplification circuit that outputs an amplified modulated signal obtained by amplifying the modulated signal of a print head drive circuit includes a first conductor that functions as a source electrode, a second conductor that functions as a gate electrode, a third conductor that functions as a drain electrode, a first layer including a first semiconductor region of a first conductivity type having a trench and a second semiconductor region of a second conductivity type provided in the trench, and a second layer including a third semiconductor region of a first conductivity type, a fourth semiconductor region of a second conductivity type provided in the third semiconductor region, and a fifth semiconductor region of a first conductivity type provided in the fourth semiconductor region, wherein the first layer is arranged above the third conductor, the second layer is arranged above the first layer, the first conductor is arranged above the fourth semiconductor region, and the second conductor is arranged above the fifth semiconductor region.

Description

Technical Field

[0005] , ,

[0001] The present invention relates to a liquid ejection device and a print head drive circuit.

Background Art

[0002] A liquid ejection device such as an inkjet printer has a print head that ejects a liquid and a print head drive circuit that controls the print head. The print head drive circuit outputs a drive signal for driving a drive element such as a piezoelectric element provided in the print head, and the print head ejects ink by driving the drive element. The liquid ejection device forms an image on a medium by landing the ink ejected from the print head at a desired position on the medium.

[0003] For example, Patent Document 1 discloses a liquid ejection device having a head drive circuit that outputs a drive signal and a print head unit that ejects ink in response to the drive signal.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In recent years, in response to the market demand for improving productivity in liquid ejection devices, there has been a demand for improving the image formation speed on a medium in liquid ejection devices. Therefore, the print head drive circuit that drives the print head that ejects a liquid is required to output a drive signal that can drive more drive elements at a higher frequency. However, the technology described in Patent Document 1 is not sufficient from the viewpoint of outputting a drive signal that can drive more drive elements at a higher frequency, and there is room for improvement.

Means for Solving the Problems

[0006] One embodiment of the liquid dispensing device according to the present invention is: A print head that ejects liquid in response to a drive signal, A print head drive circuit that outputs the aforementioned drive signal, Equipped with, The print head drive circuit is A modulation circuit that outputs a modulated signal obtained by modulating the base drive signal which is the basis of the drive signal, An amplification circuit that outputs an amplified modulated signal obtained by amplifying the modulated signal with a first transistor and a second transistor, A demodulation circuit that demodulates the amplified modulated signal and outputs it as the drive signal, It has, The first transistor is, A first conductor that functions as a source electrode, A second conductor that functions as a gate electrode, A third conductor that functions as a drain electrode, A first layer comprising a first semiconductor region of a first conductivity type having a trench, and a second semiconductor region of a second conductivity type provided in the trench, A second layer including a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type provided in the third semiconductor region, and a fifth semiconductor region of the first conductivity type provided in the fourth semiconductor region, Includes, The first layer is positioned above the third conductor. The second layer is positioned above the first layer. The first conductor is positioned above the fourth semiconductor region. The second conductor is positioned above the fifth semiconductor region.

[0007] One embodiment of the print head drive circuit according to the present invention is: A print head drive circuit that outputs the drive signal to a print head that ejects liquid in response to the drive signal, A modulation circuit that outputs a modulated signal obtained by modulating the base drive signal which is the basis of the drive signal, An amplification circuit that outputs an amplified modulation signal obtained by amplifying the modulation signal by the first transistor and the second transistor; A demodulation circuit that demodulates the amplified modulation signal and outputs it as the drive signal; and has The first transistor includes a first conductor that functions as a source electrode; a second conductor that functions as a gate electrode; a third conductor that functions as a drain electrode; a first layer including a first semiconductor region of the first conductivity type having a trench and a second semiconductor region of the second conductivity type provided in the trench; a second layer including a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type provided in the third semiconductor region, and a fifth semiconductor region of the first conductivity type provided in the fourth semiconductor region; and includes the first layer is disposed above the third conductor; the second layer is disposed above the first layer; the first conductor is disposed above the fourth semiconductor region; the second conductor is disposed above the fifth semiconductor region.

Brief Description of Drawings

[0008] [Figure 1] It is a diagram showing an example of the schematic configuration of a liquid ejection device. [Figure 2] It is a diagram showing an example of the functional configuration of a liquid ejection device. [Figure 3] It is a diagram showing the schematic structure of a discharge part. [Figure 4] It is a diagram showing an example of the signal waveforms of the drive signals COMA, COMB, and COMC. [Figure 5] It is a diagram showing an example of the configuration of a selection control circuit and a selection circuit. [Figure 6] It is a diagram showing an example of the decoding content in a decoder. [Figure 7] It is a diagram showing an example of the configuration of a selection circuit. [Figure 8]It is a diagram for explaining the operations of the selection control circuit and the selection circuit. [Figure 9] It is a diagram showing an example of the configuration of the drive circuit. [Figure 10] It is a diagram showing an example of the structure of the transistor M1.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. The drawings used are for convenience of explanation. Note that the embodiments described below do not unduly limit the content of the present invention described in the claims. Also, not all of the configurations described below are essential constituent elements of the present invention.

[0010] 1. Outline of the Liquid Discharge Device FIG. 1 is a diagram showing an example of the schematic configuration of the liquid discharge device 1. The liquid discharge device 1 includes a carriage 21 on which a print head 20 for discharging ink, which is an example of a liquid, is mounted. The carriage 21 reciprocates along the scanning axis and discharges ink onto a medium P that is conveyed along the conveyance direction, thereby forming a desired image on the medium P. It is a serial printing type inkjet printer. As the medium P used in such a liquid discharge device 1, any printing target such as printing paper, resin film, cloth, etc. can be used. Note that the liquid discharge device 1 is not limited to a serial printing type inkjet printer and may be a line printing type inkjet printer. Also, the liquid discharge device 1 is not limited to an inkjet printer and may be a color material discharge device used for manufacturing color filters such as liquid crystal displays, an electrode material discharge device used for forming electrodes such as organic EL displays and FEDs (surface emission displays), a bio-organic substance discharge device used for manufacturing biochips, a three-dimensional modeling device, a printing device, and the like. As shown in FIG. 1, the liquid discharge device 1 includes an ink container 2, a control unit 10, a print head 20, a moving unit 30, and a conveyance unit 40.

[0011] In ​

[0012] The ink container 2 stores multiple types of ink that are dispensed onto the medium P. The colors of the ink stored in the ink container 2 include black, cyan, magenta, yellow, red, and gray. The ink container 2 can be an ink cartridge, a bag-shaped ink pack made of flexible film, or an ink tank that allows for ink replenishment.

[0013] The control unit 10 includes, for example, processing circuits such as a CPU (Central Processing Unit) and an FPGA (Field Programmable Gate Array), storage circuits such as semiconductor memory, and various other circuits, and controls each element of the liquid ejection device 1, including the print head 20.

[0014] The print head 20 is mounted on the carriage 21. The carriage 21 is fixed to an endless belt 32 included in the moving unit 30. In addition to the print head 20, the carriage 21 may also be equipped with an ink container 2.

[0015] The print head 20 mounted on the carriage 21 receives a control signal Ctrl-H and a drive signal COM, both output by the control unit 10, to control the print head 20. Ink stored in the ink container 2 is supplied to the print head 20 via a tube (not shown). The print head 20 then ejects the ink supplied from the ink container 2 based on the input control signal Ctrl-H and drive signal COM.

[0016] The moving unit 30 includes a carriage motor 31 and an endless belt 32. The carriage motor 31 is driven based on a control signal Ctrl-C input from the control unit 10. The endless belt 32 rotates in accordance with the drive of the carriage motor 31. As a result, the carriage 21 fixed to the endless belt 32 reciprocates along the scanning axis. That is, the print head 20 mounted on the carriage 21 reciprocates along the scanning axis that intersects the transport direction in which the medium P is transported.

[0017] The transport unit 40 includes a transport motor 41 and transport rollers 42. The transport motor 41 is driven based on a control signal Ctrl-T input from the control unit 10. The transport rollers 42 rotate in accordance with the drive of the transport motor 41. As the transport rollers 42 rotate, the medium P is transported in the transport direction.

[0018] In the liquid dispensing device 1 configured as described above, the transport unit 40 transports the medium P and the moving unit 30 reciprocates the carriage 21, and the print head 20 mounted on the carriage 21 dispenses ink onto the medium P. As a result, the ink dispensed from the print head 20 lands at any desired position on the surface of the medium P. Consequently, the desired ink is applied to the medium P. An image is formed.

[0019] A specific example of the functional configuration of the liquid dispensing device 1, which is configured as described above, will now be explained. Figure 2 is a diagram showing an example of the functional configuration of the liquid dispensing device 1. As shown in Figure 2, the liquid dispensing device 1 has a control unit 10, a print head 20, a moving unit 30, and a transport unit 40.

[0020] The control unit 10 includes a control circuit 100, drive circuits 50a, 50b, 50c, and a reference voltage output circuit 52.

[0021] The control circuit 100 receives an image signal from an external device such as a host computer, generates various control signals corresponding to the image signal, and outputs them to the corresponding configuration.

[0022] Specifically, the control circuit 100 generates control signals Ctrl-T and Ctrl-C when an image signal is input and printing is performed on the medium P. The control signal Ctrl-T output by the control circuit 100 is input to the transport motor 41 included in the transport unit 40. The transport motor 41 is driven according to the control signal Ctrl-T. The medium P is transported along the transport direction by the driving force of this transport motor 41. The control signal Ctrl-C output by the control circuit 100 is input to the carriage motor 31 included in the moving unit 30. The carriage motor 31 is driven according to the control signal Ctrl-C. The carriage 21 on which the print head 20 is mounted moves back and forth along the scanning axis by the driving force of this carriage motor 31. The transport unit 40 may include one or more transport rotors in addition to the transport motor 41. The transport unit 40 may also include a transport motor driver circuit for converting the control signal Ctrl-T into a predetermined signal to drive the transport motor 41. Furthermore, the mobile unit 30 may include a carriage motor driver circuit for converting the control signal Ctrl-C into a predetermined signal for driving the carriage motor 31.

[0023] Furthermore, the control circuit 100 generates digital base drive signals dA, dB, and dC and outputs them to the corresponding drive circuits 50a, 50b, and 50c.

[0024] The base drive signal dA is input to the drive circuit 50a. The drive circuit 50a converts the input base drive signal dA from digital to analog, and generates a drive signal COMA as a drive signal COM by amplified in Class D, which is output to the print head 20. The base drive signal dB is input to the drive circuit 50b. The drive circuit 50b converts the input base drive signal dB from digital to analog, and generates a drive signal COMB as a drive signal COM by amplified in Class D, which is output to the print head 20. The base drive signal dC is input to the drive circuit 50c. The drive circuit 50c converts the input base drive signal dC from digital to analog, and generates a drive signal COMC as a drive signal COM by amplified in Class D, which is output to the print head 20.

[0025] In other words, the control circuit 100 outputs base drive signals dA, dB, dC, which are the basis for the drive signals COMA, COMB, COMC, and the drive circuits 50a, 50b, 50c generate the drive signals COMA, COMB, COMC by performing Class D amplification of the signal waveform defined by the input base drive signals dA, dB, dC, and output them to the print head 20.

[0026] The reference voltage output circuit 52 generates a reference voltage signal VBS, which is a constant DC voltage with a voltage value of 5.5V, 6V, etc., and outputs it to the print head 20. The reference voltage signal VBS functions as the reference potential for driving the piezoelectric element 60 of the print head 20, which will be described later. The potential of the voltage signal VBS is not limited to 5.5V or 6V; it may also be ground potential.

[0027] Furthermore, the control circuit 100 generates a clock signal SCK, a print data signal SI, and a latch signal LAT as control signals Ctrl-H based on the image signal input from an external device, and outputs them to the print head 20.

[0028] The print head 20 includes a selection control circuit 210, a plurality of selection circuits 230, and a plurality of ejection units 600. The plurality of ejection units 600 are provided corresponding to each of the plurality of selection circuits 230.

[0029] The selection control circuit 210 receives the clock signal SCK, print data signal SI, and latch signal LAT as control signals Ctrl-H. Based on the input clock signal SCK, print data signal SI, and latch signal LAT, the selection control circuit 210 generates a selection signal S corresponding to each of the multiple selection circuits 230 and outputs it to the corresponding selection circuit 230.

[0030] Each selection circuit 230 receives drive signals COMA, COMB, and COMC as drive signals COM, and a corresponding selection signal S output by the selection control circuit 210. Based on the input selection signal S, the selection circuit 230 generates a drive signal VOUT by selecting or deselecting each of the drive signals COMA, COMB, and COMC, and supplies the generated drive signal VOUT to the corresponding discharge unit 600.

[0031] Each of the multiple ejection units 600 includes a piezoelectric element 60. A drive signal VOUT, output by the corresponding selection circuit 230, is supplied to one end of the piezoelectric element 60 in each of the multiple ejection units 600. A reference voltage signal VBS, output by the reference voltage output circuit 52, is supplied to the other end of the piezoelectric element 60 in each of the multiple ejection units 600. The piezoelectric element 60 is driven according to the potential difference between the drive signal VOUT supplied to one end and the reference voltage signal VBS supplied to the other end. An amount of ink corresponding to the drive of the piezoelectric element 60 is ejected from the ejection unit 600.

[0032] In other words, the liquid ejection device 1 comprises a print head 20 that ejects ink in response to a drive signal COM, and a drive circuit 50 that is part of a control unit 10 that outputs a drive signal COM to the print head 20. To put it another way, the drive circuit 50 of the control unit 10 outputs a drive signal COM to the print head 20 that ejects ink in response to the drive signal COM.

[0033] Here, an example of the structure of the ejection unit 600 of the print head 20 will be described. Figure 3 is a schematic diagram of one of the multiple ejection units 600 of the print head 20. As shown in Figure 3, the ejection unit 600 includes a piezoelectric element 60, a diaphragm 621, a cavity 631, and a nozzle 651.

[0034] Cavity 631 is filled with ink supplied from reservoir 641. Ink is also introduced into reservoir 641 from ink container 2 via an ink tube (not shown) and supply port 661. In other words, cavity 631 is filled with ink stored in the corresponding ink container 2.

[0035] The diaphragm 621 is displaced by the drive of the piezoelectric element 60 located on its upper surface in Figure 3. As the diaphragm 621 is displaced, the internal volume of the cavity 631, where the ink is filled, expands and contracts. In other words, the diaphragm 621 changes the internal volume of the cavity 631. It functions as a diaphragm that converts matter.

[0036] The nozzle 651 is provided on the nozzle plate 632 and is an opening that communicates with the cavity 631. As the internal volume of the cavity 631 changes, an amount of ink corresponding to the change in internal volume is ejected from the nozzle 651.

[0037] The piezoelectric element 60 has a structure in which a piezoelectric body 601 is sandwiched between a pair of electrodes 611 and 612. In a piezoelectric body 601 with this structure, the central portion of the electrodes 611 and 612 flexes vertically together with the diaphragm 621 in accordance with the potential difference of the signal supplied to the electrodes 611 and 612.

[0038] For example, a drive signal VOUT is supplied to one end of the piezoelectric element 60, to either electrode 611 or electrode 612, and a reference voltage signal VBS is supplied to the other end of the piezoelectric element 60, to the other electrode 611 or electrode 612. When the voltage value of the drive signal VOUT increases, the piezoelectric element 60 bends upward. As the piezoelectric element 60 bends upward, the diaphragm 621 is displaced, and the internal volume of the cavity 631 expands. As a result, ink is drawn in from the reservoir 641. On the other hand, when the voltage value of the drive signal VOUT decreases, the piezoelectric element 60 bends downward. As the piezoelectric element 60 bends downward, the diaphragm 621 is displaced, and the internal volume of the cavity 631 shrinks. As a result, an amount of ink corresponding to the degree of shrinkage is ejected from the nozzle 651.

[0039] In other words, the ejection unit 600 includes a piezoelectric element 60 that is driven by a drive signal VOUT based on a drive signal COM, and the piezoelectric element 60 is driven to eject ink. In other words, the print head 20 ejects ink according to the drive signals COMA, COMB, and COMC.

[0040] In this embodiment, the liquid ejection device 1 is assumed to have a print head 20 with 3,000 or more ejection units 600, and the drive circuits 50a, 50b, and 50c supply drive signals COMA, COMB, and COMC to the 3,000 or more ejection units 600, with the aim of improving the speed of image formation on the medium P and increasing productivity in the liquid ejection device 1. Specifically, the print head 20 is assumed to have 3,000 or more piezoelectric elements 60, and the drive circuits 50a, 50b, and 50c supply drive signals COMA, COMB, and COMC to the 3,000 or more piezoelectric elements 60. This increases the amount of ink that can be ejected at once, which in turn increases the number of dots that can be formed on the medium P at once, thereby improving the speed of image formation on the medium P and increasing productivity in the liquid ejection device 1. Specifically, the print head 20 includes 3,000 or more piezoelectric elements 60, and these 3,000 or more piezoelectric elements 60 are driven by the drive signal COM output by the drive circuit 50.

[0041] The structure of the piezoelectric element 60 is not limited to the example shown in Figure 3; any structure that allows ink to be ejected from the ejection unit 600 is acceptable. Therefore, the structure of the piezoelectric element 60 is not limited to the bending vibration structure described above; for example, a structure using longitudinal vibration may also be used. Furthermore, the piezoelectric element 60 may be configured to bend downward when the voltage value of the drive signal VOUT increases, and to bend upward when the voltage value of the drive signal VOUT decreases.

[0042] 2. Signal waveform of the drive signal Next, we will describe examples of the signal waveforms of the drive signals COMA, COMB, and COMC output by the drive circuits 50a, 50b, and 50c. Figure 4 shows examples of the signal waveforms of the drive signals COMA, COMB, and COMC. As shown in Figure 4, each of the drive signals COMA, COMB, and COMC includes drive waveforms Adp, Bdp, and Cdp, which are arranged in the period tp from when the latch signal LAT rises until the next latch signal LAT rises. Then, at each period tp, the selection control circuit 210 and the selection circuit 230 select one of the drive signals COMA, COMB, or COMC and one of the drive waveforms Adp, Bdp, or Cdp based on the clock signal SCK and the print data signal SI, and output it as the drive signal VOUT.

[0043] As shown in Figure 4, the drive waveform Adp drives the corresponding piezoelectric element 60 by changing the voltage value between voltages va1 and va5 during the period tp. This driving of the piezoelectric element 60 causes a predetermined amount of ink to be ejected from the corresponding nozzle 651. In other words, the drive waveform Adp included in the drive signal COMA is a signal waveform for driving the corresponding piezoelectric element 60 so that a predetermined amount of ink is ejected from the ejection unit 600. Hereinafter, in the explanation, we will assume that voltage va1 is 36V, voltage va2 is 15V, voltage va3 is 12V, voltage va4 is 8V, and voltage va5 is 5V, but the values ​​of voltages va1 to va5 are not limited to these.

[0044] Specifically, at the timing when the latch signal LAT rises, which marks the start of period tp, the voltage value of the drive waveform Adp is constant at voltage va3. Subsequently, the voltage value of the drive waveform Adp begins to rise at time ta1 and becomes constant at voltage va1 at time ta2. Then, the voltage value of the drive waveform Adp begins to fall at time ta3, becomes constant at voltage va2 at time ta4, begins to fall again at time ta5, and becomes constant at voltage va5 at time ta6. Subsequently, the voltage value of the drive waveform Adp begins to rise at time ta7, becomes constant at voltage va4 at time ta8, begins to rise again at time ta9, and becomes constant at voltage va3 at time ta10. After that, the period tp ends as the latch signal LAT rises.

[0045] In the ejection unit 600 to which the drive waveform Adp described above is supplied, at the timing when the latch signal LAT rises, the ink stored in the ink container 2 is supplied to the cavity 631 via the supply port 661. At this time, the position of the meniscus in the nozzle 651, which is the position of the tip of the ink stored inside the nozzle 651 of the ejection unit 600, is approximately the same as the position of the tip of the nozzle 651. Then, at time ta1, when the voltage value of the drive waveform Adp increases, the piezoelectric element 60 in the ejection unit 600 to which the drive waveform Adp is supplied bends upward as shown in Figure 3, and the internal volume of the cavity 631 increases. As a result, the ink stored inside the nozzle 651 of the ejection unit 600 is drawn into the cavity 631, and the position of the meniscus in the nozzle 651 moves upward as shown in Figure 3.

[0046] Subsequently, at time ta2, the voltage value of the drive waveform Adp becomes constant, maintaining the position of the meniscus in the nozzle 651 of the discharge unit 600. Then, at time ta3, when the voltage value of the drive waveform Adp decreases, the piezoelectric element 60 in the discharge unit 600 to which the drive waveform Adp is supplied bends downward as shown in Figure 3, and the internal volume of the cavity 631 decreases. As a result, the ink stored in the cavity 631 is pressurized and moves toward the corresponding nozzle 651. At this time, the central part of the meniscus formed by the ink stored inside the nozzle 651 is pushed out, forming a downward-extending liquid column as shown in Figure 3.

[0047] At time ta4, when the voltage value of the drive waveform Adp becomes constant, the liquid column formed in the center of the meniscus tends to extend downward due to inertia, as shown in Figure 3. Then, at time ta5, the voltage value of the drive waveform Adp decreases, and the internal volume of the cavity 631 decreases, pressurizing the ink stored in the cavity 631. As a result, the ink separates from the liquid column and is ejected as droplets.

[0048] Subsequently, at time ta6, the voltage value of the drive waveform Adp becomes constant, and from time ta7 to ta10, the voltage value of the drive waveform Adp increases and becomes constant at voltage va3. As a result, the displacement of the piezoelectric element 60 in the ejection unit 600 to which the drive waveform Adp is supplied, and the internal volume of the cavity 631, are in the state corresponding to the rising edge of the latch signal LAT. At this time, an amount of ink corresponding to the amount of ink ejected is supplied from the ink container 2 to the cavity 631 via the supply port 661 by capillary action. As a result, the position of the meniscus in the nozzle 651 of the ejection unit 600 at the timing of the rising edge of the latch signal LAT is approximately the same as the position of the tip of the nozzle 651.

[0049] Furthermore, as shown in Figure 4, the drive waveform Bdp drives the corresponding piezoelectric element 60 by changing the voltage value between voltage vb1 and voltage vb5 during the period tp. This driving of the piezoelectric element 60 causes a smaller amount of ink than the predetermined amount described above to be ejected from the corresponding nozzle 651. In other words, the drive waveform Bdp included in the drive signal COMB is a signal waveform for driving the corresponding piezoelectric element 60 so that a smaller amount of ink than the predetermined amount is ejected from the ejection unit 600. Hereinafter, in the following explanation, we will assume that voltage vb1 is 36V, voltage vb2 is 20V, voltage vb3 is 12V, voltage vb4 is 10V, and voltage vb5 is 7V, but the values ​​of voltages vb1 to vb5 are not limited to these.

[0050] Specifically, at the timing when the latch signal LAT rises, which marks the start of period tp, the voltage value of the drive waveform Bdp is constant at voltage vb3. Subsequently, the voltage value of the drive waveform Bdp begins to rise at time tb1 and becomes constant at voltage vb1 at time tb2. Then, the voltage value of the drive waveform Bdp begins to fall at time tb3, becomes constant at voltage vb4 at time tb4, then begins to rise at time tb5, becomes constant at voltage vb2 at time tb6, then begins to fall at time tb7, and becomes constant at voltage vb5 at time tb8. Finally, the voltage value of the drive waveform Bdp begins to rise at time tb9 and becomes constant at voltage vb3 at time tb10. After that, the period tp ends as the latch signal LAT rises.

[0051] In the ejection unit 600 to which the drive waveform Bdp is supplied as described above, at the timing when the latch signal LAT rises, the ink stored in the ink container 2 is supplied to the cavity 631 via the supply port 661. At this time, the position of the meniscus in the nozzle 651, which is the position of the tip of the ink stored inside the nozzle 651 of the ejection unit 600, is approximately the same as the position of the tip of the nozzle 651. Then, at time tb1, when the voltage value of the drive waveform Bdp increases, the piezoelectric element 60 in the ejection unit 600 to which the drive waveform Bdp is supplied bends upward as shown in Figure 3, and the internal volume of the cavity 631 increases. As a result, the ink stored inside the nozzle 651 of the ejection unit 600 is drawn into the cavity 631, and the position of the meniscus in the nozzle 651 moves upward as shown in Figure 3.

[0052] Subsequently, at time tb2, the voltage value of the drive waveform Bdp becomes constant, maintaining the position of the meniscus in the nozzle 651 of the ejection unit 600. Then, at time tb3, when the voltage value of the drive waveform Bdp decreases, the piezoelectric element 60 in the ejection unit 600 to which the drive waveform Bdp is supplied bends downward as shown in Figure 3, reducing the internal volume of the cavity 631. As a result, the ink stored in the cavity 631 is pressurized and moves toward the corresponding nozzle 651. At this time, the central part of the meniscus formed by the ink stored inside the nozzle 651 is pushed out, forming a downward-extending liquid column as shown in Figure 3.

[0053] At time tb4, when the voltage value of the drive waveform Bdp becomes constant, the liquid column formed in the center of the meniscus tends to extend downwards due to inertial force, as shown in Figure 3. Then, at time t At time b5, as the voltage value of the drive waveform Bdp increases and the internal volume of the cavity 631 increases, the liquid column that was trying to extend downward as shown in Figure 3 is pulled in by inertia. Subsequently, at time tb6, after the voltage value of the drive waveform Bdp becomes constant, at time tb7, as the voltage value of the drive waveform Bdp decreases, the internal volume of the cavity 631 decreases, the ink stored in the cavity 631 is pressurized, the ink separates from the liquid column and is ejected as droplets. At this time, at time tb5, the liquid column that was trying to extend downward as shown in Figure 3 is pulled in by inertia, and at time tb7, the pressurized ink separated from the liquid column is ejected as droplets. As a result, the amount of ink ejected from the ejection unit 600 supplied with the drive waveform Bdp is less than the amount of ink ejected from the ejection unit 600 supplied with the drive waveform Adp.

[0054] Subsequently, at time tb8, the voltage value of the drive waveform Bdp becomes constant, and at times tb9 to tb10, the voltage value of the drive waveform Bdp increases and becomes constant at voltage vb3. As a result, the displacement of the piezoelectric element 60 in the ejection unit 600 to which the drive waveform Bdp is supplied, and the internal volume of the cavity 631, are in the state corresponding to the rising edge of the latch signal LAT. At this time, an amount of ink corresponding to the amount of ink ejected is supplied from the ink container 2 to the cavity 631 via the supply port 661 by capillary action. As a result, the position of the meniscus in the nozzle 651 of the ejection unit 600 at the timing of the rising edge of the latch signal LAT is approximately the same as the position of the tip of the nozzle 651.

[0055] Furthermore, as shown in Figure 4, the drive waveform Cdp drives the corresponding piezoelectric element 60 by changing the voltage value between voltage vc1 and voltage vc2 during the period tp. This driving of the piezoelectric element 60 prevents ink from being ejected from the corresponding nozzle 651, and causes the ink near the opening of the nozzle 651 to vibrate. This reduces the risk of an increase in the viscosity of the ink near the opening of the nozzle 651. In other words, the drive waveform Cdp included in the drive signal COMC is a signal waveform for driving the piezoelectric element 60 so that ink is not ejected from the ejection unit 600, and the ink near the opening of the nozzle 651 of the ejection unit 600 vibrates. Hereinafter, in the following explanation, we will assume that voltage vc1 is 15V and voltage vc2 is 12V, but the values ​​of voltage vc1 and voltage vc2 are not limited to these.

[0056] Specifically, at the timing when the latch signal LAT rises, which marks the start of period tp, the voltage value of the drive waveform Cdp is constant at voltage vc2. Subsequently, the voltage value of the drive waveform Cdp begins to rise at time tc1 and becomes constant at voltage vc1 at time tc2. Then, the voltage value of the drive waveform Cdp begins to fall at time tc3 and becomes constant at voltage vc1 at time tc4. After that, the period tp ends when the latch signal LAT rises.

[0057] In the ejection unit 600 to which the drive waveform Cdp described above is supplied, at the timing when the latch signal LAT rises, the ink stored in the ink container 2 is supplied to the cavity 631 via the supply port 661. At this time, the position of the meniscus in the nozzle 651, which is the position of the tip of the ink stored inside the nozzle 651 of the ejection unit 600, is approximately the same as the position of the tip of the nozzle 651. Then, at time tc1, when the voltage value of the drive waveform Cdp increases, the piezoelectric element 60 in the ejection unit 600 to which the drive waveform Cdp is supplied bends upward as shown in Figure 3, and the internal volume of the cavity 631 increases. As a result, the ink stored inside the nozzle 651 of the ejection unit 600 is drawn into the cavity 631, and the position of the meniscus in the nozzle 651 moves upward as shown in Figure 3. Subsequently, at time tc2, the voltage value of the drive waveform Bdp becomes constant, maintaining the position of the meniscus in the nozzle 651 of the discharge unit 600. Then, at time tc3, when the voltage value of the drive waveform Cdp decreases, the piezoelectric element 60 in the discharge unit 600 to which the drive waveform Cdp is supplied bends downward as shown in Figure 3, creating a cavity 6 The internal volume of 31 decreases. As a result, the ink stored in the cavity 631 is pressurized and moves toward the corresponding nozzle 651. At this time, the central part of the meniscus formed by the ink stored inside the nozzle 651 is pushed out, forming the downward-extending liquid column shown in Figure 3. Subsequently, at time tc4, the voltage value of the drive waveform Bdp becomes constant. At this time, the change in the voltage value of the drive waveform Cdp is smaller than the change in the voltage value of the drive waveform Adp and the change in the voltage value of the drive waveform Bdp, and therefore the ink does not separate from the liquid column. Consequently, the ink only vibrates from the nozzle 651 and is not ejected.

[0058] Furthermore, at time tc4, as the voltage value of the drive waveform Cdp becomes constant at voltage vc2, the displacement of the piezoelectric element 60 in the discharge section 600 to which the drive waveform Cdp is supplied, and the internal volume of the cavity 631, are in the rising edge state of the latch signal LAT.

[0059] As described above, the drive circuit 50a outputs a drive signal COMA including a drive waveform Adp that drives the piezoelectric element 60 so that a predetermined amount of ink is ejected from the ejection unit 600, the drive circuit 50b outputs a drive signal COMB including a drive waveform Bdp that drives the piezoelectric element 60 so that a smaller amount than a predetermined amount of ink is ejected from the ejection unit 600, and the drive circuit 50c outputs a drive signal COMC including a drive waveform Cdp that drives the piezoelectric element 60 so that no ink is ejected from the ejection unit 600, but the ink near the opening of the corresponding nozzle 651 vibrates. In the following description, when the drive waveform Adp is supplied to one end of the piezoelectric element 60, the amount of ink ejected from the corresponding ejection unit 600 may be referred to as a large amount, and when the drive waveform Bdp is supplied to one end of the piezoelectric element 60, the amount of ink ejected from the corresponding ejection unit 600 may be referred to as a small amount. Furthermore, when the drive waveform Cdp is supplied to one end of the piezoelectric element 60, the operation that vibrates the ink near the nozzle opening of the ejection unit 600 corresponding to the piezoelectric element 60 is sometimes referred to as micro-vibration.

[0060] In this embodiment, the liquid ejection device 1 aims to improve the speed of image formation on the medium P and, from the viewpoint of improving productivity in the liquid ejection device 1, assumes that the period tp during which ink is ejected from the ejection unit 600 by the drive signals COMA, COMB, COMC is 10 μs or less. That is, assume that the frequency of the period tp of the drive signals COMA, COMB, COMC output by the drive circuits 50a, 50b, 50c is 100 kHz or higher. As a result, the liquid ejection device 1 of this embodiment can improve the speed of image formation on the medium P and improve productivity in the liquid ejection device 1. That is, the frequency of the drive signal COM in this embodiment is 100 kHz or higher.

[0061] 3. Configuration and Operation of Selection Control Circuit and Selection Circuit Next, the configuration and operation of the selection control circuit 210 and selection circuit 230, which generate the drive signal VOUT by selecting or deselecting the signal waveforms included in the drive signals COMA, COMB, and COMC and outputting it to the corresponding ejection unit 600, will be described. Figure 5 shows an example of the configuration of the selection control circuit 210 and selection circuit 230. In the following description, the more than 3000 piezoelectric elements 60 in the print head 20 will be described as n piezoelectric elements 60.

[0062] The selection control circuit 210 receives a clock signal SCK, a print data signal SI, and a latch signal LAT. Furthermore, the selection control circuit 210 is equipped with a set of shift registers (S / R) 212, latch circuits 214, and decoders 216, each corresponding to one of the n piezoelectric elements 60. In other words, the selection control circuit 210 includes n shift registers 212, n latch circuits 214, and n decoders 216.

[0063] The print data signal SI is input to the selection control circuit 210 in synchronization with the clock signal SCK. Furthermore, the print data signal SI serially includes 2 bits of print data [SIH,SIL] corresponding to each of the n piezoelectric elements 60 for selecting one of the following: "large dot LD", "small dot SD", "non-recorded ND", and "micro-vibration BSD". The print data [SIH,SIL] included in the print data signal SI is held in n shift registers 212 corresponding to the n piezoelectric elements 60. Specifically, the n shift registers 212 corresponding to the piezoelectric elements 60 are connected in cascading order, and the serially input print data signal SI is sequentially transferred to the subsequent shift registers 212 according to the clock signal SCK. Then, when the print data [SIH,SIL] is held in the corresponding shift register 212, the clock signal SCK stops. As a result, the print data [SIH,SIL] included in the print data signal SI is held in the corresponding shift register 212. In Figure 5, the n shift registers 212 are labeled as 1st stage, 2nd stage, ..., nth stage in order from the upstream side where the print data signal SI is input, in order to distinguish them.

[0064] Each of the n latch circuits 214 simultaneously latches the print data [SIH,SIL] held in the corresponding shift register 212 on the rising edge of the latch signal LAT. The print data [SIH,SIL] latched by the latch circuits 214 is then input to the corresponding decoder 216. Figure 6 shows an example of the decoding content in the decoder 216. At period tp, the decoder 216 outputs selection signals S1, S2, and S3 as selection signals S of a logic level defined by the input print data [SIH,SIL]. For example, if print data [SIH,SIL]=[1,0] is input to the decoder 216, the decoder 216 outputs an L-level selection signal S1, an H-level selection signal S2, and an L-level selection signal S3 at period tp.

[0065] The selection signals S1, S2, and S3 output by the decoder 216 are input to the selection circuit 230. The selection circuit 230 is provided corresponding to each of the n output units 600. Figure 7 shows an example of the configuration of the selection circuit 230. As shown in Figure 7, the selection circuit 230 includes inverters 232a, 232b, and 232c, which are NOT gates, and transfer gates 234a, 234b, and 234c.

[0066] The selection signal S1 is input to the positive control terminal of the transfer gate 234a that is not marked with a circle, and after its logic level is inverted by the inverter 232a, it is also input to the negative control terminal of the transfer gate 234a that is marked with a circle. In addition, the drive signal COMA is supplied to the input terminal of the transfer gate 234a. The transfer gate 234a conducts between its input terminal and output terminal when a high-level selection signal S1 is input, and does not conduct between its input terminal and output terminal when a low-level selection signal S1 is input. That is, the transfer gate 234a outputs the drive waveform Adp included in the drive signal COMA from its output terminal when the logic level of the selection signal S1 is high, and does not output the drive waveform Adp included in the drive signal COMA from its output terminal when the logic level of the selection signal S1 is low.

[0067] The selection signal S2 is input to the positive control terminal of the transfer gate 234b that is not marked with a circle, and after its logic level is inverted by the inverter 232b, it is also input to the negative control terminal of the transfer gate 234b that is marked with a circle. In addition, the drive signal COMB is supplied to the input terminal of the transfer gate 234b. The transfer gate 234b conducts between its input terminal and output terminal when a high-level selection signal S2 is input, and does not conduct between its input terminal and output terminal when a low-level selection signal S2 is input. That is, the transfer gate 234b outputs the drive waveform Bdp included in the drive signal COMB from its output terminal when the logic level of the selection signal S2 is high, and does not output the drive waveform Bdp included in the drive signal COMB from its output terminal when the logic level of the selection signal S2 is low.

[0068] The selection signal S3 is input to the positive control terminal of the transfer gate 234c that is not marked with a circle, and after its logic level is inverted by the inverter 232c, it is also input to the negative control terminal of the transfer gate 234c that is marked with a circle. In addition, the drive signal COMC is supplied to the input terminal of the transfer gate 234c. The transfer gate 234c conducts between its input terminal and output terminal when a high-level selection signal S3 is input, and does not conduct between its input terminal and output terminal when a low-level selection signal S3 is input. That is, the transfer gate 234c outputs the drive waveform Cdp included in the drive signal COMC from its output terminal when the logic level of the selection signal S3 is high, and does not output the drive waveform Cdp included in the drive signal COMC from its output terminal when the logic level of the selection signal S3 is low.

[0069] Then, in the selection circuit 230, the output terminals of transfer gate 234a, transfer gate 234b, and transfer gate 234c are connected in common. The signal at this connection point where the output terminals of transfer gate 234a, transfer gate 234b, and transfer gate 234c are connected in common is output as the drive signal VOUT.

[0070] Here, the operation of the selection control circuit 210 and the selection circuit 230 will be explained using Figure 8. Figure 8 is a diagram illustrating the operation of the selection control circuit 210 and the selection circuit 230. The print data signal SI is input to the selection control circuit 210 as a serial signal synchronized with the clock signal SCK, and in synchronization with the clock signal SCK, it is sequentially transferred to the n shift registers 212 corresponding to the n piezoelectric elements 60. After that, when the input of the clock signal SCK stops, the shift registers 212 hold the print data [SIH, SIL] corresponding to each of the n piezoelectric elements 60. The print data signal SI is input in the order corresponding to the nth, ..., 2nd, and 1st stages of the piezoelectric elements 60 in the shift registers 212.

[0071] Then, when the latch signal LAT rises, each of the latch circuits 214 simultaneously latches the print data [SIH,SIL] held in the shift register 212. Note that LT1, LT2, ..., LTn shown in Figure 8 represent the print data [SIH,SIL] latched by the latch circuits 214 corresponding to the 1st, 2nd, ..., nth stage shift register 212.

[0072] The decoder 216 outputs selection signals S1, S2, and S3, whose logic levels are defined by the latched print data [SIH, SIL], at each period tp. The selection circuit 230 then generates the drive signal VOUT by selecting or deselecting the drive signals COMA, COMB, and COMC according to the logic levels of the selection signals S1, S2, and S3 output by the decoder 216.

[0073] Specifically, when the decoder 216 receives print data [SIH,SIL]=[1,1], the decoder 216 sets the logic levels of the selection signals S1, S2, and S3 at period tp to H, L, and L levels. As a result, the selection circuit 230 supplies a drive signal VOUT, including the drive waveform Adp, to the piezoelectric element 60 of the corresponding ejection unit 600 at period tp. Consequently, a large amount of ink is ejected from the corresponding ejection unit 600. This large amount of ink ejected from the ejection unit 600 lands on the medium P, forming a large dot LD on the medium P.

[0074] Furthermore, when the printed data [SIH,SIL]=[1,0] is input to the decoder 216, the decoder 216 sets the logic levels of the selection signals S1, S2, S3 at period tp to L, H, L levels. As a result, the selection circuit 230 controls the drive waveform B at period tp. A drive signal VOUT, including dp, is supplied to the piezoelectric element 60 of the corresponding ejection unit 600. As a result, a small amount of ink is ejected from the corresponding ejection unit 600. This small amount of ink ejected from the ejection unit 600 lands on the medium P, forming small dots SD on the medium P.

[0075] Furthermore, when the decoder 216 receives print data [SIH,SIL]=[0,1], the decoder 216 sets the logic levels of the selection signals S1, S2, S3 at period tp to L, L, L. As a result, the selection circuit 230 does not select any of the drive waveforms Adp, Bdp, or Cdp at period tp. At this time, the piezoelectric element 60 of the corresponding ejection unit 600 is supplied with a signal of a constant voltage value held by the capacitive component of the piezoelectric element 60. That is, at period tp, the selection circuit 230 supplies a drive signal VOUT of a constant voltage value to the piezoelectric element 60 of the corresponding ejection unit 600. As a result, the piezoelectric element 60 of the corresponding ejection unit 600 is not driven, and no ink is ejected from this ejection unit 600. Therefore, no ink lands on the medium P, and non-recording ND is performed, which does not form dots on the medium P.

[0076] Furthermore, when the decoder 216 receives print data [SIH,SIL]=[0,0], the decoder 216 sets the logic levels of the selection signals S1, S2, and S3 at period tp to L, L, and H levels. As a result, the selection circuit 230 supplies a drive signal VOUT, including the drive waveform Cdp, to the piezoelectric element 60 of the corresponding ejection unit 600 at period tp. Consequently, no ink is ejected from the corresponding ejection unit 600, and a micro-vibration BSD is performed, which vibrates the ink near the opening of the nozzle 651 of the ejection unit 600.

[0077] As described above, the selection control circuit 210 and the selection circuit 230 generate the drive signal VOUT by selecting or deselecting the signal waveforms of the drive signals COMA, COMB, and COMC output by the drive circuits 50a, 50b, and 50c, and output it to the piezoelectric element 60 of the corresponding discharge unit 600.

[0078] 4. Configuration and Operation of the Drive Circuit Next, the configuration and operation of the drive circuits 50a, 50b, and 50c of the liquid dispensing device 1 of this embodiment will be described. Here, the drive circuits 50a, 50b, and 50c have the same configuration, differing only in the input signals and output signals. Therefore, in the following description, the drive circuits 50a, 50b, and 50c will not be distinguished and will simply be referred to as drive circuit 50. In this description, the drive circuit 50 will be described as receiving a base drive signal dO as base drive signals dA, dB, and dC, and outputting a drive signal COM as drive signals COMA, COMB, and COMC.

[0079] Figure 9 shows an example of the configuration of the drive circuit 50. As shown in Figure 9, the drive circuit 50 has an integrated circuit 500, an amplification circuit 550, a demodulation circuit 560, feedback circuits 570, 572, and several other circuit elements. The integrated circuit 500 generates gate signals Hgd and Lgd based on the base drive signal dO which is the basis of the drive signal COM, and outputs them to the amplification circuit 550. The amplification circuit 550 has transistors M1 and M2, and when transistors M1 and M2 are driven based on the gate signals Hgd and Lgd, it generates amplified modulated signals AMs and outputs them to the demodulation circuit 560. The demodulation circuit 560 demodulates the amplified modulated signals AMs by smoothing them. The signal demodulated by this demodulation circuit 560 is output from the drive circuit 50 as the drive signal COM.

[0080] The integrated circuit 500 has multiple terminals, including terminal In, terminal Bst, terminal Hdr, terminal Sw, terminal Gvd, terminal Ldr, terminal Gnd, terminal Ifb, and terminal Vfb. The integrated circuit 500 is electrically connected to an external circuit through these multiple terminals. The circuit 500 includes a DAC (Digital to Analog Converter) 511, a modulation circuit 510, and a gate drive circuit 520.

[0081] The DAC511 converts the base drive signal dO, which is a digital signal defining the waveform of the drive signal COM, into an analog base drive signal aO, and outputs it to the modulation circuit 510. The amplified signal of the base drive signal aO output by the DAC511 corresponds to the drive signal COM. In other words, the base drive signal aO is the target signal before amplification of the drive signal COM, and the base drive signal dO is the target signal before amplification of the drive signal COM, and is the signal that defines the shape of the waveform of the drive signal COM. The voltage amplitude of the base drive signal aO output by the DAC511 is set to, for example, 1V to 2V.

[0082] The modulation circuit 510 generates a modulated signal Ms by modulating the base drive signal aO and outputs it to the gate drive circuit 520. The modulation circuit 510 includes adders 512, 513, a comparator 514, an inverter 515, an integral attenuator 516, and an attenuator 517.

[0083] The integrating attenuator 516 attenuates and integrates the voltage value of the drive signal COM input via terminal Vfb, and outputs the integrated signal to the negative input terminal of adder 512. The base drive signal aO is input to the positive input terminal of adder 512. Adder 512 generates a signal with a voltage value obtained by subtracting the voltage value of the signal input to the negative input terminal from the voltage value of the signal input to the positive input terminal and integrating it, and outputs this signal to the positive input terminal of adder 513. Here, while the maximum voltage amplitude of the base drive signal aO is about 2V as described above, the voltage value of the drive signal COM can exceed 40V at its maximum value. In order to determine the deviation, the integrating attenuator 516 attenuates the drive signal COM input via terminal Vfb in order to match the range of the voltage amplitude of the base drive signal aO with the range of the voltage value amplitude of the drive signal COM.

[0084] The attenuator 517 supplies a voltage obtained by attenuating the high-frequency component of the drive signal COM input via terminal Ifb to the negative input terminal of the adder 513. The signal output by adder 512 is input to the positive input terminal of adder 513. Adder 513 generates a voltage signal As by subtracting the voltage value of the signal input to the negative input terminal from the voltage value of the signal input to the positive input terminal, and outputs it to comparator 514. The voltage signal As is obtained by subtracting the voltage value of the signal supplied to terminal Vfb from the voltage value of the base drive signal aO, and then further subtracting the voltage value of the signal supplied to terminal Ifb. Therefore, the voltage signal As is a signal in which the deviation obtained by subtracting the attenuated voltage of the drive signal COM from the target voltage value of the base drive signal aO is corrected by the high-frequency component of the drive signal COM.

[0085] The comparator 514 pulse-modulates the voltage signal As and outputs it as a modulated signal Ms. Specifically, the comparator 514 outputs a modulated signal Ms that is high level when the voltage value of the voltage signal As rises and exceeds a predetermined threshold Vth1, and low level when the voltage value of the voltage signal As falls below a predetermined threshold Vth2 during the period when the voltage value of the voltage signal As is falling. Here, the thresholds Vth1 and Vth2 are set such that threshold Vth1 > threshold Vth2. The frequency and duty cycle of this modulated signal Ms change in accordance with the base drive signals dO and aO. That is, by adjusting the modulation gain corresponding to the sensitivity of the attenuator 517, the amount of change in the frequency and duty cycle of the modulated signal Ms can be adjusted.

[0086] The modulated signal Ms is input to the gate driver 521 included in the gate drive circuit 520. Furthermore, the modulated signal Ms is inverted at a logic level by the inverter 515 and then input to the gate driver 522 also included in the gate drive circuit 520. In other words, signals with mutually exclusive logic levels are input to gate driver 521 and gate driver 522.

[0087] Here, the timing of the signals input to gate drivers 521 and 522 may be controlled so that their logic levels are not simultaneously at a high level. In other words, the "mutually exclusive relationship of logic levels" mentioned above means that the logic level of the signal input to gate driver 521 and the logic level of the signal input to gate driver 522 are not simultaneously at a high level, and this includes the case where the logic level of the signal input to gate driver 521 and the logic level of the signal input to gate driver 522 are simultaneously at a low level.

[0088] The gate drive circuit 520 includes gate driver 521 and gate driver 522.

[0089] The gate driver 521 generates a gate signal Hgd by level-shifting the modulated signal Ms output by the comparator 514, and outputs it from the integrated circuit 500 via terminal Hdr. Of the power supply voltage of the gate driver 521, the high-potential side is supplied via terminal Bst, and the low-potential side is supplied via terminal Sw. Terminal Bst is electrically connected to one end of capacitor C5 and the cathode of diode D1. The other end of capacitor C5 is electrically connected to terminal Sw. The anode of diode D1 is electrically connected to terminal Gvd. In addition, a voltage signal Vm, which is a DC voltage of, for example, 7.5V generated by a power supply circuit (not shown), is supplied to terminal Gvd. As a result, the potential difference between terminal Bst and terminal Sw is the potential difference across capacitor C5, which is approximately equal to the voltage value of the voltage signal Vm. Therefore, the gate driver 521 generates a gate signal Hgd, which, according to the logic level of the input modulation signal Ms, has a high-level voltage value that is greater than the voltage value of terminal Sw by the voltage value of the voltage signal Vm, and a low-level voltage value that is the voltage value of terminal Sw, and outputs this signal from terminal Hdr.

[0090] The gate driver 522 operates at a lower potential than the gate driver 521. The gate driver 522 generates a gate signal Lgd by level-shifting the signal obtained by inverting the logic level of the modulated signal Ms output by the comparator 514 with the inverter 515, and outputs it from the integrated circuit 500 via terminal Ldr. Of the power supply voltage of the gate driver 522, the voltage signal Vm is supplied to the high potential side, and the ground potential is supplied to the low potential side via terminal Gnd. The gate driver 522 then generates a gate signal Lgd at ground potential, where the H level voltage value is greater than the voltage value of the voltage signal Vm relative to terminal Gnd, and the L level voltage value is the voltage value of terminal Gnd, and outputs it from terminal Ldr.

[0091] As described above, the gate signal Hgd is a signal obtained by level-shifting the voltage value of the modulated signal Ms, and the gate signal Lgd is a signal obtained by level-shifting the voltage value of the inverted signal after inverting the logic level of the modulated signal Ms. In light of this, the gate signals Hgd and Lgd output by the gate drive circuit 520 can also be considered as signals obtained by modulating the base drive signals dO and aO, respectively.

[0092] The amplification circuit 550 includes a pair of transistors M1 and M2, which are semiconductor elements such as N-type FETs (Field Effect Transistors).

[0093] A voltage signal VHV, for example, a DC voltage of 42V, is supplied to the drain terminal of transistor M1. The voltage value of the voltage signal VHV is not limited to 42V; it only needs to be greater than the maximum voltage value of the drive signal COM output by the drive circuit 50. The gate terminal of transistor M1 is electrically connected to one end of resistor R1. The other end of resistor R1 is electrically connected to terminal Hdr of integrated circuit 500. The gate signal Hgd, output by the integrated circuit 500, is input to the gate terminal. The source terminal of transistor M1 is electrically connected to terminal Sw of the integrated circuit 500. The conduction state between the drain terminal and the source terminal of transistor M1 is controlled by the gate signal Hgd input to the gate terminal.

[0094] The drain terminal of transistor M2 is electrically connected to terminal Sw of integrated circuit 500. That is, the drain terminal of transistor M2 and the source terminal of transistor M1 are electrically connected to each other. The gate terminal of transistor M2 is electrically connected to one end of resistor R2. The other end of resistor R2 is electrically connected to terminal Ldr of integrated circuit 500. That is, the gate signal Lgd output by integrated circuit 500 is input to the gate terminal of transistor M2. Ground potential is supplied to the source terminal of transistor M2. The conduction state between the drain terminal and the source terminal of transistor M2 is controlled by the gate signal Lgd input to the gate terminal.

[0095] In the following explanation, the state in which the drain and source terminals of transistors M1 and M2 are controlled to conduct is referred to as "on," and the state in which the drain and source terminals of transistors M1 and M2 are controlled to not conduct is referred to as "off."

[0096] In the amplifier circuit 550 configured as described above, when transistor M1 is controlled to be off and transistor M2 is controlled to be on, the node to which terminal Sw is connected becomes ground potential. At this time, a voltage signal Vm is supplied to terminal Bst. On the other hand, when transistor M1 is controlled to be on and transistor M2 is controlled to be off, the node to which terminal Sw is connected becomes a voltage signal VHV. Therefore, a signal with the voltage value of the sum of the voltage value of voltage signal VHV and the voltage value of voltage signal Vm is supplied to terminal Bst. In other words, the gate driver 521 that drives transistor M1 uses capacitor C5 as a floating power supply, and the potential of terminal Sw at the other end of capacitor C5 changes to ground potential or the voltage value of voltage signal VHV in accordance with the operation of transistors M1 and M2. As a result, the gate driver 521 generates a gate signal Hgd where the L level is the voltage value of voltage signal VHV and the H level is the sum of the voltage value of voltage signal VHV and the voltage value of voltage signal Vm, and supplies it to the gate terminal of transistor M1.

[0097] On the other hand, the gate driver 522 that drives transistor M2 generates a gate signal Lgd where the L level is ground potential and the H level is the voltage value of the voltage signal Vm, regardless of the operation of transistors M1 and M2, and supplies it to the gate terminal of transistor M2.

[0098] As described above, the amplifier circuit 550 operates transistors M1 and M2 in response to gate signals Hgd and Lgd, thereby amplifying the modulated signal Ms, which is obtained by modulating the base drive signals dO and aO, based on the voltage signal VHV. The amplifier circuit 550 then outputs the amplified signal as the amplified modulated signal AMs from the connection point where the source terminal of transistor M1 and the drain terminal of transistor M2 are commonly connected.

[0099] The demodulation circuit 560 demodulates the amplified modulation signal AMs by smoothing them and generates a drive signal COM. The demodulation circuit 560 then outputs the generated drive signal COM from the drive circuit 50.

[0100] The demodulation circuit 560 includes a coil L1 and a capacitor C1. One end of coil L1 is electrically connected to the source terminal of transistor M1 and the drain terminal of transistor M2. As a result, the amplified modulation signal AMs is input to one end of coil L1. The other end of coil L1 is connected to the output terminal Out of the drive circuit 50. The other end of coil L1 is also connected to one end of capacitor C1. The other end of capacitor C1 is supplied with ground potential. In other words, coil L1 and capacitor C1 form a low-pass filter. The low-pass filter in the demodulation circuit 560 smooths the amplified modulation signal AMs, generating the drive signal COM.

[0101] The feedback circuit 570 includes resistors R3 and R4. One end of resistor R3 is connected to terminal Out, where the drive signal COM is output, and the other end of resistor R3 is connected to terminal Vfb and one end of resistor R4. A voltage signal VHV is supplied to the other end of resistor R4. As a result, the drive signal COM, which has passed through the feedback circuit 570 from terminal Out, is fed back to terminal Vfb in a pulled-up state.

[0102] The feedback circuit 572 includes capacitors C2, C3, and C4, and resistors R5 and R6. One end of capacitor C2 is connected to the Out terminal, where the drive signal COM is output, and the other end of capacitor C2 is connected to one end of resistor R5 and one end of resistor R6. Ground potential is supplied to the other end of resistor R5. As a result, capacitor C2 and resistor R5 function as a high-pass filter.

[0103] Furthermore, the other end of resistor R6 is connected to one end of capacitor C4 and one end of capacitor C3. Ground potential is supplied to the other end of capacitor C3. As a result, resistor R6 and capacitor C3 function as a low-pass filter.

[0104] As described above, the feedback circuit 572 is configured with a high-pass filter and a low-pass filter. As a result, the feedback circuit 572 functions as a band-pass filter that allows a predetermined frequency range of the drive signal COM to pass through. The other end of capacitor C4 included in the feedback circuit 572 is connected to terminal Ifb of the integrated circuit 500. As a result, the signal that is fed back to terminal Ifb is the drive signal COM that has passed through the feedback circuit 572, which functions as a band-pass filter that allows predetermined frequency components to pass through, with the DC component of the high-frequency components removed.

[0105] Incidentally, the drive signal COM output from terminal Out is a signal demodulated by the demodulation circuit 560 smoothing the amplified modulated signal AMs based on the base drive signal dO. The drive signal COM output by the demodulation circuit 560 is then integrated and attenuated via the feedback circuit 570 and terminal Vfb before being fed back to the adder 512. As a result, the drive circuit 50 self-oscillates at a frequency determined by the feedback delay and the feedback transfer function. However, the delay is large if only the feedback path via terminal Vfb is used, and therefore, it may not be possible to raise the self-oscillation frequency high enough to ensure sufficient accuracy of the drive signal COM using only the feedback via terminal Vfb.

[0106] In this embodiment, the drive circuit 50 has a separate path for feeding back the high-frequency component of the drive signal COM via the feedback circuit 572 and terminal Ifb, in addition to the path via terminal Vfb. As a result, in the drive circuit 50 of this embodiment, the delay when considering the entire circuit constituting the drive circuit 50 is reduced, and the frequency of the voltage signal As can be increased to a level that sufficiently ensures the accuracy of the drive signal COM, compared to the case where there is no path via terminal Ifb.

[0107] As described above, the drive circuit 50 of this embodiment includes a modulation circuit 510 that outputs a modulated signal Ms obtained by modulating the base drive signals dO and aO, which are the basis of the drive signal COM, and an amplification circuit 550 that has a pair of transistors including transistors M1 and M2 and outputs an amplified modulated signal AMs obtained by amplified the modulated signal Ms by driving the pair of transistors, and an amplified modulated signal It includes a demodulation circuit 560 that demodulates the AMs and outputs them as a drive signal COM.

[0108] Here, as the oscillation frequency of the self-oscillation of the drive circuit 50 increases, and the drive frequency of transistors M1 and M2 increases, the switching loss generated in transistors M1 and M2 increases, and the amount of heat generated by transistors M1 and M2 increases. When the amount of heat generated by transistors M1 and M2 increases, the operational stability of the drive circuit 50, including transistors M1 and M2, decreases, and as a result, the waveform accuracy of the drive signal COM output by the drive circuit 50 decreases. In particular, as in the liquid dispensing device 1 of this embodiment, when the drive circuit 50 supplies a high-frequency drive signal COM of 100 kHz or higher to a large number of piezoelectric elements 60, such as 3,000 or more piezoelectric elements 60, in response to market demands for increased productivity, the amount of current flowing through transistors M1 and M2 increases, and the drive frequency of transistors M1 and M2 may exceed 10 MHz. As a result, the switching loss of transistors M1 and M2 increases, and as a result, the amount of heat generated by transistors M1 and M2 increases significantly, increasing the risk of a decrease in the operational stability of the drive circuit 50.

[0109] To address this problem, it is possible to reduce the switching loss of transistors M1 and M2 and the amount of heat generated in the drive circuit 50 by lowering the drive frequency of transistors M1 and M2. However, in a configuration in which a piezoelectric element 60 is used as a drive element, as in the liquid ejection device 1 shown in this embodiment, it is necessary to finely control the displacement of the piezoelectric element 60 in period tp from the viewpoint of precisely controlling the amount of ink ejected. Therefore, the voltage value of the drive signal changes significantly in a short time, as shown in Figure 4. As a result, when the frequency of the drive signal COM is a high frequency of 100 kHz or higher, the change in the voltage value of the drive signal COM per 1 μs may exceed 20 V, and the period during which the voltage value of the drive signal is kept constant may be less than 0.3 μs. Therefore, if the drive frequency of transistors M1 and M2 is lowered, it is not possible to secure a sufficient number of samples to maintain the waveform accuracy of the drive signal COM, resulting in a decrease in the waveform accuracy of the output drive signal COM and a decrease in the ink ejection accuracy.

[0110] In other words, from the viewpoint of improving productivity in the liquid dispensing device 1, when the drive circuit 50 supplies a drive signal COM of 100 kHz or higher to a large number of piezoelectric elements 60, specifically 3,000 or more piezoelectric elements 60, it was difficult to reduce the amount of heat generated in the drive circuit 50 while simultaneously reducing the risk of a decrease in the waveform accuracy of the output drive signal COM. To address this problem, in the drive circuit 50 of this embodiment, the transistors M1 and M2 have a distinctive structure, so that even when the drive circuit 50 supplies drive signals COMA, COMB, and COMC of 100 kHz or higher to a large number of piezoelectric elements 60, specifically 3,000 or more piezoelectric elements 60, it is possible to reduce the amount of heat generated in the drive circuit 50 while simultaneously reducing the risk of a decrease in the waveform accuracy of the output drive signal COM.

[0111] An example of the structure of transistors M1 and M2 will be described below. Here, transistors M1 and M2 have similar structures. Therefore, the following explanation will only describe the structure of transistor M1, and the explanation of the structure of transistor M2 will be omitted.

[0112] Figure 10 shows an example of the structure of transistor M1. The structure of transistor M1 will be explained using mutually orthogonal X and Y axes. Furthermore, in the following explanation, the starting point of the X-axis arrow will be referred to as the -X side and the tip as the +X side, and the starting point of the Y-axis arrow will be referred to as the -Y side and the tip as the +Y side.

[0113] As shown in Figure 10, transistor M1 consists of layers 701-703 stacked along the Y axis from the +Y side to the -Y side, a source electrode 721, a gate electrode 722, and a drain electrode. It has pole 723 and, in addition, layer 701 includes an n-type semiconductor layer 715, a p-type well 716, and an n-type well 717, layer 702 includes an n-type column layer 712 and a p-type column layer 713, and layer 703 includes an n-type semiconductor layer 711. Hereinafter, in the following description, the n-type semiconductor layer 711 included in layer 703 and the n-type column layer 712 and p-type column layer 713 included in layer 702 may be collectively referred to as the semiconductor substrate 710.

[0114] The n-type semiconductor layer 711 included in layer 703 is an n-type semiconductor layer located on the -Y side of the semiconductor substrate 710. The n-type column layer 712 included in layer 702 is an n-type semiconductor layer, and the p-type column layer 713 is a p-type semiconductor layer. The n-type column layer 712 is located on the +Y side of layer 704 and has a plurality of trenches 733 formed from the +Y side surface toward the -Y side. The p-type column layer 713 is provided in each of the plurality of trenches 733 of the n-type column layer 712. Specifically, the n-type column layer 712 is an n-type semiconductor layer formed on the +Y side of the n-type semiconductor layer 711 of the semiconductor substrate 710 and has a plurality of trenches 733 aligned along the X axis. The p-type column layer 713 is a p-type semiconductor layer formed by epitaxially growing p-type crystals in the trenches 733. In other words, the n-type column layer 712 and the p-type column layer 713 are located on the +Y side of the n-type semiconductor layer 711 and are adjacent to each other, alternating in the direction along the X-axis. To put it another way, the semiconductor substrate 710 includes a plurality of n-type column layers 712 and a plurality of p-type column layers 713, and the column regions are formed on the semiconductor substrate 710 by the alternating arrangement of the plurality of n-type column layers 712 and a plurality of p-type column layers 713 in the direction along the X-axis.

[0115] The n-type semiconductor layer 715 included in layer 701 is an n-type semiconductor layer located on the +Y side of layer 702. This n-type semiconductor layer 715 is formed on the +Y side of the semiconductor substrate 710 by, for example, epitaxial growth. The p-type well 716 is a diffusion layer formed by doping the n-type semiconductor layer 715 with impurities. Specifically, the p-type well 716 is a p-type diffusion layer formed so as to reach the p-type column layer 713 from the surface layer on the +Y side of the n-type semiconductor layer 715, and the n-type semiconductor layer 715 has multiple p-type wells 716 corresponding to multiple p-type column layers 713, which are spaced apart and aligned along the X-axis.

[0116] The n-type well 717 is an n-type diffusion layer formed on the +Y side surface of the p-type well 716. In this embodiment, each of the multiple p-type wells 716 has two n-type wells 717 formed spaced apart along the X-axis. However, the number of n-type wells 717 formed in each p-type well 716 is not limited to two.

[0117] Here, the impurity concentration of the n-type semiconductor layer 715 is lower than that of the n-type column layer 712, the impurity concentration of the n-type semiconductor layer 711 and the n-type well 717 are higher than that of the n-type column layer 712, and the impurity concentration of the p-type well 716 is set higher than that of the p-type column layer 713.

[0118] The gate electrode 722 is formed to bridge two adjacent p-type wells 716 located along the X-axis, out of a plurality of p-type wells 716 arranged along the X-axis. Specifically, the gate electrode 722 is positioned such that its -X end overlaps with the n-type well 717 of the -X-side p-type well 716, when viewed along the Y-axis, and its +X end overlaps with the n-type well 717 of the +X-side p-type well 716, when viewed along the Y-axis. Furthermore, a gate insulating film 730, which includes a silicon oxide film or a silicon nitride film, is located between the gate electrode 722, the n-type semiconductor layer 715, the p-type wells 716, and the n-type wells 717.

[0119] The source electrode 721 is located on the +Y side of the p-type well 716, and the entire transistor M1 The p-type well 716 is positioned to cover the transistor M1 and is connected to the n-type well 717 provided in the p-type well 716 via a contact (not shown). The drain electrode 723 is located on the -Y side of the semiconductor substrate 710 and on the -Y side of the n-type semiconductor layer 711, positioned to cover the entire transistor M1, and is connected to the n-type semiconductor layer 711 via a contact (not shown).

[0120] As described above, transistor M1 includes a layer 702 which includes an n-type n-type column layer 712 having a trench 733 and a p-type p-type column layer 713 provided in the trench 733; a gate electrode 722 and a source electrode 721 located on the +Y side, which is one side of layer 702 in the direction along the Y axis; a drain electrode 723 located on the -Y side, which is the other side of layer 702 in the direction along the Y axis; a layer 701 which includes an n-type n-type semiconductor layer 715, a p-type p-type well 716 provided in the n-type semiconductor layer 715, and an n-type n-type well 717 provided in the p-type well 716, and at least a portion of it located between layer 702 and the source electrode 721 in the direction along the Y axis; and a layer 703 which includes an n-type n-type semiconductor layer 711, and at least a portion of it located between layer 702 and the drain electrode 723 in the direction along the Y axis.

[0121] In other words, transistor M1 includes a source electrode 721 that functions as a source terminal, a gate electrode 722 that functions as a gate terminal, a drain electrode 723 that functions as a drain terminal, a layer 702 that includes an n-type n-type column layer 712 having a trench 733 and a p-type p-type column layer 713 provided in the trench 733, and a layer 701 that includes an n-type n-type semiconductor layer 715, a p-type p-type well 716 provided in the n-type semiconductor layer 715, and an n-type n-type well 717 provided in the p-type well 716, with layer 702 positioned above the drain electrode 723, layer 701 positioned above layer 702, the source electrode 721 positioned above the p-type well 716, and the gate electrode 722 positioned above the n-type well 717. Furthermore, transistor M1 includes a layer 703 that includes an n-type n-type semiconductor layer 711, and layer 703 is positioned between the drain electrode 723 and layer 702. Here, "configuration B is positioned above configuration A" means that configuration B is located at least on the +Y side of configuration A. In other words, "configuration B is positioned above configuration A" means that configuration B may be positioned adjacent to configuration A along the Y-axis, and there may be a different configuration between configuration A and configuration B along the Y-axis.

[0122] In the transistor M1 configured as described above, when a positive voltage is supplied to the drain electrode 723 such that the potential on the drain side is positive relative to the potential on the source side, a depletion layer spreads along the X-axis in the column region where multiple n-type column layers 712 and multiple p-type column layers 713 are alternately located along the X-axis. At this time, because the distance between the n-type column layer 712 and the p-type column layer 713 is small, if the impurity concentration of the n-type column layer 712 is low enough, the depletion layer spreading along the X-axis in the column region can come into contact with it, causing the column region to become depleted. As a result, the limiting intensity distribution along the Y-axis of the column region becomes uniform, and the dielectric strength of the transistor M1 is improved.

[0123] Furthermore, in the transistor M1 of this embodiment, the voltage withstand capability can be improved if the impurity concentration of the n-type column layer 712 is low enough. Therefore, compared to conventional N-type FETs, the impurity concentration of the n-type column layer 712 can be increased and its thickness reduced. This makes it possible to reduce the on-resistance while maintaining the high voltage withstand capability of the transistor M1.

[0124] Furthermore, a transistor M2 with a similar configuration can also achieve low on-resistance while maintaining high voltage resistance.

[0125] Here, the control unit 10 and the drive circuit 50 included in the control unit 10 are examples of print head drive circuits, and at least one of the base drive signals dO and aO is one of the base drive signals This is an example where one of transistors M1 and M2 is an example of a first transistor, and the other of transistors M1 and M2 is an example of a second transistor. Also, n-type is an example of a first conductivity type, p-type is an example of a second conductivity type, layer 702 is an example of a first layer, layer 701 is an example of a second layer, layer 703 is an example of a third layer, n-type column layer 712 is an example of a first semiconductor region, p-type column layer 713 is an example of a second semiconductor region, n-type semiconductor layer 715 is an example of a third semiconductor region, p-type well 716 is an example of a fourth semiconductor region, n-type well 717 is an example of a fifth semiconductor region, and n-type semiconductor layer 711 is an example of a sixth semiconductor region. In addition, source electrode 721 is an example of a first conductor, gate electrode 722 is an example of a second conductor, and drain electrode 723 is an example of a third conductor.

[0126] 5. Effects In the liquid dispensing device 1 of this embodiment configured as described above, the control unit 10 has a drive circuit 50 which has a modulation circuit 510 that outputs a modulation signal Ms obtained by modulating the base drive signals dO and aO which are the basis of the drive signal COM, an amplification circuit 550 which has a pair of transistors including transistors M1 and M2 and outputs an amplified modulation signal AMs obtained by driving the modulation signal Ms, and a demodulation circuit 560 which demodulates the amplified modulation signal AMs and outputs it as a drive signal COM, and transistor M1 has a source electrode 721 which functions as a source terminal, a gate electrode 722 which functions as a gate terminal, and a drive The transistor M1 includes a drain electrode 723 that functions as an input terminal, an n-type n-type column layer 712 having a trench 733, a layer 702 including a p-type p-type column layer 713 provided in the trench 733, and an n-type n-type semiconductor layer 715, a p-type p-type well 716 provided in the n-type semiconductor layer 715, and an n-type n-type well 717 provided in the p-type well 716. The on-resistance of transistor M1 can be reduced by positioning layer 702 above the drain electrode 723, layer 701 above layer 702, a source electrode 721 above the p-type well 716, and a gate electrode 722 above the n-type well 717.

[0127] As a result, even if the amount of current flowing through the transistor M1 in the amplification circuit 550 increases due to the propagation of the drive signal COM output by the drive circuit 50, the loss in transistor M1 is reduced. Therefore, even when the drive circuit 50 supplies the drive signal COM to a large number of piezoelectric elements 60, the amount of heat generated in transistor M1 can be reduced, and because the loss in transistor M1 is reduced, the loss in transistor M1 is also reduced when the frequency of the drive signal COM output by the drive circuit 50 is high. As a result, in the liquid dispensing device 1 of this embodiment, even when the drive circuit 50 supplies a high-frequency drive signal COM to a large number of piezoelectric elements 60, the amount of heat generated in the drive circuit 50 can be reduced, while the risk of a decrease in the waveform accuracy of the output drive signal COM can be reduced. Therefore, the productivity of the liquid dispensing device 1 can be improved.

[0128] In this configuration, transistor M2 has a similar configuration to transistor M1. When the amount of current flowing through transistor M2 in the amplification circuit 550 increases due to the propagation of the drive signal COM output by the drive circuit 50, the loss in transistor M2 is also reduced. As a result, when the drive circuit 50 supplies the drive signal COM to a large number of piezoelectric elements 60, the amount of heat generated in transistor M2 is reduced, and the loss in transistor M2 is also reduced. Therefore, when the frequency of the drive signal COM output by the drive circuit 50 is high, the loss in transistor M2 is also reduced. Consequently, even when the drive circuit 50 supplies a high-frequency drive signal COM to a large number of piezoelectric elements 60, the amount of heat generated in the drive circuit 50 is further reduced, and the risk of a decrease in the waveform accuracy of the output drive signal COM is further reduced, thereby further improving the productivity of the liquid dispensing device 1.

[0129] Furthermore, in the liquid ejection device 1 of this embodiment, the losses of transistors M1 and M2 in the drive circuit 50 are reduced, which allows for the stable supply of high-frequency drive signals COM to the numerous piezoelectric elements 60 in the print head 20. Therefore, even when the print head 20 includes 3,000 or more piezoelectric elements 60 and the drive circuit 50 supplies drive signals COM to these 3,000 or more piezoelectric elements 60, or when the drive circuit 50 outputs drive signals COM with a frequency of 100 kHz or higher, and the voltage value of the drive signals COM output by the drive circuit 50 includes a period in which it changes by 20V or more per 1 μs, or the voltage value of the drive signals COM includes a period in which it remains constant for less than 0.3 μs, the drive circuit 50 can still stably supply high-frequency drive signals COM of 100 kHz or higher to the 3,000 or more piezoelectric elements 60 in the print head 20. This increases the productivity of the liquid ejection device 1.

[0130] Although embodiments and modified examples have been described above, the present invention is not limited to these embodiments and can be implemented in various forms without departing from its spirit. For example, the above embodiments can be combined as appropriate.

[0131] The present invention includes configurations that are substantially identical to those described in the embodiments (for example, configurations with the same function, method, and result, or configurations with the same purpose and effect). Furthermore, the present invention includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. Furthermore, the present invention includes configurations that produce the same effects or achieve the same purpose as those described in the embodiments. Furthermore, the present invention includes configurations that add known technology to the configurations described in the embodiments.

[0132] The following conclusions can be drawn from the embodiments described above.

[0133] One embodiment of a liquid dispensing device is: A print head that ejects liquid in response to a drive signal, A print head drive circuit that outputs the aforementioned drive signal, Equipped with, The print head drive circuit is A modulation circuit that outputs a modulated signal obtained by modulating the base drive signal which is the basis of the drive signal, An amplification circuit that outputs an amplified modulated signal obtained by amplifying the modulated signal with a first transistor and a second transistor, A demodulation circuit that demodulates the amplified modulated signal and outputs it as the drive signal, It has, The first transistor is, A first conductor that functions as a source electrode, A second conductor that functions as a gate electrode, A third conductor that functions as a drain electrode, A first layer comprising a first semiconductor region of a first conductivity type having a trench, and a second semiconductor region of a second conductivity type provided in the trench, A second layer including a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type provided in the third semiconductor region, and a fifth semiconductor region of the first conductivity type provided in the fourth semiconductor region, Includes, The first layer is positioned above the third conductor. The second layer is positioned above the first layer. The first conductor is positioned above the fourth semiconductor region. The second conductor is positioned above the fifth semiconductor region.

[0134] In this liquid ejection device, the print head drive circuit includes a modulation circuit that outputs a modulated signal obtained by modulating a base drive signal which is the basis of the drive signal; an amplification circuit that has a pair of transistors including a first transistor and a second transistor and outputs an amplified modulated signal obtained by driving the pair of transistors; and a demodulation circuit that demodulates the amplified modulated signal and outputs it as a drive signal. In this case, the first transistor includes a first conductor that functions as a source electrode, a second conductor that functions as a gate electrode, and a third conductor that functions as a drain electrode. The first transistor includes a first semiconductor region of a first conductivity type having a trench, and a second semiconductor region of a second conductivity type provided in the trench; and a second layer including a third semiconductor region of a first conductivity type, a fourth semiconductor region of a second conductivity type provided in the third semiconductor region, and a fifth semiconductor region of a first conductivity type provided in the fourth semiconductor region. The first layer is positioned above the third conductor, the second layer above the first layer, the first conductor above the fourth semiconductor region, and the second conductor above the fifth semiconductor region, thereby reducing the on-resistance of the first transistor. As a result, even when the amount of current generated due to the propagation of the drive signal increases, the loss of the first transistor can be reduced.

[0135] As a result, even when the print head drive circuit supplies drive signals to a large number of drive elements, the amount of heat generated in the first transistor can be reduced, and because the loss in the first transistor is reduced, the loss in the first transistor is also reduced when the frequency of the drive signal output by the print head drive circuit is high. Consequently, in this liquid ejection device, even when the print head drive circuit supplies high-frequency drive signals to a large number of drive elements, the amount of heat generated in the print head drive circuit can be reduced, while the risk of a decrease in the waveform accuracy of the output drive signal can be reduced. Therefore, productivity in the liquid ejection device can be improved.

[0136] In one embodiment of the liquid dispensing device, The impurity concentration in the third semiconductor region is lower than the impurity concentration in the first semiconductor region. The impurity concentration in the fifth semiconductor region is higher than the impurity concentration in the first semiconductor region. The impurity concentration in the fourth semiconductor region may be higher than the impurity concentration in the second semiconductor region.

[0137] In one embodiment of the liquid dispensing device, The first transistor further includes a third layer containing a sixth semiconductor region of the first conductivity type, The third layer is disposed between the third conductor and the first layer. The impurity concentration in the sixth semiconductor region may be higher than the impurity concentration in the first semiconductor region.

[0138] In one embodiment of the liquid dispensing device, The print head includes more than 3,000 piezoelectric elements, More than 3,000 of the piezoelectric elements may be driven by the drive signal.

[0139] This liquid ejection device reduces the amount of heat generated in the print head drive circuit and minimizes the risk of a decrease in the waveform accuracy of the output drive signal, even when supplying high-frequency drive signals to a large number of drive elements. Therefore, even when drive signals are supplied to 3,000 or more piezoelectric elements, stable operation of the liquid ejection device and print head drive circuit can be achieved.

[0140] In one embodiment of the liquid dispensing device, The frequency of the drive signal may be 100 kHz or higher.

[0141] This liquid ejection device reduces the amount of heat generated in the print head drive circuit and minimizes the risk of a decrease in the waveform accuracy of the output drive signal, even when supplying high-frequency drive signals to a large number of drive elements. Therefore, even when the drive signal frequency is 100 kHz or higher, stable operation of the liquid ejection device and print head drive circuit can be achieved.

[0142] In one embodiment of the liquid dispensing device, The aforementioned drive signal may include a period during which the voltage value changes by 20V or more per 1μs.

[0143] This liquid ejection device reduces the amount of heat generated in the print head drive circuit and minimizes the risk of a decrease in the waveform accuracy of the output drive signal, even when supplying high-frequency drive signals to a large number of drive elements. Therefore, even when the drive signal includes periods in which the voltage value changes by 20V or more per 1μs, stable operation of the liquid ejection device and the print head drive circuit can be achieved.

[0144] In one embodiment of the liquid dispensing device, The aforementioned drive signal may include a period of less than 0.3 μs during which the voltage value remains constant.

[0145] This liquid ejection device reduces the amount of heat generated in the print head drive circuit and minimizes the risk of a decrease in the waveform accuracy of the output drive signal, even when supplying high-frequency drive signals to a large number of drive elements. Therefore, even when the drive signal includes a period of less than 0.3 μs during which the voltage value remains constant, stable operation of the liquid ejection device and the print head drive circuit can be achieved.

[0146] One embodiment of a print head drive circuit is: A print head drive circuit that outputs the drive signal to a print head that ejects liquid in response to the drive signal, A modulation circuit that outputs a modulated signal obtained by modulating the base drive signal which is the basis of the drive signal, An amplification circuit that outputs an amplified modulated signal obtained by amplifying the modulated signal with a first transistor and a second transistor, A demodulation circuit that demodulates the amplified modulated signal and outputs it as the drive signal, It has, The first transistor is, A first conductor that functions as a source electrode, A second conductor that functions as a gate electrode, A third conductor that functions as a drain electrode, A first layer comprising a first semiconductor region of a first conductivity type having a trench, and a second semiconductor region of a second conductivity type provided in the trench, A second layer including a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type provided in the third semiconductor region, and a fifth semiconductor region of the first conductivity type provided in the fourth semiconductor region, Includes, The first layer is positioned above the third conductor. The second layer is positioned above the first layer. The first conductor is positioned above the fourth semiconductor region. The second conductor is positioned above the fifth semiconductor region.

[0147] This printhead drive circuit includes a modulation circuit that outputs a modulated signal obtained by modulating the base drive signal which is the basis of the drive signal, and a transistor including a first transistor and a second transistor. In a case where an amplification circuit has a pair of transistors and outputs an amplified modulated signal obtained by driving a modulated signal, and a demodulation circuit demodulates the amplified modulated signal and outputs it as a drive signal, the on-resistance of the first transistor can be reduced by having an amplification circuit that has a pair of transistors and outputs an amplified modulated signal obtained by driving a pair of transistors, and a demodulation circuit that demodulates the amplified modulated signal and outputs it as a drive signal, the first transistor includes a first conductor that functions as a source electrode, a second conductor that functions as a gate electrode, a third conductor that functions as a drain electrode, a first layer including a first semiconductor region of a first conductivity type having a trench, and a second semiconductor region of a second conductivity type provided in the trench, and a second layer including a third semiconductor region of a first conductivity type provided in the third semiconductor region, with the first layer positioned above the third conductor, the second layer positioned above the first layer, the first conductor positioned above the fourth semiconductor region, and the second conductor positioned above the fifth semiconductor region. As a result, the on-resistance of the first transistor can be reduced even when the amount of current generated due to the propagation of the drive signal increases.

[0148] As a result, even when the printhead drive circuit supplies drive signals to a large number of drive elements, the amount of heat generated in the first transistor can be reduced, and because the loss in the first transistor is reduced, the loss in the first transistor is also reduced when the frequency of the drive signal output by the printhead drive circuit is high. Consequently, even when the printhead drive circuit supplies high-frequency drive signals to a large number of drive elements, the amount of heat generated in the printhead drive circuit can be reduced, while the risk of a decrease in the waveform accuracy of the output drive signal can be reduced. Therefore, the productivity of a liquid ejection device equipped with such a printhead drive circuit can be improved.

[0149] In one embodiment of the print head drive circuit, The impurity concentration in the third semiconductor region is lower than the impurity concentration in the first semiconductor region. The impurity concentration in the fifth semiconductor region is higher than the impurity concentration in the first semiconductor region. The impurity concentration in the fourth semiconductor region may be higher than the impurity concentration in the second semiconductor region.

[0150] In one embodiment of the print head drive circuit, The first transistor further includes a third layer containing a sixth semiconductor region of the first conductivity type, The third layer is disposed between the third conductor and the first layer. The impurity concentration in the sixth semiconductor region may be higher than the impurity concentration in the first semiconductor region.

[0151] In one embodiment of the print head drive circuit, The print head includes more than 3,000 piezoelectric elements, The aforementioned drive signal may be used to drive 3,000 or more of the piezoelectric elements.

[0152] This printhead drive circuit reduces the amount of heat generated in the printhead drive circuit and minimizes the risk of a decrease in the waveform accuracy of the output drive signal, even when supplying high-frequency drive signals to a large number of drive elements. Therefore, even when drive signals are supplied to 3,000 or more piezoelectric elements, stable operation of the liquid ejection device and the printhead drive circuit can be achieved.

[0153] In one embodiment of the print head drive circuit, The frequency of the drive signal may be 100 kHz or higher.

[0154] This printhead drive circuit reduces the amount of heat generated in the printhead drive circuit while supplying high-frequency drive signals to a large number of drive elements. Because the risk of a decrease in the waveform accuracy of the drive signal can be reduced, stable operation of the liquid ejection device and print head drive circuit can be achieved even when the drive signal frequency is 100 kHz or higher.

[0155] In one embodiment of the print head drive circuit, The aforementioned drive signal may include a period during which the voltage value changes by 20V or more per 1μs.

[0156] This printhead drive circuit reduces the amount of heat generated in the printhead drive circuit and minimizes the risk of a decrease in the waveform accuracy of the output drive signal, even when supplying high-frequency drive signals to a large number of drive elements. Therefore, even when the drive signal includes periods in which the voltage value changes by more than 20V per 1μs, stable operation of the liquid ejection device and the printhead drive circuit can be achieved.

[0157] In one embodiment of the print head drive circuit, The aforementioned drive signal may include a period of less than 0.3 μs during which the voltage value remains constant.

[0158] This printhead drive circuit reduces the amount of heat generated in the printhead drive circuit and minimizes the risk of a decrease in the waveform accuracy of the output drive signal, even when supplying high-frequency drive signals to a large number of drive elements. Therefore, even when the drive signal includes a period of less than 0.3 μs during which the voltage value remains constant, stable operation of the liquid ejection device and the printhead drive circuit can be achieved. [Explanation of Symbols]

[0159] 1…Liquid ejection device, 2…Ink container, 10…Control unit, 20…Print head, 21…Carriage, 30…Movement unit, 31…Carriage motor, 32…Endless belt, 40…Conveyor unit, 41…Conveyor motor, 42…Conveyor roller, 50, 50a, 50b, 50c…Drive circuit, 52…Reference voltage output circuit, 60…Piezoelectric element, 100…Control circuit, 210…Selection control circuit, 212…Shift register, 214…Latch circuit, 216…Decoder, 230…Selection circuit, 232a, 232b, 232c…Inverter, 234a, 234b, 234c…Transfer gate, 500…Integrated circuit, 510…Modulation circuit, 512, 513…Adder, 514…Comparator, 515…Inverter, 516…Integrating attenuator, 517…Attenuator, 520 …gate drive circuit, 521, 522…gate driver, 550…amplifier circuit, 560…demodulation circuit, 570, 572…feedback circuit, 600…discharge section, 601…piezoelectric element, 611, 612…electrode, 621…diaphragm, 631…cavity, 632…nozzle plate, 641…reservoir, 651…nozzle, 661…feed port, 701~704…layer, 710…semiconductor substrate, 711… n-type semiconductor layer, 712...n-type column layer, 713...p-type column layer, 715...n-type semiconductor layer, 716...p-type well, 717...n-type well, 721...source electrode, 722...gate electrode, 723...drain electrode, 730...gate insulating film, 733...trench, C1~C5...capacitors, D1...diode, L1...coil, M1,M2...transistors, P...medium, R1~R6...resistors

Claims

1. A print head that ejects liquid in response to a drive signal, A print head drive circuit that outputs the aforementioned drive signal, Equipped with, The print head drive circuit is A modulation circuit that outputs a modulated signal obtained by modulating the base drive signal which is the basis of the drive signal, An amplification circuit that outputs an amplified modulated signal obtained by amplifying the modulated signal with a first transistor and a second transistor, A demodulation circuit that demodulates the amplified modulated signal and outputs it as the drive signal, It has, The aforementioned first transistor is A first conductor that functions as a source electrode, A second conductor that functions as a gate electrode, A third conductor that functions as a drain electrode, A first layer comprising a first semiconductor region of a first conductivity type having a trench, and a second semiconductor region of a second conductivity type provided in the trench, A second layer comprising a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type provided in the third semiconductor region, and a fifth semiconductor region of the first conductivity type provided in the fourth semiconductor region, Includes, The first layer is positioned above the third conductor. The second layer is positioned above the first layer. The first conductor is positioned above the fourth semiconductor region. The second conductor is positioned above the fifth semiconductor region. A liquid dispensing device characterized by the following features.

2. The impurity concentration in the third semiconductor region is lower than the impurity concentration in the first semiconductor region. The impurity concentration in the fifth semiconductor region is higher than that in the first semiconductor region. The impurity concentration in the aforementioned fourth semiconductor region is higher than the impurity concentration in the aforementioned second semiconductor region. The liquid dispensing device according to feature 1.

3. The first transistor further includes a third layer containing a sixth semiconductor region of the first conductivity type, The third layer is disposed between the third conductor and the first layer. The impurity concentration in the sixth semiconductor region is higher than the impurity concentration in the first semiconductor region. The liquid dispensing device according to feature 1.

4. The print head includes more than 3,000 piezoelectric elements, The more than 3,000 piezoelectric elements are driven by the drive signal. The liquid dispensing device according to feature 1.

5. The frequency of the aforementioned drive signal is 100 kHz or higher. The liquid dispensing device according to feature 1.

6. The aforementioned drive signal includes a period during which the voltage value changes by 20V or more per 1μs. The liquid dispensing device according to feature 1.

7. The aforementioned drive signal includes a period of less than 0.3 μs during which the voltage value remains constant. The liquid dispensing device according to feature 1.

8. A print head drive circuit that outputs the drive signal to a print head that ejects liquid in response to the drive signal, A modulation circuit that outputs a modulated signal obtained by modulating the base drive signal which is the basis of the drive signal, An amplification circuit that outputs an amplified modulated signal obtained by amplifying the modulated signal with a first transistor and a second transistor, A demodulation circuit that demodulates the amplified modulated signal and outputs it as the drive signal, It has, The aforementioned first transistor is A first conductor that functions as a source electrode, A second conductor that functions as a gate electrode, A third conductor that functions as a drain electrode, A first layer comprising a first semiconductor region of a first conductivity type having a trench, and a second semiconductor region of a second conductivity type provided in the trench, A second layer comprising a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type provided in the third semiconductor region, and a fifth semiconductor region of the first conductivity type provided in the fourth semiconductor region, Includes, The first layer is positioned above the third conductor. The second layer is positioned above the first layer. The first conductor is positioned above the fourth semiconductor region. The second conductor is positioned above the fifth semiconductor region. A print head drive circuit characterized by the following features.

9. The impurity concentration in the third semiconductor region is lower than the impurity concentration in the first semiconductor region. The impurity concentration in the fifth semiconductor region is higher than that in the first semiconductor region. The impurity concentration in the aforementioned fourth semiconductor region is higher than the impurity concentration in the aforementioned second semiconductor region. The print head drive circuit according to feature 8.

10. The first transistor further includes a third layer containing a sixth semiconductor region of the first conductivity type, The third layer is disposed between the third conductor and the first layer. The impurity concentration in the sixth semiconductor region is higher than the impurity concentration in the first semiconductor region. The print head drive circuit according to feature 8.

11. The print head includes more than 3,000 piezoelectric elements, The aforementioned drive signal drives 3,000 or more of the piezoelectric elements. The print head drive circuit according to feature 8.

12. The frequency of the aforementioned drive signal is 100 kHz or higher. The print head drive circuit according to feature 8.

13. The aforementioned drive signal includes a period during which the voltage value changes by 20V or more per 1μs. The print head drive circuit according to feature 8.

14. The aforementioned drive signal includes a period of less than 0.3 μs during which the voltage value remains constant. The print head drive circuit according to feature 8.

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