Gate drive circuit

Abstract

This invention provides a gate drive circuit that avoids malfunctions of the overcurrent protection unit that occur under specific conditions, and is always capable of normal operation. [Solution] The gate drive circuit comprises a drive signal generation unit, an overcurrent protection unit, and a control unit. The drive signal generation unit generates a drive signal for driving the switching element based on a control signal for turning the switching element on / off. The overcurrent protection unit controls the drive signal generation unit so that the switching element is turned off when the current flowing between the emitter and collector of the switching element exceeds a predetermined first threshold when the switching element is in the ON state. When a control signal for turning the switching element is input to the drive signal generation unit, the control unit compares the voltage at the gate terminal of the switching element to which the drive signal is input with a predetermined second threshold, and operates the overcurrent protection unit based on the result of the comparison.

Description

[Technical Field]

[0001] This invention relates to a gate drive circuit. [Background technology]

[0002] Switching elements such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal-Oxide Semiconductor Field-Effect Transistors), which switch high voltages and large currents, can cause significant damage to surrounding equipment if they are destroyed by overcurrent due to short circuits in the connected load, etc. Therefore, it is necessary to avoid destruction as much as possible. For this reason, the drive circuit that drives the switching elements has an important function to protect the switching elements in preparation for such situations. One method for detecting abnormalities such as overcurrent due to short circuits in the load is to check the voltage when the switching element is ON. CE There is a method for detecting the rise in the collector-emitter voltage (for example, Patent Document 1).

[0003] The protection circuit disclosed in Patent Document 1 is a V of the switching element in the operating state. CE The system monitors the voltage, and if it exceeds a certain level, it determines that an overcurrent has occurred and switches the switching element to the off state, thereby protecting the switching element from damage. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-138984 [Overview of the project] [Problems that the invention aims to solve]

[0005] Incidentally, under certain conditions, the protection circuit may malfunction and turn off the switching element even though no overcurrent is flowing through it.

[0006] This invention addresses a previously unresolved problem and aims to provide a gate drive circuit that can always operate normally while avoiding malfunctions of the overcurrent protection unit that occur under specific conditions. [Means for solving the problem]

[0007] To achieve the above objective, according to one aspect of the present invention, a gate drive circuit is provided comprising: a drive signal generation unit that generates a drive signal for driving a switching element based on a control signal for turning the switching element on / off; an overcurrent protection unit that controls the drive signal generation unit so that the switching element is turned off when the current flowing between the emitter and collector of the switching element exceeds a predetermined first threshold when the switching element is turned on; and a control unit that, when a control signal for turning on the switching element is input to the drive signal generation unit, compares the voltage at the gate terminal of the switching element to which the drive signal is input with a predetermined second threshold, and operates the overcurrent protection unit based on the result of the comparison. [Effects of the Invention]

[0008] According to one aspect of the present invention, it is possible to obtain a gate drive circuit that can always operate normally by avoiding malfunctions of the overcurrent protection unit that occur under specific conditions. [Brief explanation of the drawing]

[0009] [Figure 1] This is a block diagram showing the configuration of an Intelligent Power Module (IPM) to which the gate drive circuit according to the first embodiment is applied. [Figure 2] This block diagram shows the main configuration of a gate drive circuit according to the first embodiment. [Figure 3] This is a circuit diagram showing the configuration of a gate drive circuit used as a comparative example. [Figure 4] This is a signal timing diagram showing the operation of a gate drive circuit used as a comparative example. [Figure 5]This is a signal timing diagram showing the malfunction that occurs in the overcurrent protection section during the operation of a gate drive circuit used as a comparative example. [Figure 6] This diagram shows the flow of current supplied to the motor when the motor is in operation. [Figure 7] This is a characteristic diagram of the current supplied to the motor. [Figure 8] This diagram shows the current flow supplied to the motor during power operation when three series circuits of IPMs are connected in parallel. [Figure 9] This diagram shows the current flow from the motor during recirculation operation when the three-phase series circuits of IPMs are connected in parallel. [Figure 10] This diagram shows the current flow in a gate drive circuit used as a comparative example, when it causes a malfunction of the overcurrent protection unit. [Figure 11] This is a circuit diagram showing the configuration of the gate drive circuit according to the first embodiment of this invention. [Figure 12] This is a signal timing diagram showing the operation of the gate drive circuit according to the first embodiment. [Figure 13] This is a block diagram showing the configuration of an Intelligent Power Module (IPM) to which a gate drive circuit according to a modified example of the first embodiment is applied. [Modes for carrying out the invention]

[0010] Next, embodiments of the present invention will be described with reference to the drawings. In the following drawings, identical or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic. Furthermore, the embodiments described below illustrate devices and methods for realizing the technical concept of the present invention, and the technical concept of the present invention does not limit the structure, arrangement, etc. of the components to those described below. The technical concept of the present invention can be modified in various ways within the technical scope defined by the claims described in the patent claims.

[0011] <First Embodiment> Figure 1 is a block diagram showing the configuration of an Intelligent Power Module (IPM) to which the gate drive circuit according to the first embodiment is applied. The IPM100 is an intelligent power module commonly used in inverters, and here it is configured as a full bridge with six built-in switching elements. The IPM100 is supplied with a DC voltage from a DC power supply Vdc. The IPM100 converts the DC voltage to an AC voltage based on an input pulse, such as a PWM (pulse width modulation) pulse, and supplies the AC voltage to the motor M. In this first embodiment, an example using IGBTs as switching elements is described, but they are not limited to IGBTs; MOSFETs may also be used.

[0012] The IPM100 has a U-phase series circuit 101 in which a first switching element Tr11, which constitutes the lower arm, and a second switching element Tr21, which constitutes the upper arm, are connected in series. The IPM100 also has a V-phase series circuit 102 in which a first switching element Tr12, which constitutes the lower arm, and a second switching element Tr22, which constitutes the upper arm, are connected in series. Furthermore, the IPM100 has a W-phase series circuit 103 in which a first switching element Tr13, which constitutes the lower arm, and a second switching element Tr23, which constitutes the upper arm, are connected in series. These U-phase series circuit 101, V-phase series circuit 102, and W-phase series circuit 103 are connected in parallel.

[0013] A first freewheeling diode D11 is connected in parallel to the first switching element Tr11, and a second freewheeling diode D21 is connected in parallel to the second switching element Tr21. Furthermore, a first freewheeling diode D12 is connected in parallel to the first switching element Tr12, and a second freewheeling diode D22 is connected in parallel to the second switching element Tr22. In addition, a first freewheeling diode D13 is connected in parallel to the first switching element Tr13, and a second freewheeling diode D23 is connected in parallel to the second switching element Tr23.

[0014] The connection point between the first switching element Tr11 and the second switching element Tr21 of the U-phase series circuit 101 is connected to the U-phase terminal 104 of the motor M via signal line SL1. The connection point between the first switching element Tr12 and the second switching element Tr22 of the V-phase series circuit 102 is connected to the V-phase terminal 105 of the motor M via signal line SL2. The connection point between the first switching element Tr13 and the second switching element Tr23 of the W-phase series circuit 103 is connected to the W-phase terminal 106 of the motor M via signal line SL3.

[0015] Incidentally, the gate drive circuit 1 according to the first embodiment of this disclosure is connected to the gate terminals of the first switching element Tr11 and the second switching element Tr21 of the U-phase series circuit 101. Based on the input pulse signal (an example of a control signal), the gate drive circuit 1 turns on either the first switching element Tr11 or the second switching element Tr21 and turns off the other.

[0016] Figure 2 is a block diagram showing the main configuration of the gate drive circuit 1 according to the first embodiment. The gate drive circuit 1 comprises a first drive circuit 11 (an example of a first drive signal generation unit), a second drive circuit 12 (an example of a first drive signal generation unit), an overcurrent protection unit 13, and a control unit 14. A control device (not shown) is also connected to the gate drive circuit 1, and based on the pulse signals output from the control device, it alternately switches the on and off states of the first switching element Tr11 and the off and on states of the second switching element Tr21. In other words, when the first switching element Tr11 is on, the second switching element Tr21 is off, and when the first switching element Tr11 is off, the second switching element Tr21 is on. In the example in Figure 2, an example in which the gate drive circuit 1 includes both the first drive circuit 11 and the second drive circuit 12 has been described, but an example in which only the first drive circuit 11 is included in the gate drive circuit 1 is also possible. In this case, the second switching element Tr21 is turned on or off by a microcomputer or an external circuit.

[0017] The first drive circuit 11 is configured to generate a gate drive signal Sg1 based on a pulse signal Sp1 (an example of a control signal) input from the control device. The second drive circuit 12 is configured to generate a gate drive signal Sg2 based on a pulse signal Sp2 (an example of a control signal) input from the control device. When pulse signal Sp1 is off (low level), pulse signal Sp2 is on. Conversely, when pulse signal Sp1 is on (high level), pulse signal Sp2 is off.

[0018] The output terminal of the first drive circuit 11 is electrically connected to the gate terminal G of the first switching element Tr11 via a gate resistor RG. The output terminal of the second drive circuit 12 is electrically connected to the gate terminal G of the second switching element Tr21.

[0019] The collector terminal C of the first switching element Tr11 is connected to the cathode terminal K of the first freewheeling diode D11. The emitter terminal E of the first switching element Tr11 is connected to the anode terminal A of the first freewheeling diode D11. The collector terminal C of the first switching element Tr11 and the cathode terminal K of the first freewheeling diode D11 are connected to the emitter terminal E of the second switching element Tr21 and the anode terminal A of the second freewheeling diode D21. The emitter terminal E of the first switching element Tr11 and the anode terminal A of the first freewheeling diode D11 are connected to the negative terminal (side) of the DC power supply Vdc.

[0020] The collector terminal C of the second switching element Tr21 is connected to the cathode terminal K of the second freewheeling diode D21. The emitter terminal E of the second switching element Tr21 is connected to the anode terminal A of the second freewheeling diode D21. The collector terminal C of the second switching element Tr21 and the cathode terminal K of the second freewheeling diode D21 are connected to the positive terminal (side) of the DC power supply Vdc. The emitter terminal E of the second switching element Tr21 and the anode terminal A of the second freewheeling diode D21 are connected to the collector terminal C of the first switching element Tr11 and the cathode terminal K of the first freewheeling diode D11.

[0021] Furthermore, the collector terminal C of the first switching element Tr12 is connected to the cathode terminal K of the first freewheeling diode D12. The emitter terminal E of the first switching element Tr12 is connected to the anode terminal A of the first freewheeling diode D12. The collector terminal C of the first switching element Tr12 and the cathode terminal K of the first freewheeling diode D12 are connected to the emitter terminal E of the second switching element Tr22 and the anode terminal A of the second freewheeling diode D22. The emitter terminal E of the first switching element Tr12 and the anode terminal A of the first freewheeling diode D12 are connected to the negative terminal (side) of the DC power supply Vdc.

[0022] The collector terminal C of the second switching element Tr22 is connected to the cathode terminal K of the second freewheeling diode D22. The emitter terminal E of the second switching element Tr22 is connected to the anode terminal A of the second freewheeling diode D22. The collector terminal C of the second switching element Tr22 and the cathode terminal K of the second freewheeling diode D22 are connected to the positive terminal (side) of the DC power supply Vdc. The emitter terminal E of the second switching element Tr22 and the anode terminal A of the second freewheeling diode D22 are connected to the collector terminal C of the first switching element Tr12 and the cathode terminal K of the first freewheeling diode D12.

[0023] Furthermore, the collector terminal C of the first switching element Tr13 is connected to the cathode terminal K of the first freewheeling diode D13. The emitter terminal E of the first switching element Tr13 is connected to the anode terminal A of the first freewheeling diode D13. The collector terminal C of the first switching element Tr13 and the cathode terminal K of the first freewheeling diode D13 are connected to the emitter terminal E of the second switching element Tr23 and the anode terminal A of the second freewheeling diode D23. The emitter terminal E of the first switching element Tr13 and the anode terminal A of the first freewheeling diode D13 are connected to the negative terminal (side) of the DC power supply Vdc.

[0024] The collector terminal C of the second switching element Tr23 is connected to the cathode terminal K of the second freewheeling diode D23. The emitter terminal E of the second switching element Tr23 is connected to the anode terminal A of the second freewheeling diode D23. The collector terminal C of the second switching element Tr23 and the cathode terminal K of the second freewheeling diode D23 are connected to the positive terminal (side) of the DC power supply Vdc. The emitter terminal E of the second switching element Tr23 and the anode terminal A of the second freewheeling diode D23 are connected to the collector terminal C of the first switching element Tr13 and the cathode terminal K of the first freewheeling diode D13.

[0025] An overcurrent protection unit 13 is connected to the collector terminal C of the first switching element Tr11 and the cathode terminal K of the first freewheeling diode D11. When the first switching element Tr11 is in the ON state, the overcurrent protection unit 13 prevents the voltage generated by the current flowing between the emitter terminal E and collector terminal C of the first switching element Tr11 (hereinafter referred to as the ON voltage) from exceeding a predetermined threshold voltage V. DESAT_th When the value exceeds (an example of a first threshold), the first drive circuit 11 is controlled so that the first switching element Tr11 turns off.

[0026] A control unit 14 is connected to the gate terminal G of the first switching element Tr11. When a pulse signal Sp1 for turning on the first switching element Tr11 is input to the first drive circuit 11, the control unit 14 controls the voltage V at the gate terminal G of the first switching element Tr11 to which the gate drive signal Sg1 is input. G And a predetermined threshold voltage V G_th The current is compared with (an example of a second threshold), and the overcurrent protection unit 13 is activated based on the result of the comparison.

[0027] Furthermore, a drive circuit having the same function as the first drive circuit 11 is connected to the gate terminal G of the first switching element Tr12 in the V-phase series circuit 102. Note that the drive circuit connected to the gate terminal G of the first switching element Tr12 is not shared with the first drive circuit 11 connected to the gate terminal G of the first switching element Tr11.

[0028] A drive circuit having the same function as the second drive circuit 12 is connected to the gate terminal G of the second switching element Tr22 in the V-phase series circuit 102. Note that the drive circuit connected to the gate terminal G of the second switching element Tr22 is not shared with the second drive circuit 12 connected to the gate terminal G of the second switching element Tr21.

[0029] Furthermore, a drive circuit having the same function as the first drive circuit 11 is connected to the gate terminal G of the first switching element Tr13 of the W-phase series circuit 103. Note that the drive circuit connected to the gate terminal G of the first switching element Tr13 is not shared with the first drive circuit 11 connected to the gate terminal G of the first switching element Tr11.

[0030] A drive circuit having the same function as the second drive circuit 12 is connected to the gate terminal G of the second switching element Tr23 of the W-phase series circuit 103. Note that the drive circuit connected to the gate terminal G of the second switching element Tr23 is not shared with the second drive circuit 12 connected to the gate terminal G of the second switching element Tr21.

[0031] <Comparative Example> The gate drive circuit B1 has an overcurrent protection unit B13 that detects an overcurrent and turns off the first switching element Tr11 when an unintended large current (hereinafter referred to as overcurrent) flows through the first switching element Tr11. The circuit protection by the overcurrent protection unit B13 employs a method called Desat. Desat is a method that measures the voltage generated when current flows through the first switching element Tr11 in the ON state (hereinafter referred to as the ON voltage), and detects from this ON voltage whether or not the first switching element Tr11 is in an overcurrent state.

[0032] Figure 3 is a circuit diagram showing the configuration of gate drive circuit B1 as a comparative example. In Figure 3, the letter "B" is added to the beginning of the reference numerals of the components of gate drive circuit B1 in order to distinguish them from gate drive circuit 1. Hereafter, when it is necessary to distinguish the components of gate drive circuit B1 from gate drive circuit 1, the letter "B" will be added to the beginning of the reference numerals of the components of gate drive circuit B1. However, when it is not necessary to distinguish the components of gate drive circuit B1 from gate drive circuit 1, the letter "B" added to the beginning of the reference numerals of the components of gate drive circuit B1 will be omitted. The first drive circuit B11 has an AND circuit 111, a signal generation unit 112, a NOT circuit 113, a pulse signal input terminal 114, an output + terminal 115, and an output - terminal 116. The overcurrent protection unit B13 includes a constant current source 131, an FET 132, a comparator 133, a DESAT terminal 134, and an error output terminal 135.

[0033] (Configuration of the first drive circuit) In the first drive circuit B11, the output + terminal 115 is electrically connected to the gate terminal G of the first switching element Tr11 via the gate resistor RG. One input terminal of the AND circuit 111 is connected to the pulse signal input terminal 114. The NOT circuit 111a is connected to the other input terminal of the AND circuit 111. The output terminal of the AND circuit 111 is connected to the input terminal of the signal generation unit 112 and the input terminal of the NOT circuit 113. The output terminal of the signal generation unit 112 is connected to the output + terminal 115. The power supply voltage Vcc is supplied to the signal generation unit 112 via the power input terminal B21. Further, the output - terminal 116 and the GND input terminal B22 are connected to the signal generation unit 112.

[0034] The output - terminal 116 is connected to the emitter terminal E of the first switching element Tr11 and the anode terminal A of the free - wheeling diode D11. Here, an initial input signal indicating a low level is input to the NOT circuit 111a. Therefore, when a pulse signal Sp1 for turning on the first switching element Tr11 is input to the pulse signal input terminal 114, the AND circuit 111 outputs a signal with a logical value of "1", that is, a signal indicating a high level. Then, when a signal with a logical value of "1" is input to the signal generation unit 112, the signal generation unit 112 generates a gate drive signal Sg1 and outputs the gate drive signal Sg1 to the gate terminal G of the first switching element Tr11 via the gate resistor RG.

[0035] (Configuration of the over - current protection section) In the over - current protection section B13, the DESAT terminal 134 is electrically connected to the collector terminal C of the first switching element Tr11 and the cathode terminal K of the first free - wheeling diode D11 via the resistor R DESAT and the diode D DESAT . Also, one end of the capacitor C[[ID=1x]] DESAT is connected between the DESAT terminal 134 and the resistor R DESAT . The other end of the capacitor C DESAT is connected to the output - terminal 116, the emitter terminal E of the first switching element Tr11, and the anode terminal A of the first free - wheeling diode D11.

[0036] Note: There seems to be a formatting issue with the original text where "resistor R " and "diode D " etc. are split across lines in an unusual way. I've tried to make the translation flow as best as possible while maintaining the original structure. Also, the "1x" in the translation of ID=14 seems to be a formatting error in the original, and I've left it as it is in the translation for the sake of exact preservation. If this is incorrect, please clarify the original text. The DESAT terminal 134 is connected to the constant current source 131, the drain terminal D of FET 132, and one input terminal (non-inverting input) of the comparator 133. The source terminal S of FET 132 is connected to GND. The gate terminal G of FET 132 is connected to the output terminal of the NOT gate 113 of the first drive circuit B11. When a high-level signal is input from the AND gate 111, the NOT gate 113 of the first drive circuit B11 outputs a voltage of 0V, turning off FET 132. Conversely, when a low-level signal is input from the AND gate 111, the NOT gate 113 of the first drive circuit B11 outputs a voltage of ΔV, turning on FET 132.

[0037] The output terminal of comparator 133 is connected to the error output terminal 135 and the NOT gate 111a of the first drive circuit B11. Comparator 133 is connected to capacitor C DESAT The voltage V applied across both ends DESAT and threshold voltage V DESAT_th Compare this with the voltage V DESAT The threshold voltage V DESAT_th When the current exceeds a certain level, a signal indicating a logical value of "1," i.e., a high level signal, is output to the error output terminal 135 and the NOT circuit 111a of the first drive circuit B11. When the NAND circuit 111 of the first drive circuit B11 receives a signal indicating a logical value of "1" from the comparator 133, it outputs a signal indicating a logical value of "0," i.e., a low level signal. As a result, the first switching element Tr11 turns off and the FET 132 turns on. Then, the overcurrent protection unit B13 receives the current I supplied from the constant current source 131. DESAT This current is passed through FET132 and connected to GND, and capacitor C DESAT It operates to deactivate the overcurrent protection by drawing out the charge stored in it.

[0038] (Operation of gate drive circuit B1) Figure 4 is a signal timing diagram showing the operation of gate drive circuit B1, which is used as a comparative example. In Figure 4, the vertical axis represents potential and the horizontal axis represents time. Figure 4(1) shows the waveform of the pulse signal Sp1 input to the pulse signal input terminal 114. Figure 4(2) shows the on / off operation of FET 132. Figure 4(3) shows the waveform of the gate drive signal Sg1. Figure 4(4) shows the capacitor C DESAT The voltage V applied across both ends DESAT The waveform is shown. Figure 4(5) shows the gate voltage V applied to the gate terminal G of the first switching element Tr11. G The waveform is shown.

[0039] (When an ON signal is input) As shown in Figure 4(1), when a pulse signal Sp1 that turns on the first switching element Tr11 is input to the pulse signal input terminal 114 (time t11), the gate drive circuit B1 outputs a gate drive signal Sg1 to apply a positive voltage (for example, 15V) between the gate emitters of the first switching element Tr11, as shown in Figure 4(2), and also turns off the FET 132 shown in Figure 4(2) (time t12).

[0040] When FET132 is turned off, capacitor C connected to the outside of gate drive circuit B1 DESAT This is the current I supplied from the constant current source 131. DESAT Therefore, it is gradually charged. As a result, the voltage V at the DESAT terminal 134 shown in Figure 4(4) DESAT It gradually increases (from time t12 to time t13).

[0041] Under normal circumstances (i.e., no abnormalities such as overcurrent), the first switching element Tr11 turns on, and the voltage V of the DESAT terminal 134 is turned on. DESAT The threshold voltage V of comparator 133 DESAT_th Without reaching a voltage below that level (=V CE_SAT@通常電流 +VF+R DESAT ×I DESAT ) becomes. Note that in reality, the voltage V DESAT This is the resistor R DESAT The threshold voltage V is set considering the value of the above, etc. DESAT_thIt is adjusted so as not to exceed that limit.

[0042] However, when an overcurrent occurs, the voltage V between the collector and emitter of the first switching element Tr11 increases. CE_SAT The voltage is higher than normal, and the voltage of terminal DESAT 134 is higher. DESAT The threshold voltage V DESAT_th The overcurrent protection unit B13 is activated when the current exceeds a certain value. As a result, the gate drive circuit B1 turns off the first switching element Tr11.

[0043] During period 1, 15V is output from the + terminal 115 of the gate drive circuit B1, but as shown in Figure 4(5), the voltage between the gate and emitter of the first switching element Tr11 is V ge (The gate voltage V is below) G This period (referred to as such) is a CR charge due to the gate resistor RG and the input capacitance component of the first switching element Tr11, and the voltage does not rise all at once.

[0044] Period 2 is the so-called Miller period, during which the first switching element Tr11 starts to turn on, but the gate voltage V shown in Figure 4(5) is affected by the feedback capacitance component of the first switching element Tr11. G This is the period during which the rise is suppressed. During this period 2, the voltage V between the emitter and collector of the first switching element Tr11 CE Since it is high (= incomplete ON state), the voltage V shown in Figure 4(4) DESAT It continues to increase. To explain in detail, the voltage V CE When the value becomes low, that is, when the first switching element Tr11 is sufficiently turned on, the I supplied from the constant current source 131 DESAT is a capacitor C DESAT Without charging the resistor R DESAT and diode D DESAT The current flows through the collector-emitter junction of the first switching element Tr11. Therefore, the voltage V DESAT It does not rise. Therefore, the voltage V CE The fact that it is in an incomplete ON state is due to the voltage V DESAT This is one of the conditions under which it will rise.

[0045] During period 3, the Miller period ends, and as shown in Figure 4(5), the first switching element Tr11 begins to transition to a fully ON state (=saturated state). At some point during period 3, V DESAT The current begins to decrease, but the timing of this decrease varies depending on the circumstances. These circumstances include, for example, the load current (collector-emitter current of the first switching element Tr11) and the gate resistance R G These include the resistance value and the switching characteristics of the first switching element Tr11 (gate capacitance or feedback capacitance).

[0046] During period 4, as shown in Figure 4(5), the first switching element Tr11 is fully ON, and the voltage V CE is in a saturation state (=voltage V CE_SAT )

[0047] (When an off signal is input) As shown in Figure 4(1), when a pulse signal Sp1 that turns the first switching element Tr11 from on to off is input to the pulse signal input terminal 114 of the gate drive circuit B1 (time t14), the voltage between the gate and emitter of the first switching element Tr11 is reduced to zero volts (0V), turning off the first switching element Tr11 and turning on the FET 132 (time t15). Here, since the FET 132 is turned on, when the pulse signal Sp1 that turns on the first switching element Tr11 is input, capacitor C DESAT The charge stored in the capacitor is instantly withdrawn, and for this reason, the capacitor C DESAT The voltage V applied across both ends DESAT It drops instantly (time t16).

[0048] And FET132 remains turned on afterwards. Therefore, the current supplied from constant current source 131 DESAT The current always flows through FET132 to GND. Therefore, capacitor C DESAT Since it is not charged, the voltage V DESAT It is kept at zero volts (0V).

[0049] The FET132 remains ON until a pulse signal Sp1 that turns on the first switching element Tr11 is input to the pulse signal input terminal 114.

[0050] (Issues arising in comparative examples) Incidentally, during the operation of the gate drive circuit B1, when the first switching element Tr11 is changed from off to on, a malfunction may occur in the overcurrent protection unit B13. Figure 5 is a signal timing diagram showing the malfunction that occurs in the overcurrent protection unit B13 during the operation of the gate drive circuit B1, which is used as a comparative example. In Figure 5, the vertical axis represents potential and the horizontal axis represents time. Figures 5(1) to (5) are the same as Figures 4(1) to (5) above, so a detailed explanation is omitted.

[0051] When the pulse signal Sp1 that turns on the first switching element Tr11 shown in Figure 5(1) is input to the pulse signal input terminal 114 (time t11), the gate drive circuit B1 outputs a gate drive signal Sg1 to apply a positive voltage (e.g., 15V) across the gate emitter of the first switching element Tr11, and also turns off the FET 132 shown in Figure 5(2) (time t12). Then, the current I supplied from the constant current source 131 is... DESAT Therefore, V shown in Figure 5(4) DESAT It will begin to rise.

[0052] Then, when the first switching element Tr11 is turned on, the voltage V shown in Figure 5(4) is generated. DESAT In period 4, V CE_SAT +VF+R DESAT ×I DESAT This is the case (the period shown by the dashed line in Figure 5(4)). Here, if no overcurrent occurs, (V CE_SAT If the voltage is normal, the overcurrent protection unit B13 will not activate.

[0053] Here, after the pulse signal Sp1 that turns on the first switching element Tr11 shown in Figure 5(1) is input to the pulse signal input terminal 114, the first switching element Tr11 is actually turned on and V DESATThere is a delay period (from time t11 to time t13) shown in Figure 5(4) before the voltage begins to decrease, that is, before the first switching element Tr11 is fully turned on.

[0054] However, during the aforementioned delay period, capacitor C DESAT Current I DESAT V shown in Figure 5(4) is due to charging currents other than the current. DESAT This increases the capacitance (shown as a solid line in Figure 5(4)). In other words, capacitor C DESAT As will be explained in more detail later, current I DESAT In addition, the voltage V between the collector and emitter of the first switching element Tr11 due to voltage resonance CE Due to the sharp increase, the first freewheeling diode D11 is discharged from capacitor C DESAT A current flows through it, and this current and current I DESAT Therefore, voltage V DESAT The voltage rises. As a result, even though no overcurrent flows between the collector and emitter of the first switching element Tr11, the overcurrent protection unit B13 malfunctions and forcibly turns off the first switching element Tr11.

[0055] (Mechanism by which the overcurrent protection unit B13 malfunctions) The mechanism of the malfunction that actually occurred is as follows: Figure 6 shows the flow of current supplied to the motor during motor operation. Figure 7 is a characteristic diagram of the current supplied to the motor. In Figure 7, the vertical axis represents the magnitude of the supplied current, and the horizontal axis represents time.

[0056] In Figure 6, when motor M is driven, the current supplied to motor M flows in both the positive direction (sweeping direction when viewed from the U-phase series circuit B101) and the negative direction (drawing direction when viewed from the U-phase series circuit B101). The malfunction occurs at the timing when transitioning from the "current sweeping state" to the "current drawing state," as shown in Figure 7.

[0057] Figure 8 shows the flow of current supplied to the motor during powering operation when the three-phase series circuits of the IPM are connected in parallel. Here, we will explain a part of the operation of the three phases. In the IPMB100 in Figure 8, the U-phase series circuit B101 is the phase of interest, and the V-phase series circuit B102 is the opposing phase. Here, if the first switching element Tr11 of the lower arm of the U-phase is in the off state and the second switching element Tr21 of the upper arm of the U-phase is in the on state, then the first switching element Tr12 of the lower arm of the opposing V-phase is in the on state, and the second switching element Tr22 of the upper arm of the V-phase is in the off state.

[0058] When the motor is being pushed out and the second switching element Tr21 of the upper arm is ON, current is supplied to the motor M via the DC power supply Vdc → second switching element Tr21 → signal line SL1. Also, during powering operation, the current flowing out of the motor M flows via the signal line SL2 → first switching element Tr12 of the V phase → DC power supply Vdc.

[0059] Figure 9 shows the current flow from the motor during freewheeling operation when the three-phase series circuits of the IPM are connected in parallel. When the second switching element Tr21 of the upper arm is off from the time of sweeping, the energy stored in the motor M flows through the signal line SL2 → the first switching element Tr12 of the V phase → the first freewheeling diode D11 of the U phase. This is called freewheeling operation. During freewheeling operation, the collector-emitter voltage of the first switching element Tr11 of the lower arm of the U phase becomes "-VF" due to the forward voltage of the freewheeling diode D11 connected in parallel.

[0060] Here, as shown in Figure 7 above, there is a moment when the motor current becomes almost zero during the transition from the "current sweep state" to the "current draw state". When the motor current becomes zero, the freewheeling current flowing through the freewheeling diode D11 of the lower arm of the U phase becomes zero, and the factor that was causing the collector-emitter voltage of the first switching element Tr11 of the lower arm to be -VF disappears. In other words, when the current becomes zero, it can be said that the collector-emitter voltage of the first switching element Tr11 of the lower arm becomes unstable (similar to an undefined state like the voltage value of a high impedance line). Furthermore, the freewheeling current flowing through the freewheeling diode D12 of the lower arm of the V phase also becomes zero, and the freewheeling current flowing through the freewheeling diode D13 of the lower arm of the W phase also becomes zero.

[0061] When instability occurs, the charge accumulated in the stray capacitance C11 of the motor current supply line (cable, etc.) resonates with the parasitic inductance L11 component of the same motor current supply line. Because this voltage resonance is a phenomenon with small energy compared to the motor current, it does not appear unless the motor current is zero.

[0062] Returning to Figure 5, the above voltage resonance occurs when the voltage V between the collector and emitter of the first switching element Tr11 of the lower arm occurs during the above delay period. CE It can cause a sharp increase.

[0063] Figure 10 shows the current flow in the gate drive circuit B1, which is used as a comparative example, when the overcurrent protection unit B13 malfunctions. During the delay period shown in Figure 5(4), the first switching element Tr11 and FET132 of the lower arm are in the off state, and therefore the current I supplied from the constant current source 131 is off. DESAT Therefore, capacitor C DESAT The battery is charged. Here, as shown in Figure 10, the voltage V between the collector and emitter of the first switching element Tr11 of the lower arm due to the voltage resonance is CE The sharp rise is due to the parasitic capacitance C21 through capacitor C DESAT This causes the capacitor C to charge.DESAT Voltage V DESAT This causes the voltage to rise, leading to a malfunction of the overcurrent protection unit B13.

[0064] The above malfunction does not always occur, but it is particularly likely to occur under the following conditions, for example, when conditions 1 and 2 occur simultaneously. Condition 1: The motor cable is long. If the motor cable is long, the parasitic capacitance C11 of the current supply line increases, and the voltage resonance increases. Condition 2: Motor M is rotating at a low speed. When motor M rotates at a low speed, the waveform of the current supplied to motor M, as shown in Figure 7, becomes elongated in the time direction. This increases the time during which the supply current is nearly zero, and thus increases the number of times voltage resonance occurs.

[0065] To address the above problem, capacitor C DESAT One possible solution is to increase the capacity of the overcurrent protection unit B13 to prevent malfunction. However, this solution has the following problems. Problem 1: Capacitor C DESAT Increasing the capacitance would, in principle, extend the time it takes to turn off the first switching element Tr11 when an overcurrent actually occurs. As a result, there is a concern that the first switching element Tr11 may be destroyed. Problem 2: Capacitor C that can solve Problem 1 above. DESAT Even if we find the capacitance and prevent the destruction of the first switching element Tr11, due to the influence of various circuit constants such as changes in the parameters of conditions 1 and 2, it is still necessary to find a capacitor C that can reliably turn off the first switching element Tr11 only when an overcurrent that we want to suppress occurs. DESAT The capacity changes. Therefore, it is extremely difficult to derive it uniquely.

[0066] <Implementation means according to the first embodiment> The problem caused by the above comparative example occurs during the delay period from when the pulse signal Sp1 for turning on the first switching element Tr11 is input to the gate drive circuit B1 until the first switching element Tr11 actually turns on and the voltage V DESAT decreases. During this delay period, since the FET132 is off even though the first switching element Tr11 has not yet fully turned on, the above voltage resonance and other unexpected external noises charge the capacitor C DESAT . As a result, the voltage V DESAT increases, which may cause a malfunction of the overcurrent protection unit B13. Note that when the pulse signal Sp1 for turning on the first switching element Tr11 is input to the gate drive circuit B1, the MOSFET132 turns off in a time much shorter than the delay period (see times t11 to t12 in FIG. 4). Also, the turn-on time of the MOSFET132 (time t15 in FIG. 4) is longer than the delay period.

[0067] Conversely, even if a sudden increase in the voltage V CE between the collector and emitter of the first switching element Tr11 due to voltage resonance or unexpected external noise occurs when the FET132 is in the on state or when the first switching element Tr11 is fully on, V DESAT will not increase, and thus no malfunction of the overcurrent protection unit B13 will occur.

[0068] From the above, it can be seen that by making the timing of turning off the FET132 and the timing when the first switching element Tr11 is fully on closer, the occurrence of malfunctions in the overcurrent protection unit B13 can be suppressed. To realize a method of making the timing of turning off the FET132 and the timing when the first switching element Tr11 is fully on closer, the on state of the first switching element Tr11 can be monitored and added to the off condition of the FET132.

[0069] FIG. 11 is a circuit diagram showing the configuration of the gate drive circuit 1 according to the first embodiment. In FIG. 11, the same parts as those in FIG. 3 are denoted by the same reference numerals and detailed descriptions thereof are omitted.

[0070] The control unit 14 comprises a comparator 141, a NAND circuit 142, and an input terminal 143. One input terminal (non-inverting input) of the comparator 141 is connected via the input terminal 143 between the gate terminal G of the first switching element Tr11 and the gate resistor RG. A predetermined threshold voltage V is connected to the other input terminal (inverting input) of the comparator 141. G_th (An example of a second threshold) is input. Comparator 141 receives the gate voltage V applied to the gate terminal G of the first switching element Tr11. G and a predetermined threshold voltage V G_th Compare this with the gate voltage V G The predetermined threshold voltage V G_th If it exceeds a certain value, it outputs the logical value "1".

[0071] One input terminal of the NAND circuit 142 receives a logic value "0" or logic value "1" signal output from the comparator 141. The other input terminal of the NAND circuit 142 receives a logic value "0" or logic value "1" signal output from the AND circuit 111. That is, when the NAND circuit 142 receives a logic value "1" signal output from the comparator 141 and a logic value "1" signal output from the AND circuit 111, it outputs a voltage of 0V and turns off the FET 132 of the overcurrent protection unit 13. On the other hand, when the NAND circuit 142 receives a logic value "0" signal output from the comparator 141 and a logic value "1" signal output from the AND circuit 111, it outputs a voltage of ΔV and turns on the FET 132 of the overcurrent protection unit 13. Furthermore, when the NAND circuit 142 receives a logic value "0" signal output from the comparator 141 and a logic value "0" signal output from the AND circuit 111, it outputs a voltage of ΔV and turns on the FET 132 of the overcurrent protection unit 13.

[0072] (Operation of gate drive circuit 1) FIG. 12 is a signal timing diagram showing the operation of the gate drive circuit 1 according to the first embodiment. In FIG. 12, the vertical axis represents potential and the horizontal axis represents time. Since FIGS. 12(1) to (5) are the same as FIGS. 4(1) to (5) described above, detailed description thereof is omitted.

[0073] When a pulse signal Sp1 for turning on the first switching element Tr11 shown in FIG. 12(1) is input to the pulse signal input terminal 114 (at time t21), the gate drive circuit 1 outputs a gate drive signal Sg1 for applying a positive voltage (for example, 15 V) between the gate and emitter of the first switching element Tr11 (at time t22). At this time, 15 V is output from the output + terminal 115 of the gate drive circuit B1. However, as shown in FIG. 12(5), the gate voltage V between the gate and emitter of the first switching element Tr11 is a CR charge due to the gate resistor RG and the input capacitance component of the first switching element Tr11, and is the period 1 during which it does not rise instantaneously. Therefore, the FET 132 shown in FIG. 12(2) maintains the on state. G When the period 2 (mirror period) ends, as shown in FIG. 12(5), the first switching element Tr11 starts to transition to a complete on state (= saturation state). At this time, the gate voltage V between the gate and emitter of the first switching element Tr11 exceeds the threshold voltage V, and thereby the FET 132 shown in FIG. 12(2) turns off (at time t23). Then, due to the current I supplied from the constant current source 131, V shown in FIG. 12(4) starts to rise.

[0074] When the first switching element Tr11 is turned on, V shown in FIG. 12(4) becomes V + VF + R × I in period 4. Here, if no overcurrent occurs (if V is the normal voltage), the overcurrent protection unit 13 does not operate. G is the threshold voltage V G_th exceeds, whereby the FET 132 shown in FIG. 12(2) turns off (at time t23). Then, due to the current I supplied from the constant current source 131, V shown in FIG. 12(4) starts to rise. DESAT by which V shown in FIG. 12(4) DESAT begins to rise.

[0075] And when the first switching element Tr11 is turned on, V shown in FIG. 12(4) DESAT in period 4 becomes V CE_SAT +VF+R DESAT ×I DESAT . Here, if no overcurrent occurs (if V CE_SAT is the normal voltage), the overcurrent protection unit 13 does not activate.

[0076] <Effects and Effects of the First Embodiment> As described above, according to the first embodiment, when a pulse signal Sp1 for turning on the first switching element Tr11 is input to the first drive circuit 11, the gate voltage V at the gate terminal G of the first switching element Tr11 to which the gate drive signal Sg1 is input G And the threshold voltage V G_th The comparator 141 of the control unit 14 compares these two states to determine whether the first switching element Tr11 is fully turned on or not. Until the first switching element Tr11 is fully turned on, the NAND circuit 142 maintains the ON state of the FET 132, preventing the overcurrent protection unit 13 from operating.

[0077] Therefore, malfunctions of the overcurrent protection unit 13, which are triggered under specific conditions, are avoided, and the gate drive circuit 1 can always be operated normally.

[0078] <Modified form of the first embodiment> Figure 13 is a block diagram showing the configuration of an Intelligent Power Module (IPM) to which a gate drive circuit according to a modified example of the first embodiment is applied. In Figure 13, the same parts as in Figure 1 are denoted by the same reference numerals, and detailed descriptions are omitted.

[0079] In the IPM100A, the gate drive circuit 2 according to the second embodiment of this disclosure is connected to the gate terminals of the first switching element Tr12 and the second switching element Tr22 of the V-phase series circuit 102. In addition, the gate drive circuit 3 according to the second embodiment of this disclosure is connected to the gate terminals of the first switching element Tr12 and the second switching element Tr22 of the W-phase series circuit 103. The gate drive circuits 2 and 3 have the same circuit configuration as the gate drive circuit 1 described above.

[0080] Here, the series circuit 102 of the V phase of the IPM100A is the phase of interest, and the series circuit 103 of the W phase is the opposing phase. If the first switching element Tr12 of the lower arm of the V phase is in the off state and the second switching element Tr22 of the upper arm of the V phase is in the on state, then the first switching element Tr13 of the lower arm of the opposing W phase is in the on state, and the second switching element Tr23 of the upper arm of the W phase is in the off state.

[0081] When the arm is being pushed out and the second switching element Tr22 of the upper arm is ON, current is supplied to the motor M via the DC power supply Vdc → second switching element Tr22 → signal line SL2. Also, during powering operation, the current flowing out of the motor M flows via the signal line SL3 → first switching element Tr13 of the W phase → DC power supply Vdc.

[0082] Conversely, when the second switching element Tr22 of the upper arm is off from the time of sweeping, the energy stored in the motor M flows through the signal line SL3 → the first switching element Tr13 of the W phase → the first freewheeling diode D12 of the V phase.

[0083] Furthermore, the series circuit 103 of the W phase of the IPM100A is designated as the phase of interest, and the series circuit 101 of the U phase is designated as the opposing phase. Here, if the first switching element Tr13 of the lower arm of the W phase is in the off state and the second switching element Tr23 of the upper arm of the W phase is in the on state, then the first switching element Tr11 of the lower arm of the opposing U phase is in the on state, and the second switching element Tr21 of the upper arm of the U phase is in the off state.

[0084] When the arm is being pushed out and the second switching element Tr23 of the upper arm is ON, current is supplied to the motor M via the DC power supply Vdc → second switching element Tr23 → signal line SL3. Also, during powering operation, the current flowing out of the motor M flows through the signal line SL1 → first switching element Tr11 of the U phase → DC power supply Vdc.

[0085] Conversely, when the second switching element Tr23 of the upper arm is off from the time of sweeping, the energy stored in the motor M flows through the signal line SL1 → the first switching element Tr11 of the U phase → the first freewheeling diode D13 of the W phase.

[0086] Therefore, the same problems as in the comparative example of the first embodiment may occur in the V-phase series circuit 102 and the W-phase series circuit 103. In this modified version of the first embodiment, a gate drive circuit 2 with the same circuit configuration as the gate drive circuit 1 provided in the U-phase series circuit 101 is provided in the V-phase series circuit 102, and a gate drive circuit 3 with the same circuit configuration as the gate drive circuit 1 is provided in the W-phase series circuit 103. Accordingly, as in the first embodiment, malfunctions of the overcurrent protection unit 13 that are activated under specific conditions are avoided, and the gate drive circuits 2 and 3 can always be operated normally. In addition, in the gate drive circuit 1, the overcurrent protection unit 13 and the control unit 14 may be provided in correspondence with the second drive circuit 12. Furthermore, in the gate drive circuits 2 and 3, the overcurrent protection unit and the control unit may be provided in correspondence with the second drive circuit.

[0087] <Other Embodiments> As described above, the present invention has been described by the first embodiment and its modifications; however, the descriptions and drawings that constitute part of this disclosure should not be understood as limiting the present invention. Those skilled in the art will understand, upon understanding the spirit of the technical content disclosed by the above embodiments, that various alternative embodiments, examples, and operational techniques may be included in the present invention. Furthermore, the configurations disclosed in the first embodiment can be combined as appropriate, within the bounds of consistency. For example, configurations disclosed by multiple different embodiments may be combined, or configurations disclosed by multiple different modifications of the same embodiment may be combined. [Explanation of symbols]

[0088] 1,2,3,B1 Gate drive circuit 11, B11 First drive circuit 12. Second drive circuit 13,B13 Overcurrent protection section 14 Control Unit 100, 100A, B100 IPM 101, B101 U-phase series circuit 102, B102 V-phase series circuit 103, B103 W-phase series circuit 104 U phase terminal 105 V phase terminal 106 W phase terminal 111 AND circuit 111a NOT circuit 112 Signal Generation Unit 113 NOT circuit 114 Pulse signal input terminal 115 Output + terminal 116 Output Terminals 131 Constant current source 132 FET 133,141 Comparators 134 DESAT terminal 135 Error output terminal 142 NAND circuits 143 Input terminals Anode terminal B21 Power input terminal B22 GND input terminal C Collector terminal C DESAT Capacitor C11 Parasitic capacitance of the current supply line C21 parasitic capacitance D drain terminal D11, D12, D13 First freewheeling diodes D21, D22, D23 Second freewheeling diodes E emitter terminal G gate terminal K Cathode terminal M Motor RG gate resistor S Source terminal SL1, SL2, SL3 signal lines Tr11, Tr12, Tr13 First switching element Tr21, Tr22, Tr23 Second switching element Vdc DC power supply

Claims

1. A drive signal generation unit generates a drive signal for driving a switching element based on a control signal for turning the switching element on / off, When the switching element is in the ON state, an overcurrent protection unit controls the drive signal generation unit so that the switching element is turned OFF if the current flowing between the emitter and collector of the switching element exceeds a predetermined first threshold; When a control signal for turning on the switching element is input to the drive signal generation unit, the control unit compares the voltage at the gate terminal of the switching element to which the drive signal is input with a predetermined second threshold value, and operates the overcurrent protection unit based on the result of the comparison. A gate drive circuit equipped with the following features.

2. The aforementioned drive signal generation unit is provided in two parts. Of the two drive signal generation units, the first drive signal generation unit is connected in series with the first switching element constituting the lower arm and the second switching element constituting the upper arm, and the second drive signal generation unit is connected to the gate terminal of the second switching element. The first drive signal generation unit and the second drive signal generation unit receive a control signal that turns on either the first switching element or the second switching element, and turns off either the other. The gate drive circuit according to claim 1, wherein the overcurrent protection unit and the control unit are provided in correspondence with the first drive signal generation unit.

3. The gate drive circuit according to claim 2, wherein the first drive signal generation unit, the second drive signal generation unit, the overcurrent protection unit, and the control unit are provided in correspondence with at least two series circuits connected in parallel to each other when the series circuit of the first switching element and the second switching element is considered as one phase.

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