Semiconductor circuits and power supply circuits

Abstract

To provide a semiconductor circuit capable of improving the accuracy of current sensing circuits. [Solution] The semiconductor circuit of the embodiment includes first to fifth transistors and an operational amplifier section. One end of the first transistor is connected to the first node. One end of the second transistor is connected to the second node, and its gate is connected to the gate and other end of the first transistor. One end of the third transistor is connected to the other end of the first transistor, and a reference voltage is input to its gate. One end of the fourth transistor is connected to the other end of the second transistor, and its other end is connected to the other end of the third transistor. One end of the fifth transistor is connected to the first node, and its gate is connected to the other end of the second transistor. The operational amplifier section has its first input terminal connected to the first node, and its second input terminal connected to the second node, and inputs a voltage corresponding to the voltage difference between the voltage at the first input terminal and the voltage at the second input terminal to the gate of the fourth transistor.

Description

Technical Field

[0006] , , ,

[0001] Embodiments relate to a semiconductor circuit and a power supply circuit.

Background Art

[0002] A power supply circuit having a current protection circuit is known. The current protection circuit has, for example, a current sense circuit that detects a current flowing between an input terminal and an output terminal of the power supply circuit using an operational amplifier. And the current protection circuit is configured to limit the output current of the power supply circuit so as not to exceed a predetermined value based on the current detection result by the current sense circuit.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, the accuracy of the power sense circuit may decrease due to variations in the characteristics of the operational amplifier. As a method for improving the accuracy of the current sense circuit, it is conceivable to calibrate the chip and write parameters in the test process. On the other hand, the addition of such a calibration process can be a factor in increasing the cost of the power supply circuit. Therefore, it is preferable that the current sense circuit used in the power protection circuit can be automatically calibrated on-chip.

[0005] The present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor circuit and a power supply circuit capable of automatically calibrating a current sense circuit on-chip and improving the accuracy of the current sense circuit.

Means for Solving the Problems

[0006] The semiconductor circuit of the embodiment includes first to fifth transistors and an operational amplifier section. One end of the first transistor is connected to a first node. One end of the second transistor is connected to a second node different from the first node, and its gate is connected to the gate and other end of the first transistor. One end of the third transistor is connected to the other end of the first transistor, and a first reference voltage is input to its gate. One end of the fourth transistor is connected to the other end of the second transistor, and its other end is connected to the other end of the third transistor. One end of the fifth transistor is connected to the first node, and its gate is connected to the other end of the second transistor. The operational amplifier section has a first input terminal connected to the first node and a second input terminal connected to the second node, and inputs a voltage corresponding to the voltage difference between the voltage at the first input terminal and the voltage at the second input terminal to the gate of the fourth transistor. [Brief explanation of the drawing]

[0007] [Figure 1] A circuit diagram showing an example of the circuit configuration of a power supply circuit equipped with a power supply protection circuit according to the first embodiment. [Figure 2] A circuit diagram showing a more detailed example of the circuit configuration of a power supply circuit equipped with a power supply protection circuit according to the first embodiment. [Figure 3] A schematic diagram showing a first example of the operation of the power protection circuit according to the first embodiment. [Figure 4] A schematic diagram showing a second example of the operation of the power protection circuit according to the first embodiment. [Figure 5] A circuit diagram showing an example of the circuit configuration of a power supply circuit equipped with a power supply protection circuit according to the second embodiment. [Figure 6] A circuit diagram showing a more detailed example of the circuit configuration of a power supply circuit equipped with a power supply protection circuit according to the second embodiment. [Figure 7] A timing chart showing an example of the operation of the power protection circuit according to the second embodiment. [Figure 8] A schematic diagram showing a first example of the operation of the power protection circuit according to the second embodiment. [Figure 9] A schematic diagram showing a second example of the operation of the power protection circuit according to the second embodiment. [Figure 10]A circuit diagram showing an example of the circuit configuration of a power supply circuit equipped with a power supply protection circuit according to the third embodiment. [Figure 11] A schematic diagram showing a first example of the operation of the power protection circuit according to the third embodiment. [Figure 12] A schematic diagram showing a second example of the operation of the power protection circuit according to the third embodiment. [Figure 13] A circuit diagram showing an example of the circuit configuration of a power supply circuit equipped with a power supply protection circuit according to the fourth embodiment. [Figure 14] A schematic diagram showing a first example of the operation of the power protection circuit according to the fourth embodiment. [Figure 15] A schematic diagram showing a second example of the operation of the power protection circuit according to the fourth embodiment. [Figure 16] A circuit diagram showing an example of the circuit configuration of a power supply circuit equipped with a power supply protection circuit according to the fifth embodiment. [Modes for carrying out the invention]

[0008] Each embodiment will be described below with reference to the drawings. Each embodiment illustrates an apparatus or method for realizing the technical idea of ​​the invention. The drawings are schematic or conceptual. Components having substantially the same function and configuration are denoted by the same reference numerals.

[0009] <1> First Embodiment The power protection circuit according to the first embodiment is calibrated to enable automatic on-chip calibration of the current sense circuit. Details of the power protection circuit according to the first embodiment are described below.

[0010] <1-1> Composition FIG. 1 is a circuit diagram showing an example of the circuit configuration of a power supply circuit 1 including a power supply protection circuit PC according to the first embodiment. As shown in FIG. 1, the power supply circuit 1 includes, for example, an input terminal 11, an output terminal 12, an operational amplifier section 13, an operational amplifier 14, a charge pump 15, transistors M1 to M5, resistors R1 to R3, nodes N1 to N5, and a ground node GND. Each of the transistors M1, M2, and M5 is an N-type high breakdown voltage MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Each of the transistors M3 and M4 is a P-type high breakdown voltage MOSFET. A ground voltage is applied to the ground node GND.

[0011] The input terminal 11 is connected to an external power supply (not shown). An input voltage VIN is supplied to the input terminal 11 as an external power supply. The input terminal 11 is connected to the node N1. The output terminal 12 can output an output voltage VOUT of the power supply circuit 1. The output terminal 12 is connected to a core circuit (not shown). The core circuit is configured to operate based on the output voltage VOUT supplied from the power supply circuit 1.

[0012] The transistor M1 is connected between the input terminal 11 and the output terminal 12. Specifically, the drain of the transistor M1 is connected to the input terminal 11. The source of the transistor M1 is connected to the output terminal 12. One end of the resistor R1 is connected to the input terminal 11 via the node N1. The other end of the resistor R1 is connected to the drain of the transistor M2 via the node N2. The source of the transistor M2 is connected to the output terminal 12.

[0013] Thus, between the input terminal 11 and the output terminal 12, a transistor M1, and a resistor R1 and a transistor M2 connected in series are connected in parallel. The gates of transistors M1 and M2 are each connected to node N4. In this specification, the gate voltages of transistors M1 and M2 are referred to as "VGATE". In the power supply circuit 1, the size ratio of transistors M1 and M2 is 1:N. The gate-source voltage Vgs applied between the source and gate of transistor M1 and the gate-source voltage Vgs applied between the source and gate of transistor M2 are substantially equal. Thus, transistors M1 and M2 constitute a current mirror circuit.

[0014] One end of resistor R2 is connected to the input terminal 11 via node N1. The other end of resistor R2 is connected to the source of transistor M3 via node N3. The drain of transistor M3 is connected to one end of resistor R3 via node N5. The other end of resistor R3 is connected to the ground node GND. In this specification, the current flowing through transistor M3 is referred to as "IMON".

[0015] The operational amplifier section 13 is configured to control the gate voltage of transistor M3 so that the voltage at node N2 and the voltage at node N3 become equal. Specifically, the non-inverting input terminal (first input terminal) of the operational amplifier section 13 is connected to node N2. The inverting input terminal (second input terminal) of the operational amplifier section 13 is connected to node N3. The output terminal of the operational amplifier section 13 is connected to the gate of transistor M3. And the operational amplifier section 13 outputs a signal corresponding to the difference between the voltage at the first input terminal and the voltage at the second input terminal.

[0016] Thus, transistor M3 outputs a signal corresponding to the signal output from the operational amplifier section 13. In the power supply circuit 1, the resistance value of resistor R1 and the resistance value of resistor R2 are designed to be substantially equal. Therefore, the current IMON flowing through transistor M3 is substantially equal to the current flowing through resistor R1. The current IMON also flows through resistor R3. Thus, resistor R3 generates a voltage corresponding to the current flowing through resistor R1.

[0017] The operational amplifier 14 is configured to control the gate voltage VGATE based on the voltage at node N5. Specifically, a predetermined reference voltage VREF is input to the non-inverting input (first input terminal) of the operational amplifier 14. The inverting input (second input terminal) of the operational amplifier 14 is connected to node N5. The output terminal of the operational amplifier 14 is connected to node N4. As a result, the operational amplifier 14 can output a signal corresponding to the voltage difference between the first input terminal and the second input terminal to the gates of transistor M1 and transistor M2.

[0018] The charge pump 15 generates a predetermined voltage based on the input voltage VIN and outputs the generated voltage. The input terminal of the charge pump 15 is connected to input terminal 11. The output terminal of the charge pump 15 is connected to the source of transistor M4. The drain of transistor M4 is connected to the drain of transistor M5 via node N4. The source of transistor M5 is connected to the ground node GND. On / off input signals are input to the gates of transistors M4 and M5, respectively. In Figure 1, the pair of transistors M4 and M5 is shown as an on / off control circuit SW. The on / off control circuit SW has transistors M4 and M5 connected in series.

[0019] The voltage at node N4, which corresponds to the connection node between transistors M4 and M5, changes according to the on / off input signal. Specifically, when the on / off input signal is high level, conduction occurs between node N4 and the ground node GND via transistor M5, and the voltage at node N4 (gate voltage VGATE) becomes low level. As a result, transistors M1 and M2 are turned off, and the power supply circuit 1 does not output output voltage VOUT from output terminal 12. On the other hand, when the on / off input signal is low level, conduction occurs between the charge pump 15 and node N4 via transistor M4, and the voltage at node N4 (gate voltage VGATE) becomes high level. As a result, transistors M1 and M2 are turned on, and the power supply circuit 1 outputs output voltage VOUT from output terminal 12.

[0020] When the power supply circuit 1 is turned on, the current flowing through transistor M2 also flows through resistor R1. The pair of transistors M1 and M2 constitute a current mirror circuit. Therefore, the amount of current IM1 flowing through transistor M1 and the amount of current IM2 flowing through transistor M2 are proportional. Specifically, the amount of current IM2 is 1 / N of the amount of current IM1, according to the size ratio. The operational amplifier section 13 controls transistor M3 so that the voltage at node N2 and the voltage at node N3 are equal. That is, the current flowing through resistor R1 and the current flowing through resistor R2 are controlled to be equal. When the voltage at node N2 and the voltage at node N3 are equal, IMON is equal to the amount of current IM2. The current flowing through transistor M3 also flows through resistor R3. Therefore, a voltage corresponding to the current flowing through transistor M2 is generated at node N5. The operational amplifier 14 controls the gate voltages (VGATE) of transistors M1 and M2 so that the voltage at node N4 is equal to the reference voltage VREF.

[0021] In the power supply circuit 1 described above, the set of transistors M2 and M3, resistors R1 to R3, operational amplifier section 13, and operational amplifier 14 corresponds to a semiconductor circuit that functions as a power supply protection circuit PC according to the first embodiment. The power supply protection circuit PC detects the input current input from the input terminal 11. Transistor M3 then outputs a current IMON corresponding to the input current. The power supply protection circuit PC can adjust the gate voltages of transistors M1 and M2 based on the comparison result between the voltage corresponding to the detected current amount (IMON) and the reference voltage VREF. A more detailed circuit configuration of the power supply protection circuit PC is described below.

[0022] Figure 2 is a circuit diagram showing a more detailed example of the circuit configuration of the power supply circuit 1 equipped with the power supply protection circuit PC according to the first embodiment. Note that in the drawings referred to below, some parts of the configuration of the power supply circuit 1 are omitted as appropriate. As shown in Figure 2, the power supply protection circuit PC according to the first embodiment further includes a calibration operational amplifier section AMP. The operational amplifier section 13 includes, for example, transistors M11 to M16, a constant current source CS1, and nodes N11 and N12. Transistors M11 and M12 are each P-type high-voltage MOSFETs. Transistors M13 and M14 are each N-type high-voltage MOSFETs. Transistors M15 and M16 are each, for example, N-type low-voltage MOSFETs.

[0023] The source of transistor M11 is connected to node N3. The drain of transistor M11 is connected to the drain of transistor M13 via node N11. The source of transistor M12 is connected to node N2. The drain of transistor M12 is connected to the drain of transistor M14 via node N12. The gates of transistors M11 and M12 are connected to node N11. The sizes of transistors M11 and M12 are approximately equal. Transistors M11 and M12 form a current mirror circuit. Node N12 corresponds to the output terminal of the operational amplifier section 13. That is, node N12 is connected to the gate of transistor M3.

[0024] The source of transistor M13 is connected to the drain of transistor M15. The source of transistor M14 is connected to the drain of transistor M16. A clamp voltage VCL is applied to the gates of transistors M13 and M14, respectively. The clamp voltage VCL is higher than the ground voltage. Transistor M13 lowers the source voltage based on the clamp voltage VCL. Transistor M14 lowers the source voltage based on the clamp voltage VCL. The sizes of transistors M13 and M14 are approximately equal. Low-voltage MOSFETs may be used as transistors connected to the source node by clamping the voltage, with each of transistors M13 and M14 doing so.

[0025] The sources of transistor M15 and transistor M16 are each connected to node N13. A reference voltage VREF is applied to the gate of transistor M15. The sizes of transistors M15 and M16 are approximately equal.

[0026] The constant current source CS1 is connected between node N13 and the ground node GND. As a result, the constant current source CS1 operates so that the sum of the current flowing from node N3 to node N13 via transistors M11, M13, and M15, and the current flowing from node N2 to node N13 via transistors M12, M14, and M16, remains constant.

[0027] The calibration operational amplifier (AMP) section is configured to calibrate the operational amplifier (OPA) section 13 by controlling the gate voltage of transistor M16 based on the error between the voltage at node N2 and the voltage at node N3. Specifically, the non-inverting input (first input terminal) of the calibration operational amplifier (AMP) section is connected to node N3. The inverting input (second input terminal) of the calibration operational amplifier (AMP) section is connected to node N2. The output terminal of the calibration operational amplifier (AMP) section is connected to the gate of transistor M16. As a result, the calibration operational amplifier (AMP) section can output a signal to the gate of transistor M16 corresponding to the voltage difference between the first input terminal and the second input terminal. When the voltage at the first input terminal and the voltage at the second input terminal are equal, the calibration operational amplifier (AMP) section outputs a reference voltage VREF.

[0028] In the power supply protection circuit PC according to the first embodiment described above, transistors M3 and M11-M14 function as a current sense circuit. Transistors M15 and M16, constant current source CS1, and calibration operational amplifier section AMP function as a calibration amplifier.

[0029] <1-2> Operation Next, the operation of the power protection circuit PC according to the first embodiment will be described.

[0030] Figure 3 is a schematic diagram showing a first example of the operation of the power protection circuit PC according to the first embodiment. Figure 3 illustrates the operation of the power protection circuit PC when the voltage at node N3 is higher than the voltage at node N2. In this example, as shown in Figure 3(1), the voltage at node N3 (high) is higher than the voltage at node N2 (low). In this case, as shown in Figure 3(2), the calibration operational amplifier section AMP controls the output voltage to be higher than the reference voltage VREF (high). As a result, as shown in Figure 3(3), the gate voltage of transistor M16 increases, and the amount of current flowing through transistor M16 increases (high). Consequently, as shown in Figure 3(4), the gate voltage of transistor M3 decreases, and the amount of current flowing through transistor M3 increases, causing the voltage at node N3 to decrease.

[0031] Figure 4 is a schematic diagram showing a second example of the operation of the power protection circuit PC according to the first embodiment. Figure 4 illustrates the operation of the power protection circuit PC when the voltage at node N2 is higher than the voltage at node N3. In this example, as shown in Figure 4(1), the voltage at node N2 (high) is higher than the voltage at node N3 (low). In this case, as shown in Figure 4(2), the calibration operational amplifier section AMP controls the output voltage to be lower than the reference voltage VREF (low). As a result, as shown in Figure 4(3), the gate voltage of transistor M16 decreases, and the amount of current flowing through transistor M16 decreases (low). Consequently, as shown in Figure 4(4), the gate voltage of transistor M3 increases, and the amount of current flowing through transistor M3 decreases, causing the voltage at node N3 to increase.

[0032] As described above, the power protection circuit PC according to the first embodiment can adjust the gate voltage of transistor M16 and the amount of current flowing through transistor M3 based on the error between the voltage at node N2 and the voltage at node N3.

[0033] <1-3> Effects of the First Embodiment In the power protection circuit PC according to the first embodiment, the operational amplifier section 13 is configured to be self-calibrated, thereby suppressing (reducing) variations in the current amount IMON flowing through transistor M3. As a result, the power protection circuit PC according to the first embodiment can automatically calibrate the current sense circuit on-chip, improving the accuracy of current sensing. Therefore, the power supply circuit 1 equipped with the power protection circuit PC according to the first embodiment can limit the output current with high precision. Furthermore, since the power protection circuit PC according to the first embodiment is calibrated to be self-calibrated, the testing process can be simplified. As a result, the power protection circuit PC according to the first embodiment can reduce the manufacturing cost of the power supply circuit 1.

[0034] <2> Second Embodiment The second embodiment relates to a more specific circuit configuration of the calibration operational amplifier section AMP used as a calibration amplifier. Below, the details of the power supply protection circuit PCa according to the second embodiment will be described, mainly focusing on the differences from the first embodiment.

[0035] <2-1> Composition Figure 5 is a circuit diagram showing an example of the circuit configuration of a power supply circuit 1A equipped with a power supply protection circuit PCa according to the second embodiment. As shown in Figure 5, the power supply protection circuit PCa according to the second embodiment has a configuration in which the calibration operational amplifier section AMP is replaced with a calibration operational amplifier section AMPa compared to the power supply protection circuit PC according to the first embodiment. The calibration operational amplifier section AMPa includes, for example, transistors M21 to M26, capacitors C1 and C2, switches S11, S12, S21 and S22, a constant current source CS2, and nodes N21 to N25. Transistors M21 and M22 are each P-type high-voltage MOSFETs. Transistors M23 and M24 are each N-type high-voltage MOSFETs. Transistors M25 and M26 are each, for example, N-type low-voltage MOSFETs.

[0036] The pair of switches S11 and S12 and the pair of switches S21 and S22 are controlled complementaryly, for example. When switches S11 and S12 are controlled to the ON state, switches S21 and S22 are controlled to the OFF state. When switches S21 and S22 are controlled to the ON state, switches S11 and S12 are controlled to the OFF state.

[0037] The source of transistor M21 is connected to node N3 via switch S11 and to node N2 via switch S21. The drain of transistor M21 is connected to the drain of transistor M23 via node N21. The source of transistor M22 is connected to node N3. The drain of transistor M22 is connected to the drain of transistor M24. The gates of transistors M21 and M22 are connected to node N21. The sizes of transistors M21 and M22 are approximately equal. Transistors M21 and M22 form a current mirror circuit.

[0038] The source of transistor M23 is connected to the drain of transistor M25. The source of transistor M24 is connected to the drain of transistor M26 via node N22. A clamp voltage VCL is applied to the gates of transistors M23 and M24, respectively. Transistor M23 lowers the source voltage based on the clamp voltage VCL. Transistor M24 lowers the source voltage based on the clamp voltage VCL. The sizes of transistors M23 and M24 are approximately equal. Low-voltage MOSFETs may be used as transistors connected to the source node by clamping the voltage, respectively.

[0039] The sources of transistor M25 and transistor M26 are each connected to node N23. A reference voltage VREF is applied to the gate of transistor M25. The sizes of transistors M25 and M26 are approximately equal.

[0040] The constant current source CS2 is connected between node N23 and the ground node GND. This causes the constant current source CS2 to operate in such a way that the sum of the current flowing from node N2 or N3 to node N23 via transistors M21, M23, and M25, and the current flowing from node N3 to node N23 via transistors M22, M24, and M26, remains constant.

[0041] Furthermore, node N22 is connected to node N24 via switch S12, and to node N25 via switch S22. Node N24 is connected to the gate of transistor M26. Node N25 is connected to the gate of transistor M16. In other words, node N25 corresponds to the output terminal of the calibration operational amplifier section AMPa.

[0042] One end of capacitor C1 is connected to node N24. The other end of capacitor C1 is connected to the ground node GND. This configures capacitor C1 to store charge based on the voltage at node N24. One end of capacitor C2 is connected to node N25. The other end of capacitor C2 is connected to the ground node GND. This configures capacitor C2 to store charge based on the voltage at node N24.

[0043] Figure 6 is a circuit diagram showing a more detailed example of the circuit configuration of a power supply circuit 1A equipped with a power supply protection circuit PCa according to the second embodiment. As shown in Figure 6, the power supply protection circuit PCa according to the second embodiment further includes transistors M17-M19 and M27-M30, inverters IV1 and IV2, and level shifters LS1 and LS2. Each of the transistors M17, M27 and M30 is, for example, an N-type low-voltage MOSFET. Each of the transistors M18, M19, M28 and M29 is, for example, a P-type low-voltage MOSFET.

[0044] The drain of transistor M17 is connected to node N13. The drain of transistor M27 is connected to node N23. The sources of transistors M17, M27, and M30 are connected to the ground node GND. The voltage IBIAS is applied to the gates of transistors M17, M27, and M30, respectively. A constant current based on the voltage IBIAS flows between the source and drain of transistor M30. Transistors M17 and M27 mirror the constant current flowing through transistor M30 by applying the voltage IBIAS to their gates. Thus, transistors M17 and M27 function as constant current sources CS1 and CS2, respectively.

[0045] The source of transistor M28 is connected to node N3. The source of transistor M18 is connected to node N2. The drains of transistor M28 and M18 are each connected to the source of transistor M21. Control signals P1 and P2 are input to level shifters LS1 and LS2, respectively. Level shifter LS1 inverts the input control signal P1 to obtain a level-shifted control signal P1bh, which is then input to the gate of transistor M28. Level shifter LS2 inverts the input control signal P2 to obtain a level-shifted control signal P2bh, which is then input to the gate of transistor M18. As a result, transistors M28 and M18 function as switches S11 and S21, respectively.

[0046] The sources of transistor M29 and transistor M19 are connected to node N22, respectively. The drain of transistor M29 is connected to node N24. The drain of transistor M19 is connected to node N25. Control signals P1 and P2 are input to inverters IV1 and IV2, respectively. Inverter IV1 inputs control signal P1b, which is the inverted version of the input control signal P1, to the gate of transistor M29. Inverter IV2 inputs control signal P2b, which is the inverted version of the input control signal P2, to the gate of transistor M19. As a result, transistors M29 and M19 function as switches S12 and S22, respectively.

[0047] <2-2> Operation Next, the operation of the power protection circuit PCa according to the second embodiment will be described. In this specification, the high-level voltage is the voltage at which an N-type MOSFET with that voltage applied to its gate turns on, and a P-type MOSFET with that voltage applied to its gate turns off. The high-level voltage is, for example, 3V. The low-level voltage is the voltage at which an N-type MOSFET with that voltage applied to its gate turns off, and a P-type MOSFET with that voltage applied to its gate turns on. The low-level voltage is, for example, 0V. Vin is a voltage higher than the ground voltage. The ground voltage is, for example, 0V.

[0048] Figure 7 is a timing chart showing an example of the operation of the power protection circuit PCa according to the second embodiment. Figure 7 illustrates the operation of each of the control signals P1, P1b, P1bh, P2, P2b, and P2bh when the power circuit 1 is in the ON state. As shown in Figure 7, control signals P1 and P2 are clock signals that are out of phase and do not overlap with each other. Specifically, for control signals P1, P1b, and P1bh, the control of the period T_P1on and the control of the period T_P1off are repeated alternately. For control signals P2, P2b, and P2bh, the control of the period T_P1on and the control of the period T_P1off are repeated alternately.

[0049] During period T_P1on, control signal P1 is controlled to, for example, 3V (high level). During period T_P1on, control signal P1b is controlled to, for example, 0V (low level). During period T_P1on, control signal P1bh is controlled to, for example, Vin-3V (low level). As a result, during period T_P1on, transistors M28 and M29 are turned on. That is, during period T_P1on, switches S11 and S12 are controlled to be turned on.

[0050] During the period T_P1off, the control signal P1 is controlled to, for example, 0V (low level). During the period T_P1off, the control signal P1b is controlled to, for example, 3V (high level). During the period T_P1off, the control signal P1bh is controlled to, for example, Vin (high level). As a result, during the period T_P1off, transistors M28 and M29 are both turned off. That is, during the period T_P1off, switches S11 and S12 are controlled to be turned off.

[0051] During the period T_P2on, the control signal P2 is controlled to, for example, 3V (high level). During the period T_P2on, the control signal P2b is controlled to, for example, 0V (low level). During the period T_P2on, the control signal P2bh is controlled to, for example, Vin-3V (low level). As a result, during the period T_P2on, transistors M18 and M19 are turned on. That is, during the period T_P2on, switches S21 and S22 are controlled to be turned on.

[0052] During the period T_P2off, the control signal P2 is controlled to, for example, 0V (low level). During the period T_P2off, the control signal P2b is controlled to, for example, 3V (high level). During the period T_P1off, the control signal P2bh is controlled to, for example, Vin (high level). As a result, during the period T_P2off, transistors M18 and M19 are both turned off. That is, during the period T_P2on, switches S21 and S22 are controlled to be turned off.

[0053] The period T_P1on is included in the period T_P2off. The period T_P2on is included in the period T_P1off. In this way, the pair of switches S11 and S12 and the pair of switches S21 and S22 are controlled so that they do not turn on at the same time. The period T_P1on may be set to be shorter than the period T_P2off. The period T_P2on may be set to be shorter than the period T_P1off. Figure 7 illustrates a case where a portion of the period T_P1off and a portion of the period T_P2off overlap.

[0054] Figure 8 is a schematic diagram showing a first example of the operation of the power protection circuit PCa according to the second embodiment. Figure 8 illustrates the operation of the power protection circuit PCa during the period when the periods T_P1on and T_P2off overlap. As shown in Figure 8, in this example, since switches S11 and S21 are in the ON state and the OFF state, respectively, current flows into node N23 from node N3 via transistors M21, M23 and M25, and current flows in via transistors M22, M24 and M26.

[0055] Furthermore, in this example, since switches S12 and S22 are ON and OFF respectively, current flows from node N22 to node N24 via switch S12, and node N24 can be charged. Capacitor C1 can then store the charge that has flowed into node N24. In addition, the calibration operational amplifier section AMPa adjusts the voltage at node N24, i.e., the gate voltage of transistor M26, so that the difference between the drain voltage of transistor M21 and the drain voltage of transistor M22 approaches zero.

[0056] Specifically, in the calibration operational amplifier section AMPa, if the drain voltage of transistor M21 is lower than the drain voltage of transistor M22, the voltage at node N24 (gate voltage of transistor M26) increases, and the amount of current flowing through transistor M26 increases. As a result, the drain voltage of transistor M22 decreases. On the other hand, in the calibration operational amplifier section AMPa, if the drain voltage of transistor M21 is higher than the drain voltage of transistor M22, the voltage at node N24 (gate voltage of transistor M26) decreases, and the amount of current flowing through transistor M26 decreases. As a result, the drain voltage of transistor M22 increases.

[0057] As explained above, during the period when periods T_P1on and T_P2off overlap, the calibration operational amplifier section AMPa, which functions as a calibration amplifier, can itself be calibrated. During the period when periods T_P1on and T_P2off overlap, the voltage at node N25 becomes the voltage based on the charge stored in capacitor C2.

[0058] Figure 9 is a schematic diagram showing a second example of the operation of the power protection circuit PCa according to the second embodiment. Figure 9 illustrates the operation of the power protection circuit PCa during the period when the periods T_P2on and T_P1off overlap. As shown in Figure 9, in this example, since switches S11 and S21 are in the off state (OFF) and on state (ON), respectively, current flows into node N23 from node N3 through transistors M22, M24 and M26, and from node N2 through transistors M21, M23 and M25.

[0059] Furthermore, in this example, since switches S12 and S22 are in the OFF and ON states, respectively, current flows from node N22 to node N25 via switch S22, and node N25 can be charged. Capacitor C2 can then store the charge that has flowed into node N25. In addition, the calibration operational amplifier section AMPa adjusts the voltage at node N25, i.e., the gate voltage of transistor M16, so that the difference between the voltage at node N3 and the voltage at node N2 approaches zero.

[0060] Specifically, the calibration operational amplifier AMPa increases the voltage at node N25 when the voltage at node N3 is higher than the voltage at node N2. As a result, the current flowing through transistor M16 increases, and the gate voltage of transistor M3 decreases. This increases the current flowing through transistor M3, and the voltage at node N3 decreases. On the other hand, the calibration operational amplifier AMPa decreases the voltage at node N25 when the voltage at node N3 is lower than the voltage at node N2. As a result, the current flowing through transistor M16 decreases, and the gate voltage of transistor M3 increases. This decreases the current flowing through transistor M3, and the voltage at node N3 increases.

[0061] As explained above, the current sense circuit (transistors M11-M14) can be calibrated during the overlapping period between periods T_P2on and T_P1off. Furthermore, during the overlapping period between T_P1on and T_P2off, the voltage at node N24 is based on the charge stored in capacitor C1.

[0062] <2-3> Effects of the second embodiment In the power protection circuit PCa according to the second embodiment, the calibration operational amplifier section AMPa and the current sense circuit are configured to be calibrated alternately, and the accuracy of the calibration operational amplifier section AMPa can be improved compared to the first embodiment. As a result, the power protection circuit PCa according to the second embodiment can suppress (reduce) the variation in the amount of current IMON flowing through transistor M3 compared to the first embodiment, and the accuracy of current sensing can be improved. Therefore, the power supply circuit 1A equipped with the power protection circuit PCa according to the second embodiment can limit the output current with higher accuracy than the first embodiment. In addition, the power protection circuit PCa according to the second embodiment can simplify the test process, similar to the first embodiment, and the manufacturing cost of the power supply circuit 1 can be reduced.

[0063] <3> Third Embodiment The power protection circuit PCB according to the third embodiment is a modified version of the power protection circuit PCB according to the second embodiment. The details of the power protection circuit PCB according to the third embodiment will be described below, mainly focusing on the differences from the first and second embodiments.

[0064] <3-1> Composition Figure 10 is a circuit diagram showing an example of the circuit configuration of a power supply circuit 1B equipped with a power supply protection circuit PCb according to the third embodiment. As shown in Figure 10, the power supply protection circuit PCb according to the third embodiment has a configuration in which the calibration operational amplifier section AMPa is replaced with a calibration operational amplifier section AMPb compared to the power supply protection circuit PCa according to the second embodiment. The calibration operational amplifier section AMPb has a configuration in which transistors M25 and M26, constant current source CS2, and node N23 are omitted compared to the calibration operational amplifier section AMPa, and resistors R4 and R5, constant current sources CS3 and CS4, transistor M31, and nodes N31 and N32 are added. Transistor M31 is, for example, an N-type high-voltage MOSFET.

[0065] The constant current source CS3 is connected between the source of transistor M23 and the ground node GND. The constant current source CS4 is connected between the source of transistor M24 and the ground node GND. The switch S11 of the third embodiment is connected between nodes N3 and N31. The switch S21 of the third embodiment is connected between nodes N2 and N31. The source of transistor M21 of the third embodiment is connected to node N31 via resistor R4. The source of transistor M22 of the third embodiment is connected to node N32. Node N32 is connected to node N3 via resistor R5. The drain of transistor M31 is connected to node N32. The source of transistor M31 is connected to the ground node GND. Node N24 of the third embodiment is connected to the gate of transistor M31.

[0066] <3-2> Operation Next, the operation of the power protection circuit PCB according to the third embodiment will be described. The control method for switches S11, S12, S21, and S22 in the power protection circuit PCB according to the third embodiment is the same as the control method described with reference to Figure 7 in the first embodiment.

[0067] Figure 11 is a schematic diagram showing a first example of the operation of the power protection circuit PCB according to the third embodiment. Figure 11 illustrates the operation of the power protection circuit PCB during the period when switches S11 and S12 are ON and switches S21 and S22 are OFF. The calibration operational amplifier section AMPb adjusts the voltage at node N24, i.e., the gate voltage of transistor M31, so that the difference between the voltage across resistor R5 and the voltage across resistor R4 approaches zero.

[0068] In this example, as shown in Figure 11(1), the voltage across resistor R5 (high) is higher than the voltage across resistor R4 (low). In this case, in the calibration operational amplifier section AMPb, as shown in Figure 11(2), the voltage at node N24 rises (high). Then, as shown in Figure 11(3), the gate voltage of transistor M31 increases, the amount of current flowing through transistor M31 increases (high), and the voltage at node N32 decreases. On the other hand, although not shown in the diagram, if the voltage across resistor R5 is lower than the voltage across resistor R4, the voltage at node N24 in the calibration operational amplifier section AMPb decreases. Then, the gate voltage of transistor M31 decreases, the amount of current flowing through transistor M31 decreases, and the voltage at node N32 rises.

[0069] As described above, the calibration operational amplifier section AMPa, used as a calibration amplifier, can be calibrated by adjusting the gate voltage of transistor M31. Also, as shown in Figure 11(4), capacitor C1 can store the charge flowing through node N24. The amount of charge stored in capacitor C1 can vary depending on the magnitude of the voltages across resistors R4 and R5.

[0070] Figure 12 is a schematic diagram showing a second example of the operation of the power protection circuit PCB according to the third embodiment. Figure 12 illustrates the operation of the power protection circuit PCB during a period when switches S11 and S12 are in the off state (OFF) and switches S21 and S22 are in the on state (ON).

[0071] In this example, current flows from node N3 to node N25 via resistor R5, transistors M22 and M24, and switch S22, allowing node N25 to be charged. Capacitor C2 can then store the charge that has flowed into node N25. Additionally, current flows from node N2 to the ground node GND via switch S21, resistor R4, and transistors M21 and M23. Furthermore, the calibration operational amplifier section AMPb adjusts the voltage at node N25, i.e., the gate voltage of transistor M16, so that the difference between the voltage at node N3 and the voltage at node N2 approaches zero.

[0072] Specifically, the calibration operational amplifier AMPb increases the voltage at node N25 when the voltage at node N3 is higher than the voltage at node N2. As a result, the current flowing through transistor M16 increases, and the gate voltage of transistor M3 decreases. This increases the current flowing through transistor M3, and the voltage at node N3 decreases. On the other hand, the calibration operational amplifier AMPb decreases the voltage at node N25 when the voltage at node N3 is lower than the voltage at node N2. As a result, the current flowing through transistor M16 decreases, and the gate voltage of transistor M3 increases. This decreases the current flowing through transistor M3, and the voltage at node N3 increases.

[0073] As explained above, the current sense circuit (transistors M11-M14) can be calibrated during the period when switches S11 and S12 are in the OFF state and switches S21 and S22 are in the ON state. During the period when switches S11 and S12 are in the ON state and switches S21 and S22 are in the OFF state, the voltage at node N24 is the voltage based on the charge stored in capacitor C1.

[0074] <3-3> Effects of the Third Embodiment The power protection circuit PCB according to the third embodiment, like the second embodiment, can suppress (reduce) variations in the amount of current IMON flowing through transistor M3, thereby improving the accuracy of current sensing. Therefore, the power supply circuit 1B equipped with the power protection circuit PCB according to the third embodiment can limit the output current with higher precision than the first embodiment. Furthermore, the power protection circuit PCB according to the third embodiment, like the first embodiment, can simplify the testing process, thereby reducing the manufacturing cost of the power supply circuit 1B.

[0075] <4> Fourth Embodiment The power protection circuit PCc according to the fourth embodiment is configured to perform calibration of the current sense circuit using two calibration operational amplifier sections AMP. The details of the power protection circuit PCc according to the fourth embodiment will be described below, mainly focusing on the differences from the first to third embodiments.

[0076] <4-1> Composition Figure 13 is a circuit diagram showing an example of the circuit configuration of a power supply circuit 1C equipped with a power supply protection circuit PCc according to the fourth embodiment. As shown in Figure 13, the power supply protection circuit PCc according to the fourth embodiment has a configuration in which the calibration operational amplifier section AMPa is replaced with two calibration operational amplifier sections AMPc1 and AMPc2 compared to the power supply protection circuit PCa according to the second embodiment. Calibration operational amplifier section AMPc1 has the same configuration as calibration operational amplifier section AMPa. Calibration operational amplifier section AMPc2 includes, for example, transistors M41 to M46, capacitor C3, switches S13, S14, S23 and S24, constant current source CS5, and nodes N41 to N44. Transistors M41 and M42 are each P-type high-voltage MOSFETs. Transistors M43 and M44 are each N-type high-voltage MOSFETs. Transistors M45 and M46 are each, for example, N-type low-voltage MOSFETs. The set of switches S11-S14 and the set of switches S21-S24 are controlled complementaryly, for example.

[0077] The source of transistor M41 is connected to node N2 via switch S13 and to node N3 via switch S23. The drain of transistor M41 is connected to the drain of transistor M43 via node N41. The source of transistor M42 is connected to node N3. The drain of transistor M42 is connected to the drain of transistor M44. The gates of transistors M41 and M42 are connected to node N41. The sizes of transistors M41 and M42 are approximately equal. Transistors M41 and M42 form a current mirror circuit.

[0078] The source of transistor M43 is connected to the drain of transistor M45. The source of transistor M44 is connected to the drain of transistor M46 via node N42. A clamp voltage VCL is applied to the gates of transistors M43 and M44, respectively. Transistor M43 lowers the source voltage based on the clamp voltage VCL. Transistor M44 lowers the source voltage based on the clamp voltage VCL. The sizes of transistors M43 and M44 are approximately equal. Low-voltage MOSFETs may be used as transistors connected to the source node by clamping the voltage, respectively.

[0079] The sources of transistor M45 and transistor M46 are each connected to node N43. A reference voltage VREF is applied to the gate of transistor M45. The sizes of transistors M45 and M46 are approximately equal.

[0080] The constant current source CS5 is connected between node N43 and the ground node GND. This causes the constant current source CS5 to operate in such a way that the sum of the current flowing from node N2 or N3 to node N43 via transistors M41, M43, and M45, and the current flowing from node N3 to node N43 via transistors M42, M44, and M46, remains constant.

[0081] Furthermore, node N42 is connected to node N25 via switch S14 and to node N44 via switch S24. Node N44 is connected to the gate of transistor M46. One end of capacitor C3 is connected to node N44. The other end of capacitor C3 is connected to the ground node GND. That is, capacitor C3 is configured to store charge based on the voltage at node N44.

[0082] <4-2>Operation Next, the operation of the power protection circuit PCc according to the fourth embodiment will be described. The control method for switches S11, S12, S21, and S22 in the power protection circuit PCc according to the fourth embodiment is the same as the control method described with reference to Figure 7 in the first embodiment. Also, the control method for switches S13 and S14 in the fourth embodiment is the same as for switches S11 and S12. The control method for switches S23 and S24 in the fourth embodiment is the same as for switches S21 and S22.

[0083] Figure 14 is a schematic diagram showing a first example of the operation of the power protection circuit PCc according to the fourth embodiment. Figure 14 illustrates the operation of the power protection circuit PCc during a period when switches S11 to S14 are ON and switches S21 to S24 are OFF. In this example, the operation of the calibration operational amplifier section AMPc1 is the same as the operation of the calibration operational amplifier section AMPb described using Figure 8 in the second embodiment.

[0084] As shown in Figure 14, in this example, switches S13 and S23 are ON and OFF, respectively, in the calibration operational amplifier section AMPc2. Therefore, current flows into node N43 from node N2 through transistors M41, M43, and M45, and from node N3 through transistors M42, M44, and M46. Also, in this example, since switches S14 and S24 are ON and OFF, respectively, current flows from node N42 to node N25 through switch S14, and node N25 can be charged. Capacitor C2 can then store the charge that has flowed into node N24. Furthermore, the calibration operational amplifier section AMPc2 adjusts the voltage of node N25, i.e., the gate voltage of transistor M16, so that the difference between the voltage of node N3 and the voltage of node N2 approaches zero.

[0085] In other words, during the period when switches S11 to S14 are ON and switches S21 to S24 are OFF, the calibration operational amplifier AMPc1 performs self-calibration, and the calibration operational amplifier AMPc2 performs calibration of the current sense circuit.

[0086] Figure 15 is a schematic diagram showing a second example of the operation of the power protection circuit PCc according to the fourth embodiment. Figure 15 illustrates the operation of the power protection circuit PCc during a period when switches S11 to S14 are in the off state (OFF) and switches S21 to S24 are in the on state (ON). In this example, the operation of the calibration operational amplifier section AMPc1 is the same as the operation of the calibration operational amplifier section AMPb described using Figure 9 in the second embodiment.

[0087] As shown in Figure 15, in this example, switches S13 and S23 are in the OFF and ON states, respectively, in the calibration operational amplifier section AMPc2. Therefore, current flows into node N43 from node N3 through transistors M41, M43, and M45, and through transistors M42, M44, and M46. Also, in this example, since switches S14 and S24 are in the OFF and ON states, respectively, current flows from node N42 to node N44 through switch S24, and node N44 can be charged. Capacitor C3 can then store the charge that has flowed into node N44. Furthermore, the calibration operational amplifier section AMPc2 adjusts the voltage at node N24, i.e., the gate voltage of transistor M46, so that the difference between the source voltage of transistor M41 and the source voltage of transistor M42 approaches zero.

[0088] In other words, during the period when switches S11 to S14 are in the OFF state and switches S21 to S24 are in the ON state, the calibration operational amplifier AMPc1 performs calibration of the current sense circuit, and the calibration operational amplifier AMPc2 performs self-calibration.

[0089] <4-3> Effects of the fourth embodiment In the power protection circuit PCc according to the fourth embodiment, when the power supply circuit 1C is ON, one of the calibration operational amplifier units AMPc1 and AMPc2 performs self-calibration, and the other of the calibration operational amplifier units AMPc1 and AMPc2 performs calibration of the current sense circuit. In other words, the calibration operational amplifier units AMPc1 and AMPc2 alternately perform self-calibration and calibration of the current sense circuit.

[0090] As a result, the power protection circuit PCc according to the fourth embodiment can suppress (reduce) the variation in the gate voltage of transistor M16, which is used to adjust the gate voltage of transistor M3, compared to the second embodiment, and improve the accuracy of current sensing. Therefore, the power supply circuit 1C equipped with the power protection circuit PCc according to the fourth embodiment can limit the output current with higher precision than the second embodiment. In addition, the power protection circuit PCc according to the fourth embodiment can simplify the testing process, similar to the first embodiment, and can reduce the manufacturing cost of the power supply circuit 1C.

[0091] Furthermore, the total capacitance of capacitors C1 to C3 in the power protection circuit PCc according to the fourth embodiment can be designed to be smaller than the total capacitance of capacitors C1 and C2 in the power protection circuit PC1. In other words, the total capacitance of the power protection circuit PCc according to the fourth embodiment can be reduced compared to the power protection circuit PCa according to the second embodiment. This is because, in the power protection circuit PCc according to the fourth embodiment, the frequency at which capacitor C2 is charged is higher than in the second embodiment, and the capacitance of capacitor C2 used to control the gate voltage of transistor M16 can be reduced. As a result, the chip size of the power protection circuit PCc according to the fourth embodiment can be reduced compared to the second embodiment, and the manufacturing cost of the power protection circuit PCc can be suppressed.

[0092] <5> Fifth Embodiment The power protection circuit PCd according to the fifth embodiment has a configuration in which cascode-connected transistors are added to the power protection circuit PCc according to the fourth embodiment. The details of the power protection circuit PCd according to the fifth embodiment will be described below, mainly focusing on the differences from the first to fourth embodiments.

[0093] <5-1> Composition Figure 16 is a circuit diagram showing an example of the circuit configuration of a power supply circuit 1D equipped with a power supply protection circuit PCd according to the fifth embodiment. As shown in Figure 16, the power supply protection circuit PCd according to the fifth embodiment has a configuration that adds transistors M51 to M56, M61 to M68, constant current sources CS6 to CS8, and nodes N51 to N54, N61 and N62 to the power supply protection circuit PCc according to the fourth embodiment. Each of the transistors M51 to M56 and M61 is, for example, a low-voltage PMOS transistor. Each of the transistors M62 to M68 is, for example, a low-voltage NMOS transistor.

[0094] The source of transistor M51 is connected to node N1. The drain of transistor M51 is connected to node N53. In the fifth embodiment, the gates of transistors M21 and M22 are connected to node N53 instead of node N21. A constant current source CS6 is connected between node N53 and the ground node GND. The constant current source CS6 operates so that the amount of current flowing through transistor M51 remains constant.

[0095] The source of transistor M52 is connected to node N1. The drain of transistor M52 is connected to node N54. In the fifth embodiment, the gates of transistors M41 and M42 are connected to node N54 instead of node N41. A constant current source CS7 is connected between node N54 and the ground node GND. The constant current source CS7 operates so that the amount of current flowing through transistor M52 is constant.

[0096] The source of transistor M53 is connected to node N3 via switch S11 and to node N2 via switch S21. The drain of transistor M53 is connected to the source of transistor M21. The source of transistor M54 is connected to node N3. The drain of transistor M53 is connected to the source of transistor M22 via node N51. Node N51 is connected to the gate of transistor M51. The gates of transistors M53 and M54, respectively, are connected to node N21.

[0097] The source of transistor M55 is connected to node N3 via switch S23 and to node N2 via switch S13. The drain of transistor M55 is connected to the source of transistor M41. The source of transistor M56 is connected to node N3. The drain of transistor M56 is connected to the source of transistor M42 via node N52. Node N52 is connected to the gate of transistor M52. The gates of transistors M55 and M56, respectively, are connected to node N41.

[0098] The gates of transistors M23, M24, M43, and M44, and the source of transistor M61, are connected to node N61. A clamp voltage VCL is applied to node N61. The drain and gate of transistor M61 are connected to node N62. The drain and gate of transistor M62 are connected to node N62. Node N62 is connected to the gates of transistors M63 through M68. A constant current source CS8 is connected between the source of transistor M62 and the ground node GND. The constant current source CS8 operates to keep the amount of current flowing through transistor M62 constant.

[0099] Transistor M63 is connected between transistors M13 and M15. Specifically, the drain of transistor M63 is connected to the source of transistor M13, and the source of transistor M63 is connected to the drain of transistor M15. Transistor M64 is connected between transistors M14 and M16. Specifically, the drain of transistor M64 is connected to the source of transistor M14, and the source of transistor M64 is connected to the drain of transistor M16. The size of transistor M63 and the size of transistor M64 are approximately equal.

[0100] Transistor M65 is connected between transistors M23 and M25. Specifically, the drain of transistor M65 is connected to the source of transistor M23, and the source of transistor M65 is connected to the drain of transistor M25. Transistor M66 is connected between transistors M24 and M26. Specifically, the drain of transistor M66 is connected to the source of transistor M24, and the source of transistor M66 is connected to the drain of transistor M26. The sizes of transistors M65 and M66 are approximately equal.

[0101] Transistor M67 is connected between transistors M43 and M45. Specifically, the drain of transistor M67 is connected to the source of transistor M43, and the source of transistor M67 is connected to the drain of transistor M45. Transistor M68 is connected between transistors M44 and M46. Specifically, the drain of transistor M68 is connected to the source of transistor M44, and the source of transistor M68 is connected to the drain of transistor M46. The size of transistor M67 and the size of transistor M68 are approximately equal.

[0102] <5-2>Operation The operation of the power protection circuit PCd according to the fifth embodiment is the same as in the fourth embodiment.

[0103] <5-3> Effects of the Fifth Embodiment In the power protection circuit PCd according to the fifth embodiment, transistors M51 to M56 and M61 to M68 form a cascode connection. As a result, the power protection circuit PCd according to the fifth embodiment can reduce the variation in the current IMON flowing through transistor M3 compared to the fourth embodiment, and can improve the accuracy of current sensing. Therefore, the power supply circuit 1D equipped with the power protection circuit PCd according to the fifth embodiment can limit the output current with higher precision than the fourth embodiment.

[0104] <6> others The circuit configurations described in the above embodiments are merely examples. For example, in the power supply protection circuit PC according to the first embodiment, transistors M13 and M14 may be omitted. In the power supply protection circuit PCa according to the second embodiment, transistors M13, M14, M23 and M24 may be omitted. In the power supply protection circuit PCb according to the third embodiment, transistors M13, M14, M23 and M24 may be omitted. In the power supply protection circuit PCc according to the fourth embodiment, transistors M13, M14, M23, M24, M43 and M44 may be omitted. In the power supply protection circuit PCd according to the fifth embodiment, transistors M13, M14, M23, M24, M43, M44, M61 to M68 may be omitted.

[0105] Furthermore, the types of transistors in the circuit configuration described in the above embodiments may be other combinations. Either N-type transistors or P-type transistors may be used, as long as they can operate in the same manner as in the above embodiments. The fifth embodiment may be combined with the second to fourth embodiments. That is, multiple transistors constituting a cascode connection may be added to each of the power protection circuits PC, PCa, and PCb. This can further improve the variation in the current IMON flowing through transistor M3. The reference voltage VREF input to the operational amplifier 14 and the reference voltage VREF used in the operational amplifier section 13 may be different.

[0106] In this specification, “connection” means that an electrical connection is made, and does not exclude, for example, the interposition of another element. “Electrically connected” may be via an insulator, as long as it is possible to operate as if it were electrically connected. Word lines WL, selection gate lines SGD and SGS, etc., may be referred to as “wiring.” Nodes that connect some elements to each other may be referred to as “connection nodes.” In this specification, one of the source and drain of a transistor may be referred to as “one end” and the other as “the other end.” In this specification, a switch S may be referred to as a “switching element.” In this specification, the size of a transistor may be compared based on the gate length, gate width, etc.

[0107] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0108] 1, 1A, 1B, 1C, 1D… Power supply circuit, 11… Input terminal, 12… Output terminal, 13… Op-amp section, 14… Op-amp, 15… Charge pump, PC, PCa, PCb, PCc, PCd… Power supply protection circuit, AMP, AMPa, AMPb, AMPc1, AMPc2, AMPd1, AMPd2… Calibration op-amp section, C1~C3… Capacitor, CS1~CS8… Constant current source, IM1, IM2… Current quantity, IV1, IV2… Inverter Level shifters (LS1, LS2), transistors (M1-M5, M11-M19, M21-M31, M41-M46, M51-M56, M61-M68), nodes (N1-N5, N11-N13, N21-N25, N31, N32, N41-N44, N51-N54, N61, N62), control signals (P1, P1b, P1bh, P2, P2b, P2bh), resistors (R1-R5), switches (S11-S14, S21-S24)

Claims

1. A first transistor with one end connected to the first node, One end of the second transistor is connected to a second node different from the first node, and the gate of the second transistor is connected to the gate of the first transistor and the other end of the second transistor, A third transistor, one end of which is connected to the other end of the first transistor, and to which a first reference voltage is input at its gate, A fourth transistor, one end of which is connected to the other end of the second transistor and the other end of which is connected to the other end of the third transistor, A fifth transistor, one end of which is connected to the first node and the gate of which is connected to the other end of the second transistor, The device comprises an operational amplifier section having a first input terminal connected to the first node, a second input terminal connected to the second node, and inputting a voltage corresponding to the voltage difference between the voltage at the first input terminal and the voltage at the second input terminal to the gate of the fourth transistor. Semiconductor circuit.

2. A first resistor, one end of which is connected to the first node, A second resistor having one end connected to the second node and the other end connected to the other end of the first resistor, The system further comprises a first constant current source connected between the other end of the third transistor and a ground node, The semiconductor circuit according to claim 1.

3. Each of the first, second, third, fourth, and fifth transistors is a P-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The semiconductor circuit according to claim 1.

4. The semiconductor circuit described in claim 2, A sixth transistor is connected between the input terminal connected to the other end of the first resistor and the output terminal, The system further comprises a seventh transistor, one end of which is connected to the second node, the other end of which is connected to the output terminal, and whose gate is connected to the gate of the sixth transistor. power circuit.

5. A control circuit that inputs a voltage based on the input voltage input to the input terminal to the gate of the sixth transistor and the gate of the seventh transistor, A third resistor connected between the other end of the fifth transistor and the ground node, The present invention further comprises an operational amplifier whose first input terminal is connected to the other terminal of the fifth transistor, to which a second reference voltage is input, and which inputs a voltage corresponding to the voltage difference between the voltage at the first input terminal and the voltage at the second input terminal to the gate of the sixth transistor and the gate of the seventh transistor, respectively. The power supply circuit according to claim 4.

6. The operational amplifier section includes first to fourth switches, eighth to eleventh transistors, and first and second capacitors. One end of the eighth transistor is connected to the first node via the first switch and to the second node via the second switch. The ninth transistor has one end connected to the first node, and its gate is connected to the gate and the other end of the eighth transistor. The 10th transistor has one end connected to the other end of the 8th transistor, and the first reference voltage is input to its gate. The 11th transistor has one end connected to the other end of the 9th transistor, and the other end connected to the other end of the 10th transistor. The first capacitor is connected to the gate of the 11th transistor and is also connected to the one end of the 11th transistor via the third switch. The second capacitor is connected to the gate of the fourth transistor and to one end of the eleventh transistor via the fourth switch. The semiconductor circuit according to claim 1.

7. The first switch and the third switch are controlled based on the first clock signal. The second switch and the fourth switch are controlled based on a second clock signal which is in the opposite phase to the first clock signal. The semiconductor circuit according to claim 6.

8. A first resistor, one end of which is connected to the first node, A second resistor having one end connected to the second node and the other end connected to the other end of the first resistor, A first constant current source connected between the other end of the third transistor and the ground node, The present invention further comprises a second constant current source connected between the other end of the 11th transistor and the ground node, The semiconductor circuit according to claim 6.

9. Each of the first, second, third, fourth, fifth, eighth, ninth, tenth, and eleventh transistors is a P-type MOSFET. The semiconductor circuit according to claim 6.

10. The operational amplifier section includes first to fourth switches, third and fourth resistors, eighth, ninth and twelfth transistors, and first and second capacitors. One end of the third resistor is connected to the first node via the first switch and to the second node via the second switch. One end of the fourth resistor is connected to the first node, One end of the eighth transistor is connected to the other end of the third resistor, The ninth transistor has one end connected to the other end of the fourth resistor, and its gate connected to the gate and the other end of the eighth transistor. One end of the 12th transistor is connected to the other end of the 4th resistor, The first capacitor is connected to the gate of the 12th transistor and to the other end of the 9th transistor via the third switch. The second capacitor is connected to the gate of the fourth transistor and to the other end of the ninth transistor via the fourth switch. The semiconductor circuit according to claim 1.

11. The first switch and the third switch are controlled based on the first clock signal. The second switch and the fourth switch are controlled based on a second clock signal which is in the opposite phase to the first clock signal. The semiconductor circuit according to claim 10.

12. A first resistor, one end of which is connected to the first node, A second resistor having one end connected to the second node and the other end connected to the other end of the first resistor, A first constant current source connected between the other end of the third transistor and the ground node, A third constant current source connected between the other end of the eighth transistor and the ground node, The system further comprises a fourth constant current source connected between the other end of the ninth transistor and the ground node, The semiconductor circuit according to claim 10.

13. Each of the first, second, third, fourth, fifth, eighth, and ninth transistors is a P-type MOSFET. The 12th transistor is an N-type MOSFET. The semiconductor circuit according to claim 10.

14. The operational amplifier section further includes a fifth to eighth switch, a thirteenth to sixteenth transistor, and a third capacitor. One end of the 13th transistor is connected to the first node via the 5th switch and to the second node via the 6th switch. The 14th transistor has one end connected to the first node, and its gate is connected to the gate and the other end of the 13th transistor. The 15th transistor has one end connected to the other end of the 13th transistor, and the first reference voltage is input to its gate. The 16th transistor has one end connected to the other end of the 14th transistor and the other end connected to the gate of the 4th transistor via the 7th switch, and the other end connected to the other end of the 15th transistor. The third capacitor is connected to the gate of the 16th transistor and is also connected to the one end of the 16th transistor via the 8th switch. The semiconductor circuit according to claim 6.

15. The first switch, the third switch, the sixth switch, and the seventh switch are controlled based on the first clock signal. The second switch, the fourth switch, the fifth switch, and the eighth switch are controlled based on a second clock signal which is in the opposite phase to the first clock signal. The semiconductor circuit according to claim 14.

16. A first resistor, one end of which is connected to the first node, A second resistor having one end connected to the second node and the other end connected to the other end of the first resistor, A first constant current source connected between the other end of the third transistor and the ground node, A second constant current source connected between the other end of the 11th transistor and the ground node, The device further comprises a third constant current source connected between the other end of the 16th transistor and the ground node, The semiconductor circuit according to claim 14.

17. Each of the first, second, third, fourth, fifth, eighth, ninth, tenth, eleventh, thirteenth, fourteenth, fifteenth, and sixteenth transistors is a P-type MOSFET. The semiconductor circuit according to claim 14.

18. The operational amplifier section includes a cascode connection, The semiconductor circuit according to claim 16.

19. The operational amplifier section further includes the 17th to 22nd transistors, The 17th transistor is connected between the first switch and the second switch and the 8th transistor, The 18th transistor is connected between the first node and the 9th transistor, and the gate of the 18th transistor is connected to the gate of the 17th transistor and the other end of the 8th transistor. The 19th transistor has one end connected to the other end of the first resistor, and its gate connected to the connection node between the 9th transistor and the 18th transistor. The 20th transistor is connected between the 5th switch and the 6th switch and the 13th transistor, The 21st transistor is connected between the first node and the 14th transistor, and the gate of the 21st transistor is connected to the gate of the 20th transistor and the other end of the 13th transistor. The 22nd transistor has one end connected to the other end of the first resistor, and its gate connected to the connection node between the 14th transistor and the 21st transistor. The gates of the eighth transistor and the ninth transistor are each connected to the other end of the 19th transistor, rather than to the other end of the eighth transistor. The gate of the 13th transistor and the gate of the 14th transistor are connected to the other end of the 22nd transistor, rather than to the other end of the 13th transistor. The semiconductor circuit according to claim 18.

20. Each of the first transistor, second transistor, third transistor, fourth transistor, fifth transistor, eighth transistor, ninth transistor, tenth transistor, eleventh transistor, thirteenth transistor, fourteenth transistor, fifteenth transistor, and sixteenth transistor is a P-type MOSFET. Each of the 17th, 18th, 19th, 20th, 21st, and 22nd transistors is an N-type MOSFET. The semiconductor circuit according to claim 19.

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