Image sensor and method for manufacturing the same

Abstract

The present invention provides an image sensor and a method for manufacturing an image sensor that reduce the difficulty of reducing the pixel pitch. [Solution] The integrated chip includes a photodetector 114, a transfer transistor 116, a first pixel transistor 124, a capacitor (first LOFIC 150), a second pixel transistor 158, and a bonding structure. The first terminal of the transfer transistor is coupled to the first terminal of the photodetector. The first pixel transistor is located on the first semiconductor chip 102. The first terminal of the first pixel transistor is coupled to the second terminal of the transfer transistor. The first terminal of the capacitor located on the first semiconductor chip is coupled to the second terminal of the first pixel transistor. The second pixel transistor is located on the second semiconductor chip bonded to the first semiconductor chip. The bonding structure is located at the interface where the first semiconductor chip and the second semiconductor chip are joined, and it couples the second terminal of the capacitor to the first terminal of the second pixel transistor.

Description

Technical Field

[0001] The present invention generally relates to an image sensor and a method for manufacturing the image sensor.

Background Art

[0002] Complementary metal oxide semiconductor (CMOS) image sensors are used in a wide range of modern electronic devices such as, for example, cameras, tablets, smartphones, etc. The CMOS image sensor can be a front side illumination type (FSI) or a back side illumination type (BSI). Compared with the FSI image sensor, the BSI image sensor has better sensitivity, better angular response, and higher metal wiring flexibility.

[0003] Many modern integrated chips include transistors as well as passive devices. Some examples of passive devices include capacitors, resistors, inductors, varactors, etc. Passive devices are widely used to control integrated chip characteristics such as gain, time constant, etc. Some passive devices include integrated passive devices (IPDs). An IPD is a collection of one or more passive devices incorporated into a single monolithic device and packaged as an integrated circuit (IC).

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention generally relates to reducing the difficulty of decreasing the pixel pitch of an image sensor.

Means for Solving the Problems

[0005] ? In one embodiment of the present invention, the integrated chip includes a photodetector, a transfer transistor, a first pixel transistor, a first capacitor, a second pixel transistor, and a bonding structure. The photodetector has a first terminal. The transfer transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the transfer transistor is coupled to the first terminal of the photodetector. The first pixel transistor is located on a first semiconductor chip. The first pixel transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the first pixel transistor is coupled to the second terminal of the transfer transistor. The first capacitor is located on a first semiconductor chip. The first capacitor has a first terminal and a second terminal. The first terminal of the first capacitor is coupled to the second terminal of the first pixel transistor. The second pixel transistor is located on a second semiconductor chip bonded to the first semiconductor chip. The second pixel transistor has a first terminal, a second terminal, and a control terminal. The second terminal of the second pixel transistor is coupled to a first reference voltage terminal. The bonding structure is located at the interface where the first semiconductor chip and the second semiconductor chip are joined. The bonding structure connects the second terminal of the first capacitor to the first terminal of the second pixel transistor.

[0006] In one embodiment of the present invention, the integrated chip includes a photodetector, a transfer transistor, a first pixel transistor, a first lateral overflow storage capacitor (LOFIC), a first bonding pad, a second bonding pad, and a second pixel transistor. The photodetector and the transfer transistor are located on a first semiconductor chip and along a first semiconductor substrate, on a second semiconductor chip and along a second semiconductor substrate, or on a third semiconductor chip and along a third semiconductor substrate. The transfer transistor includes a first source / drain, a second source / drain, and a gate. The first source / drain of the transfer transistor is coupled to the photodetector. The first pixel transistor is located on a first semiconductor chip and along a first semiconductor substrate. The first pixel transistor includes a first source / drain, a second source / drain, and a gate. The first source / drain of the first pixel transistor is coupled to the second source / drain of the transfer transistor. The first LOFIC is located on the first semiconductor chip. The first LOFIC includes a first electrode, a second electrode, and a dielectric between the first and second electrodes. The first electrode is coupled to the second source / drain of the first pixel transistor via a first conductive interconnect on the first semiconductor chip. The first bonding pad is located on the first semiconductor chip and is coupled to the second electrode of the first LOFIC via a second conductive interconnect on the first semiconductor chip. The second bonding pad is located on the second semiconductor chip and is bonded to the first bonding pad. The second pixel transistor is located on the second semiconductor chip and is provided along the second semiconductor substrate. The second pixel transistor includes a first source / drain, a second source / drain, and a gate. The second source / drain of the second pixel transistor is coupled to the first reference voltage terminal via a fourth conductive interconnect on the second semiconductor chip. The first source / drain of the second pixel transistor is coupled to the second bonding pad via a third conductive interconnect on the second semiconductor chip.

[0007] In one embodiment of the present invention, a method for forming an integrated chip includes forming a photodetector and a transfer transistor. The transfer transistor includes a first source / drain, a second source / drain, and a gate. The first source / drain of the transfer transistor is coupled to the photodetector. The method includes forming a first pixel transistor along a first semiconductor substrate of a first semiconductor chip. The first pixel transistor includes a first source / drain, a second source / drain, and a gate. The first source / drain of the first pixel transistor is coupled to the second source / drain of the transfer transistor. The method includes forming a first conductive interconnect on the first semiconductor chip that is coupled to the second source / drain of the first pixel transistor. The method includes forming a first capacitor on the first semiconductor chip. The first capacitor includes a first electrode, a second electrode, and a dielectric between the first electrode and the second electrode. The first electrode is coupled to the first conductive interconnect. The method includes forming a second conductive interconnect on the first semiconductor chip that is coupled to the second electrode of the first capacitor. The method includes forming a first bonding pad on a first semiconductor chip that is coupled to a second conductive interconnect. The method includes forming a second pixel transistor along a second semiconductor substrate of the second semiconductor chip. The second pixel transistor includes a first source / drain, a second source / drain, and a gate. The method includes forming a third conductive interconnect on the second semiconductor chip that is coupled to the first source / drain of the second pixel transistor. The method includes forming a second bonding pad on the second semiconductor chip that is coupled to the third conductive interconnect. The method includes bonding the first bonding pad to the second bonding pad. The second electrode of the first capacitor is coupled to the first source / drain of the second pixel transistor via the second conductive interconnect, the first bonding pad, the second bonding pad, and the third conductive interconnect. [Effects of the Invention]

[0008] Based on the above, the second pixel transistor is located on the second semiconductor chip bonded to the first semiconductor chip. By moving the second pixel transistor to the second semiconductor chip, at least a portion of the second interconnect can be removed from the first semiconductor chip. In this way, the difficulty of reducing the pixel pitch can be lowered. [Brief explanation of the drawing]

[0009] The aspects of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, the features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for the sake of clarity in the description.

[0010] [Figure 1] The diagram shows cross-sectional views of several embodiments of an integrated chip including a first LOFIC on a first semiconductor chip, and pixel transistors on a second semiconductor chip coupled to the first LOFIC and bonded to the first semiconductor chip. [Figure 2] Figure 1 shows top views of several embodiments of the integrated chip. [Figure 3] Figure 1 shows circuit diagrams of several embodiments of the integrated chip. [Figure 4] Figure 3 shows circuit diagrams of several embodiments of the integrated chip, where an application-specific integrated circuit (ASIC) is located on a second semiconductor chip. [Figure 5] Figure 4 shows cross-sectional views of several embodiments of the integrated chip. [Figure 6] Figure 4 shows circuit diagrams of several embodiments of the integrated chip, further including a third semiconductor chip bonded to the first semiconductor chip. [Figure 7] Figure 6 shows cross-sectional views of several embodiments of the integrated chip. [Figure 8] Figure 6 shows cross-sectional views of several other embodiments of the integrated chip. [Figure 9] Figure 6 shows circuit diagrams of several embodiments of the integrated chip in which the pixel transistors are located on a third semiconductor chip. [Figure 10] Shows cross-sectional views of some embodiments of the integrated chip of FIG. 9. [Figure 11] Shows circuit diagrams of some embodiments of the integrated chip of FIG. 4, where the second LOFIC is on the first semiconductor chip. [Figure 12] Shows cross-sectional views of some embodiments of the integrated chip of FIG. 11. [Figure 13] Shows circuit diagrams of some embodiments of the integrated chip of FIG. 6, where the second LOFIC is on the first semiconductor chip. [Figure 14] Shows cross-sectional views of some embodiments of the integrated chip of FIG. 13. [Figure 15] Shows cross-sectional views of some other embodiments of the integrated chip of FIG. 13. [Figure 16] Shows circuit diagrams of some embodiments of the integrated chip of FIG. 9, where the second LOFIC is on the first semiconductor chip. [Figure 17] Shows cross-sectional views of some embodiments of the integrated chip of FIG. 16. [Figure 18] Shows cross-sectional views of various embodiments of the first LOFIC. [Figure 19] Shows cross-sectional views of various embodiments of the first LOFIC. [Figure 20] Shows cross-sectional views of various embodiments of the first LOFIC. [Figure 21] Shows cross-sectional views of various embodiments of the first LOFIC and the second LOFIC. [Figure 22] Shows cross-sectional views of various embodiments of the first LOFIC and the second LOFIC. [Figure 23] Shows cross-sectional views of various embodiments of the first LOFIC and the second LOFIC. [Figure 24] Shows cross-sectional views of various embodiments of the first LOFIC and the second LOFIC. [Figure 25] Shows cross-sectional views of some embodiments of a method of forming an integrated chip including a first LOFIC on a first semiconductor chip and pixel transistors on another chip bonded to the first semiconductor chip. [Figure 26]Shows cross-sectional views of some embodiments of a method of forming an integrated chip including a first LOFIC on a first semiconductor chip and pixel transistors on another chip bonded to the first semiconductor chip. [Figure 27] Shows cross-sectional views of some embodiments of a method of forming an integrated chip including a first LOFIC on a first semiconductor chip and pixel transistors on another chip bonded to the first semiconductor chip. [Figure 28] Shows cross-sectional views of some embodiments of a method of forming an integrated chip including a first LOFIC on a first semiconductor chip and pixel transistors on another chip bonded to the first semiconductor chip. [Figure 29] Shows cross-sectional views of some embodiments of a method of forming an integrated chip including a first LOFIC on a first semiconductor chip and pixel transistors on another chip bonded to the first semiconductor chip. [Figure 30] Shows cross-sectional views of some other embodiments of a method of forming an integrated chip including a first LOFIC on a first semiconductor chip and pixel transistors on another chip bonded to the first semiconductor chip. [Figure 31] Shows cross-sectional views of some other embodiments of a method of forming an integrated chip including a first LOFIC on a first semiconductor chip and pixel transistors on another chip bonded to the first semiconductor chip. [Figure 32] Shows cross-sectional views of some other embodiments of a method of forming an integrated chip including a first LOFIC on a first semiconductor chip and pixel transistors on another chip bonded to the first semiconductor chip. [Figure 33] Shows cross-sectional views of some other embodiments of a method of forming an integrated chip including a first LOFIC on a first semiconductor chip and pixel transistors on another chip bonded to the first semiconductor chip. [Figure 34] Shows cross-sectional views of some other embodiments of a method of forming an integrated chip including a first LOFIC on a first semiconductor chip and pixel transistors on another chip bonded to the first semiconductor chip. [Figure 35]This shows cross-sectional views of several other embodiments of a method for forming an integrated chip that includes a first LOFIC on a first semiconductor chip and pixel transistors on another chip bonded to the first semiconductor chip. [Figure 36] This shows cross-sectional views of several other embodiments of a method for forming an integrated chip that includes a first LOFIC on a first semiconductor chip and pixel transistors on another chip bonded to the first semiconductor chip. [Figure 37] This shows cross-sectional views of several other embodiments of a method for forming an integrated chip that includes a first LOFIC on a first semiconductor chip and pixel transistors on another chip bonded to the first semiconductor chip. [Figure 38] This shows cross-sectional views of several other embodiments of a method for forming an integrated chip that includes a first LOFIC on a first semiconductor chip and pixel transistors on another chip bonded to the first semiconductor chip. [Figure 39] This shows cross-sectional views of several other embodiments of a method for forming an integrated chip that includes a first LOFIC on a first semiconductor chip and pixel transistors on another chip bonded to the first semiconductor chip. [Figure 40] This shows cross-sectional views of several other embodiments of a method for forming an integrated chip that includes a first LOFIC on a first semiconductor chip and pixel transistors on another chip bonded to the first semiconductor chip. [Figure 41] This diagram shows a flow chart of several embodiments of a method for forming an integrated chip that includes a first capacitor on a first semiconductor chip and a pixel transistor on another chip bonded to the first semiconductor chip. [Modes for carrying out the invention]

[0011] The following disclosure provides many different embodiments or examples for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below for the sake of brevity of this disclosure. These are, of course, merely examples and are not intended to limit the scope. For example, forming a first feature above or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, or it may include embodiments in which an additional feature is formed between the first and second features and the first and second features are not in direct contact. In addition, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of brevity and clarity and does not in itself determine the relationships between the various embodiments and / or configurations discussed.

[0012] Furthermore, spatial relative terms such as “down,” “below,” “lower,” “up,” and “up” may be used herein for descriptive convenience to describe the relationship between one element or feature and another, as shown in the figures. Spatial relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented in other directions (rotated 90 degrees, or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0013] The integrated chip includes an image sensor. The image sensor includes a plurality of pixels. Each pixel includes a photodetector and a transfer transistor coupled to the photodetector. Each pixel includes a first pixel transistor located on a first semiconductor chip and coupled to the transfer transistor. Each pixel includes a lateral overflow storage capacitor (LOFIC) on the first semiconductor chip. The first electrode of the LOFIC is coupled to the first pixel transistor via a first conductive interconnect on the first semiconductor chip. The second electrode of the LOFIC is coupled to the second pixel transistor via a second conductive interconnect.

[0014] In some cases, the second pixel transistor and therefore the second conductive interconnect are located on the first semiconductor chip. However, when the second pixel transistor and second conductive interconnect are located on the first semiconductor chip, it may be difficult to reduce the pixel pitch of the image sensor (e.g., the distance between the centers of adjacent pixels). For example, the second interconnect may increase the complexity of the interconnect wiring on the first semiconductor chip. This may reduce the design flexibility of the interconnect wiring on the first semiconductor chip, which may make it more difficult to reduce the pixel pitch. Furthermore, the second pixel transistor and second conductive interconnect may occupy a considerable amount of space on the first semiconductor chip, which may make it more difficult to reduce the pixel pitch.

[0015] In various embodiments of the present invention, the second pixel transistor is located on a second semiconductor chip bonded to a first semiconductor chip. By moving the second pixel transistor to the second semiconductor chip, at least a portion of the second interconnect can be removed from the first semiconductor chip. This reduces the difficulty of reducing the pixel pitch. For example, the complexity of the interconnect wiring on the first semiconductor chip can be reduced, the design flexibility of the interconnect wiring on the first semiconductor chip can be improved, and the available space on the first semiconductor chip can be increased. Thus, the difficulty of reducing the pixel pitch can be reduced.

[0016] Figure 1 shows cross-sectional views 100 of several embodiments of an integrated chip including a first LOFIC 150 on a first semiconductor chip 102 and a pixel transistor 158 on a second semiconductor chip 104 coupled to the first LOFIC 150 and bonded to the first semiconductor chip 102.

[0017] The integrated chip includes a first semiconductor chip 102 and a second semiconductor chip 104 bonded to the first semiconductor chip 102. The first semiconductor chip 102 includes a first semiconductor substrate 108. The second semiconductor chip 104 includes a second semiconductor substrate 110.

[0018] The integrated chip includes a plurality of pixels. Each pixel includes a photodetector 114 and a transfer transistor 116. The photodetector 114 and the transfer transistor 116 are located on a first semiconductor chip 102 and are provided along a first semiconductor substrate 108. In some embodiments, the photodetector 114 is a photodiode formed by the first semiconductor substrate 108 and a photodiode region 118 in the first semiconductor substrate 108 (for example, a doped region in the first semiconductor substrate 10 having a different doping type than the first semiconductor substrate 108). The transfer transistor 116 includes a first source / drain 119 along the first semiconductor substrate 108, a second source / drain 120 along the first semiconductor substrate 108, and a gate 122 located between the first source / drain 119 and the second source / drain 120 along the first semiconductor substrate 108. In some embodiments, the photodiode region 118 forms the first source / drain 119 of the transfer transistor 116 (for example, the photodiode region 118 and the source / drain 119 are identical).

[0019] The first pixel transistor 124 is located on the first semiconductor chip 102. The first pixel transistor 124 is provided along the first semiconductor substrate 108 and includes a first source / drain 126, a second source / drain 128, and a gate 130 between the first source / drain 126 and the second source / drain 128. In some embodiments, the source / drain 126 and the source / drain 120 are identical. In some other embodiments, the source / drain 120 is separate from the source / drain 126, and the two are coupled via a conductive interconnect on the first semiconductor chip 102.

[0020] A first dielectric structure 132, which includes a first plurality of dielectric layers (not shown), is located on a first semiconductor chip 102. A first interconnect structure, which includes a first plurality of conductive interconnects (e.g., conductive contacts 136, conductive vias 138, 140, conductive wires 142, 144, conductive bonding contact 146, conductive bonding pad 148), is located on the first semiconductor chip 102 and is within the first dielectric structure 132.

[0021] The first lateral overflow storage capacitor (LOFIC) 150 is located on the first semiconductor chip 102. The first LOFIC 150 includes a first electrode layer 152, a second electrode layer 156, and a dielectric layer 154 between the first electrode layer 152 and the second electrode layer 156. The first electrode layer 152 of the first LOFIC 150 is coupled to the source / drain 128 of the first pixel transistor 124 by one or more conductive interconnects (e.g., contact 136, conductive wire 142, and conductive via 138) on the first semiconductor chip 102. The conductive via 140 is located on the second electrode layer 156 and coupled to the second electrode layer 156. The conductive wire 144 is located on the conductive via 140 and coupled to the conductive via 140.

[0022] The first source / drain 160 of the second pixel transistor 158 is coupled to the second electrode 156 of the first LOFIC 150 via a conductive wire 144 and a conductive via 140. In some integrated chips, the second pixel transistor 158 is on the same chip as the first LOFIC 150, as shown in 112 (for example, the second pixel transistor 158 is on the first semiconductor chip 102). In such a chip, additional interconnects are provided on the first semiconductor chip 102 to couple the first source / drain 160 of the second pixel transistor 158 to the conductive wire 144, and thus to the second electrode 156 of the first LOFIC 150. For example, additional contacts 166, additional conductive wires 168, 170, and additional conductive vias 172, 174 are on the first semiconductor chip 102 to couple the first source / drain 160 of the second pixel transistor 158 to the conductive wire 144. However, these additional interconnects could increase the complexity of the interconnect wiring on the first semiconductor chip 102 and reduce the space available for interconnect wiring on the first semiconductor chip 102. As a result, it may become more difficult to reduce the pixel pitch on the integrated chip.

[0023] In various embodiments of the present invention, the second pixel transistor 158 is located on the second semiconductor chip 104, as shown in 106. Therefore, additional interconnects (e.g., contacts 166, conductive wires 168, 170, and conductive vias 172, 174) can be omitted from the first semiconductor chip 102. As a result, the complexity of the interconnect wiring on the first semiconductor chip 102 can be reduced, the design flexibility of the interconnect wiring on the first semiconductor chip 102 can be improved, and the available space for interconnect wiring on the first semiconductor chip 102 can be increased. Thus, the difficulty of reducing the pixel pitch on the integrated chip can be lowered.

[0024] The second pixel transistor 158 (on the second semiconductor chip 104) is coupled to the second electrode layer 156 of the first LOFIC 150 (on the first semiconductor chip 102) by conductive wires 144 and conductive vias 140, by a bonding structure at the interface between the first semiconductor chip 102 and the second semiconductor chip 104, and by conductive interconnects of a second interconnect structure located on the second semiconductor chip 104 and within the second dielectric structure 188 of the second semiconductor chip 104. For example, the bonding structure includes a first bonding contact 146 and a first bonding pad 148 on the first semiconductor chip 102. The bonding structure further includes a second bonding contact 178 and a second bonding pad 176 on the second semiconductor chip 104. The first bonding pad 148 is coupled to the conductive wire 144 (the conductive wire 144 is coupled to the second electrode layer 156 by conductive vias 140) by the first bonding contact 146. The second bonding pad 176 is bonded to and coupled to the first bonding pad 148. Conductive wires 180, 182 and conductive via 184 on the second semiconductor chip 104 are coupled to the second bonding pad 176 by the second bonding contact 178. The first source / drain 160 of the second pixel transistor 158 is coupled to the conductive wires 180, 182 and conductive via 184 by the contact 186 on the second semiconductor chip 104. The second source / drain 162 of the second pixel transistor 158 is coupled to the first reference voltage terminal (e.g., 330 in Figure 3) via a conductive interconnect on the second semiconductor chip 104.

[0025] Figure 2 shows top views 200 of several embodiments of the integrated chip of Figure 1. In some embodiments, the top view 200 is obtained along the line A-A' in Figure 1.

[0026] In some embodiments, there is a minimum distance 202 (e.g., minimum pitch) that must be maintained between a conductive via 140 and an adjacent conductive via. Furthermore, in some embodiments, there is a minimum distance 204 that must be maintained between a LOFIC 150 and an adjacent conductive via. Thus, in some integrated chips where an additional conductive via 174 is located on the first semiconductor chip 102 (due to the second pixel transistor 158 being located on the first semiconductor chip 102), it may be difficult to reduce the pixel width and / or pixel length (e.g., from the first pixel width 206 to the second pixel width 208, and from the first pixel length 210 to the second pixel length 212) while maintaining the minimum distances 202 and 204. However, by removing the additional conductive via 174 from the first semiconductor chip 102 (by providing the second pixel transistor 158 on the second semiconductor chip 104), the pixel width and / or pixel length can be reduced more easily. Thus, the pixel pitch can be reduced more easily.

[0027] Figure 3 shows circuit diagrams 300 of several embodiments of the integrated chip shown in Figure 1.

[0028] The photodetector 114 and the transfer transistor 116 are located on the first semiconductor chip 102. The photodetector 114 (e.g., a photodiode) has a first terminal 302 (e.g., corresponding to the first semiconductor substrate 108) and a second terminal 304 (e.g., corresponding to the photodiode region 118). In some embodiments, the first terminal 302 is coupled to ground or another reference voltage source.

[0029] The transfer transistor 116 has a first terminal 306 (corresponding to, for example, the source / drain 119), a second terminal 308 (corresponding to, for example, the source / drain 120), and a control terminal 310 (corresponding to, for example, the gate 122). The first terminal 306 is coupled to terminal 304 of the photodetector 114.

[0030] The first pixel transistor 124 is located on the first semiconductor chip 102. The first pixel transistor 124 has a first terminal 312 (e.g., corresponding to source / drain 126), a second terminal 314 (e.g., corresponding to source / drain 128), and a control terminal 316 (e.g., corresponding to gate 130). The first terminal 312 is coupled to terminal 308 of the transfer transistor 116.

[0031] The first LOFIC 150 is located on the first semiconductor chip 102. The first LOFIC 150 has a first terminal 318 (for example, corresponding to the first electrode layer 152) and a second terminal 320 (for example, corresponding to the second electrode layer 156). The first terminal 318 is coupled to terminal 314 of the first pixel transistor 124.

[0032] The second pixel transistor 158 is located on the second semiconductor chip 104. The second pixel transistor 158 has a first terminal 322 (e.g., corresponding to a source / drain 160), a second terminal 324 (e.g., corresponding to a source / drain 162), and a control terminal 326 (e.g., corresponding to a gate 164). The first terminal 322 is coupled to terminal 320 of the first LOFIC 150 through a bonding structure 328 (e.g., corresponding to bonding pads 148, 176 and bonding contacts 146, 178). The second terminal 324 is coupled to the first reference voltage terminal 330. In some embodiments, the first reference voltage terminal 330 is coupled to ground. In some other embodiments, the first reference voltage terminal 330 is coupled to a first reference voltage source (not shown).

[0033] Figure 4 shows circuit diagrams 400 of several embodiments of the integrated chip shown in Figure 3, in which the application-specific integrated circuit (ASIC) 401 is located on the second semiconductor chip 104.

[0034] The integrated chip includes a third pixel transistor 402 (e.g., a reset transistor), a fourth pixel transistor 404 (e.g., a source follower transistor), and a fifth pixel transistor 406 (e.g., a row selection transistor) on the first semiconductor chip 102.

[0035] The third pixel transistor 402 has a first terminal 408, a second terminal 410, and a control terminal 412. Terminal 408 is coupled to terminal 314 of the first pixel transistor 124 and terminal 318 of the first LOFIC 150. Terminal 410 is coupled to the first power supply voltage terminal 426. In some embodiments, the first power supply voltage terminal 426 is coupled to a first power supply voltage source (not shown).

[0036] The fourth pixel transistor 404 has a first terminal 414, a second terminal 416, and a control terminal 418. Terminal 414 is coupled to terminal 410 of the third pixel transistor 402 and to the first power supply voltage terminal 426. The control terminal 418 is coupled to terminal 308 of the transfer transistor 116.

[0037] The fifth pixel transistor 406 has a first terminal 420, a second terminal 422, and a control terminal 424. Terminal 420 is coupled to terminal 416 of the fourth pixel transistor 404. Terminal 422 is coupled to the first terminal 428 of the ASIC 401 through a bonding structure 430 at the interface between the first semiconductor chip 102 and the second semiconductor chip 104.

[0038] In some embodiments, the control terminal 310 of the transfer transistor 116, the control terminal 316 of the first pixel transistor 124, the control terminal 326 of the second pixel transistor 158, the control terminal 412 of the third pixel transistor 402, and the control terminal 424 of the fifth pixel transistor 406 are coupled to the control circuit (not shown) of the ASIC 401 and receive control signals from the control circuit.

[0039] In some embodiments, the first pixel transistor 124, the third pixel transistor 402, and the first LOFIC 150 may be referred to as a conversion gain circuit. In some embodiments, the first pixel transistor 124 is turned off (e.g., by the control circuit of ASIC 401), the second pixel transistor 158 is turned on, and the third pixel transistor 402 is turned on to reset the voltage across the first LOFIC 150 according to the voltage at the reference voltage terminal 330 and the voltage at the power supply voltage terminal 426. In some embodiments, a first conversion gain operation (e.g., high conversion gain operation) is performed by turning off the first pixel transistor 124 to isolate the first LOFIC 150 from terminal 308 of the transfer transistor 116 and control terminal 418 of the fourth pixel transistor 404. In some embodiments, a second conversion gain operation (e.g., low conversion gain operation) is performed by turning on the first pixel transistor 124 to couple the first LOFIC 150 to terminal 312 and control terminal 418.

[0040] Figure 5 shows cross-sectional views 500 of several embodiments of the integrated chip shown in Figure 4.

[0041] In some embodiments, the ASIC401 includes transistors (e.g., transistors 502, 504, 506) provided along the second semiconductor substrate 110. The transistors of the ASIC401 are interconnected by conductive interconnects (not shown) on the second semiconductor chip 104. The transistors of the ASIC401 are coupled to conductive interconnects on the first semiconductor chip 102 through conductive interconnects (e.g., contacts, conductive wires, conductive vias, etc.) on the second semiconductor chip 104, bonding pads (e.g., 532) and bonding contacts (e.g., 534) on the second semiconductor chip 104, and bonding pads (e.g., 530) and bonding contacts (e.g., 528) on the first semiconductor chip 102.

[0042] The third pixel transistor 402 (e.g., a reset transistor) includes a first source / drain 508 (e.g., corresponding to terminal 408), a second source / drain 510 (e.g., corresponding to terminal 410), and a gate 512 between the first source / drain 508 and the second source / drain 510 (e.g., corresponding to control terminal 412). The source / drain 508 is coupled to the source / drain 128. In some embodiments, the source / drain 508 and the source / drain 128 are identical. In some other embodiments, the source / drain 508 and the source / drain 128 are separate and coupled together via a conductive interconnect on the first semiconductor chip 102.

[0043] The fourth pixel transistor 404 (e.g., a source follower transistor) includes a first source / drain 514 (e.g., corresponding to terminal 414), a second source / drain 516 (e.g., corresponding to terminal 416), and a gate 518 between the first source / drain 514 and the second source / drain 516 (e.g., corresponding to control terminal 418). The source / drain 514 is coupled to the source / drain 510. In some embodiments, the source / drain 514 and source / drain 510 are identical. In some other embodiments, the source / drain 514 and source / drain 510 are separate and coupled together via a conductive interconnect on the first semiconductor chip 102. The gate 518 is coupled to the source / drain 120 via a conductive interconnect (not marked) on the first semiconductor chip 102. The source / drain 514 is coupled to a first power supply voltage terminal (e.g., 426 in Figure 4) via a conductive interconnect.

[0044] The fifth pixel transistor 406 (e.g., a row selection transistor) includes a first source / drain 520 (e.g., corresponding to terminal 420), a second source / drain 522 (e.g., corresponding to terminal 422), and a gate 524 between the first source / drain 520 and the second source / drain 522 (e.g., corresponding to control terminal 424). The source / drain 520 is coupled to the source / drain 516. In some embodiments, the source / drain 520 and the source / drain 516 are identical. In some other embodiments, the source / drain 520 and the source / drain 516 are separate and coupled together via a conductive interconnect on the first semiconductor chip 102. The source / drain 522 is coupled to the ASIC 401 through a conductive interconnect 526 on the first semiconductor chip 102, a bonding pad 530 and bonding contact 528 on the first semiconductor chip 102 (corresponding to, for example, a bonding structure 430), a bonding pad 532 and bonding contact 534 on the second semiconductor chip 104 (corresponding to, for example, a bonding structure 430), and a conductive interconnect 536 on the second semiconductor chip 104 (for example, the source / drain 522 is coupled to the source / drain of transistor 502).

[0045] In some embodiments, the gate 122 of the transfer transistor 116, the gate 130 of the first pixel transistor 124, the gate 164 of the second pixel transistor 158, the gate 512 of the third pixel transistor 402, and the gate 524 of the fifth pixel transistor 406 are coupled to the control circuit (not shown) of the ASIC 401 through conductive interconnects (not shown) on the first semiconductor chip 102 and the second semiconductor chip 104, and through bonding pads (not shown) and bonding contacts (not shown) on the first semiconductor chip 102 and the second semiconductor chip 104.

[0046] In some embodiments, the source / drain is a doped region of a semiconductor substrate. In some other embodiments, the source / drain may be an epitaxial semiconductor layer or another suitable source / drain structure. Depending on the context, the source / drain region may refer to the source or the drain individually or collectively.

[0047] Figure 6 shows circuit diagrams 600 of several embodiments of the integrated chip shown in Figure 4, in which the photodetector 114 and the transfer transistor 116 are located on a third semiconductor chip 602 bonded to the first semiconductor chip 102.

[0048] The terminal 308 of the transfer transistor 116 is coupled to the terminal 312 of the first pixel transistor 124 and the control terminal 418 of the fourth pixel transistor 404 through a bonding structure 604 at the interface between the first semiconductor chip 102 and the third semiconductor chip 602.

[0049] Figure 7 shows a cross-sectional view 700 of several embodiments of the integrated chip shown in Figure 6. Figure 8 shows a cross-sectional view 800 of several other embodiments of the integrated chip shown in Figure 6.

[0050] Referring to Figures 7 and 8, the third semiconductor chip 602 includes a third semiconductor substrate 702 and a third dielectric structure 704. The photodetector 114 and the transfer transistor 116 are provided along the third semiconductor substrate 702. For example, the photodiode region 118 is in the third semiconductor substrate 702, the source / drain 119 is in the third semiconductor substrate 702, the source / drain 120 is in the third semiconductor substrate 702, and the gate 122 is provided along the third semiconductor substrate 702 between the source / drain 119 and the source / drain 120. Conductive interconnects 710, bonding contacts 712, and bonding pads 714 are on the third semiconductor chip 602. The back surface dielectric layer 706 is on the first semiconductor chip 102 along the back surface of the first semiconductor substrate 108. The back surface bonding pad 716 is in the back surface dielectric layer 706. The through-substrate via (TSV) 708 extends through the first semiconductor substrate 108 from the conductive interconnect of the dielectric structure 132 to the back bonding pad 716 of the back dielectric layer 706.

[0051] By placing the photodetector 114 and the transfer transistor 116 on a different chip from the pixel transistors 124, 402, 404, and 406, the size of the photodetector 114 can be more easily increased, and / or the pixel pitch can be more easily reduced.

[0052] In some embodiments (for example, as shown in Figure 7), the first semiconductor chip 102 and the third semiconductor chip 602 are bonded in a "front-to-front" configuration, and the first semiconductor chip 102 and the second semiconductor chip 104 are bonded in a "back-to-front" configuration. The third semiconductor chip 602 is bonded to the first semiconductor chip 102 along the bonding pad 718 on the first semiconductor chip 102 and the bonding pad 714 on the third semiconductor chip 602. The first semiconductor chip 102 is bonded to the second semiconductor chip 104 along the back bonding pad 716 of the first semiconductor chip 102 and along the bonding pad 720 of the second semiconductor chip 104. The source / drain 120 is coupled to the source / drain 126 through the interconnect 710 on the third semiconductor chip 602, the bonding pad 714 and bonding contact 712 on the third semiconductor chip 602, the bonding pad 718 and bonding contact 722 on the first semiconductor chip 102, and the conductive interconnect 728 on the first semiconductor chip 102 (for example, as shown by conductive interconnect 728 and connection 724). The second electrode layer 156 of the first LOFIC 150 is coupled to the source / drain 160 of the pixel transistor 158 through the conductive interconnect 730 on the first semiconductor chip 102, the TSV 708 on the first semiconductor chip 102, the bonding pad 716 on the first semiconductor chip 102, the bonding pad 720 and bonding contact 726 on the second semiconductor chip 104, and the conductive interconnect 732 on the second semiconductor chip 104. The source / drain 522 of the pixel transistor 406 is coupled to the ASIC 401 through a conductive interconnect 526 on the first semiconductor chip 102, a TSV (not shown) on the first semiconductor chip 102, a back surface bonding pad (not shown) on the first semiconductor chip 102, a bonding pad (not shown) and bonding contact (not shown) on the second semiconductor chip 104, and a conductive interconnect on the second semiconductor chip 104.

[0053] In some other embodiments (for example, as shown in Figure 8), the first semiconductor chip 102 and the third semiconductor chip 602 are bonded in a "back-to-front" configuration, and the first semiconductor chip 102 and the second semiconductor chip 104 are bonded in a "front-to-front" configuration. The third semiconductor chip 602 is bonded to the first semiconductor chip 102 along the back bonding pad 716 of the first semiconductor chip 102 and the bonding pad 714 on the third semiconductor chip 602. The first semiconductor chip 102 is bonded to the second semiconductor chip 104 along the bonding pad 148 of the first semiconductor chip 102 and the bonding pad 176 of the second semiconductor chip 104. The source / drain 120 is coupled to the source / drain 126 through the interconnect 710 on the third semiconductor chip 602, the bonding pad 714 and bonding contact 712 on the third semiconductor chip 602, the bonding pad 716 on the first semiconductor chip 102, the TSV 708 on the first semiconductor chip 102, and the conductive interconnect 728 on the first semiconductor chip 102.

[0054] Figure 9 shows the circuit diagrams 900 of several embodiments of the integrated chip of Figure 6, in which the second pixel transistor 158 is located on the third semiconductor chip 602.

[0055] The terminal 322 of the second pixel transistor 158 is coupled to the terminal 320 of the first LOFIC 150 through a bonding structure 902 at the interface between the first semiconductor chip 102 and the third semiconductor chip 602.

[0056] Figure 10 shows cross-sectional views 1000 of several embodiments of the integrated chip shown in Figure 9.

[0057] The second pixel transistor 158 is provided along the semiconductor substrate 702 of the third semiconductor chip 602. The second electrode layer 156 of the first LOFIC 150 is coupled to the source / drain 160 of the pixel transistor 158 through the conductive interconnect 1002 on the first semiconductor chip 102, the bonding pad 1004 and bonding contact 1006 on the first semiconductor chip 102, the bonding pad 1008 and bonding contact 1010 on the third semiconductor chip 602, and the conductive interconnect 1012 on the third semiconductor chip 602.

[0058] The source / drain 522 of the pixel transistor 406 is coupled to the ASIC 401 through a conductive interconnect 526 on the first semiconductor chip 102, a TSV 1014 on the first semiconductor chip 102, a back surface bonding pad 1016 on the first semiconductor chip 102, a bonding pad 1018 and bonding contact 1020 on the second semiconductor chip 104, and a conductive interconnect 1022 on the second semiconductor chip 104.

[0059] Figure 11 shows circuit diagrams 1100 of several embodiments of the integrated chip of Figure 4, in which the sixth pixel transistor 1102 and the second LOFIC 1104 are located on the first semiconductor chip 102 and are coupled between the transfer transistor 116 and the first pixel transistor 124.

[0060] The sixth pixel transistor 1102 has a first terminal 1106 coupled to terminal 308 of the transfer transistor 116. The sixth pixel transistor 1102 has a second terminal 1108 coupled to terminal 312 of the first pixel transistor 124. The sixth pixel transistor 1102 has a control terminal 1110. In some embodiments, the control terminal 1110 is coupled to a control circuit (not shown) in the ASIC 401 and receives control signals from the control circuit.

[0061] The second LOFIC 1104 has a first terminal 1112 coupled to terminal 1108 of pixel transistor 1102 and terminal 312 of pixel transistor 124. The second LOFIC has a second terminal 1114 coupled to a second reference voltage terminal 1116. In some embodiments, the second reference voltage terminal 1116 is coupled to ground. In some other embodiments, the second reference voltage terminal 1116 is coupled to a second reference voltage source (not shown).

[0062] In some embodiments, the first pixel transistor 124, the third pixel transistor 402, the first LOFIC 150, the sixth pixel transistor 1102, and the second LOFIC 1104 may be referred to as a conversion gain circuit. In some embodiments, the sixth pixel transistor 1102 is turned off, the first pixel transistor 124 is turned on, the second pixel transistor 158 is turned on, and the third pixel transistor 402 is turned on to reset the voltage across the first LOFIC 150 according to the voltage at the reference voltage terminal 330 and the voltage at the power supply voltage terminal 426, and to reset the voltage across the second LOFIC 1104 according to the voltage at the reference voltage terminal 1116 and the power supply voltage terminal 426. In some embodiments, a first conversion gain operation (e.g., high conversion gain operation) is performed by turning off the sixth pixel transistor 1102 to isolate the first LOFIC 150 and the second LOFIC 1104 from the terminal 308 of the transfer transistor 116 and the control terminal 418 of the fourth pixel transistor 404. In some embodiments, a second conversion gain operation (e.g., a medium conversion gain operation) is performed by turning on the sixth pixel transistor 1102 to couple the second LOFIC 1104 to terminal 308 and the control terminal 418, and by turning off the first pixel transistor 124 to isolate the first LOFIC 150 from terminal 308 and the control terminal 418. In some embodiments, a third conversion gain operation (e.g., a low conversion gain operation) is performed by turning on both the sixth pixel transistor 1102 and the first pixel transistor 124 to couple both the first LOFIC 150 and the second LOFIC to terminal 308 and the control terminal 418.

[0063] Figure 12 shows cross-sectional views 1200 of several embodiments of the integrated chip of Figure 11 (for example, the integrated chip of Figure 5 in which the sixth pixel transistor 1102 and the second LOFIC 1104 are located on the first semiconductor chip 102 and coupled between the transfer transistor 116 and the first pixel transistor 124).

[0064] The sixth pixel transistor 1102 includes a first source / drain 1202 (corresponding to terminal 1106) along the first semiconductor substrate 108, a second source / drain 1204 (e.g., corresponding to terminal 1108) along the first semiconductor substrate 108, and a gate 1206 (e.g., corresponding to control terminal 1110) located between the source / drain 1202 and source / drain 1204 along the first semiconductor substrate 108. In some embodiments, source / drain 120 and source / drain 1202 are identical. In some other embodiments, source / drain 120 and source / drain 1202 are separate and coupled together by a conductive interconnect on the first semiconductor chip 102. In some embodiments, source / drain 1204 and source / drain 126 are identical. In some other embodiments, source / drain 1204 and source / drain 126 are separate and coupled together by a conductive interconnect on the first semiconductor chip 102.

[0065] The second LOFIC 1104 includes a first electrode layer 1208, a second electrode layer 1212, and a dielectric layer 1210 between the first electrode layer 1208 and the second electrode layer 1212. The first electrode layer 1208 is coupled to source / drain 1204 and source / drain 126 by a conductive interconnect 1214 on the first semiconductor chip 102. The second electrode layer 1212 is coupled to a reference voltage terminal (e.g., 1116 in Figure 11) by a conductive interconnect 1216 on the first semiconductor chip 102.

[0066] Figure 13 shows circuit diagrams 1300 of several embodiments of the integrated chip of Figure 6, in which the sixth pixel transistor 1102 and the second LOFIC 1104 are located on the first semiconductor chip 102 and coupled between the transfer transistor 116 and the first pixel transistor 124.

[0067] Figure 14 shows cross-sectional views 1400 of several embodiments of the integrated chip of Figure 13 (for example, the integrated chip of Figure 7 in which the sixth pixel transistor 1102 and the second LOFIC 1104 are located on the first semiconductor chip 102 and coupled between the transfer transistor 116 and the first pixel transistor 124).

[0068] Figure 15 shows cross-sectional views 1500 of several other embodiments of the integrated chip of Figure 13 (for example, the integrated chip of Figure 8, in which the sixth pixel transistor 1102 and the second LOFIC 1104 are located on the first semiconductor chip 102 and coupled between the transfer transistor 116 and the first pixel transistor 124).

[0069] Figure 16 shows circuit diagrams 1600 of several embodiments of the integrated chip of Figure 9, in which the sixth pixel transistor 1102 and the second LOFIC 1104 are located on the first semiconductor chip 102 and coupled between the transfer transistor 116 and the first pixel transistor 124.

[0070] Figure 17 shows cross-sectional views 1700 of several embodiments of the integrated chip of Figure 16 (for example, the integrated chip of Figure 10 in which the sixth pixel transistor 1102 and the second LOFIC 1104 are located on the first semiconductor chip 102 and coupled between the transfer transistor 116 and the first pixel transistor 124).

[0071] Figures 18 to 20 show cross-sectional views 1800 to 2000 of various embodiments of the first LOFIC 150.

[0072] In some embodiments (for example, as shown in Figure 18), the first LOFIC 150 is a metal-insulator-metal (MIM) capacitor in which a first electrode layer 152, a dielectric layer 154, and a second electrode layer 156 are stacked vertically on top of each other. In some embodiments, the conductive wire 144 is the "top" position wiring of the first semiconductor chip 102, and the conductive via 140 is the "top" position via. For example, the bonding contact 146 is in direct contact with the conductive wire 144, the conductive wire 144 is in direct contact with the conductive via 140, and the conductive via 140 is in direct contact with the second electrode layer 156 of the first LOFIC 150.

[0073] In some embodiments (for example, as shown in Figure 19), the first LOFIC 150 is a metal-oxide-metal (MOM) capacitor in which the second electrode layer 156 is spaced laterally apart from the first electrode layer 152, and the dielectric layer 154 is positioned laterally between the first electrode layer 152 and the second electrode layer 156.

[0074] In some embodiments (for example, as shown in Figure 20), the conductive wire 144 and conductive via 140 are below the top wiring and top via level. For example, conductive via 140 is in direct contact with the second electrode 156, conductive wire 144 is in direct contact with conductive via 140, and one or more additional conductive interconnects (e.g., conductive via 2002 and conductive wire 2004) are electrically and physically between conductive wire 144 and bonding contact 146. The first LOFIC 150 is represented as an MIM capacitor in Figure 20, but it should be understood that in some embodiments, the first LOFIC 150 in Figure 20 may be an MOM capacitor instead.

[0075] Figures 21 to 24 show cross-sectional views 2100 to 2400 of various embodiments of the first LOFIC 150 and the second LOFIC 1104.

[0076] In some embodiments (for example, as shown in Figure 21), the second LOFIC 1104 is a MIM capacitor in which the first electrode layer 1208, the dielectric layer 1210, and the second electrode layer 1212 are stacked vertically on top of each other. In some embodiments, the second LOFIC 1104 is at a different height from the first LOFIC 150 (for example, from the first semiconductor substrate 108). For example, in some embodiments, the first LOFIC 150 is on top of the second LOFIC 1104.

[0077] In some embodiments (for example, as shown in Figure 22), the second LOFIC 1104 is a MOM capacitor in which the second electrode layer 1212 is laterally spaced apart from the first electrode layer 1208, and the dielectric layer 1210 is laterally located between the first electrode layer 1208 and the second electrode layer 1212.

[0078] In some embodiments (for example, as shown in Figure 23), the second LOFIC is a metal-oxide-semiconductor (MOS) capacitor in which the source / drain 1204 and / or source / drain 126 form the first electrode layer 1208, the dielectric layer 1210 is on the source / drain 1204 and / or source / drain 126, and the second electrode layer 1212 is on the dielectric layer 1210. In some embodiments, the second electrode layer 1212 contains a metal. In some other embodiments, the second electrode layer contains polysilicon or other suitable material.

[0079] In some embodiments (for example, as shown in Figure 24), the first electrode layer 1208 is located on the source / drain 1204 and / or source / drain 126, the dielectric layer 1210 is located above the first electrode layer 1208, and the second electrode layer 1212 is located above the dielectric layer 1210. In some embodiments, the first electrode layer 1208 and the second electrode layer 1212 include polysilicon or other suitable material.

[0080] In Figures 21 to 24, the first LOFIC150 is represented as an MIM capacitor, but please understand that in some embodiments, the first LOFIC150 in Figures 21 to 24 may be an MOM capacitor instead.

[0081] Figures 25 to 29 show cross-sectional views 2500 to 2900 of several embodiments of a method for forming an integrated chip that includes a first LOFIC 150 on a first semiconductor chip 102 and a pixel transistor 158 on another chip bonded to the first semiconductor chip 102.

[0082] As shown in the cross-sectional view 2500 of Figure 25, the photodetector 114, the transfer transistor 116, and the pixel transistors 124, 402, 404, and 406 are formed along the first semiconductor substrate 108 of the first semiconductor chip 102. In some embodiments, the pixel transistor 1102 is also formed along the first semiconductor substrate 108.

[0083] As shown in the cross-sectional view 2600 of Figure 26, the dielectric structure 132 and the conductive interconnect are formed on top of the first semiconductor substrate 108 and on the first semiconductor chip 102. In addition, the first LOFIC 150 is formed on top of the first semiconductor substrate 108 and on the first semiconductor chip 102. In some embodiments, the second LOFIC 1104 is also formed on top of the first semiconductor substrate 108 and on the first semiconductor chip 102.

[0084] As shown in the cross-sectional view 2700 of Figure 27, the pixel transistor 158 and ASIC transistors (for example, transistors 502, 504, and 506) are formed along the second semiconductor substrate 110 of the second semiconductor chip 104.

[0085] As shown in the cross-sectional view 2800 of Figure 28, the dielectric structure 188 and the conductive interconnect are formed on top of the second semiconductor substrate 110 and on the second semiconductor chip 104. In addition, the remaining portion of the ASIC 401 is formed on the second semiconductor chip 104.

[0086] As shown in the cross-sectional view 2900 of Figure 29, the first semiconductor chip 102 and the second semiconductor chip 104 are bonded together along the dielectric structures 132 and 188 of the first and second semiconductor chips, and along the bonding pads (e.g., 148, 176, and 530, 532) of the first and second semiconductor chips. For example, dielectric structure 132 and dielectric structure 188 are bonded together. In addition, the bonding pad on the first semiconductor chip 102 and the bonding pad on the second semiconductor chip 104 are bonded together. In some embodiments, bonding includes a direct bonding process, a fusion bonding process, or other suitable process.

[0087] Figures 30 to 35 show cross-sectional views 3000 to 3500 of several other embodiments of a method for forming an integrated chip that includes a first LOFIC 150 on a first semiconductor chip 102 and a pixel transistor 158 on another chip bonded to the first semiconductor chip 102.

[0088] As shown in the cross-sectional view 3000 of Figure 30, the photodetector 114 and the transfer transistor 116 are formed along the third semiconductor substrate 702 of the third semiconductor chip 602. In addition, the dielectric structure 704, the conductive interconnect 710, the bonding contact 712, and the bonding pad 714 are formed above the third semiconductor substrate 702 and on the third semiconductor chip 602.

[0089] As shown in the cross-sectional view 3100 of Figure 31, pixel transistors 124, 402, 404, and 406 are formed along the first semiconductor substrate 108 of the first semiconductor chip 102. In some embodiments, pixel transistor 1102 is formed along the first semiconductor substrate 108. Furthermore, dielectric structures 132 and conductive interconnects are formed on the first semiconductor substrate 108 and the first semiconductor chip 102. Furthermore, a first LOFIC 150 is formed on the first semiconductor substrate 108 and the first semiconductor chip 102. In some embodiments, a second LOFIC 1104 is also formed on the first semiconductor substrate 108 and the first semiconductor chip 102.

[0090] As shown in the cross-sectional view 3200 of Figure 32, the first semiconductor chip 102 and the third semiconductor chip 602 are bonded together along dielectric structures 132, 704 and along bonding pads 718, 714. In some embodiments, bonding includes a direct bonding process, a fusion bonding process, or other suitable process. In addition, in some embodiments, the first semiconductor substrate 108 is thinned from the back surface. In some embodiments, thinning includes an etching process, a chemical mechanical planarization (CMP) process, or other suitable process.

[0091] As shown in the cross-sectional view 3300 of Figure 33, the back surface dielectric layer 706 is formed on the first semiconductor chip 102 along the back surface of the first semiconductor substrate 108. Furthermore, the TSV 708 is formed on the first semiconductor chip 102 and extends through the first semiconductor substrate 108. Furthermore, the bonding pad 716 is formed on the first semiconductor chip 102 along the back surface dielectric layer 706.

[0092] As shown in the cross-sectional view 3400 of Figure 34, the pixel transistor 158 and the ASIC 401 are formed along the second semiconductor substrate 110 of the second semiconductor chip 104. In addition, the dielectric structure 188, the conductive interconnect 732, the bonding contact 726, and the bonding pad 720 are formed above the second semiconductor substrate 110 and on the second semiconductor chip 104.

[0093] As shown in the cross-sectional view 3500 of Figure 35, the first semiconductor chip 102 and the second semiconductor chip 104 are bonded together along dielectric structures 132, 188 and along bonding pads 716, 720. In some embodiments, bonding includes a direct bonding process, a fusion bonding process, or other suitable process.

[0094] Figures 36 to 40 show cross-sectional views 3600 to 4000 of several other embodiments of a method for forming an integrated chip including a first LOFIC 150 on a first semiconductor chip 102 and a pixel transistor 158 on another chip bonded to the first semiconductor chip 102. Although Figures 25 to 40 are described in relation to the method, it should be understood that the structures disclosed in Figures 25 to 40 are not limited to such a method and may instead exist independently as structures separate from the method.

[0095] As shown in the cross-sectional view 3600 of Figure 36, the photodetector 114 and the transfer transistor 116 are formed along the third semiconductor substrate 702 of the third semiconductor chip 602. Furthermore, the pixel transistor 158 is formed on the third semiconductor chip 602 along the third semiconductor substrate 702. In addition, the dielectric structure 704, the conductive interconnects 710 and 1012, the bonding contacts 712 and 1010, and the bonding pads 714 and 1008 are formed above the third semiconductor substrate 702 and on the third semiconductor chip 602.

[0096] As shown in the cross-sectional view 3700 of Figure 37, pixel transistors 124, 402, 404, and 406 are formed along the first semiconductor substrate 108 of the first semiconductor chip 102. In some embodiments, pixel transistors 1102 are also formed along the first semiconductor substrate 108. Furthermore, dielectric structures 132, conductive interconnects, bonding contacts 722, 1006, and bonding pads 718, 1004 are formed above the first semiconductor substrate 108 and on the first semiconductor chip 102. Furthermore, a first LOFIC 150 is formed above the first semiconductor substrate 108 and on the first semiconductor chip 102. In some embodiments, a second LOFIC 1104 is also formed above the first semiconductor substrate 108 and on the first semiconductor chip 102.

[0097] As shown in the cross-sectional view 3800 of Figure 38, the first semiconductor chip 102 and the third semiconductor chip 602 are bonded together along dielectric structures 132, 704 and along bonding pads 718, 714, 1004, 1008. In some embodiments, bonding includes a direct bonding process, a fusion bonding process, or other suitable process. In some embodiments, the first semiconductor substrate 108 is thinned from the back surface. In some embodiments, thinning includes an etching process, a CMP process, or other suitable process. A back surface dielectric layer 706 is formed on the first semiconductor chip 102 along the back surface of the first semiconductor substrate 108. A TSV 1014 is stretched through the first semiconductor substrate 108 and formed on the first semiconductor chip 102. A bonding pad 1016 is formed on the first semiconductor chip 102 along the back surface dielectric layer 706.

[0098] As shown in the cross-sectional view 3900 of Figure 39, the ASIC 401 is formed along the second semiconductor substrate 110 of the second semiconductor chip 104. In addition, a dielectric structure 188, a conductive interconnect 1022, a bonding contact 1020, and a bonding pad 1018 are formed above the second semiconductor substrate 110 and on the second semiconductor chip 104.

[0099] As shown in the cross-sectional view 4000 of Figure 40, the first semiconductor chip 102 and the second semiconductor chip 104 are bonded together along dielectric structures 132 and 188, and along bonding pads 1016 and 1018. In some embodiments, bonding includes a direct bonding process, a fusion bonding process, or other suitable process.

[0100] Figure 41 shows a flowchart of several embodiments of Method 4100 for forming an integrated chip including a first capacitor on a first semiconductor chip and a pixel transistor on another chip bonded to the first semiconductor chip. Method 4100 is described below as a series of operations or events, but it should be understood that the order in which such operations or events are described should not be interpreted as restrictive. For example, some operations may occur in a different order and / or simultaneously with other operations or events not described herein. Furthermore, not all operations described may be required to implement one or more aspects or embodiments of this specification. Moreover, one or more of the operations illustrated herein may be performed in one or more other operations and / or stages.

[0101] Block 4102 forms a photodetector and a transfer transistor coupled to the photodetector. Figure 25 shows a cross-sectional view 2500 of several embodiments corresponding to block 4102. Figure 30 shows a cross-sectional view 3000 of several other embodiments corresponding to block 4102. Figure 36 shows a cross-sectional view 3600 of several other embodiments corresponding to block 4102.

[0102] In block 4104, a first pixel transistor is formed on the first semiconductor chip and coupled to a transfer transistor. Figure 25 shows a cross-sectional view 2500 of several embodiments corresponding to block 4104. Figure 31 shows a cross-sectional view 3100 of several other embodiments corresponding to block 4104. Figure 37 shows a cross-sectional view 3700 of several other embodiments corresponding to block 4104.

[0103] In block 4106, a first LOFIC is formed on the first semiconductor chip and coupled to the first pixel transistor. Figure 26 shows a cross-sectional view 2600 of several embodiments corresponding to block 4106. Figure 31 shows a cross-sectional view 3100 of several other embodiments corresponding to block 4106. Figure 37 shows a cross-sectional view 3700 of several other embodiments corresponding to block 4106.

[0104] In block 4108, a second pixel transistor is formed on the second semiconductor chip. Figure 27 shows a cross-sectional view 2700 of several embodiments corresponding to block 4108. Figure 34 shows a cross-sectional view 3400 of several other embodiments corresponding to block 4108. Figure 36 shows a cross-sectional view 3600 of several other embodiments corresponding to block 4108.

[0105] In block 4110, the first semiconductor chip and the second semiconductor chip are joined so that the second pixel transistor is coupled to the first capacitor. Figure 29 shows a cross-sectional view 2900 of several embodiments corresponding to block 4110. Figure 35 shows a cross-sectional view 3500 of several other embodiments corresponding to block 4110. Figure 38 shows a cross-sectional view 3800 of several other embodiments corresponding to block 4110.

[0106] Thus, the present invention relates to an integrated chip and a method for forming an integrated chip, the integrated chip comprising a first LOFIC on a first semiconductor chip and pixel transistors on another chip coupled to the first LOFIC and bonded to the first semiconductor chip.

[0107] Accordingly, in some embodiments, the present invention relates to an integrated chip comprising a photodetector, a transfer transistor, a first pixel transistor, a first capacitor, a second pixel transistor, and a bonding structure. The photodetector has a first terminal. The transfer transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the transfer transistor is coupled to the first terminal of the photodetector. The first pixel transistor is located on a first semiconductor chip. The first pixel transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the first pixel transistor is coupled to the second terminal of the transfer transistor. The first capacitor is located on a first semiconductor chip. The first capacitor has a first terminal and a second terminal. The first terminal of the first capacitor is coupled to the second terminal of the first pixel transistor. The second pixel transistor is located on a second semiconductor chip bonded to the first semiconductor chip. The second pixel transistor has a first terminal, a second terminal, and a control terminal. The second terminal of the second pixel transistor is coupled to a first reference voltage terminal. The bonding structure is located at the interface where the first semiconductor chip and the second semiconductor chip are joined. The bonding structure connects the second terminal of the first capacitor to the first terminal of the second pixel transistor. In some embodiments, the photodetector and transfer transistor are on the first semiconductor chip, and the integrated chip further includes an application-specific integrated circuit on the second semiconductor chip. The control terminals of the transfer transistor, the control terminals of the first pixel transistor, and the control terminals of the second pixel transistor are coupled to the application-specific integrated circuit. In some embodiments, the photodetector and transfer transistor are on the second semiconductor chip, and the integrated chip further includes an application-specific integrated circuit on a third semiconductor chip bonded to the first semiconductor chip. The control terminals of the transfer transistor, the control terminals of the first pixel transistor, and the control terminals of the second pixel transistor are coupled to the application-specific integrated circuit. In some embodiments, the photodetector and transfer transistor are on a third semiconductor chip bonded to the first semiconductor chip, and the integrated chip further includes an application-specific integrated circuit on the second semiconductor chip. The control terminals of the transfer transistor, the control terminals of the first pixel transistor, and the control terminals of the second pixel transistor are coupled to the application-specific integrated circuit.In some embodiments, the integrated chip further includes a third pixel transistor, a fourth pixel transistor, a fifth pixel transistor, and an application-specific integrated circuit. The third pixel transistor is located on a first semiconductor chip. The third pixel transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the third pixel transistor is coupled to the second terminal of the first pixel transistor and to the first terminal of the first capacitor. The second terminal of the third pixel transistor is coupled to a first power supply voltage terminal. The fourth pixel transistor is located on a first semiconductor chip. The fourth pixel transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the fourth pixel transistor is coupled to the second terminal of the third pixel transistor and to the first power supply voltage terminal. The control terminal of the fourth pixel transistor is coupled to the second terminal of the transfer transistor. The fifth pixel transistor is located on a first semiconductor chip. The fifth pixel transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the fifth pixel transistor is coupled to the second terminal of the fourth pixel transistor. The application-specific integrated circuit is coupled to the second terminal of the fifth pixel transistor. In some embodiments, the integrated chip further includes a sixth pixel transistor and a second capacitor. The sixth pixel transistor is located on the first semiconductor chip and is coupled between the transfer transistor and the first pixel transistor. The sixth pixel transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the sixth pixel transistor is coupled to the second terminal of the transfer transistor. The second terminal of the sixth pixel transistor is coupled to the first terminal of the first pixel transistor. The second capacitor is located on the first semiconductor chip. The second capacitor has a first terminal and a second terminal. The first terminal of the second capacitor is coupled to the second terminal of the sixth pixel transistor and the first terminal of the first pixel transistor. The second terminal of the second capacitor is coupled to the second reference voltage terminal.

[0108] In other embodiments, the present invention relates to an integrated chip comprising a photodetector, a transfer transistor, a first pixel transistor, a first lateral overflow storage capacitor (LOFIC), a first bonding pad, a second bonding pad, and a second pixel transistor. The photodetector and transfer transistor are located on a first semiconductor chip and arranged along a first semiconductor substrate, on a second semiconductor chip and arranged along a second semiconductor substrate, or on a third semiconductor chip and arranged along a third semiconductor substrate. The transfer transistor comprises a first source / drain, a second source / drain, and a gate. The first source / drain of the transfer transistor is coupled to the photodetector. The first pixel transistor is located on a first semiconductor chip and arranged along a first semiconductor substrate. The first pixel transistor comprises a first source / drain, a second source / drain, and a gate. The first source / drain of the first pixel transistor is coupled to the second source / drain of the transfer transistor. The first LOFIC is located on the first semiconductor chip. The first LOFIC includes a first electrode, a second electrode, and a dielectric between the first and second electrodes. The first electrode is coupled to the second source / drain of the first pixel transistor via a first conductive interconnect on the first semiconductor chip. The first bonding pad is located on the first semiconductor chip and is coupled to the second electrode of the first LOFIC via a second conductive interconnect on the first semiconductor chip. The second bonding pad is located on the second semiconductor chip and is bonded to the first bonding pad. The second pixel transistor is located on the second semiconductor chip and is arranged along the second semiconductor substrate. The second pixel transistor includes a first source / drain, a second source / drain, and a gate. The second source / drain of the second pixel transistor is coupled to the first reference voltage terminal via a fourth conductive interconnect on the second semiconductor chip. The first source / drain of the second pixel transistor is coupled to the second bonding pad via a third conductive interconnect on the second semiconductor chip. In some embodiments, the integrated chip further includes a third pixel transistor, a fourth pixel transistor, a fifth pixel transistor, and an application-specific integrated circuit.The third pixel transistor is located on the first semiconductor chip and is arranged along the first semiconductor substrate. The third pixel transistor includes a first source / drain, a second source / drain, and a gate. The first source / drain of the third pixel transistor is coupled to the second source / drain of the first pixel transistor and the first electrode of the first LOFIC. The second source / drain of the third pixel transistor is coupled to the power supply voltage terminal. The fourth pixel transistor is located on the first semiconductor chip and is arranged along the first semiconductor substrate. The fourth pixel transistor includes a first source / drain, a second source / drain, and a gate. The first source / drain of the fourth pixel transistor is coupled to the second source / drain of the third pixel transistor and the power supply voltage terminal. The gate of the fourth pixel transistor is coupled to the second source / drain of the transfer transistor. The fifth pixel transistor is located on the first semiconductor chip and is arranged along the first semiconductor substrate. The fifth pixel transistor includes a first source / drain, a second source / drain, and a gate. The first source / drain of the fifth pixel transistor is coupled to the second source / drain of the fourth pixel transistor. The application-specific integrated circuit is coupled to the second source / drain of the fifth pixel transistor. In some embodiments, the integrated chip further includes a sixth pixel transistor and a second LOFIC. The sixth pixel transistor is located on a first semiconductor chip and arranged along a first semiconductor substrate. The sixth pixel transistor includes a first source / drain, a second source / drain, and a gate. The first source / drain of the sixth pixel transistor is coupled to the second source / drain of the transfer transistor. The second source / drain of the sixth pixel transistor is coupled to the first source / drain of the first pixel transistor. The second LOFIC is located on the first semiconductor chip. The second LOFIC includes a first electrode, a second electrode, and a dielectric between the first and second electrodes. The first electrode of the second LOFIC is coupled to the second source / drain of the sixth pixel transistor and the first source / drain of the first pixel transistor via a fifth conductive interconnect on the first semiconductor chip. The second electrode of the second LOFIC is coupled to the second reference voltage terminal via a sixth conductive interconnect on the first semiconductor chip.In some embodiments, the gates of the transfer transistor, the gate of the first pixel transistor, the gate of the second pixel transistor, the gate of the third pixel transistor, the gate of the fifth pixel transistor, and the gate of the sixth pixel transistor are coupled to an application-specific integrated circuit. In some embodiments, the photodetector and transfer transistors are located on a first semiconductor chip and arranged along a first semiconductor substrate. The application-specific integrated circuit is located on a second semiconductor chip, and the integrated chip further includes a third bonding pad and a fourth bonding pad. The third bonding pad is located on the first semiconductor chip and is coupled to the second source / drain of the fifth pixel transistor via a seventh conductive interconnect on the first semiconductor chip. The fourth bonding pad is located on the second semiconductor chip and is coupled to the application-specific integrated circuit via an eighth conductive interconnect on the second semiconductor chip. The fourth bonding pad is bonded to the third bonding pad. In some embodiments, the photodetector and transfer transistors are located on a second semiconductor chip and arranged along a second semiconductor substrate. The application-specific integrated circuit is located on a third semiconductor chip, and the integrated chip further includes a third bonding pad, a fourth bonding pad, a fifth bonding pad, and a sixth bonding pad. The third bonding pad is located on a first semiconductor chip and is coupled to the second source / drain of the fifth pixel transistor via a seventh conductive interconnect on the first semiconductor chip. The fourth bonding pad is located on a third semiconductor chip and is coupled to the application-specific integrated circuit via an eighth conductive interconnect on the third semiconductor chip. The fourth bonding pad is bonded to the third bonding pad. The fifth bonding pad is located on a first semiconductor chip and is coupled to the first source / drain of the sixth pixel transistor via a ninth conductive interconnect on the first semiconductor chip. The sixth bonding pad is located on a second semiconductor chip and is coupled to the second source / drain of the transfer transistor via a tenth conductive interconnect on the second semiconductor chip. The sixth bonding pad is bonded to the fifth bonding pad.In some embodiments, the photodetector and transfer transistor are located on a third semiconductor chip and arranged along a third semiconductor substrate. The application-specific integrated circuit is located on a second semiconductor chip, and the integrated chip further includes a third bonding pad, a fourth bonding pad, a fifth bonding pad, and a sixth bonding pad. The third bonding pad is located on a first semiconductor chip and is coupled to the second source / drain of the fifth pixel transistor via a seventh conductive interconnect on the first semiconductor chip. The fourth bonding pad is located on a second semiconductor chip and is coupled to the application-specific integrated circuit via an eighth conductive interconnect on the second semiconductor chip. The fourth bonding pad is bonded to the third bonding pad. The fifth bonding pad is located on a first semiconductor chip and is coupled to the first source / drain of the sixth pixel transistor via a ninth conductive interconnect on the first semiconductor chip. The sixth bonding pad is located on a third semiconductor chip and is coupled to the second source / drain of the transfer transistor via a tenth conductive interconnect on the third semiconductor chip. The sixth bonding pad is bonded to and connected to the fifth bonding pad. In some embodiments, the second conductive interconnect is an upper conductive wiring on the first semiconductor chip, and the integrated chip further includes a first bonding contact and an upper conductive via. The first bonding contact is located on the first semiconductor chip and extends from the first bonding pad to the upper conductive wiring. The upper conductive via is located on the first semiconductor chip and extends from the second conductive interconnect to the second electrode of the first LOFIC.

[0109] In yet another embodiment, the present invention relates to a method for forming an integrated chip. The method includes forming a photodetector and a transfer transistor. The transfer transistor includes a first source / drain, a second source / drain, and a gate. The first source / drain of the transfer transistor is coupled to the photodetector. The method includes forming a first pixel transistor along a first semiconductor substrate of a first semiconductor chip. The first pixel transistor includes a first source / drain, a second source / drain, and a gate. The first source / drain of the first pixel transistor is coupled to the second source / drain of the transfer transistor. The method includes forming a first conductive interconnect on the first semiconductor chip and coupled to the second source / drain of the first pixel transistor. The method includes forming a first capacitor on the first semiconductor chip. The first capacitor includes a first electrode, a second electrode, and a dielectric between the first electrode and the second electrode. The first electrode is coupled to the first conductive interconnect. The method includes forming a second conductive interconnect on the first semiconductor chip and coupled to the second electrode of the first capacitor. The method includes forming a first bonding pad on a first semiconductor chip that is coupled to a second conductive interconnect. The method includes forming a second pixel transistor along a second semiconductor substrate of the second semiconductor chip. The second pixel transistor includes a first source / drain, a second source / drain, and a gate. The method includes forming a third conductive interconnect on the second semiconductor chip that is coupled to the first source / drain of the second pixel transistor. The method includes forming a second bonding pad on the second semiconductor chip and coupling it to the third conductive interconnect. The method includes bonding the first bonding pad to the second bonding pad. The second electrode of the first capacitor is coupled to the first source / drain of the second pixel transistor via the second conductive interconnect, the first bonding pad, the second bonding pad, and the third conductive interconnect. In some embodiments, the method further includes forming a third pixel transistor along a first semiconductor substrate of the first semiconductor chip.The third pixel transistor includes a first source / drain, a second source / drain, and a gate. The first source / drain of the third pixel transistor is coupled to the second source / drain of the first pixel transistor and to the first electrode of the first capacitor. The second source / drain of the third pixel transistor is coupled to the power supply voltage terminal. The method includes forming a fourth pixel transistor along a first semiconductor substrate of a first semiconductor chip. The fourth pixel transistor includes a first source / drain, a second source / drain, and a gate. The first source / drain of the fourth pixel transistor is coupled to the second source / drain of the third pixel transistor and to the power supply voltage terminal. The gate of the fourth pixel transistor is coupled to the second source / drain of the transfer transistor. The method includes forming a fifth pixel transistor along a first semiconductor substrate of a first semiconductor chip. The fifth pixel transistor includes a first source / drain, a second source / drain, and a gate. The first source / drain of the fifth pixel transistor is coupled to the second source / drain of the fourth pixel transistor. The method includes forming an application-specific integrated circuit coupled to a second source / drain of a fifth pixel transistor. In some embodiments, the photodetector and transfer transistor are formed along a first semiconductor substrate of a first semiconductor chip, and the application-specific integrated circuit is formed on a second semiconductor chip. In some embodiments, the photodetector and transfer transistor are formed along a second semiconductor substrate of a second semiconductor chip, and the application-specific integrated circuit is formed on a third semiconductor chip. In some embodiments, the photodetector and transfer transistor are formed along a third semiconductor substrate of a third semiconductor chip, and the application-specific integrated circuit is formed on a second semiconductor chip. In some embodiments, the method includes forming a third pixel transistor along a first semiconductor substrate of a first semiconductor chip. The third pixel transistor includes a first source / drain, a second source / drain, and a gate. The first source / drain of the third pixel transistor is coupled to the second source / drain of the transfer transistor. The second source / drain of the third pixel transistor is coupled to the first source / drain of the first pixel transistor.The method includes forming a fourth conductive interconnect on a first semiconductor chip, which is coupled to the second source / drain of a third pixel transistor and the first source / drain of a first pixel transistor. The method also includes forming a second capacitor on the first semiconductor chip. The second capacitor includes a first electrode, a second electrode, and a dielectric between the first and second electrodes. The first electrode of the first capacitor is coupled to the fourth conductive interconnect.

[0110] The above outlines some features of embodiments so that those skilled in the art may better understand aspects of the present invention. Those skilled in the art should understand that the present invention can be readily used as a basis for designing or modifying other processes and structures to perform the same objectives and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent configurations do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention. [Industrial applicability]

[0111] This invention relates to reducing the difficulty of reducing the pixel pitch of an image sensor. [Explanation of Symbols]

[0112] 100: Cross-sectional view 102: First semiconductor chip 104: Second semiconductor chip 106, 112:Position 108: First Semiconductor Substrate 110: Second semiconductor substrate 114: Photodetector 116: Transfer transistor 118: Photodiode region 119, 120, 126, 128: Source / Drain 122, 130, 164: Gates 124: First pixel transistor 132, 188: Dielectric structure 136: Contact 138, 140, 172, 174, 184: Conductive vias 142, 144, 168, 170, 180, 182: Conductive wires 146, 178: Bonding contacts 148, 176: Bonding pads 150: 1st LOFIC 152:First electrode layer 154: Dielectric layer 156:Second electrode layer 158: Second Pixel Transistor 160: 1st Source / Drain 162: Second Source / Drain 166, 186: Contact 4100: Method 4102, 4104, 4106, 4108, 4110: Block A-A': horizontal line

Claims

1. A photodetector having a first terminal, A transfer transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the transfer transistor is coupled to the first terminal of the photodetector, A first pixel transistor on a first semiconductor chip, wherein the first pixel transistor has a first terminal, a second terminal, and a control terminal, and the first terminal of the first pixel transistor is coupled to the second terminal of the transfer transistor, A first capacitor on the first semiconductor chip, wherein the first capacitor has a first terminal and a second terminal, and the first terminal of the first capacitor is coupled to the second terminal of the first pixel transistor, A second pixel transistor on a second semiconductor chip bonded to the first semiconductor chip, wherein the second pixel transistor has a first terminal, a second terminal, and a control terminal, and the second terminal of the second pixel transistor is coupled to a first reference voltage terminal, A bonding structure at the interface where the first semiconductor chip and the second semiconductor chip are joined, wherein the bonding structure connects the second terminal of the first capacitor to the first terminal of the second pixel transistor. An integrated chip, including

2. The photodetector and the transfer transistor are located on the first semiconductor chip. The aforementioned integrated chip is Application-specific integrated circuit on the second semiconductor chip. It further includes, The control terminal of the transfer transistor, the control terminal of the first pixel transistor, and the control terminal of the second pixel transistor are coupled to the application-specific integrated circuit. The integrated chip according to claim 1.

3. The photodetector and the transfer transistor are located on the second semiconductor chip. The aforementioned integrated chip is Application-specific integrated circuit on a third semiconductor chip bonded to the first semiconductor chip It further includes, The control terminal of the transfer transistor, the control terminal of the first pixel transistor, and the control terminal of the second pixel transistor are coupled to the application-specific integrated circuit. The integrated chip according to claim 1.

4. The photodetector and the transfer transistor are located on a third semiconductor chip bonded to the first semiconductor chip. The aforementioned integrated chip is Application-specific integrated circuit on the second semiconductor chip. It further includes, The control terminal of the transfer transistor, the control terminal of the first pixel transistor, and the control terminal of the second pixel transistor are coupled to the application-specific integrated circuit. The integrated chip according to claim 1.

5. A third pixel transistor on the first semiconductor chip, wherein the third pixel transistor has a first terminal, a second terminal, and a control terminal, the first terminal of the third pixel transistor is coupled to the second terminal of the first pixel transistor and the first terminal of the first capacitor, and the second terminal of the third pixel transistor is coupled to a first power supply voltage terminal, A fourth pixel transistor on the first semiconductor chip, wherein the fourth pixel transistor has a first terminal, a second terminal, and a control terminal, the first terminal of the fourth pixel transistor is coupled to the second terminal and the first power supply voltage terminal of the third pixel transistor, and the control terminal of the fourth pixel transistor is coupled to the second terminal of the transfer transistor, A fifth pixel transistor on the first semiconductor chip, wherein the fifth pixel transistor has a first terminal, a second terminal, and a control terminal, and the first terminal of the fifth pixel transistor is coupled to the second terminal of the fourth pixel transistor, An application-specific integrated circuit coupled to the second terminal of the fifth pixel transistor and This also includes, The integrated chip according to claim 1.

6. A sixth pixel transistor coupled between the transfer transistor and the first pixel transistor on the first semiconductor chip, wherein the sixth pixel transistor has a first terminal, a second terminal and a control terminal, the first terminal of the sixth pixel transistor is coupled to the second terminal of the transfer transistor, and the second terminal of the sixth pixel transistor is coupled to the first terminal of the first pixel transistor, A second capacitor on the first semiconductor chip, wherein the second capacitor has a first terminal and a second terminal, the first terminal of the second capacitor is coupled to the second terminal of the sixth pixel transistor and the first terminal of the first pixel transistor, and the second terminal of the second capacitor is coupled to the second reference voltage terminal. This also includes, The integrated chip according to claim 5.

7. A photodetector and a transfer transistor, which are provided on a first semiconductor chip along a first semiconductor substrate, on a second semiconductor chip along a second semiconductor substrate, or on a third semiconductor chip along a third semiconductor substrate, wherein the transfer transistor includes a first source / drain, a second source / drain, and a gate, and the first source / drain of the transfer transistor is coupled to the photodetector, A first pixel transistor provided on the first semiconductor chip and along the first semiconductor substrate, wherein the first pixel transistor includes a first source / drain, a second source / drain, and a gate, and the first source / drain of the first pixel transistor is coupled to the second source / drain of the transfer transistor, A first lateral overflow storage capacitor on the first semiconductor chip, the first lateral overflow storage capacitor comprising a first electrode, a second electrode, and a dielectric between the first electrode and the second electrode, wherein the first electrode is coupled to the second source / drain of the first pixel transistor via a first conductive interconnect on the first semiconductor chip, A first bonding pad is located on the first semiconductor chip and is coupled to the second electrode of the first lateral overflow storage capacitor via a second conductive interconnect on the first semiconductor chip, A second bonding pad on the second semiconductor chip, wherein the second bonding pad is bonded and connected to the first bonding pad, A second pixel transistor provided on the second semiconductor chip and along the second semiconductor substrate, wherein the second pixel transistor includes a first source / drain, a second source / drain, and a gate, the second source / drain of the second pixel transistor being coupled to a first reference voltage terminal via a fourth conductive interconnect on the second semiconductor chip, and the first source / drain of the second pixel transistor being coupled to a second bonding pad via a third conductive interconnect on the second semiconductor chip, and including, Integrated chip.

8. A third pixel transistor provided on the first semiconductor chip and along the first semiconductor substrate, wherein the third pixel transistor includes a first source / drain, a second source / drain, and a gate, the first source / drain of the third pixel transistor being coupled to the second source / drain of the first pixel transistor and the first electrode of the first lateral overflow storage capacitor, and the second source / drain of the third pixel transistor being coupled to the power supply voltage terminal, A fourth pixel transistor provided on the first semiconductor chip and along the first semiconductor substrate, wherein the fourth pixel transistor includes a first source / drain, a second source / drain, and a gate, the first source / drain of the fourth pixel transistor being coupled to the second source / drain and the power supply voltage terminal of the third pixel transistor, and the gate of the fourth pixel transistor being coupled to the second source / drain of the transfer transistor, A fifth pixel transistor provided on the first semiconductor chip and along the first semiconductor substrate, wherein the fifth pixel transistor includes a first source / drain, a second source / drain, and a gate, and the first source / drain of the fifth pixel transistor is coupled to the second source / drain of the fourth pixel transistor, The application-specific integrated circuit coupled to the second source / drain of the fifth pixel transistor and This also includes, The integrated chip according to claim 7.

9. A sixth pixel transistor provided on the first semiconductor chip and along the first semiconductor substrate, wherein the sixth pixel transistor includes a first source / drain, a second source / drain, and a gate, the first source / drain of the sixth pixel transistor being coupled to the second source / drain of the transfer transistor, and the second source / drain of the sixth pixel transistor being coupled to the first source / drain of the first pixel transistor, A second lateral overflow storage capacitor on the first semiconductor chip, the second lateral overflow storage capacitor comprising a first electrode, a second electrode, and a dielectric between the first electrode and the second electrode, wherein the first electrode of the second lateral overflow storage capacitor is coupled to the second source / drain of the sixth pixel transistor and the first source / drain of the first pixel transistor via a fifth conductive interconnect on the first semiconductor chip, and the second electrode of the second lateral overflow storage capacitor is coupled to a second reference voltage terminal via a sixth conductive interconnect on the first semiconductor chip. This also includes, The integrated chip according to claim 8.

10. The gate of the transfer transistor, the gate of the first pixel transistor, the gate of the second pixel transistor, the gate of the third pixel transistor, the gate of the fifth pixel transistor, and the gate of the sixth pixel transistor are coupled to the application-specific integrated circuit. The integrated chip according to claim 9.

11. The photodetector and the transfer transistor are located on the first semiconductor chip and arranged along the first semiconductor substrate, and the application-specific integrated circuit is located on the second semiconductor chip. The aforementioned integrated chip is A third bonding pad, located on the first semiconductor chip and coupled to the second source / drain of the fifth pixel transistor via a seventh conductive interconnect on the first semiconductor chip, A fourth bonding pad located on the second semiconductor chip and coupled to the application-specific integrated circuit via an eighth conductive interconnect on the second semiconductor chip, wherein the fourth bonding pad is bonded to and coupled to the third bonding pad. This also includes, The integrated chip according to claim 9.

12. The photodetector and the transfer transistor are located on the second semiconductor chip and arranged along the second semiconductor substrate, and the application-specific integrated circuit is located on the third semiconductor chip. The aforementioned integrated chip is A third bonding pad, located on the first semiconductor chip and coupled to the second source / drain of the fifth pixel transistor via a seventh conductive interconnect on the first semiconductor chip, A fourth bonding pad located on the third semiconductor chip and coupled to the application-specific integrated circuit via an eighth conductive interconnect on the third semiconductor chip, wherein the fourth bonding pad is bonded to and coupled to the third bonding pad, A fifth bonding pad, located on the first semiconductor chip and coupled to the first source / drain of the sixth pixel transistor via a ninth conductive interconnect on the first semiconductor chip, A sixth bonding pad located on the second semiconductor chip and coupled to the second source / drain of the transfer transistor via a tenth conductive interconnect on the second semiconductor chip, wherein the sixth bonding pad is bonded to and coupled to the fifth bonding pad. This also includes, The integrated chip according to claim 9.

13. The photodetector and the transfer transistor are located on the third semiconductor chip and arranged along the third semiconductor substrate, and the application-specific integrated circuit is located on the second semiconductor chip. A third bonding pad, located on the first semiconductor chip and coupled to the second source / drain of the fifth pixel transistor via a seventh conductive interconnect on the first semiconductor chip, A fourth bonding pad located on the second semiconductor chip and coupled to the application-specific integrated circuit via an eighth conductive interconnect on the second semiconductor chip, the fourth bonding pad being bonded to and coupled to the third bonding pad, A fifth bonding pad, located on the first semiconductor chip and coupled to the first source / drain of the sixth pixel transistor via a ninth conductive interconnect on the first semiconductor chip, A sixth bonding pad located on the third semiconductor chip and coupled to the second source / drain of the transfer transistor via a tenth conductive interconnect on the third semiconductor chip, wherein the sixth bonding pad is bonded to and coupled to the fifth bonding pad. This also includes, The integrated chip according to claim 9.

14. The second conductive interconnect is an upper conductive wire on the first semiconductor chip. The aforementioned integrated chip is A first bonding contact is provided on the first semiconductor chip, extending from the first bonding pad to the upper conductive wire, An upper conductive via extending from the second conductive interconnect to the second electrode of the first lateral overflow storage capacitor is located on the first semiconductor chip, This also includes, The integrated chip according to claim 7.

15. The invention involves forming a photodetector and a transfer transistor, wherein the transfer transistor includes a first source / drain, a second source / drain, and a gate, and the first source / drain of the transfer transistor is coupled to the photodetector. The first pixel transistor is formed along a first semiconductor substrate of a first semiconductor chip, wherein the first pixel transistor includes a first source / drain, a second source / drain, and a gate, and the first source / drain of the first pixel transistor is coupled to the second source / drain of the transfer transistor. To form a first conductive interconnect on the first semiconductor chip that is coupled to the second source / drain of the first pixel transistor, The first capacitor is formed on the first semiconductor chip, wherein the first capacitor includes a first electrode, a second electrode, and a dielectric between the first electrode and the second electrode, and the first electrode is coupled to the first conductive interconnect. To form a second conductive interconnect on the first semiconductor chip that is coupled to the second electrode of the first capacitor, To form a first bonding pad on the first semiconductor chip that is coupled to the second conductive interconnect, The method involves forming a second pixel transistor along a second semiconductor substrate of a second semiconductor chip, wherein the second pixel transistor includes a first source / drain, a second source / drain, and a gate. To form a third conductive interconnect on the second semiconductor chip that is coupled to the first source / drain of the second pixel transistor, To form a second bonding pad on the second semiconductor chip that is coupled to the third conductive interconnect, The first bonding pad is joined to the second bonding pad, wherein the second electrode of the first capacitor is coupled to the first source / drain of the second pixel transistor via the second conductive interconnect, the first bonding pad, the second bonding pad, and the third conductive interconnect. including, A method for forming an integrated chip.

16. The method involves forming a third pixel transistor along the first semiconductor substrate of the first semiconductor chip, wherein the third pixel transistor includes a first source / drain, a second source / drain, and a gate, the first source / drain of the third pixel transistor being coupled to the second source / drain of the first pixel transistor and the first electrode of the first capacitor, and the second source / drain of the third pixel transistor being coupled to the power supply voltage terminal. A fourth pixel transistor is formed along the first semiconductor substrate of the first semiconductor chip, wherein the fourth pixel transistor includes a first source / drain, a second source / drain, and a gate, the first source / drain of the fourth pixel transistor is coupled to the second source / drain and the power supply voltage terminal of the third pixel transistor, and the gate of the fourth pixel transistor is coupled to the second source / drain of the transfer transistor. The method involves forming a fifth pixel transistor along the first semiconductor substrate of the first semiconductor chip, wherein the fifth pixel transistor includes a first source / drain, a second source / drain, and a gate, and the first source / drain of the fifth pixel transistor is coupled to the second source / drain of the fourth pixel transistor. To form an application-specific integrated circuit that is coupled to the second source / drain of the fifth pixel transistor, This also includes, The method according to claim 15.

17. The photodetector and the transfer transistor are formed along the first semiconductor substrate of the first semiconductor chip, and the application-specific integrated circuit is formed on the second semiconductor chip. The method according to claim 16.

18. The photodetector and the transfer transistor are formed along the second semiconductor substrate of the second semiconductor chip, and the application-specific integrated circuit is formed on the third semiconductor chip. The method according to claim 16.

19. The photodetector and the transfer transistor are formed along the third semiconductor substrate of the third semiconductor chip, and the application-specific integrated circuit is formed on the second semiconductor chip. The method according to claim 16.

20. The present invention relates to forming a third pixel transistor along the first semiconductor substrate of the first semiconductor chip, wherein the third pixel transistor includes a first source / drain, a second source / drain, and a gate, and the first source / drain of the third pixel transistor is coupled to the second source / drain of the transfer transistor, and the second source / drain of the third pixel transistor is coupled to the first source / drain of the first pixel transistor. To form a fourth conductive interconnect on the first semiconductor chip that is coupled to the second source / drain of the third pixel transistor and the first source / drain of the first pixel transistor, The present invention relates to forming a second capacitor on the first semiconductor chip, wherein the second capacitor includes a first electrode, a second electrode, and a dielectric between the first electrode and the second electrode, and the first electrode of the first capacitor is coupled to the fourth conductive interconnect. This also includes, The method according to claim 15.

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