Filter device and high-frequency front-end circuit incorporating it

Abstract

The present invention provides a filter device and a high-frequency front-end circuit that improve robustness against external metal shields in a diplexer. [Solution] In the filter device 100, filter circuit FLT1 has a passband of the first frequency band of the low band (LB) group. Filter circuit FLT2 has a passband of the second frequency band of the high band (HB) group, which is higher than the first frequency band. Filter circuit FLT1 includes coils L11 and L12 connected in series between the input terminal and the output terminal. Filter circuit FLT2 includes coil L21 connected between the signal path connecting the input terminal and the output terminal and the ground terminal, and coil L22 connected between the output terminal and the ground terminal. Coils L11 and L22 are coils whose winding axis is in the direction along the stacking direction of the laminate 110. Coils L12 and L21 are coils whose winding axis is in the direction intersecting the stacking direction.

Description

Technical Field

[0001] The present disclosure relates to a filter device and a high-frequency front-end circuit equipped with the same, and more particularly to a technique for suppressing deterioration of the characteristics of a diplexer.

Background Art

[0002] Japanese Patent Application Laid-Open No. 2021-19304 (Patent Document 1) discloses a diplexer including a filter circuit (high-pass circuit) having a relatively high frequency band as a passband and a filter circuit (low-pass circuit) having a relatively low frequency band as a passband in a dielectric substrate in which a plurality of dielectric layers are laminated. In the diplexer disclosed in Japanese Patent Application Laid-Open No. 2021-19304 (Patent Document 1), each filter circuit is configured to include a coil having the lamination direction of the dielectric substrate as a winding direction (hereinafter, also referred to as a "planar coil"), and a coil having a direction intersecting the lamination direction as a winding axis (hereinafter, also referred to as a "vertical coil").

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The filter device as described above may be used, for example, in a small portable terminal such as a mobile phone or a smartphone. In such devices, the needs for miniaturization and thinning are still high, and with further high functionality, new components may need to be added to the housing, and miniaturization and high integration are also required for the built-in components.

[0005] In this case, the distance between components within the enclosure becomes shorter, making it necessary to prevent electromagnetic interference between electronic components. For this reason, metal shields are sometimes placed around the outer circumference of each electronic component to suppress the effects of external electromagnetic noise.

[0006] Diplexers typically include coils (inductors) and capacitors to form the resonator of the filter circuit. While these coils form an electromagnetic field, if other electronic components with metal shields are brought close to the diplexer, the electromagnetic field formed by the coils may couple with the metal shields, potentially affecting the characteristics of the diplexer.

[0007] This disclosure was made to solve the above-mentioned problems, and its purpose is to improve robustness to an external metal shield in a filter device (diplexer) having two different passbands. [Means for solving the problem]

[0008] The filter device according to this disclosure comprises a laminate in which a plurality of dielectric layers are stacked, an input terminal, a ground terminal, a first output terminal and a second output terminal, and a first filter circuit and a second filter circuit. The first filter circuit is connected between the input terminal and the first output terminal. The second filter circuit is connected between the input terminal and the second output terminal. The laminate has a first main surface and a second main surface that face each other. The input terminal, the ground terminal, the first output terminal and the second output terminal are arranged on the second main surface. The first filter circuit has a first frequency band as its passband. The second filter circuit has a second frequency band higher than the first frequency band as its passband. The first filter circuit includes a first coil connected to the input terminal and a second coil connected between the first coil and the first output terminal. The second filter circuit includes a third coil connected between the signal path connecting the input terminal and the second output terminal and the ground terminal, and a fourth coil connected between a position on the signal path closer to the second output terminal than the third coil and the ground terminal. The first and fourth coils are coils whose winding axis is in a first direction along the stacking direction of the laminate. The second and third coils are coils whose winding axis is in a second direction intersecting the stacking direction. When viewed from a plan view from the stacking direction, at least a portion of the first coil and at least a portion of the fourth coil are located within a first region between the second and third coils. [Effects of the Invention]

[0009] In the filter device (diplexer) according to this disclosure, the first coil near the input terminal of the low-band filter circuit (first filter circuit) and the fourth coil near the second output terminal of the high-band filter circuit (second filter circuit) are composed of planar coils. At least a portion of each of the first and fourth coils is positioned in the region between the second coil of the first filter circuit and the third coil of the second filter circuit, which are composed of vertical coils.

[0010] By using planar coils for the first and fourth coils, which require relatively large inductance values, and vertical coils for the remaining coils, the number of planar coils in the filter device can be minimized while ensuring sufficient inductance and suppressing the effects of external metal shielding. Furthermore, by positioning the first and fourth coils between the second and third vertical coils, the distance between the second and third coils is maintained, weakening the coupling between the low-band and high-band filter circuits. This suppresses the degradation of filter characteristics while improving robustness against external metal shielding. [Brief explanation of the drawing]

[0011] [Figure 1] This is a block diagram of a communication device having a high-frequency front-end circuit to which the filter device of Embodiment 1 is applied. [Figure 2] This is an equivalent circuit diagram of the filter device according to Embodiment 1. [Figure 3] This is an outline view of the filter device according to Embodiment 1. [Figure 4] Figure 3 is an exploded perspective view showing an example of a detailed structure of the filter device. [Figure 5] This is a plan view illustrating the arrangement of coils included in the filter device shown in Figure 3. [Figure 6] Figure 3 is a side view of the filter device. [Figure 7] This figure illustrates the filter characteristics of the filter device of Embodiment 1 and the filter device of the comparative example. [Figure 8] This is a plan view of the filter device of modified example 1. [Figure 9] This is a plan view of the filter device of modified example 2. [Figure 10] This is a side perspective view of the filter device of modified example 3. [Figure 11] This is a block diagram of a communication device having a high-frequency front-end circuit to which the filter device of Embodiment 2 is applied.

Mode for Carrying Out the Invention

[0012] Hereinafter, Embodiment 1 of the present disclosure will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and their description will not be repeated.

[0013] [Embodiment 1] (Basic Configuration of Communication Device) FIG. 1 is a block diagram of a communication device 10 including a high-frequency front-end circuit 20 to which a filter device 100 according to Embodiment 1 is applied. The high-frequency front-end circuit 20 divides a high-frequency signal received by an antenna device ANT into a plurality of predetermined frequency bands and transmits it to a subsequent processing circuit. The high-frequency front-end circuit 20 is used in, for example, a mobile terminal such as a mobile phone, a smartphone or a tablet, or a communication device such as a personal computer having a communication function.

[0014] Referring to FIG. 1, the communication device 10 includes a high-frequency front-end circuit 20 including a filter device 100 and an RF signal processing circuit (hereinafter also referred to as "RFIC") 30. The high-frequency front-end circuit 20 shown in FIG. 1 is a reception front-end circuit. The high-frequency front-end circuit 20 includes a filter device 100 and amplifier circuits LNA1 and LNA2.

[0015] The filter device 100 includes an antenna terminal TA which is a common terminal, terminals T1 and T2, and filter circuits FLT1 and FLT2. The filter device 100 is a diplexer including filter circuits FLT1 and FLT2 having different frequency ranges as passbands. In the following description, the filter device 100 may be referred to as a "diplexer". In the present specification, the "passband" of a filter circuit is a frequency band between two frequencies 3 dB higher than the minimum value of the insertion loss.

[0016] The filter circuit FLT1 is connected between the antenna terminal TA and the terminal T1. The filter circuit FLT1 is a low-pass filter that has a passband in the frequency range (first frequency band) of the low band (LB) group and a stopband in the frequency range (second frequency band) of the high band (HB) group. The filter circuit FLT2 is connected between the antenna terminal TA and the terminal T2. The filter circuit FLT2 is a high-pass filter that has a passband in the frequency range of the high band group and a stopband in the frequency range of the low band group. Note that the filter circuits FLT1 and FLT2 may be band-pass filters.

[0017] Each of the filter circuits FLT1 and FLT2 passes a high-frequency signal corresponding to the passband of each filter among the high-frequency signals received by the antenna device ANT. Thereby, the high-frequency signal received by the antenna device ANT is demultiplexed into signals of a plurality of predetermined frequency bands.

[0018] Each of the amplifier circuits LNA1 and LNA2 is a so-called low-noise amplifier. The amplifier circuits LNA1 and LNA2 amplify the high-frequency signal that has passed through the filter device 100 with low noise and transmit it to the RFIC30.

[0019] The RFIC30 is an RF signal processing circuit that processes the high-frequency signals transmitted and received by the antenna device ANT. Specifically, the RFIC30 processes the high-frequency signal input from the antenna device ANT via the reception-side signal path of the high-frequency front-end circuit 20, such as by down-converting, and outputs the reception signal generated by the signal processing to a baseband signal processing circuit (not shown).

[0020] When the high-frequency front-end circuit 20 is a reception-system front-end circuit as shown in FIGURE 1, in the filter device 100, the antenna terminal TA becomes the input terminal IN, and the terminals T1 and T2 become the first output terminal OUT1 and the second output terminal OUT2, respectively.

[0021] On the other hand, the high-frequency front-end circuit can also be used as a transmission front-end circuit. In this case, terminals T1 and T2 of the filter device 100 become input terminals, and the antenna terminal TA becomes a common output terminal. In this case, a power amplifier is used instead of a low-noise amplifier as the amplifier included in the amplification circuit.

[0022] (Configuration of the filter device) Figure 2 shows an example of the equivalent circuit of the filter device (diplexer) 100 in Figure 1. As explained in Figure 1, filter circuit FLT1 is connected between antenna terminal TA and terminal T1. Filter circuit FLT2 is connected between antenna terminal TA and terminal T2. Filter circuits FLT1 and FLT2 each include an LC resonator composed of a capacitor and an inductor. In the following explanation, the inductor will also be referred to as a "coil".

[0023] The filter circuit FLT1 includes coils L11 and L12 and capacitors C11 and C12, and is connected between antenna terminal TA and terminal T1. One end of coil L11 is connected to antenna terminal TA. The other end of coil L11 is connected to terminal T1 via coil L12. In other words, coils L11 and L12 are connected in series between antenna terminal TA and terminal T1.

[0024] Capacitor C11 is connected between the connection node N1 between coils L11 and L12 and the ground terminal GND. Capacitor C12 is connected in parallel with coil L12. With this configuration, the filter circuit FLT1 functions as a low-pass filter with a passband frequency band lower than a predetermined cutoff frequency.

[0025] The filter circuit FLT2 includes coils L21 and L22 and capacitors C21 to C23, and is connected between antenna terminal TA and terminal T2. One end of capacitor C21 is connected to antenna terminal TA. The other end of capacitor C21 is connected to terminal T2 via capacitor C22. In other words, capacitors C21 and C22 are connected in series between antenna terminal TA and terminal T2.

[0026] Coil L21 is connected between the connection node N2 between capacitors C21 and C22 and the ground terminal GND. One end of coil L22 is connected to terminal T2, and the other end is connected to the ground terminal GND via capacitor C23. In other words, coil L22 is connected between a position closer to terminal T2 than coil L21 and the ground terminal GND in the signal path between antenna terminal TA and terminal T2. With this configuration, the filter circuit FLT2 functions as a high-pass filter with a passband frequency band higher than a predetermined cutoff frequency.

[0027] Next, the detailed configuration of the filter device 100 will be described using Figures 3 to 6. Figure 3 is an external view of the filter device 100. Figure 4 is an exploded perspective view showing an example of the detailed internal structure of the filter device 100. Figure 5 is a plan view illustrating the arrangement of coils L11, L12, L21, and L22 included in the filter device 100. Figure 6 is a side perspective view of the filter device shown in Figure 3.

[0028] Note that in Figures 5 and 6, the dielectric layer of the laminate 110 is omitted, and only the conductors of the electrodes, vias, and terminals arranged inside the laminate 110 are shown. Furthermore, in Figure 5, electrodes other than coils L11, L12, L21, and L22 are omitted for the sake of clarity.

[0029] The filter device 100 includes a rectangular or substantially rectangular parallelepiped laminate 110 formed by stacking multiple dielectric layers LY1 to LY13 in a predetermined direction. Each dielectric layer of the laminate 110 is made of a ceramic such as low-temperature co-fired ceramics (LTCC) or a resin. Inside the laminate 110, inductors and capacitors constituting the filter circuits FLT1 and FLT2 are formed by multiple electrodes provided on each dielectric layer and multiple vias arranged between the dielectric layers. Furthermore, in the following description, for the sake of simplicity, the laminate 110 will be described as a multilayer substrate as described above, but the laminate 110 may also be a single-layer substrate.

[0030] In this specification, "via" refers to a conductor provided in a dielectric layer for connecting electrodes provided in different dielectric layers. Vias are formed, for example, by conductive paste, plating, and / or metal pins. In the following description, the stacking direction of dielectric layers LY1 to LY13 in the laminate 110 is referred to as the "Z-axis direction," the direction perpendicular to the Z-axis direction and along the long side of the laminate 110 is referred to as the "X-axis direction," and the direction along the short side of the laminate 110 is referred to as the "Y-axis direction." In the following, the positive Z-axis direction in each figure may be referred to as the upper side, and the negative Z-axis direction as the lower side.

[0031] Referring to Figures 3 to 6, the laminate 110 includes an upper surface 111, a lower surface 112, and side surfaces 113 to 116. Directional mark DM for identifying the direction of the filter device 100 is placed on the upper surface 111 (dielectric layer LY1) of the laminate 110. As shown in Figure 3, external terminals (antenna terminal TA, terminals T1, T2, and ground terminal GND) for connecting the filter device 100 to external equipment are placed on the lower surface 112 (dielectric layer LY13) of the laminate 110. That is, the antenna terminal TA, terminals T1, T2, and ground terminal GND constitute an LGA (Land Grid Array).

[0032] In Figure 4, filter circuit FLT1 is generally provided on the right side (positive direction of the X-axis) of the laminate 110, and filter circuit FLT2 is provided on the left side (non-positive direction of the X-axis).

[0033] First, the details of the filter circuit FLT1 will be explained. Referring to Figure 4, the antenna terminal TA located on the lower surface 112 (dielectric layer LY13) of the laminate 110 is connected to the flat electrode PL1 located on the dielectric layer LY9 by vias V1 and V2.

[0034] When the laminate 110 is viewed from the Z-axis direction, the flat electrode PL1 is a linear, strip-shaped electrode, with via V2 connected to one end and via V3 connected to the other end. Via V3 is connected to the flat electrode PL10 located in the dielectric layer LY4, and to the capacitor electrode PC20 located in the dielectric layer LY3.

[0035] The plate electrode PL10 is a strip-shaped electrode with a roughly U-shape or O-shape, wound around the Z-axis. One end of the plate electrode PL10 is connected to via V3. The other end of the plate electrode PL10 is connected via VL10 to plate electrode PL11, which is located in the dielectric layer LY6.

[0036] The flat electrode PL11 is a strip-shaped electrode with a roughly U-shape or J-shape, wound around the Z-axis. One end of the flat electrode PL11 is connected to via VL10. The other end of the flat electrode PL11 is connected via via VL11 to the capacitor electrode PC10 located in the dielectric layer LY8. The flat electrodes PL10 and PL11 and vias VL10 and VL11 constitute the coil L11 in Figure 2.

[0037] The capacitor electrode PC10 is connected by via VL20 to the flat electrode PL20 located in the dielectric layer LY2, and to the capacitor electrode PC12 located in the dielectric layer LY10. The capacitor electrodes PC10 and PC12 are flat electrodes having a substantially rectangular shape.

[0038] When the laminate 110 is viewed from the Z-axis direction, at least a portion of capacitor electrode PC10 and at least a portion of capacitor electrode PC12 overlap with capacitor electrode PC11, which is located in the dielectric layer LY9. Capacitor electrode PC11 is also a flat electrode with a substantially rectangular shape. In other words, capacitor electrodes PC10, PC12 and capacitor electrode PC11 constitute the capacitor C12 in Figure 2.

[0039] The capacitor electrode PC11 is connected by via VL21 to a plate electrode PL15 located in the dielectric layer LY12. The plate electrode PL15 is connected by via V4 to a terminal T1 located in the dielectric layer LY13.

[0040] Furthermore, via VL21 is also connected to a flat electrode PL20 located in the dielectric layer LY2. The flat electrode PL20 is an electrode with a substantially rectangular shape that extends in the Y-axis direction. Via VL21 is connected to the negative Y-axis end of the flat electrode PL20. Via VL20 is connected to the positive Y-axis end of the flat electrode PL20. In other words, coil L12 in Figure 2 is formed by the flat electrode PL20 and vias VL20 and VL21.

[0041] When the laminate 110 is viewed from the Z-axis direction, at least a portion of the capacitor electrode PC12 overlaps with the capacitor electrode PC13 located in the dielectric layer LY11. The capacitor electrode PC13 is a flat electrode with a substantially rectangular shape and is connected to the ground terminal GND located in the dielectric layer LY13 by via VG1. In other words, the capacitor electrode PC12 and the capacitor electrode PC13 constitute the capacitor C11 in Figure 2.

[0042] Next, the details of the filter circuit FLT2 will be described. The capacitor electrode PC20 connected to via V3 in the dielectric layer LY3 overlaps at least partially with the capacitor electrode PC21 located in the dielectric layer LY2 when the laminate 110 is viewed from the Z-axis direction. The capacitor electrode PC21 is a flat plate electrode with a substantially rectangular shape extending in the Y-axis direction. When the laminate 110 is viewed from the Z-axis direction, at least a portion of the capacitor electrode PC21 also overlaps with the capacitor electrode PC22 located in the dielectric layer LY3.

[0043] The capacitor electrode PC22 is connected by via VL30 to the plate electrode PL30 located in the dielectric layer LY12. The plate electrode PL30 is connected by via V5 to terminal T2 located in the dielectric layer LY13.

[0044] Specifically, capacitor C21 in Figure 2 is formed by capacitor electrodes PC20 and PC21. Furthermore, capacitor C22 in Figure 2 is formed by capacitor electrodes PC21 and PC22.

[0045] In Figure 4, although it is somewhat difficult to see, the capacitor electrode PC21 is connected to the plate electrode PL40 located in the dielectric layer LY9 by via VL40. The plate electrode PL40 is a strip-shaped electrode extending in the Y-axis direction, with via VL40 connected to one end. Via VL41 is connected to the other end of the plate electrode PL40. Via VL41 is connected to the plate electrode PL41 located in the dielectric layer LY2.

[0046] The plate electrode PL41 is a strip-shaped electrode, with via VL41 connected to one end and via VL42 connected to the other end. Via VL42 is connected to the plate electrode PL42 located in the dielectric layer LY13.

[0047] The flat electrode PL42 is a strip-shaped electrode extending in the Y-axis direction, with via VL42 connected to one end and via VL43 connected to the other end. Via VL43 is connected to the ground terminal GND located in the dielectric layer LY13 via the flat electrode PL43 located in the dielectric layer LY12 and via VG2. The flat electrodes PL40~PL42 and vias VL40~VL42 constitute the coil L21 in Figure 2.

[0048] Via VL30, which is connected to the capacitor electrode PC22, is also connected to a flat electrode PL50 located in the dielectric layer LY4. The flat electrode PL50 is a strip-shaped electrode with a roughly U-shape or O-shape, wound around the Z-axis. Via VL30 is connected to one end of the flat electrode PL50, and via VL50 is connected to the other end. Via VL50 is connected to a flat electrode PL51 located in the dielectric layer LY5.

[0049] The flat electrode PL51 is a strip-shaped electrode having a roughly U-shape or O-shape, wound around the same winding axis as the flat electrode PL50. A via VL50 is connected to one end of the flat electrode PL51, and a via VL51 is connected to the other end. Via VL51 is connected to the flat electrode PL52, which is located in the dielectric layer LY6.

[0050] The plate electrode PL52 is a strip-shaped electrode with a roughly U-shape or O-shape, wound around the same winding axis as the plate electrodes PL50 and PL51. Via VL51 is connected to one end of plate electrode PL52, and via VL52 is connected to the other end. Via VL52 is connected to plate electrode PL53, which is located in the dielectric layer LY7.

[0051] The flat electrode PL53 is a strip-shaped electrode with a roughly C-shape or J-shape, wound around the same winding axis as the flat electrodes PL50, PL51, and PL52. A via VL52 is connected to one end of the flat electrode PL53, and a via VL53 is connected to the other end. Via VL53 is connected to the capacitor electrode PC50 located in the dielectric layer LY8. In other words, the flat electrodes PL50 to PL53 and vias VL50 to VL53 constitute the coil L22 in Figure 2.

[0052] When the laminate 110 is viewed from the Z-axis direction, at least a portion of the capacitor electrode PC50 overlaps with the capacitor electrode PC51 located in the dielectric layer LY12. The capacitor electrode PC51 is connected to the ground terminal GND located in the dielectric layer LY13 by via VG3. In other words, the capacitor electrode PC50 and the capacitor electrode PC51 constitute the capacitor C23 in Figure 2.

[0053] As shown in Figures 4 and 5, coil L11 of filter circuit FLT1 and coil L22 of filter circuit FLT2 are planar coils with the winding direction in the Z-axis direction. Coil L12 of filter circuit FLT1 and coil L21 of filter circuit FLT2 are vertical coils with the winding direction in the X-axis direction.

[0054] In the laminate 110, coil L12 is located at the positive end of the X-axis, and coil L21 is located at the negative end of the X-axis. In the filter device 100, the opening of coil L12 faces the opening of coil L21.

[0055] When the laminate 110 is viewed from a planar perspective along the Z-axis, coils L11 and L22 are positioned within the region RG1 between coils L12 and L21. Coil L11 is positioned further away from coil L22 in the positive Y-axis direction and does not overlap with coil L22.

[0056] Furthermore, when the laminate 110 is viewed from a plan view in the Z-axis direction, coil L11 is wound in a clockwise direction (CW direction), and coil L22 is wound in a counterclockwise direction (CCW direction). In other words, the winding direction of coil L11 and the winding direction of coil L22 are opposite to each other.

[0057] As shown in Figure 6, the planar coils L11 and L22 are positioned such that the height H2 from the bottom surface 112 to the top is lower than the height H1 from the bottom surface 112 to the top of the vertical coils L12 and L21. In other words, the distance from the top surface 111 for coils L11 and L22 is greater than the distance from the top surface 111 for coils L12 and L21.

[0058] Diplexers, such as filter device 100, are sometimes used in small portable devices such as mobile phones or smartphones, as described above. In such devices, there remains a high need for miniaturization and thinning, and further enhancement of functionality may necessitate the addition of new components within the housing, thus requiring miniaturization and high integration of internal components. As a result, the distance between components within the device housing becomes smaller, and the electromagnetic field generated by the coil in the filter may couple with the metal shield provided on adjacent electronic components. This can cause the inductance value of the coil to change, potentially leading to an increase in losses as the resonant frequency of the resonator shifts from the design value.

[0059] To reduce the influence of such external metal shields, it is possible to install a metal shield on the top side of the diplexer. However, in this case, although fluctuations due to the external metal shield can be suppressed, the influence of the metal shield within the diplexer cannot be avoided, which may result in a decrease in characteristics such as a reduction in the Q value. To eliminate this decrease in characteristics, it is necessary to increase the distance between the internal metal shield and the coil or to increase the air core diameter of the coil, but in this case, the size of the device itself will increase, which will hinder miniaturization.

[0060] In a diplexer having a stacked structure like the filter device 100, a situation is likely to occur where the external metal shield is in close proximity to the upper surface 111, which is opposite to the mounting surface. In this case, the influence of the metal shield becomes significant for the planar coil, which generates an electromagnetic field in the direction normal to the upper surface 111.

[0061] On the other hand, to increase the inductance and Q value of a coil, it is necessary to increase the air core diameter or the number of turns, but such coils are easier to realize with planar coils than with vertical coils. Therefore, in the filter device 100 according to this embodiment 1, among the coils constituting the filter, only the coils that require a relatively large Q value are configured as planar coils, and the other coils are configured as vertical coils, thereby reducing the influence of metal shielding while maintaining the characteristics of the coils.

[0062] More specifically, in the case of filter device 100, for the low-band filter circuit FLT1, in order to prevent signals from the high-band side from entering, the coil L11 closest to the antenna terminal TA needs to have a higher impedance, i.e., a larger inductance value, compared to coil L12. Similarly, for the high-band filter circuit FLT2, in order to match the impedance with external equipment connected to the output terminal T2, the coil L22 closest to the output terminal T2 needs to have a larger inductance value than coil L21, resulting in a higher impedance. Therefore, in filter device 100, only coils L11 and L22 are made of planar coils, while the other coils L12 and L21 are made of vertical coils.

[0063] Furthermore, as explained in Figure 6, the planar coils L11 and L22 are positioned below the uppermost ends of the vertical coils L12 and L21, and as far away from the upper surface 111 as possible. This reduces the impact of the external metal shield even when it approaches the upper surface 111. In other words, robustness against the external metal shield can be improved.

[0064] Furthermore, considering the influence of the external metal shield, it is preferable for the planar coil to be as close to the bottom surface 112 as possible. However, the capacitor electrodes and external connection terminals (antenna terminal TA, output terminal T1, output terminal T2, ground terminal GND) that constitute the capacitor are located on the bottom surface 112 side of the laminate 110, and in some cases the RFIC 30 may also be mounted on the bottom surface 112. Therefore, if the coil is placed too close to the bottom surface 112, the Q value may actually decrease. For this reason, the arrangement position of the planar coil in the Z-axis direction is designed taking into consideration the influence of the external metal shield and the influence of the electrodes on the bottom surface 112 side.

[0065] Furthermore, by positioning the planar coils L11 and L22 below the uppermost ends of the vertical coils L12 and L21, the magnetic field in the X-axis direction due to the vertical coils L12 and L21 becomes dominant over the magnetic field in the Z-axis direction near the upper surface 111 of the laminate 110. Therefore, even if an external metal shield approaches the upper surface 111, it becomes difficult for the magnetic field to couple with the metal shield.

[0066] Furthermore, the vertical coils L12 and L21 are arranged so that their openings face each other. In this case, generally, there is a concern that the magnetic fields generated by each coil will couple with each other, worsening the isolation between high-band and low-band signals. However, in the filter device 100 of Embodiment 1, since most of the planar coils L11 and L22 are arranged in the region RG1 between coil L12 and coil L21, coupling between coil L12 and coil L21 is suppressed.

[0067] Furthermore, although the planar coils L11 and L22 are positioned adjacent to each other, their winding directions are opposite, thus suppressing coupling between the two coils. In other words, this arrangement facilitates isolation between filter circuit FLT1 and filter circuit FLT2.

[0068] (Filter characteristics) Next, the filter characteristics of the filter device 100 of Embodiment 1 will be described using Figure 7. Figure 7 shows the change in insertion loss when an external metal shield is brought closer to a position 1 mm above the top surface of the laminate in the filter device of Embodiment 1 and the filter device of the comparative example. In Figure 7, the filter device having the configuration disclosed in Japanese Patent Application Publication No. 2021-19304 (Patent Document 1) is used as the comparative example.

[0069] In Figure 7, the solid lines (LN10, LN15, LN20, LN25) show the characteristics without metal shielding, while the dashed lines (LN11, LN16, LN21, LN26) show the characteristics with metal shielding brought close. Additionally, lines LN10, LN11, LN21, LN22 show the characteristics of the low-band filter circuit, while lines LN15, LN16, LN25, LN26 show the characteristics of the high-band filter circuit.

[0070] In the comparative example shown in the figure on the right, it can be seen that when the metal shield is brought closer (dashed lines LN21, LN25), the frequency of the attenuation pole is shifted to a higher level in both the high-band and low-band directions compared to the case without the metal shield. As a result, the insertion loss at the lower limit of the passband increases, especially in the high-band direction.

[0071] On the other hand, in the case of Embodiment 1 shown in the left figure, even when the metal shield is brought closer, the wavenumber of the attenuation pole hardly changes in both the low band and the high band, and the change in insertion loss is also small.

[0072] As described above, in the filter device of Embodiment 1, by minimizing the number of planar coils and devising the arrangement and winding direction of each coil, it is possible to secure the desired inductance value and Q value while reducing characteristic fluctuations due to external metal shielding (improving robustness) and ensuring isolation between filter circuits.

[0073] In Embodiment 1, "coil L11," "coil L12," "coil L21," and "coil L22" correspond to "first coil" to "fourth coil," respectively, in this disclosure. In Embodiment 1, "capacitor C11," "capacitor C12," "capacitor C21," "capacitor C22," and "capacitor C23" correspond to "first capacitor" to "fifth capacitor," respectively, in this disclosure. In Embodiment 1, "filter circuit FLT1" and "filter circuit FLT2" correspond to "first filter circuit" and "second filter circuit," respectively, in this disclosure. In Embodiment 1, "upper surface 111" and "lower surface 112" correspond to "first main surface" and "second main surface," respectively, in this disclosure. In Embodiment 1, "Z-axis direction" and "X-axis direction" correspond to "first direction" and "second direction," respectively, in this disclosure.

[0074] <Variation> The following describes some variations in the coil arrangement in a filter device.

[0075] (Variation 1) Modification 1 describes an example of a different arrangement of coils on the low band side. Figure 8 is a plan view of the filter device 100A of Modification 1. In filter device 100A, coils L11 and L12 in the filter circuit FLT1 of filter device 100 shown in Figure 5 are replaced with coils L11A and L12A, respectively.

[0076] Referring to Figure 8, the coil L12A in the filter circuit FLT1 has a shorter Y-axis length of the flat electrode PL20 compared to the coil L12 in the filter device 100, and is positioned on the negative Y-axis side 116 in the laminate 110.

[0077] Accordingly, in coil L11A, the shape of the flat electrodes PL10 and PL11 is extended in the positive X-axis direction so that the air core diameter in the X-axis direction is increased compared to coil L11 in the filter device 100. As a result, a portion of coil L11A is positioned outside the region RG1.

[0078] By adopting this coil shape, the Q value of coil L12A is slightly lower compared to coil L12 in Embodiment 1, but since the air core diameter of coil L11A is larger than that of coil L11, the inductance value can be increased and the Q value can be improved.

[0079] Furthermore, the degree of overlap between the opening of coil L21 and the opening of coil L12A when viewed from the X-axis direction is reduced, thus improving the isolation between filter circuit FLT1 and filter circuit FLT2.

[0080] In Figure 8, the filter device 100A was described in which coil L12A is located on the side 116 and coil L11A is extended in the X-axis direction. Alternatively, coil L12A may be located on the side 115 and coil L22 may be extended in the X-axis direction.

[0081] (Modification 2) In the second modified example, we will describe a configuration in which the vertical coil in the filter device 100A shown in Figure 8 has a different shape.

[0082] Figure 9 is a plan view of filter device 100B of modified example 2. In filter device 100B, coil L12A in filter device 100A is replaced with coil L12B, and furthermore, coil L22 on the high band side is replaced with coil L22B.

[0083] In the coil L12B of the filter device 100B, the flat electrode PL20B arranged in the dielectric layer LY2 has a roughly L-shape. That is, in the coil L12B, a part of the opening is parallel to the ZX plane.

[0084] As a result, the X-axis dimension of coil L12B is larger than that of coil L12A, so the air core diameter of coil L22B on the high-band side is smaller than that of coil L22.

[0085] This configuration results in a larger inductance value for coil L12B compared to coil L12A. Conversely, the inductance value of coil L22B is smaller than that of coil L22. The shape and arrangement of each coil are appropriately selected based on the required filter characteristics and the parameter values ​​of each element necessary to achieve them.

[0086] (Variation 3) Modification 3 describes a modification of the arrangement of the planar coils. Figure 10 is a side perspective view of the filter device 100C of Modification 3, as seen from the X-axis direction. In the filter device 100C, the shape of each coil is basically the same as that of the filter device 100 of Embodiment 1, but the position of the planar coils L11 and L22 in the Y-axis direction is different.

[0087] More specifically, in the filter device 100C, coil L11 is positioned slightly offset in the positive direction of the Y-axis, and coil L22 is positioned slightly offset in the negative direction of the Y-axis. As a result, as shown by the dashed lines in Figure 10, the end of coil L11 on the side 115 and the end of coil L22 on the side 116 are positioned outside the opening of coil L12, which is a vertical coil. Alternatively, instead of offsetting the positions of coils L11 and L22, the air core diameter of coils L11 and L22 may be expanded in the Y-axis direction.

[0088] By positioning the planar coil such that its side ends are outside the opening of the vertical coil, the portion that does not interfere with the electrodes of the vertical coil is increased, thereby improving the Q value of the planar coil.

[0089] Furthermore, in the filter device 100C, in the stacking direction (Z-axis direction), the flat plate electrode PL51 constituting the high-band coil L22 is positioned in the dielectric layer between the flat plate electrodes PL10 and PL11 constituting the low-band coil L11. This arrangement reduces the interlayer stray capacitance of the low-band coil while efficiently achieving a high inductance value relative to the high-band coil within the dielectric space. This configuration makes it possible to realize a filter device that is compact and has high filtering characteristics.

[0090] [Embodiment 2] Embodiment 2 describes a case where the high-frequency front-end circuit includes a triplexer that separates the signal into three different frequency bands.

[0091] Figure 11 is a block diagram of a communication device 10A having a high-frequency front-end circuit 20A according to Embodiment 2. In the high-frequency front-end circuit 20A, a filter circuit FLT3 and an amplification circuit LNA3 are added to the high-frequency front-end circuit 20 shown in Figure 1. For Figure 11, explanations of elements that overlap with those in Figure 1 will not be repeated.

[0092] The filter circuit FLT3 is a bandpass filter whose passband is in the middle band (MB) frequency range, which is higher than the passband of the low-band filter circuit FLT1 and lower than the passband of the high-band filter circuit FLT2. One end of the filter circuit FLT3 is connected to the antenna terminal TA, and the other end is connected to the RFIC30 via the amplification circuit LNA3.

[0093] Furthermore, the filter device 100, which functions as a diplexer, employs a diplexer having the coil arrangement described in Embodiment 1. Therefore, in the high-frequency front-end circuit 20A of Embodiment 2, as in Embodiment 1, it is possible to improve robustness to external metal shields and ensure isolation between filter circuits while securing the desired inductance value and Q value.

[0094] The "filter circuit FLT3" in Embodiment 2 corresponds to the "third filter circuit" in this disclosure.

[0095] [Pattern] Those skilled in the art will understand that the above-described exemplary embodiments are specific examples of the following embodiments.

[0096] (Section 1) A filter device according to one embodiment comprises a laminate in which a plurality of dielectric layers are stacked, an input terminal, a ground terminal, a first output terminal and a second output terminal, and a first filter circuit and a second filter circuit. The first filter circuit is connected between the input terminal and the first output terminal. The second filter circuit is connected between the input terminal and the second output terminal. The laminate has a first main surface and a second main surface that face each other. The input terminal, ground terminal, first output terminal and second output terminal are arranged on the second main surface. The first filter circuit has a first frequency band as its passband. The second filter circuit has a second frequency band that is higher than the first frequency band as its passband. The first filter circuit includes a first coil and a second coil connected in series between the input terminal and the first output terminal. The first coil is connected to the input terminal and the second coil is connected to the first output terminal. The second filter circuit includes a third coil connected between the signal path connecting the input terminal and the second output terminal and the ground terminal, and a fourth coil connected between a position on the signal path closer to the second output terminal than the third coil and the ground terminal. The first and fourth coils are coils whose winding axis is in a first direction along the stacking direction of the laminate. The second and third coils are coils whose winding axis is in a second direction intersecting the stacking direction. When viewed from the stacking direction in a plan view, at least a portion of the first coil and at least a portion of the fourth coil are located within a first region between the second and third coils.

[0097] (Article 2) In the filter device described in Article 1, when viewed from a plan view from the first direction, the winding direction of the first coil and the winding direction of the fourth coil are in opposite directions.

[0098] (Article 3) In the filter device described in Article 1 or Article 2, when viewed from a plan view from the first direction, the first coil does not overlap with the fourth coil.

[0099] (Article 4) In the filter device described in any one of Articles 1 to 3, the distance from the first main surface to the first coil and the fourth coil in the first direction is greater than the distance from the first main surface to the second coil and the third coil in the first direction.

[0100] (Clause 5) In the filter device described in any one of paragraphs 1 to 4, when viewed from a second direction in a plan view, at least a portion of the second coil overlaps with the third coil.

[0101] (Item 6) In the filter device described in any one of Items 1 to 5, the inductance value of the first coil is greater than the inductance value of the second coil. The inductance value of the fourth coil is greater than the inductance value of the third coil.

[0102] (Clause 7) In the filter device described in any one of paragraphs 1 to 6, at least one of the part of the first coil and the part of the fourth coil is located outside the first region.

[0103] (Clause 8) In the filter apparatus described in any one of Clauses 1 to 7, each of the first coil and the fourth coil includes a plurality of planar electrodes arranged in different dielectric layers and a plurality of vias extending in the stacking direction. The first coil includes a first planar electrode and a second planar electrode. Some of the planar electrodes in the fourth coil are arranged in the dielectric layer between the first planar electrode and the second planar electrode.

[0104] (Section 9) In the filter apparatus described in any one of Sections 1 to 7, each of the first coil and the fourth coil includes a plurality of planar electrodes arranged in different dielectric layers and a plurality of vias extending in the stacking direction. In at least one of the first coil and the fourth coil, the ends of at least some of the planar electrodes included in the coil are located outside the opening of the second coil when viewed from a second direction in plan view.

[0105] (Section 10) In the filter device described in any one of Sections 1 to 9, the first filter circuit further includes a first capacitor and a second capacitor. The first capacitor is connected between the connection node between the first coil and the second coil and the ground terminal. The second capacitor is connected in parallel with the first coil.

[0106] (Section 11) In the filter device described in any one of Sections 1 to 10, the second filter circuit further includes a third capacitor connected to the input terminal, a fourth capacitor, and a fifth capacitor. The fourth capacitor is connected between the third capacitor and the second output terminal. The fifth capacitor is connected between the fourth coil and the ground terminal. The third coil is connected between the connection node between the third capacitor and the fourth capacitor and the ground terminal.

[0107] (Clause 12) A high-frequency front-end circuit according to one embodiment comprises a filter device as described in any one of paragraphs 1 to 11.

[0108] (Clause 13) The high-frequency front-end circuit described in paragraph 12 further comprises a third filter circuit having a third frequency band different from the first and second frequency bands as its passband.

[0109] Embodiment 1 disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of the present invention is indicated by the claims rather than by the description of Embodiment 1 above, and all modifications within the meaning and scope equivalent to the claims are intended to be included. [Explanation of Symbols]

[0110] 10,10A Communication equipment, 20,20A High-frequency front-end circuit, 30 RFIC, 100,100A~100C Filter equipment, 110 Laminate, 111 Top surface, 112 Bottom surface, 113~116 Side surface, ANT Antenna equipment, C11,C12,C21~C23 Capacitors, DM Directional mark, FLT1~FLT3 Filter circuit, GND Grounding terminal, L11,L12,L11A,L12A,L12B,L21,L22,L22B Coils, LNA1,LNA2,LNA3 Amplifier circuit, LY1~LY13 Dielectric layer, N1,N2 Connection node, PC10~PC13,PC20~PC22,PC50,PC51 Capacitor electrodes: PL1, PL10, PL11, PL15, PL20, PL20B, PL30, PL40~PL43, PL50~PL53; Flat electrode: T1, T2; Output terminal: TA; Antenna terminal: V1~V5, VG1~VG3, VL10, VL11, VL20, VL21, VL30; Via: VL40~VL43, VL50~VL53.

Claims

1. A laminate comprising multiple dielectric layers stacked together, having a first main surface and a second main surface facing each other, The input terminal, ground terminal, first output terminal, and second output terminal are arranged on the second main surface, A first filter circuit is connected between the input terminal and the first output terminal, and the first frequency band is used as the passband. The system includes a second filter circuit connected between the input terminal and the second output terminal, which has a passband of a second frequency band higher than the first frequency band, The first filter circuit is, It includes a first coil and a second coil connected in series between the input terminal and the first output terminal, The first coil is connected to the input terminal, The second coil is connected to the first output terminal, The second filter circuit is, A signal path connecting the input terminal and the second output terminal, and a third coil connected between them and the ground terminal, This includes a fourth coil connected between a position on the second output terminal side of the third coil in the signal path and the ground terminal, The first coil and the fourth coil are coils whose winding axis is in a first direction along the stacking direction of the laminate, The second coil and the third coil are coils whose winding axis is in a second direction intersecting the stacking direction, A filter device in which, when viewed from the stacking direction, at least a portion of the first coil and at least a portion of the fourth coil are arranged within a first region between the second coil and the third coil.

2. The filter device according to claim 1, wherein, when viewed from the first direction in a plan view, the winding direction of the first coil and the winding direction of the fourth coil are in opposite directions to each other.

3. The filter device according to claim 1, wherein, when viewed from the first direction in a plan view, the first coil does not overlap with the fourth coil.

4. The filter device according to any one of claims 1 to 3, wherein the distance from the first main surface to the first coil and the fourth coil in the first direction is greater than the distance from the first main surface to the second coil and the third coil in the first direction.

5. The filter device according to any one of claims 1 to 3, wherein, when viewed from the second direction in a plan view, at least a portion of the second coil overlaps with the third coil.

6. The inductance value of the first coil is greater than the inductance value of the second coil. The filter device according to any one of claims 1 to 3, wherein the inductance value of the fourth coil is greater than the inductance value of the third coil.

7. The filter device according to any one of claims 1 to 3, wherein at least one of the first coil and the fourth coil is located outside the first region.

8. Each of the first and fourth coils includes a plurality of flat electrodes arranged in different dielectric layers and a plurality of vias extending in the stacking direction. The first coil includes a first plate electrode and a second plate electrode, The filter device according to any one of claims 1 to 3, wherein some of the flat plates in the fourth coil are arranged in the dielectric layer between the first flat plate electrode and the second flat plate electrode.

9. Each of the first and fourth coils includes a plurality of flat electrodes arranged in different dielectric layers and a plurality of vias extending in the stacking direction. The filter device according to any one of claims 1 to 3, wherein in at least one of the first coil and the fourth coil, the ends of at least some of the planar plates among the plurality of planar plates included in the coil are located outside the opening of the second coil when viewed from the second direction.

10. The first filter circuit is, A first capacitor connected between the connection node between the first coil and the second coil and the ground terminal, The filter device according to any one of claims 1 to 3, further comprising a second capacitor connected in parallel with the first coil.

11. The second filter circuit is, A third capacitor connected to the aforementioned input terminal, A fourth capacitor connected between the third capacitor and the second output terminal, The system further includes a fifth capacitor connected between the fourth coil and the ground terminal, The filter device according to any one of claims 1 to 3, wherein the third coil is connected between the connection node between the third capacitor and the fourth capacitor and the ground terminal.

12. A high-frequency front-end circuit comprising a filter device according to any one of claims 1 to 3.

13. The high-frequency front-end circuit according to claim 12, further comprising a third filter circuit having a third frequency band different from the first frequency band and the second frequency band as its passband.

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