Switching circuit

Abstract

This device suppresses inrush current and surge voltage in switching circuits over a short period of time. [Solution] The switching circuit 1 has a first switching section 11 and a second switching section 12, each having a plurality of switch elements connected in series and corresponding drive circuits. A load circuit 14 is connected between the output terminal TMout and the other terminal of the second switching section 12. In the switching operation that switches the first switching section 11 and the second switching section 12 on / off at a first frequency, a ramp-up period is set during the initial on period of the first switching section 11. During the ramp-up period, the first switching section 11 is switched at a second frequency based on a timing signal generated based on the comparison result between a preset ramp-up signal Vcr2 and a triangular wave comparison signal Vtri2 with a second frequency higher than the first frequency.

Description

Technical Field

[0001] The present invention relates to a switching circuit.

Background Art

[0002] Conventionally, in a circuit having a switching element such as a converter or an inverter, in order to prevent damage to the switching element due to inrush current or surge voltage at startup, a soft start function may be provided.

[0003] A general soft start function prevents damage to the switching element by limiting the inrush current by limiting the duty ratio of the switch (the ratio of the time during which the switching element is on in the switching cycle) for a certain period from the start of startup (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0008] According to the present invention, inrush current and surge voltage can be suppressed in a short period of time. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a diagram showing a schematic configuration of a switching circuit according to an embodiment. [Figure 2] Figure 2 shows an example of the configuration of the switch elements in the first switching section and the second switching section. [Figure 3] Figure 3 is an explanatory diagram of the startup operation in a conventional example without a soft-start function. [Figure 4] Figure 4 is an explanatory diagram of the startup operation in a conventional example that incorporates a soft-start function. [Figure 5] Figure 5 is an explanatory diagram illustrating the relationship between the gate voltage Vgs and the surge voltage Vds. [Figure 6] Figure 6 illustrates the relationship between the gate resistance and the magnitude of the surge voltage peak. [Figure 7] Figure 7 is an explanatory diagram illustrating the relationship between gate resistance and the time change of surge voltage after startup. [Figure 8] Figure 8 is an explanatory diagram of an example of a switch element drive circuit in the timing signal output section of the embodiment. [Figure 9] Figure 9 shows the timing chart of the output waveforms for each section. [Figure 10] Figure 10 is a magnified view of the portion of Figure 9 from time 0s to 2μs. [Figure 11] Figure 11 is an explanatory diagram illustrating the relationship between ramp-up time and drive voltage Vgs. [Figure 12] Figure 12 is an explanatory diagram illustrating the relationship between ramp-up time and drive voltage Vgs when the frequency of the triangular wave comparison signal Vtri2 is set to a high value. [Figure 13] Figure 13 is an explanatory diagram illustrating an example of the second modified example. [Figure 14] Figure 14 shows another example of the configuration of the switch elements in the first switching section and the second switching section. [Modes for carrying out the invention]

[0010] An embodiment of the switching circuit according to the present invention will be described in detail below with reference to the drawings. However, the present invention is not limited to this embodiment.

[0011] Figure 1 is a diagram showing a schematic configuration of a switching circuit according to an embodiment. The switching circuit 1 shown in Figure 1 includes a first switching unit 11, a second switching unit 12, and a timing signal output unit 13.

[0012] One end of the first switching unit 11 and one end of the second switching unit are connected to the switching circuit 1. Also, in the switching circuit 1, the node Nin1 at the other end of the first switching unit 11 is connected to the voltage line (DC voltage source) on the side with a higher absolute value of the potential, and the node Nin2 at the other end of the second switching unit 12 is connected to the voltage line on the side with a lower absolute value of the potential.

[0013] As an example, in the switching circuit 1 shown in FIG. 1, the node Nin1 at the other end of the first switching unit 11 is connected to the negative power supply line (-E), and the node Nin2 at the other end of the second switching unit 12 is connected to the reference potential line, having a configuration of negative voltage output. The reference potential is the ground, which is set to 0V as an example.

[0014] The output terminal TMout is connected to the node Nout between one end of the first switching unit 11 and one end of the second switching unit 12.

[0015] The first switching unit 11 and the second switching unit 12 each have a switching element.

[0016] The timing signal output unit 13 outputs a timing signal t1 for controlling the on / off of the switching element constituting the first switching unit 11 to the first switching unit 11. Also, the timing signal output unit 13 outputs a timing signal t2 for controlling the on / off of the switching element constituting the second switching unit 12 to the second switching unit 12. In this case, the timing signal output unit 13 sets a ramp-up period (for example, 400 ns) during the first on period in the first switching unit 11, and in the ramp-up period, the first switching unit 11 is switched at the second frequency based on the timing signal t1 generated based on the comparison result between the preset ramp-up signal and the triangular wave comparison signal at the second frequency (for example, 20 MHz) higher than the first frequency (for example, 400 kHz).

[0017] In this case, the ramp-up signal used is a signal that increases linearly. Here, we will explain why a linearly increasing signal is used as the ramp-up signal. In this explanation, for the switching elements of the first switching unit 11 and the second switching unit 12, the terminal that is on the high-potential side when the switching unit to which each unit belongs is off will be referred to as the first terminal, the terminal that is on the low-potential side when it is off will be referred to as the second terminal, and the terminal to which the drive signal is input will be referred to as the third terminal. The timing signal is generated based on the comparison result between the ramp-up signal and the triangular wave comparison signal. Therefore, if the ramp-up signal is a linearly increasing signal, the signal width of the timing signal increases, and consequently, the on-duty cycle of the switching element with respect to the period of the second frequency also increases.

[0018] As a result, the proportion of the charging time in the charging and discharging of the parasitic capacitance between the first and second terminals of each switching element (or between the drain and source if an FET is used as the switching element) increases, which allows the voltage of each switching element to be increased.

[0019] In other words, by using a linearly increasing signal as the ramp-up signal, it is possible to suppress a rapid voltage rise in the voltage between the first terminal and the second terminal (or between the drain and source if an FET is used as the switching element) when the first switching unit 11 is turned on for the first time.

[0020] Furthermore, after the ramp-up period has elapsed, the timing signal output unit 13 switches the first switching unit 11 and the second switching unit 12 using timing signals t1 and t2. Here, the switching operation of the first switching unit 11 and the second switching unit 12 refers to the operation in which, when one switches from the ON state to the OFF state, the other switches from the OFF state to the ON state, and so on, complementaryly repeating the turn-on and turn-off operations.

[0021] Specifically, the first switching unit 11 and the second switching unit 12 perform a switching operation in which they complementaryly turn on and turn off at a first frequency (e.g., 400 kHz) that is higher than the third frequency, during a continuous operation period defined by a predetermined on-duty ratio (e.g., 10%) within a predetermined repeating period of a predetermined third frequency (e.g., 2 kHz). Furthermore, both the first switching unit 11 and the second switching unit 12 suspend their switching operations during a pause period defined by a predetermined off-duty ratio (for example, 90%).

[0022] In semiconductor manufacturing processes using semiconductor manufacturing equipment, the output control described above is sometimes referred to as PDM control (Pulse Density Modulation control).

[0023] The first frequency mentioned above can be set, for example, between 100kHz and 1MHz, and the duty cycle corresponding to the first frequency can be set in the range of 1% to 99%. Similarly, the third frequency mentioned above can be set, for example, between 0.01kHz and 50kHz, and the duty cycle corresponding to the third frequency can be set in the range of 1% to 99%. In this case, the third frequency is set to a lower frequency than the first frequency. However, the frequencies are not limited to those mentioned above. For example, the third frequency could be set within the range of 0.1 kHz to 100 kHz, or the first frequency could be set within the range of 100 kHz to several tens of MHz.

[0024] Furthermore, the first switching unit 11 and the second switching unit 12 may be provided with a dead time during switching so that they are both turned off at the same time.

[0025] During continuous operation, the switching circuit 1, through the switching operations of the first switching unit 11 and the second switching unit 12, repeatedly performs complementary operations and outputs a pulse voltage from the output terminal TMout in which a reference potential and a negative potential alternate.

[0026] Figure 2 shows an example of the configuration of the switch elements in the first switching section and the second switching section.

[0027] Figure 2 shows an example where a FET (Field Effect Transistor) is used as the switching element, but it is also possible to use other switching devices such as IGBTs (Insulated Gate Bipolar Transistors).

[0028] In the example shown in Figure 2, the first switching unit 11 has eight FETs 100-9 to 100-18 connected in series. These FETs 100-9 to 100-18 are turned on / off based on the timing signal t1 of the timing signal output unit 13.

[0029] Furthermore, the second switching unit 12 has eight FETs 100-1 to 100-9 connected in series. These FETs 100-1 to 100-9 are controlled on / off based on the timing signal t2 of the timing signal output unit 13.

[0030] In the example shown in Figure 2, the number of FETs in the first switching section 11 and the second switching section 12 is described as 8 and 8 respectively, totaling 16 FETs, but the number of FETs is not limited to this. As will be described later, the first switching section 11 may be composed of multiple FETs, and the second switching section 12 may have fewer FETs as switching elements than the first switching section 11 if FETs with high voltage resistance are used.

[0031] As shown in Figure 2, the source node Nin1 of FET100-16 is connected to the negative power supply line (-E), and the drain node Nin2 of FET100-1 is connected to the reference potential line. A load circuit 14 is connected between the output terminal TMout and the reference potential line. The load circuit 14 is, for example, a transformer or a plasma generation circuit. The configuration of the load circuit 14 is not particularly limited. It may be a load circuit other than a transformer or a plasma generation circuit.

[0032] When the timing signal output unit 13 first turns on the FETs 100-9 to FET 100-16 that constitute the first switching unit 11, the timing signal output unit 13 sets a ramp-up period (for example, 400 ns) during the initial on period of the first switching unit 11. Here, the initial ON period refers to the period of the first frequency (e.g., 400 kHz) in the first switching unit 11 (e.g., a period of 2.5 μs).

[0033] Furthermore, during the ramp-up period, the timing signal output unit 13 switches the first switching unit 11 at the second frequency based on a timing signal t1 generated based on the comparison result between a preset ramp-up signal and a triangular wave comparison signal of a second frequency (e.g., 20MHz) that has a higher frequency than the first frequency (e.g., 400kHz).

[0034] After the ramp-up period, the timing signal output unit 13 outputs a timing signal t1 to simultaneously turn on or off the FETs 100-9 to FET 100-16 that constitute the first switching unit 11 at a first frequency.

[0035] On the other hand, the timing signal output unit 13 outputs a timing signal t2 to simultaneously turn on FETs 100-1 to FET 100-8 of the second switching unit 12 when FETs 100-9 to FET 100-16 constituting the first switching unit 11 are simultaneously turned off after the ramp-up period.

[0036] Furthermore, when FETs 100-9 to FET 100-16, which constitute the first switching section 11, are simultaneously turned on, a timing signal t2 is output to simultaneously turn off FETs 100-1 to FET 100-8 of the second switching section 12.

[0037] Furthermore, when the system enters a shutdown period and the switching operations of the first switching unit 11 and the second switching unit 12 are suspended, all FETs 100-9 to FET 100-16 constituting the first switching unit 11 and FETs 100-1 to FET 100-8 of the second switching unit 12 are turned off.

[0038] Here, we will explain the factors that cause surge voltages during startup. First, let's explain the conventional case, which does not have a soft-start function. Figure 3 is an explanatory diagram of the startup operation in a conventional example without a soft-start function. Figure 3(A) shows, as an example, the switching operation when the switching frequency is 400 kHz, with an on-duty cycle of 10% over a repetition period of 2 kHz.

[0039] In this case, a 400kHz switching operation is performed 20 times during a period with a 10% on-duty cycle of the repetition period. Figure 3(B) shows an enlarged view of the waveforms for the first to fourth 400kHz switching operations, which correspond to the portion indicated by the window frame W in Figure 3(A), out of 20 400kHz switching operations.

[0040] In this case, the first waveform during the 400kHz switching operation corresponds to the waveform at startup after a period of inactivity.

[0041] As shown in Figure 3(B), when the input voltage is DC-3kV, in the first switching operation at 400kHz, when FETs 100-9 to FET 100-16, which constitute the first switching unit 11, switch to the ON state, the surge voltage applied to FETs 100-1 to FET 100-8, which constitute the second switching unit 12, becomes approximately twice the voltage during steady-state operation, which is -3kV, resulting in a voltage of -6.2kV.

[0042] In contrast, as shown in Figure 3(B), when the input voltage is DC-3kV, the system transitions to steady-state operation from the second cycle onward in the 400kHz switching operation. Therefore, the voltage applied to FET100-1 to FET100-8, which constitute the second switching section 12, is -3kV from the second to the 20th cycle of the 400kHz switching operation. In other words, according to conventional examples, an inrush current was generated at startup every 2kHz interval, and consequently, a surge voltage was generated every 2kHz repetition period.

[0043] In order to cope with the surge voltage, which is more than twice the input voltage, generated by the first inrush current that occurs with each 2kHz repetition period, it was necessary to use high-voltage FETs as the FETs constituting the first switching section 11 and the second switching section 12, or to increase the number of FETs in series to reduce the voltage actually applied to each FET.

[0044] Figure 4 is an explanatory diagram of the startup operation in a conventional example that incorporates a soft-start function. Figure 4 shows an enlarged view of the waveforms for the first seven repetitions (1st to 7th) of a 2kHz repetition period when using the soft-start function.

[0045] As shown in Figure 4, when using the soft-start function, the peak voltage gradually increases in multiple stages, thus suppressing surge voltage. However, in the example shown in Figure 4, it takes as many as six stages to transition to a steady state, which presents a problem with the rise time.

[0046] The following are considered to be the factors that cause surge voltages during startup. Since the drain-source voltage Vds of FETs 100-1 to FETs 100-8, which constitute the second switching section 12 on the high-side, is 0V immediately before startup, it can be inferred that an input voltage of DC-3kV is applied to FETs 100-9 to FETs 100-16, which constitute the first switching section 11 on the low-side.

[0047] By simultaneously turning on FETs 100-9 to FET 100-16, which constitute the first switching section 11 on the low side, the charge stored in the drain-source voltage Vds (output capacitance Coss) of each of FETs 100-9 to FET 100-16 becomes zero, and at the same time, the second switching section 12 on the high side is charged via the power supply line.

[0048] In this case, the discharge path contains inductance present in the wiring and devices, which is thought to resonate with the drain-source capacitance (including parasitic capacitance Coss and external snubber capacitors), resulting in a large surge voltage.

[0049] Therefore, in this embodiment, a gate resistor Rg is provided at the gate terminal of each FET as a switching element, and this gate resistor Rg and the input capacitance Ciss of the FET are considered as an RC filter.

[0050] Then, to ensure that filtering is reliably performed by this RC filter, a pulse signal is input with a PWM period of less than half the time constant of the RC filter, controlling the gate-source voltage Vgs of the FET to rise slowly.

[0051] By controlling it in this way, the on-resistance of the FET as a switching element can be maintained at a high level while the switching operation is performed, thereby suppressing inrush current and surge voltage.

[0052] Here, we will explain the relationship between the gate voltage Vgs and surge voltage Vds of a FET as a switching element.

[0053] Figure 5 is an explanatory diagram illustrating the relationship between the gate voltage Vgs and the surge voltage Vds. Figure 5(A) shows the relationship between the gate voltage Vgs and surge voltage Vds during the rising edge of the gate waveform, and Figure 5(B) shows the relationship between the gate voltage Vgs and surge voltage Vds during the falling edge of the gate waveform. In both Figure 5(A) and Figure 5(B), the vertical axis represents the gate voltage Vgs, and the horizontal axis represents time.

[0054] As shown in Figure 5(A), increasing the gate resistor value from 1.5Ω → 3Ω → 6Ω → ... → 15Ω → 20Ω results in a more gradual rise in the gate voltage Vgs.

[0055] Similarly, as shown in Figure 5(B), increasing the gate resistor value from 1.5Ω → 3Ω → 6Ω → ... → 15Ω → 20Ω results in a more gradual fall of the gate voltage Vgs.

[0056] This increases the transition time, which is the time required to pass through the active region in the drain current Id and drain-source voltage Vds characteristics of the FET as a switching element. Consequently, the time required for the FET's on-resistance Ron to change from relatively high resistance to relatively low resistance is also increased.

[0057] As a result, the inrush current flowing between the drain and source of the FET can be suppressed, and consequently, the surge voltage caused by the inrush current can be suppressed.

[0058] On the other hand, because the transition time is longer, the switching loss (= drain current Id × drain-source voltage Vds × transition time) increases, but the breakdown of the FET's breakdown voltage can be suppressed.

[0059] Figure 6 illustrates the relationship between the gate resistance and the magnitude of the surge voltage peak. Figure 7 is an explanatory diagram illustrating the relationship between gate resistance and the time change of surge voltage after startup. As shown in Figure 6, as the resistance value of the gate resistor Rg is increased from 1.5Ω to 20Ω, the peak surge voltage Vpk decreases from 430V to 236V when the input voltage is 200V.

[0060] As shown in Figure 7, it can be seen that as the resistance value of the gate resistor Rg is increased from 1.5Ω → 3Ω → 6Ω → ... → 15Ω → 20Ω, the surge voltage decreases and the time required for the surge voltage to converge also decreases.

[0061] Next, a more specific embodiment will be described. Figure 8 is an explanatory diagram of an example of a switch element drive circuit in the timing signal output section of the embodiment.

[0062] The switch element drive circuit 20 includes a first drive signal generation circuit 21, a second drive signal generation circuit 22, an AND circuit 23, and a driver circuit 24. Of these, the driver circuit 24 functions as a drive circuit and is provided in correspondence with each of the FETs 100-9 to 100-16.

[0063] The first drive signal generation circuit 21 includes a first comparator 31, a power supply (not shown), an oscillator circuit and signal generation circuits (not shown), etc. The first comparator 31 receives a switching reference signal Vcr1 as input to its non-inverting input terminal and a 400kHz triangular wave comparison signal Vtri1 as input to its inverting input terminal, and outputs the comparison result as a first gate-source voltage signal Vgs1.

[0064] The second drive signal generation circuit 22 includes a second comparator 32, a power supply (not shown), and an oscillator circuit and signal generation circuit (not shown). The second comparator 32 receives a 400 ns ramp-up signal Vcr2 at its non-inverting input terminal and a 20 MHz triangular wave comparison signal Vtri2 at its inverting input terminal, and outputs the comparison result as a second gate-source voltage signal Vgs2.

[0065] The AND gate 23 receives a first gate-source voltage signal Vgs1 at one input terminal and a second gate-source voltage signal Vgs2 at the other input terminal. It takes a logical AND operation between the first gate-source voltage signal Vgs1 and the second gate-source voltage signal Vgs2 and outputs the third gate-source voltage signal Vgs3 to the driver gate 24.

[0066] The driver circuit 24 includes a first buffer circuit 41, a NOT circuit 42, a second buffer circuit 43, a first NMOS transistor 44, a second NMOS transistor 45, a first diode 46, and a second diode 47. In the above configuration, the first NMOS transistor 44 and the second NMOS transistor 45 work together to function as an inverter for the output of the AND circuit 23.

[0067] The first buffer circuit 41 has an input terminal connected to the output terminal of the AND circuit 23, and outputs a third gate-source voltage signal Vgs3 to the gate terminal of the first NMOS transistor 34 via its output terminal.

[0068] The NOT circuit 42 has its input terminal connected to the output terminal of the AND circuit 23, and outputs an inverted gate-source voltage signal / Vgs3, which is obtained by inverting the third gate-source voltage signal Vgs3, to the input terminal of the second buffer circuit 43 via its output terminal.

[0069] The second buffer circuit 43 has its input terminal connected to the output terminal of the NOT circuit 42, and outputs an inverting third gate-source voltage signal / Vgs3 to the gate terminal of the second NMOS transistor 45 via its output terminal.

[0070] As a result, the first NMOS transistor 44 and the second NMOS transistor 45 alternate between being on and off based on the third gate-source voltage signal Vgs3, with one being on and the other off.

[0071] In this case, when the first NMOS transistor 44 is ON, the voltage of the power supply Vcc is applied as a drive voltage to the gate terminal of the corresponding FET via an RC filter consisting of a gate resistor Rg and an input capacitance Ciss.

[0072] Furthermore, when the second NMOS transistor 45 is ON, the power supply voltage Vee is applied as a drive voltage to the gate terminal of the corresponding FET via an RC filter consisting of a gate resistor Rg and an input capacitance Ciss.

[0073] More specifically, if the gate resistor Rg = 10Ω and the input capacitance Ciss = 10000pF for FET100-9 to FET100-16, the time constant τ of the RC filter becomes 100ns.

[0074] Next, we will explain the operation in more detail. In the following explanation, the ramp-up period will be assumed to be 400 ns, the first frequency to be 400 kHz, and the second frequency to be 20 MHz.

[0075] In this case, the second frequency is set to a frequency higher than the frequency corresponding to the time constant τ of the RC filter (10 MHz in the example above). This is to prevent the component of the second frequency from being input to the gate of the FET, which acts as a switching element, and causing adverse noise effects.

[0076] Figure 9 shows the timing chart of the output waveforms for each section. Figure 10 is a magnified view of the portion of Figure 9 from time 0s to 2μs. In Figures 9 and 10, time = 0s corresponds to the timing of the start of the transition from the pause period to the continuous operation period in the first switching unit 11 and the second switching unit 12.

[0077] Figures 9(A) and 10(A) are explanatory diagrams of the switching reference signal Vcr1 and the 400kHz triangular wave comparison signal Vtri3, which are input signals to the first comparator 31, with the vertical axis representing voltage and the horizontal axis representing time.

[0078] At time = 0s, when the transition from the pause period to the continuous operation period begins, the first comparator 31 of the first drive signal generation circuit 21 receives a switching reference signal Vcr1 at the non-inverting input terminal and a 400kHz triangular wave comparison signal Vtri1 at the inverting input terminal.

[0079] As a result, the first comparator 31 compares the voltage of the switching reference signal Vcr1 with the voltage of the triangular wave comparison signal Vtri1, and outputs a first gate-source voltage signal Vgs1 of the "H" level to one input terminal of the AND circuit 23 during the period when the voltage of the switching reference signal Vcr1 is higher than that of the triangular wave comparison signal Vtri1.

[0080] Figures 9(B) and 10(B) are explanatory diagrams of the output signal Vgs1 of the first comparator 31, where the vertical axis represents voltage and the horizontal axis represents time.

[0081] In the example shown in Figure 10(B), during the period from time = 0s to time = t2, the first comparator 31 outputs a first gate-source voltage signal Vgs1 at the H'' level to the AND gate 23.

[0082] Then, from time t2 onward, the first comparator 31 outputs a first gate-source voltage signal Vgs1 of the "L" level to the AND circuit 23.

[0083] Figures 9(C) and 10(C) are explanatory diagrams of the ramp-up signal Vcr2 and the 20MHz triangular wave comparison signal Vtri2, which are input signals to the second comparator 32, with the vertical axis representing voltage and the horizontal axis representing time.

[0084] As described above, the second comparator 32 of the second drive signal generation circuit 22 receives a 400ns ramp-up signal Vcr2 at its non-inverting input terminal and a 20MHz triangular wave comparison signal Vtri2 at its inverting input terminal.

[0085] As a result, the second comparator 32 compares the voltage of the ramp-up signal Vcr2 with the voltage of the triangular wave comparison signal Vtri1, and outputs a second gate-source voltage signal Vgs2 at the "H" level to the other input terminal of the AND circuit 23 during the period when the voltage of the ramp-up signal Vcr2 is higher than that of the triangular wave comparison signal Vtri2.

[0086] Figures 9(D) and 10(D) are explanatory diagrams of the output signal Vgs2 of the second comparator 32, where the vertical axis represents voltage and the horizontal axis represents time. In the example shown in Figure 10(D), during the period from time = 0s to time = t1, the second comparator 32 outputs a second gate-source voltage signal Vgs2 at the "H" level, with a gradually increasing pulse width, to the AND circuit 23. Then, from time t1 onward, a second gate-source voltage signal Vgs2 at the "H" level is always output to the AND circuit 23.

[0087] The AND gate 23 takes the logical AND of the input first gate-source voltage signal Vgs1 and the second gate-source voltage signal Vgs2, and outputs the third gate-source voltage signal Vgs3 to the driver gate 24.

[0088] Figures 9(E) and 10(E) are explanatory diagrams of the third gate-source voltage signal Vgs3, which is the output signal of the AND gate 23, with the vertical axis representing voltage and the horizontal axis representing time.

[0089] In the example shown in Figure 10(E), during the period from time = 0s to time = t1, the AND gate 23 outputs a third gate-source voltage signal Vgs3 to the driver circuit 24, which is also at an "H" level and has a gradually increasing pulse width, similar to the second gate-source voltage signal Vgs2, because the first gate-source voltage signal Vgs1 is always at an "H" level.

[0090] Then, during the period from time t1 to time t2, the AND gate 23 outputs a third gate-source voltage signal Vgs3 at the "H" level to the driver circuit 24. Furthermore, from time t2 onward, the first gate-source voltage signal Vgs1 becomes "L" level, so the AND gate 23 outputs a third gate-source voltage signal Vgs3 of "L" level to the driver gate 24.

[0091] The third gate-source voltage signal Vgs3 output by the AND gate 23 is then input to the first buffer gate 41 and the NOT gate 42 of the driver gate 24.

[0092] The first buffer circuit 41 outputs the input third gate-source voltage signal Vgs3 directly to the gate terminal of the first NMOS transistor 44. The NOT circuit 42 inverts the input third gate-source voltage signal Vgs3 and outputs the inverted gate-source voltage signal / Vgs3 to the input terminal of the second buffer circuit 43.

[0093] The second buffer circuit 43 outputs the input inverting third gate-source voltage signal / Vgs3 directly to the gate terminal of the second NMOS transistor 45.

[0094] As a result, the first NMOS transistor 44 and the second NMOS transistor 45 alternate between being on and off based on the third gate-source voltage signal Vgs3 and the inverted third gate-source voltage signal / Vgs3, with one being on and the other off.

[0095] In this case, when the first NMOS transistor 44 is ON, the voltage of the high-potential power supply Vcc becomes the output signal of the driver circuit 24 and is applied to the gate terminal of the corresponding FET as a drive voltage Vgs via an RC filter consisting of a gate resistor Rg and an input capacitance Ciss.

[0096] Furthermore, when the second NMOS transistor 45 is ON, the voltage of the low-potential power supply Vee becomes the output signal of the driver circuit 24 and is applied to the gate terminal of the corresponding FET as a drive voltage Vgs via an RC filter consisting of a gate resistor Rg and an input capacitance Ciss.

[0097] Figures 9(F) and 10(F) are explanatory diagrams of the drive voltage Vgs (gate-source voltage signal Vgs) applied to the gate terminal of the corresponding FET, with the vertical axis representing voltage and the horizontal axis representing time. As described above, a gate resistor Rg is connected between the driver circuit 24 and the corresponding FET, so the output signal of the driver circuit 24 is applied to the gate terminal of the corresponding FET as a drive voltage Vgs via an RC filter consisting of the gate resistor Rg and the input capacitance Ciss. For example, if the gate resistor Rg = 10Ω and the input capacitance Ciss = 10000pF for FET100-9 to FET100-16, the gate resistor Rg and input capacitance Ciss will work together to function as a low-pass filter with a time constant τ = 100ns.

[0098] As a result, the rise of the drive voltage Vgs is sluggish, and during the period from time 0s to time t1, the drive voltage Vgs increases slowly in a step-like manner.

[0099] Then, once time t1 is exceeded, the third gate-source voltage signal Vgs3 remains at a constant "H" level, so the drive voltage Vgs gradually rises and eventually becomes a constant voltage equal to the voltage of the high-potential power supply Vcc.

[0100] Furthermore, when time t2 is reached, the third gate-source voltage signal Vgs3 transitions to the "L" level, so the drive voltage Vgs gradually decreases and eventually becomes a constant voltage at the voltage of the low-potential power supply Vee.

[0101] As described above, according to this embodiment, a gate resistor Rg is inserted between each driver circuit 24 of the first switching unit 11 and each FET 100-9 to 100-16 which serve as switching elements, and in cooperation with the input capacitance Ciss of each FET 100-9 to 100-16, it functions as a low-pass filter.

[0102] Incidentally, in the initial state, the first switching unit 11 is in the off state and the second switching unit 12 is in the on state. Therefore, FETs 100-1 to FETs 100-8 that make up the second switching unit 12 are in the on state, so the drain-source connection is energized, and the output terminal TMout is at the same potential as the reference potential (for example, 0V).

[0103] In contrast, since FETs 100-8 to 100-16, which constitute the first switching section 11, are in the off state, a voltage E equivalent to the potential difference between 0V and the power supply line's -EV is applied across the first switching section 11, and it is thought that charge is accumulated in the parasitic capacitance (drain-source parasitic capacitance) of FETs 100-9 to 100-16, which constitute the first switching section 11.

[0104] In this state, if the second switching unit 12 is turned off and the first switching unit 11 is immediately turned on, the potential of the output terminal TMout will suddenly transition from the reference potential (0V) to the potential of the power supply line (-E), and the charge stored in the parasitic capacitances of FETs 100-1 to FETs 100-8 that constitute the first switching unit 11 will be discharged all at once.

[0105] Incidentally, in the initial state, since no current is yet flowing through the load circuit 14, an inrush current will be generated along the path including the negative power supply line of the power supply E, flowing in the direction of the reference potential from the first switching unit 11 to the second switching unit 12.

[0106] However, as described above, in this embodiment, gate resistors Rg are inserted between each driver circuit 24 of the first switching section 11 and each FET 100-9 to 100-16 as switching elements, and in cooperation with the input capacitance Ciss of each FET 100-9 to 100-16, they function as a low-pass filter, so that inrush current can be suppressed. For example, the parasitic capacitance C of FETs 100-1 to FET 100-8 constituting the second switching section 12 and the inductance L(L1+L2) (see Figure 2) of the wiring connected to the power supply E resonate in an LC circuit, and the surge voltage associated with resonance does not cause the FETs to exceed their breakdown voltage and be damaged.

[0107] Subsequently, when the second switching unit 12 turns off and the first switching unit 11 turns on, the potential of the output terminal TMout becomes -E. Therefore, a voltage E, which is 0V and -EV of the power supply line, is applied to both ends of the second switching unit 12, and it is thought that the parasitic capacitance (drain-source parasitic capacitance) of FETs 100-1 to FETs 100-8 that constitute the second switching unit 12 is charged.

[0108] Therefore, when the first switching unit 11 transitions to the off state and the second switching unit 12 transitions to the on state, the potential of the output terminal TMout changes abruptly from the potential of the power supply line (-E) to the reference potential (0V), and the charge stored in the parasitic capacitances of FETs 100-1 to FETs 100-8 that constitute the second switching unit 12 is discharged all at once.

[0109] This discharge charges the parasitic capacitance of each switch element in the first switching unit 11. However, when the first switching unit 11 transitions to the off state, the charging time for the parasitic capacitance of each switch element is determined by the load current, so the magnitude of the surge voltage is smaller than the magnitude of the surge voltage immediately after the switching circuit 1 is started up.

[0110] Therefore, when the first switching unit 11 is turned on again, the charge stored in the parasitic capacitances of FETs 100-9 to FETs 100-16 that constitute the first switching unit 11 is discharged, and the parasitic capacitances of FETs 100-1 to FETs 100-8 that constitute the second switching unit 12 are charged.

[0111] However, since current (load current) is already flowing through the load circuit 14 at this point, a large surge voltage does not occur, such as when the first switching unit 11 is turned on immediately after the switching circuit 1 is started up. Therefore, the FET will not be damaged because the surge voltage associated with resonance exceeds its breakdown voltage.

[0112] Therefore, according to the switching circuit 1 of this embodiment, the inrush current and surge voltage that occur during the initial ON period can be suppressed in a short time, and damage to the FET can be prevented.

[0113] As mentioned above, a resistor (gate resistor Rg) is inserted between each driver circuit 24 (which acts as a drive circuit) and each switch element (FET100-8 to FET100-16). Since the input capacitance of each switch element can be considered as an RC filter in the path from each gate drive circuit to each switch element, the rise time of the voltage when each switch element is turned on and the fall time of the voltage when it is turned off can be adjusted by adjusting the resistance value of the resistor.

[0114] Generally, a lower resistance value results in shorter voltage rise and fall times, but a larger surge voltage. Conversely, a higher resistance value results in a smaller surge voltage, but longer voltage rise and fall times. Therefore, in actual devices, it is preferable to determine the resistance value while considering the balance between these two factors.

[0115] Next, a modified example of the embodiment will be described. [1] First variation Figure 11 is an explanatory diagram illustrating the relationship between ramp-up time and the drive voltage Vgs of the driver circuit. Figure 11(A) is an explanatory diagram illustrating the relationship between the waveform of the ramp-up signal and the triangular wave comparison signal Vtri2 when the ramp-up time is varied to 0ns, 200ns, 400ns, 600ns, 800ns, and 1000ns. This is a diagram.

[0116] In Figure 11(A), the triangular wave comparison signal Vtri2 has a frequency of 20MHz, and the ramp-up signal Vcr2_01 is the ramp-up signal waveform when the ramp-up time is 0ns, i.e., when there is no ramp-up. Similarly, the ramp-up signal Vcr2_02 is the ramp-up signal waveform when the ramp-up time is 200ns, the ramp-up signal Vcr2_03 is the ramp-up signal waveform when the ramp-up time is 400ns, the ramp-up signal Vcr2_04 is the ramp-up signal waveform when the ramp-up time is 600ns, the ramp-up signal Vcr2_05 is the ramp-up signal waveform when the ramp-up time is 800ns, and the ramp-up signal Vcr2_06 is the ramp-up signal waveform when the ramp-up time is 1000ns.

[0117] Figure 11(B) is an explanatory diagram showing the drive voltage Vgs when the ramp-up time is varied to 0ns, 200ns, 400ns, 600ns, 800ns, and 1000ns. In Figure 11(B), the drive voltage Vgs_01 is the drive voltage Vgs when the ramp-up time is 0ns, i.e., there is no ramp-up. Similarly, drive voltage Vgs_02 is the drive voltage Vgs when the ramp-up time is 200ns, drive voltage Vgs_03 is the drive voltage Vgs when the ramp-up time is 400ns, drive voltage Vgs_04 is the drive voltage Vgs when the ramp-up time is 600ns, drive voltage Vgs_05 is the drive voltage Vgs when the ramp-up time is 800ns, and drive voltage Vgs_06 is the drive voltage Vgs when the ramp-up time is 1000ns. As the ramp-up time is increased from 0ns to 200ns to 400ns to 600ns to 800ns to 1000ns, the voltage change of the drive voltage Vgs per unit time becomes smaller, and it can be predicted that the inrush current will be reduced, and consequently the surge voltage will be reduced, as in the embodiment described above. However, as shown in Figure 11(B), as the ramp-up time increases, the waveform of the drive voltage Vgs becomes more jagged, with more step-like portions, and the smoothness of the waveform is lost, resulting in a loss of smoothness in the voltage waveform supplied to the load circuit. Therefore, by setting the frequency of the triangular wave comparison signal Vtri2 at the first startup after a period of inactivity to a higher value (for example, 100 MHz), it is thought that the waveform of the drive voltage Vgs can be smoothed, thereby suppressing the impact on the load circuit.

[0118] Figure 12 is an explanatory diagram illustrating the relationship between ramp-up time and drive voltage Vgs when the frequency of the triangular wave comparison signal Vtri2 is set to a high value. Figure 12(A) is an explanatory diagram illustrating the relationship between the waveform of the ramp-up signal and the triangular wave comparison signal Vtri2 when the ramp-up time is varied to 0ns, 200ns, 400ns, 600ns, 800ns, and 1000ns.

[0119] In Figure 12(A), the triangular wave comparison signal Vtri2 has a frequency of 100 MHz, and the ramp-up signal Vcr2_01 is the ramp-up signal waveform when the ramp-up time is 0 ns, i.e., when there is no ramp-up. Similarly, the ramp-up signal Vcr2_02 is the ramp-up signal waveform when the ramp-up time is 200 ns, the ramp-up signal Vcr2_03 is the ramp-up signal waveform when the ramp-up time is 400 ns, the ramp-up signal Vcr2_04 is the ramp-up signal waveform when the ramp-up time is 600 ns, the ramp-up signal Vcr2_05 is the ramp-up signal waveform when the ramp-up time is 800 ns, and the ramp-up signal Vcr2_06 is the ramp-up signal waveform when the ramp-up time is 1000 ns.

[0120] Figure 12(B) is an explanatory diagram illustrating the relationship between the drive voltage Vgs and the ramp-up time when the ramp-up time is varied to 0ns, 200ns, 400ns, 600ns, 800ns, and 1000ns. In Figure 12(B), the drive voltage Vgs_01 is the drive voltage Vgs when the ramp-up time is 0ns, i.e., there is no ramp-up. Similarly, drive voltage Vgs_02 is the drive voltage Vgs when the ramp-up time is 200ns, drive voltage Vgs_03 is the drive voltage Vgs when the ramp-up time is 400ns, drive voltage Vgs_04 is the drive voltage Vgs when the ramp-up time is 600ns, drive voltage Vgs_05 is the drive voltage Vgs when the ramp-up time is 800ns, and drive voltage Vgs_06 is the drive voltage Vgs when the ramp-up time is 1000ns. As the ramp-up time is increased from 0ns to 200ns to 400ns to 600ns to 800ns to 1000ns, the voltage change of the output signal per unit time decreases, reducing the inrush current and, consequently, the surge voltage, similar to the embodiment described above. Furthermore, the frequency of the triangular wave comparison signal Vtri2 is 100MHz, which is five times higher than in the case of Figure 11(B). As a result, compared to the case of Figure 11(B), the jagged portion of the waveform, which is the stepped part of the drive voltage Vgs waveform, is improved, and the smoothness of the waveform is clearly increased. The voltage waveform supplied to the load circuit is also smoother and closer to an analog waveform. Therefore, compared to the case in Figure 11(B), the waveform of the drive voltage Vgs can be made even smoother, the inrush current can be further reduced, and the effect of surge voltage on the load circuit can be suppressed.

[0121] [2] Second variation In the embodiments described above, the ramp-up signal was defined as a signal whose value (voltage value) increases linearly. However, it is not limited to this, and it is also possible to set a signal with an arbitrary waveform that temporarily maintains its value during the ramp-up period, or a ramp-up signal that temporarily decreases in the middle of the ramp-up period. This allows for more favorable voltage control based on the actual surge voltage generation conditions.

[0122] Figure 13 is an explanatory diagram illustrating an example of the second modified example. As shown in Figure 13(A), the ramp-up signal Vcr2 in the second modified example increases linearly during the period from time = 0s to time = t11.

[0123] As a result, as shown in Figures 13(B) and 13(C), the second gate-source voltage signal Vgs2 and the third gate-source voltage signal Vgs3 repeatedly transition to the "H" level and to the "L" level, while the pulse width of the "H" level gradually increases. Furthermore, the predetermined voltage is maintained during the period from time t11 to time t12.

[0124] Therefore, as shown in Figures 13(B) and 13(C), the second gate-source voltage signal Vgs2 and the third gate-source voltage signal Vgs3 repeatedly transition to the "H" level and to the "L" level, while maintaining a constant pulse width at the "H" level.

[0125] Then, the period from time t12 to time t13 increases linearly again, and upon reaching time t13, the ramp-up period ends. As a result, as shown in Figures 13(B) and 13(C), the second gate-source voltage signal Vgs2 and the third gate-source voltage signal Vgs3 repeatedly transition to the "H" level and to the "L" level, and the pulse width of the "H" level gradually increases again until the end of the ramp-up period.

[0126] As a result, as shown in Figure 13(D), the waveform of the drive voltage Vgs shows a gradual increase in a step-like manner during the period from time = 0s to time = t11, and during the period from time = t11 to time t12, although the voltage still increases gradually due to the filtering effect of the gate resistor Rg and input capacitance Ciss, the rate of increase is smaller. Also, during this period, current flows through the load circuit 14. Then, from time t12 onward, the voltage increases again in a stepwise manner, gradually becoming a constant voltage.

[0127] Therefore, according to the second modification, the current is suppressed in the initial stage when the inrush current is likely to be large, and the output of the driver circuit is increased again after the current starts to flow into the load circuit 14. This suppresses the inrush current and, consequently, reliably reduces the impact of the surge voltage on the load circuit 14. As mentioned above, setting a fixed period of time during the ramp-up period can prevent the generation of large surge voltages. This allows for more favorable voltage control based on the actual surge voltage generation conditions. Furthermore, if the ramp-up signal is a signal with any waveform, the voltage rise during the initial ON phase in the first switching section can be freely set.

[0128] [3] Third variation In the above embodiment, the configuration includes a first switching section and a second switching section with switch elements connected in series, and the output terminal is connected to a load circuit, and any configuration in which the voltage (absolute value) at the output terminal gradually increases is applicable. This embodiment is not limited to the configuration shown as an example for switching circuit 1, and may be modified as appropriate.

[0129] For example, as shown in Figure 14, a switching circuit 1 with a positive voltage output may also be used. Figure 14 shows another example of the configuration of the switch elements in the first and second switching sections, and illustrates an example of the configuration of a switching circuit 1 with a positive voltage output. In the case of a positive voltage output, node Nin1 at the other end of the first switching section 11 is connected to the positive power supply line (+E), and node Nin2 at the other end of the second switching section 12 is connected to a reference potential (0V as an example). The configuration of the FETs in the first switching section 11 and the second switching section 12 is the same as in the configuration for a negative voltage output. In other words, even in a positive voltage output configuration, similar to a negative voltage output configuration, for example, a capacitor 200 can be provided at the FET 100-9 of the first switching unit 11, and a ramp-up period (e.g., 400 ns) can be set during the initial ON period of the first switching unit 11. During the ramp-up period, the first switching unit 11 can be switched at the second frequency based on a timing signal t1 generated based on the comparison result between a preset ramp-up signal and a triangular wave comparison signal of a second frequency (e.g., 20 MHz) with a frequency higher than the first frequency (e.g., 400 kHz). The same effects as in a negative voltage output configuration can be obtained even in such a positive voltage output configuration. Note that Figure 14 omits the illustration of the inductance of the wiring connected to power supply E (corresponding to L1 and L2 in Figure 2).

[0130] [4] Fourth variation The number of FETs in the first switching section 11 and the second switching section 12 may be determined as appropriate depending on the circuit and voltage rating used. At a minimum, the number of FETs in the first switching section 11 should be multiple, and the number of FETs in the second switching section 12 is not limited as long as they have sufficient voltage rating.

[0131] Although embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. For example, each switching element is not limited to FETs; other switching devices such as IBGTs (Insulated Gate Bipolar Transistors) can be used. [Explanation of Symbols]

[0132] 1. Switching Circuit 11. First Switching Section 12. Second Switching Section 13 Timing signal output section 14 Load circuit 20 Switch element drive circuit 21 First drive signal generation circuit 22 Second drive signal generation circuit 23 AND gate 24 Driver Circuits 31 First Comparator 32 Second Comparator 33. Second Buffer Circuit 34. First NMOS Transistor 35. Second NMOS Transistor 41 First Buffer Circuit 42 NOT circuit 43. Second Buffer Circuit 44. First NMOS Transistor 45. Second NMOS transistor 46. ​​First Diode 47. Second Diode 100-1~100-16 FET L1, L2 Inductance Rg gate resistor TMout output terminal Vcc High potential side power supply Vcr1 Switching reference signal VCR2 ramp-up signal Vee Low potential side power supply Vgs1 First gate-source voltage signal Vgs2 Second gate-source voltage signal Vgs3 Third Gate-Source Voltage Signal Vgs output signal Vtri1 Triangular wave comparison signal Vtri2 triangular wave comparison signal Vtri3 triangular wave comparison signal

Claims

1. A first switching unit having a plurality of switch elements connected in series and a drive circuit corresponding to each of the plurality of switch elements, A second switching unit, one end of which is connected to one end of the first switching unit, and which has at least one switch element and a corresponding drive circuit, A timing signal output unit that outputs on / off timing signals for each switch element of the first switching unit, It has, A resistor is inserted between each drive circuit and each switch element of the first switching unit. The other end of the first switching unit is connected to a voltage line with a high absolute value. The other end of the second switching unit is connected to a voltage line with a low absolute value. A load circuit is connected between the output terminal between one end of the first switching unit and one end of the second switching unit, and the other end of the second switching unit. In a switching operation that switches the first switching unit and the second switching unit on and off at a first frequency, A ramp-up period is set during the initial ON period of the first switching unit, and during the ramp-up period, the first switching unit is switched at the second frequency based on a timing signal generated based on the comparison result between a preset ramp-up signal and a triangular wave comparison signal of a second frequency with a higher frequency than the first frequency. A switching circuit characterized by the following features.

2. The first switching unit and the second switching unit are configured to perform a switching operation in which they complementarily turn on and turn off at the first frequency during a continuous operation period defined by a predetermined on-duty ratio during a repeating period of a third frequency with a frequency lower than the first frequency, and both the first switching unit and the second switching unit are configured to pause their switching operation during a pause period defined by a predetermined off-duty ratio. The first switching unit sets a ramp-up period during the initial ON period of the continuous operation period, and during the ramp-up period, it switches the first switching unit at the second frequency based on a timing signal generated based on the comparison result between a preset ramp-up signal and a comparison signal of a second frequency with a frequency higher than the first frequency. The switching circuit according to feature 1.

3. The aforementioned ramp-up signal is a signal that increases linearly. A switching circuit according to claim 1 or 2, characterized by the above.

4. The ramp-up signal is a signal with an arbitrary waveform. A switching circuit according to claim 1 or 2, characterized by the above.

5. When the resistors inserted between each drive circuit and each switch element of the first switching unit and the input capacitance of each switch element are considered as an RC filter, the second frequency is higher than the frequency corresponding to the time constant of the RC filter. The switching circuit according to feature 1.

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