Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor that can improve the lifespan under high-temperature loads. [Solution] The multilayer ceramic capacitor 10 has a laminate in which the dimension in the first direction is shorter than the dimension in the second direction, when the direction perpendicular to the stacking direction x is defined as the first direction y, and the direction perpendicular to the stacking direction and the first direction is defined as the second direction z. The laminate has first and second external electrodes 30a and 30b on the surface facing the first direction, first and second internal electrodes connected to the first and second external electrodes, and an inner dielectric layer on which the first and second internal electrodes are arranged. The inner dielectric layer contains Ca, Sr or Zr and Li, and Li segregation exists in the external electrodes, and the magnitude of Li segregation in the external electrodes is greater than the magnitude of Li segregation in the inner dielectric layer.

Description

[Technical Field]

[0001] This invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] Multilayer ceramic capacitors used in electronic devices include multilayer ceramic capacitors with high dielectric constants and temperature-compensated multilayer ceramic capacitors, as described in Patent Document 1, in which the change in capacitance is linear with respect to temperature changes.

[0003] For example, the multilayer ceramic capacitor described in Patent Document 2 uses copper or a copper-containing alloy for the internal electrodes and calcium zirconate as the main component for the dielectric layer. However, because copper has a low melting point, when copper is used for the internal electrodes, the internal electrodes can become over-sintered during the dielectric sintering process, leading to problems such as a decrease in the effective area of ​​the internal electrodes and a reduction in capacitance. Patent Document 2 describes the use of sintering aids such as lithium and silicon, which form a liquid phase during firing, in order to lower the sintering temperature of the dielectric and bring it as close as possible to the temperature of copper. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2018-24542 [Patent Document 2] Japanese Patent Publication No. 2009-7209 [Patent Document 3] Japanese Patent Publication No. 2019-62177 [Overview of the project] [Problems that the invention aims to solve]

[0005] However, if lithium (Li) segregation occurs within the laminate during the firing process, lithium may remain within the laminate, potentially reducing the high-temperature load life of the multilayer ceramic capacitor.

[0006] Therefore, the main objective of this invention is to provide a multilayer ceramic capacitor that can move lithium within the laminate to an external electrode and improve its high-temperature load life. [Means for solving the problem]

[0007] The multilayer ceramic capacitor according to this invention comprises a laminate having a first surface and a second surface facing each other in the lamination direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the lamination direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the lamination direction and the first direction; a first external electrode disposed on the third surface of the laminate; and a second external electrode disposed on the fourth surface of the laminate, wherein the dimension l in the first direction of the laminate is shorter than the dimension w in the second direction of the laminate, and the laminate has a first internal electrode with one end exposed on the third surface, a second internal electrode with one end exposed on the fourth surface, and the first internal electrode and the second internal electrode A multilayer ceramic capacitor having an inner dielectric layer on which electrodes are arranged, wherein the inner dielectric layer mainly consists of Ca, Sr or Zr and Li, and Li segregation of Li exists in the first and / or second external electrodes in at least one of two regions: a 30 μm square region centered on the interface between the laminate and the first external electrode, which is half the dimension in the stacking direction, and half the dimension in the stacking direction, and the interface between the laminate and the second external electrode, and the magnitude of the Li segregation in the first and / or second external electrodes is greater than the magnitude of the Li segregation in the inner dielectric layer.

[0008] According to the multilayer ceramic capacitor of the present invention, the dimension l of the laminate in the first direction is shorter than the dimension w of the laminate in the second direction, the inner dielectric layer contains at least Ca, Sr or Zr and Li as its main components, and Li segregation exists in the first and / or second external electrodes in at least one of the following regions: a 30 μm square region centered on the interface between the laminate and the first external electrode, which is half the dimension in the lamination direction, and the other 30 μm square region centered on the interface between the laminate and the second external electrode, and the magnitude of Li segregation in the first and / or second external electrodes is greater than the magnitude of Li segregation in the inner dielectric layer, thus improving high-temperature load reliability. [Effects of the Invention]

[0009] This invention provides a multilayer ceramic capacitor that can move lithium within the laminate to an external electrode, thereby improving its high-temperature load life.

[0010] The above-mentioned objectives, other objectives, features, and advantages of this invention will become even clearer from the following description of embodiments for carrying out the invention, with reference to the drawings. [Brief explanation of the drawing]

[0011] [Figure 1] This is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of this invention. [Figure 2] This is a cross-sectional view along line II-II in Figure 1. [Figure 3] This is a cross-sectional view along line III-III in Figure 1. [Figure 4] This is a cross-sectional view along line IV-IV in Figure 1. [Figure 5] This is an external perspective view showing an example of a multilayer ceramic capacitor according to a modified example 1 of the embodiment of this invention. [Figure 6] This is a cross-sectional view along line VI-VI in Figure 5. [Figure 7] This is a cross-sectional view along line VII-VII in Figure 5. [Figure 8] It is a cross-sectional view taken along line VIII-VIII of FIG. 5. [Figure 9] It is an external perspective view showing an example of a multilayer ceramic capacitor according to a modification 2 of the embodiment of the present invention. [Figure 10] It is a cross-sectional view taken along line X-X of FIG. 9. [Figure 11] It is a cross-sectional view taken along line XI-XI of FIG. 9. [Figure 12] It is a cross-sectional view taken along line XII-XII of FIG. 9. [Figure 13] In the cross-sectional view shown in FIG. 10, it is a cross-sectional view showing a modification 3 of the embodiment of the present invention.

Mode for Carrying Out the Invention

[0012] 1. Multilayer ceramic capacitor The multilayer ceramic capacitor according to the embodiment of the present invention will be described.

[0013] FIG. 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to the embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1. FIG. 3 is a cross-sectional view taken along line III-III of FIG. 1. FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. 1.

[0014] As shown in FIGS. 1 to 3, the multilayer ceramic capacitor 10 includes a rectangular parallelepiped-shaped laminate 12 and external electrodes 30 disposed at both ends of the laminate 12.

[0015] (Laminate) The laminate 12 has a plurality of dielectric layers 14 stacked thereon and a plurality of internal electrodes 16 stacked on the dielectric layers 14. Further, the laminate 12 has a first surface 12a and a second surface 12b facing each other in the stacking direction x, a third surface 12c and a fourth surface 12d facing each other in a first direction y orthogonal to the stacking direction x, and a fifth surface 12e and a sixth surface 12f facing each other in a second direction z orthogonal to the stacking direction x and the first direction y.

[0016] Furthermore, it is preferable that the first surface 12a and the second surface 12b, or one of them, are flat. If they are flat, the stress received from the nozzle that picks up the multilayer ceramic capacitor 10 can be distributed across the flat surface. As a result, the strength of the multilayer ceramic capacitor can be improved during mounting.

[0017] Furthermore, the surface of the laminate 12 may be roughened.

[0018] The corners and edges of this laminate 12 may be rounded. Furthermore, the portions where two of the first, second, third, fourth, fifth, and sixth surfaces 12a, second, third, fourth, fifth, and sixth surfaces 12f intersect are called ridges, and the portions where three surfaces intersect are called corners. It is preferable that the ridges and corners are rounded and given a radius (R). By giving the ridges and corners a radius, chipping and cracking can be prevented. When the ridges and corners have a radius, the main surfaces may be flat on the surfaces excluding the ridges and corners.

[0019] Here, the dimension of the laminate 12 in the first direction y is denoted as dimension l, the dimension of the laminate 12 in the second direction z is denoted as dimension w, and the dimension of the laminate 12 in the stacking direction x is denoted as dimension t. The dimension l in the first direction y of the laminate 12 is shorter than the dimension w in the second direction z of the laminate 12. This allows the current path to be shortened, and thus the ESL of the multilayer ceramic capacitor 10 can be reduced.

[0020] As shown in Figures 2 and 3, the laminate 12 has an inner layer portion 18 in which dielectric layers 14 and internal electrodes 16 are alternately stacked in the stacking direction x connecting the first surface 12a and the second surface 12b; a first surface-side outer layer portion 20a formed from a plurality of dielectric layers 14 located between the internal electrode 16 located closest to the first surface 12a and the first surface 12a; and a second surface-side outer layer portion 20b formed from a plurality of dielectric layers 14 located between the internal electrode 16 located closest to the second surface 12b and the second surface 12b.

[0021] (Inner layer) The inner layer 18 is composed of multiple inner dielectric layers 14a from among the multiple dielectric layers 14. That is, the inner layer 18 is arranged such that multiple internal electrodes 16 face each other via the inner dielectric layers 14a.

[0022] The inner dielectric layer 14a mainly contains at least Ca, Sr or Zr, and Li. For example, it may contain CaZrO3 or SrZrO3 as dielectric components and Li as a sintering aid. In addition, it may also contain Mn, Ti, etc.

[0023] The main component of the inner dielectric layer 14a can be observed as follows. Specifically, the cross-section in the lamination direction x × first direction y is exposed when the multilayer ceramic capacitor 10 is polished in the second direction z to half of the W dimension in the second direction z. Then, the exposed cross-section is observed under □30 μm conditions using a TOF SIM (manufactured by ION-TOF).

[0024] As shown in Figures 2 and 3, the internal electrode 16 has a first internal electrode 16a and a second internal electrode 16b. The first internal electrode 16a and the second internal electrode 16b are alternately stacked with an inner dielectric layer 14a in between.

[0025] The first internal electrode 16a is arranged on a plurality of dielectric layers 14 and is located inside the laminate 12. The first internal electrode 16a has a first opposing electrode portion 22a facing the second internal electrode 16b, and a first leading electrode portion 24a located on one end side of the first internal electrode 16a, extending from the first opposing electrode portion 22a to the third surface 12c of the laminate 12. The end of the first leading electrode portion 24a is led out to the surface of the third surface 12c and exposed from the laminate 12. In other words, the end of the first leading electrode portion 24a is not exposed to the first surface 12a, the second surface 12b, the fourth surface 12d, the fifth surface 12e, and the sixth surface 12f. In detail, the end of the first internal electrode 16a is slightly recessed from the fourth surface 12d.

[0026] The shape of the first opposing electrode portion 22a of the first internal electrode 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0027] The shape of the first lead-out electrode portion 24a of the first internal electrode 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0028] The width of the first opposing electrode portion 22a of the first internal electrode 16a and the width of the first leading electrode portion 24a of the first internal electrode 16a may be the same, or one of them may be narrower.

[0029] The second internal electrode 16b is arranged on a plurality of dielectric layers 14 and is located inside the laminate 12. The second internal electrode 16b has a second opposing electrode portion 22b facing the first internal electrode 16a, and a second leading electrode portion 24b located on one end of the second internal electrode 16b, extending from the second opposing electrode portion 22b to the fourth surface 12d of the laminate 12. The end of the second leading electrode portion 24b is drawn out to the surface of the fourth surface 12d and exposed from the laminate 12. In other words, the end of the second leading electrode portion 24b is not exposed to the first surface 12a and the second surface 12b, the third surface 12c, and the fifth surface 12e and the sixth surface 12f. In detail, the end of the second internal electrode 16b is slightly recessed from the third surface 12c.

[0030] The shape of the second opposing electrode portion 22b of the second internal electrode 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0031] The shape of the second lead-out electrode portion 24b of the second internal electrode 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0032] The width of the second opposing electrode portion 22b of the second internal electrode 16b and the width of the second leading electrode portion 24b of the second internal electrode 16b may be the same, or one of them may be narrower.

[0033] As shown in Figure 3, the laminate 12 includes a side portion 26a of the laminate 12 formed between one end of the first opposing electrode portion 22a and the second opposing electrode portion 22b in the second direction z and the fifth surface 12e, and a side portion 26b of the laminate 12 formed between the other end of the first opposing electrode portion 22a and the second opposing electrode portion 22b in the second direction z and the sixth surface 12f.

[0034] Furthermore, as shown in Figure 2, the laminate 12 includes an end portion 27a of the laminate 12 formed between the end of the first internal electrode 16a opposite to the first extraction electrode portion 24a and the fourth surface 12d, and an end portion 27b of the laminate 12 formed between the end of the second internal electrode 16b opposite to the second extraction electrode portion 24b and the third surface 12c.

[0035] The internal electrode 16 is primarily composed of, for example, Cu. This allows for a lower electrical resistance of the internal electrode 16, thereby reducing the ESR. In addition, by using Cu as the main component of the internal electrode 16, it can be formed from an inexpensive material.

[0036] The main component of the internal electrode 16 can be observed as follows. Specifically, the cross-section in the lamination direction x × first direction y is exposed when the multilayer ceramic capacitor 10 is polished in the second direction z to half of the W dimension in the second direction z. Then, the exposed cross-section is observed under □30 μm conditions using a TOF SIM (manufactured by ION-TOF).

[0037] The thickness of the internal electrode 16 is preferably 0.5 μm or more and 3.5 μm or less. Furthermore, the total number of the first internal electrode 16a and the second internal electrode 16b is preferably 2 to 30.

[0038] (First outer layer on the front side, second outer layer on the front side) The first surface-side outer layer portion 20a is located on the first surface 12a side of the laminate 12 and is an aggregate of multiple outer dielectric layers 14b, which are multiple dielectric layers 14 located between the first surface 12a and the internal electrode 16 closest to the first surface 12a. The second surface-side outer layer portion 20b is located on the second surface 12b side of the laminate 12 and is an aggregate of multiple outer dielectric layers 14b, which are multiple dielectric layers 14 located between the second surface 12b and the internal electrode 16 closest to the second surface 12b. The region sandwiched between the first outer layer portion 20a and the second outer layer portion 20b is the inner layer portion 18.

[0039] The first outer surface layer 20a and the second outer surface layer 20b are each formed of an insulating material. When the first outer surface layer 20a and the second outer surface layer 20b are formed of the same dielectric material as the inner dielectric layer 14a, each outer surface layer 20a, 20b may be composed of multiple outer dielectric layers 14b or of a single outer dielectric layer 14b.

[0040] (external electrode) External electrodes 30 are arranged on the third surface 12c and the fourth surface 12d of the laminate 12, as shown in Figures 1 to 3.

[0041] The external electrode 30 includes a base electrode layer 32 containing a metal component and glass, and a plating layer 34 disposed on the surface of the base electrode layer 32.

[0042] The external electrode 30 has a first external electrode 30a and a second external electrode 30b.

[0043] The first external electrode 30a is connected to the first internal electrode 16a and is positioned on at least the surface of the third surface 12c. Preferably, the first external electrode 30a extends from the third surface 12c of the laminate 12 and is also positioned on a portion of the first surface 12a and a portion of the second surface 12b, as well as a portion of the fifth surface 12e and a portion of the sixth surface 12f. The first external electrode 30a is electrically connected to the first lead-out electrode portion 24a of the first internal electrode 16a.

[0044] The second external electrode 30b is connected to the second internal electrode 16b and is positioned on at least the surface of the fourth surface 12d. Preferably, the second external electrode 30b extends from the fourth surface 12d of the laminate 12 and is also positioned on a portion of the first surface 12a and a portion of the second surface 12b, as well as a portion of the fifth surface 12e and a portion of the sixth surface 12f. The second external electrode 30b is electrically connected to the second lead-out electrode portion 24b of the second internal electrode 16b.

[0045] Within the laminate 12, the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b face each other via the dielectric layer 14, thereby forming capacitance. As a result, capacitance can be obtained between the first external electrode 30a to which the first internal electrode 16a is connected and the second external electrode 30b to which the second internal electrode 16b is connected, and the characteristics of a capacitor are exhibited.

[0046] The base electrode layer 32 has a first base electrode layer 32a and a second base electrode layer 32b.

[0047] The first base electrode layer 32a is connected to the first internal electrode 16a and is positioned on the surface of the third surface 12c. Preferably, the first base electrode layer 32a extends from the third surface 12c and is also positioned on a portion of the first surface 12a and a portion of the second surface 12b, as well as a portion of the fifth surface 12e and a portion of the sixth surface 12f. The first base electrode layer 32a is electrically connected to the first lead-out electrode portion 24a of the first internal electrode 16a.

[0048] The second base electrode layer 32b is connected to the second internal electrode 16b and is positioned on the surface of the fourth surface 12d. Preferably, the second base electrode layer 32b extends from the fourth surface 12d and is also positioned on a portion of the first surface 12a and a portion of the second surface 12b, as well as a portion of the fifth surface 12e and a portion of the sixth surface 12f. The second base electrode layer 32b is electrically connected to the second lead electrode portion 24b of the second internal electrode 16b.

[0049] The base electrode layer 32 is mainly composed of Cu. In addition to Cu as the main component, the base electrode layer 32 also contains a glass component. By including Cu, which has low resistivity, as the main component of the base electrode layer 32, the ESR of the multilayer ceramic capacitor 10 can be reduced. Furthermore, by including a glass component, the sinterability of the base electrode layer 32 can be improved. Examples of glass components include Na, B, Si, Zn, and Ba.

[0050] In this embodiment, if the Cu diameter becomes smaller, the number of Cu particle interfaces increases, resulting in a higher ESR. Therefore, it is preferable that the D50 of the Cu particles constituting the Cu contained in the base electrode layer 32 is between 1.5 μm and 3.5 μm.

[0051] Furthermore, the base electrode layer 32 exhibits Li segregation in a 30 μm square region centered on the halfway point in the stacking direction x and the interface between the laminate 12 and the external electrode 30, and this segregation is greater than that of Li contained in the inner dielectric layer 14a. In addition, the magnitude of Li segregation in the 30 μm square region centered on the halfway point in the stacking direction x and the interface between the laminate 12 and the external electrode 30 is 1.0 μm. 2 More than 30.2μm 2 The following is preferable:

[0052] The magnitude of Li segregation in the base electrode layer 32 is defined by the presence of Li observed in a cross-section in the stacking direction x × first direction y, when the multilayer ceramic capacitor 10 is polished in the second direction z to half the length of the W direction in the second direction z, under the condition of a square of 30 μm, using TOF SIMS on the base electrode layer 32 located in the center of the stacking direction x, with the interface between the laminate 12 and the base electrode layer 32 as the center of the observed image.

[0053] Furthermore, the magnitude of Li segregation in the base electrode layer 32 and the magnitude of Li segregation in the inner dielectric layer 14a can be measured by TOF.SIMS (Time-of-Flight Secondary Ion Mass Spectrometry). The measurement conditions for this TOF.SIMS are as follows. • Device name: TOF.SIMS (manufactured by ION-TOF) Primary ion: Bi + • Acceleration voltage: 25kV Secondary ionic polarity: Positive • Number of scans: 32 • Pixel count: 256 pixels x 256 pixels • Measurement area: 30 μm x 30 μm The size of Li segregation is determined by counting pixels with a Li intensity of 1.0 or higher within a 256x256 pixel area. The size of Li segregation is 0.50 μm² in area. 2The above items are counted. For example, if there are three segregations of Li, the largest one is considered to be the size of Li.

[0054] The thickness in the first direction y connecting the third surface 12c and the fourth surface 12d at the center of the lamination direction x of the first underlay electrode layer 32a located on the third surface 12c is preferably, for example, 19 μm or more and 24 μm or less.

[0055] The thickness of the second underlay electrode layer 32b located on the fourth surface 12d in the first direction y connecting the third surface 12c and the fourth surface 12d at the center of the lamination direction x is preferably, for example, 19 μm or more and 24 μm or less.

[0056] Next, the first plating layer 34a and the second plating layer 34b, which are plating layers 34 placed on the base electrode layer 32, will be described with reference to Figures 2 and 3.

[0057] The first plating layer 34a and the second plating layer 34b include, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0058] The first plating layer 34a is positioned to completely cover the first underlay electrode layer 32a. The second plating layer 34b is positioned to completely cover the second under electrode layer 32b.

[0059] The first plating layer 34a and the second plating layer 34b may be formed by multiple layers. In this case, the plating layer 34 preferably has a two-layer structure consisting of a lower plating layer (Ni plating layer) formed on the base electrode layer 32 by Ni plating and an upper plating layer (Sn plating layer) formed on the lower plating layer by Sn plating. In other words, in this case, the first plating layer 34a has a first lower plating layer 36a and a first upper plating layer 38a located on the surface of the first lower plating layer 36a. Furthermore, the second plating layer 34b has a second lower plating layer 36b and a second upper plating layer 38b located on the surface of the second lower plating layer 36b.

[0060] The lower plating layer 36 made of Ni is used to prevent the underlying electrode layer 32 from being corroded by the solder when mounting the multilayer ceramic capacitor 10, and the upper plating layer 38 made of Sn is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, making it easier to mount. The thickness of each plating layer of the lower plating layer 36 and the upper plating layer 38 is preferably 1.0 μm or more and 15.0 μm or less.

[0061] The dimension in the first direction y of the multilayer ceramic capacitor 10, which includes the laminate 12, the first external electrode 30a, and the second external electrode 30b, is defined as dimension L. The dimension in the stacking direction x of the multilayer ceramic capacitor 10, which includes the laminate 12, the first external electrode 30a, and the second external electrode 30b, is defined as dimension T. The dimension in the second direction z of the multilayer ceramic capacitor 10, which includes the laminate 12, the first external electrode 30a, and the second external electrode 30b, is defined as dimension W. The dimensions of the multilayer ceramic capacitor 10 are as follows: the L dimension in the first direction y is 0.2 mm to 0.5 mm; the W dimension in the second direction z is 0.4 mm to 1.0 mm; and the T dimension in the stacking direction x is 0.15 mm to 0.35 mm. The dimensions of the multilayer ceramic capacitor 10 can also be measured using a microscope.

[0062] In the multilayer ceramic capacitor 10 shown in Figure 1, the dimension l of the laminate 12 in the first direction y is shorter than the dimension w of the laminate 12 in the second direction z, and the inner dielectric layer 14a of the laminate 12 mainly contains at least Ca, Sr or Zr and Li, and in a 30 μm square region centered on half of the stacking direction x and the interface between the laminate 12 and the external electrode 30, the base electrode layer 32 has Li segregation, which is greater than the Li segregation contained in the inner dielectric layer, thus improving high-temperature load reliability.

[0063] Furthermore, in the multilayer ceramic capacitor 10 shown in Figure 1, the segregation size of Li is 1.0 μm in a 30 μm square region centered on the 1 / 2 of the stacking direction x and the interface between the stacked body 12 and the external electrode 30. 2 More than 30.2μm 2 The following conditions can further improve high-temperature load reliability.

[0064] 2. Variations (1) Variation 1 Next, an example of a multilayer ceramic capacitor 10A according to Modification 1 of this embodiment will be described. Figure 5 is an external perspective view showing an example of a multilayer ceramic capacitor according to Modification 1 of this embodiment. Figure 6 is a cross-sectional view taken along line VI-VI in Figure 5. Figure 7 is a cross-sectional view taken along line VII-VII in Figure 5. Figure 8 is a cross-sectional view taken along line VIII-VIII in Figure 5. However, components that are the same as or corresponding to those in Figures 1 to 4 are denoted by the same reference numerals, and detailed descriptions are omitted.

[0065] A modified example 1 of this embodiment includes a multilayer ceramic capacitor 10A which comprises a rectangular parallelepiped-shaped laminate 12A and external electrodes 30 arranged at both ends of the laminate 12A.

[0066] The laminate 12A has a plurality of stacked dielectric layers 14. Furthermore, the laminate 12A has a first surface 12a and a second surface 12b opposite to the stacking direction x, a third surface 12c and a fourth surface 12d opposite to a first direction y perpendicular to the stacking direction x, and a fifth surface 12e and a sixth surface 12f opposite to a second direction z perpendicular to the stacking direction x and the first direction y.

[0067] In the laminate 12A, as shown in Figures 6 and 8, the first internal electrode 16a and the second internal electrode 16b are arranged on the same inner dielectric layer 14a at a predetermined distance apart in the inner layer portion 18. That is, the first internal electrode 16a and the second internal electrode 16b face each other in the first direction y.

[0068] The multilayer ceramic capacitor 10A according to the modified example 1 shown in Figure 5 produces the same effect as the multilayer ceramic capacitor 10 in Figure 1.

[0069] (2) Modification example 2 Next, an example of a multilayer ceramic capacitor 10B according to Modification 2 of this embodiment will be described. Figure 9 is an external perspective view showing an example of a multilayer ceramic capacitor according to Modification 2 of this embodiment. Figure 10 is a cross-sectional view taken along line XX in Figure 9. Figure 11 is a cross-sectional view taken along line XI-XI in Figure 9. Figure 12 is a cross-sectional view taken along line XII-XII in Figure 9. However, components that are the same as or corresponding to those in Figures 1 to 4 are denoted by the same reference numerals, and detailed descriptions are omitted.

[0070] A modified example 2 of this embodiment of a multilayer ceramic capacitor 10B includes a rectangular parallelepiped laminate 12B and external electrodes 30 arranged at both ends of the laminate 12B.

[0071] The laminate 12B has a plurality of stacked dielectric layers 14. Furthermore, the laminate 12B has a first surface 12a and a second surface 12b opposite to the stacking direction x, a third surface 12c and a fourth surface 12d opposite to a first direction y perpendicular to the stacking direction x, and a fifth surface 12e and a sixth surface 12f opposite to a second direction z perpendicular to the stacking direction x and the first direction y.

[0072] As shown in Figures 10 to 12, the laminate 12B has a first internal electrode 16a and a second internal electrode 16b as internal electrodes 16.

[0073] The first internal electrode 16a is electrically connected to the first external electrode 30a. The second internal electrode 16b is electrically connected to the second external electrode 30b.

[0074] Furthermore, a first dummy electrode 25a is positioned at the end (L gap) 27b of the laminate 12B so as to be exposed to the third surface 12c. Also, a second dummy electrode 25b is positioned at the end (L gap) 27a of the laminate 12B so as to be exposed to the fourth surface 12d.

[0075] The first dummy electrode 25a is preferably arranged on the same plane as the second internal electrode 16b and has the same thickness as the second internal electrode 16b. The second dummy electrode 25b is preferably arranged on the same plane as the first internal electrode 16a and has the same thickness as the first internal electrode 16a.

[0076] The first dummy electrode 25a and the second dummy electrode 25b may be arranged on the first and second outer surface layers 20a and 20b, respectively. In this case, it is preferable that they be arranged on portions corresponding to locations obtained by shifting the ends (L gaps) 27a and 27b of the laminate 12 parallel to the lamination direction x. This arrangement makes it easier to form the plating layer when providing the plating layer without providing the underlay electrode layer 32.

[0077] Furthermore, if the first dummy electrode 25a is to be placed on the same plane as the second internal electrode 16b, the first dummy electrode 25a and the second internal electrode 16b can be placed on the same plane by printing the first dummy electrode 25a together with the second internal electrode 16b when printing the second internal electrode 16b. Furthermore, if the second dummy electrode 25b is provided on the same plane as the first internal electrode 16a, the second dummy electrode 25b can be printed together with the first internal electrode 16a when printing the first internal electrode 16a.

[0078] The multilayer ceramic capacitor 10B according to the modified example 2 shown in Figure 9 produces the same effect as the multilayer ceramic capacitor 10 in Figure 1.

[0079] (3) Modification example 3 Next, an example of a multilayer ceramic capacitor 10C according to Modification 3 of this embodiment will be described. Figure 13 is a cross-sectional view showing Modification 3 of the embodiment of this invention in the cross-sectional view shown in Figure 10. However, components that are the same as or corresponding to those in Figures 1 to 4 are denoted by the same reference numerals, and detailed descriptions are omitted.

[0080] As shown in Figure 13, the laminated body 12C of the multilayer ceramic capacitor 10C according to the modified example 3 of this embodiment has a pair of first internal electrodes 16A and a pair of second internal electrodes 16B as internal electrodes 16.

[0081] The pair of first internal electrodes 16A is composed of two first internal electrodes 16a1 and 16a2 that are adjacent to each other in the stacking direction x. The pair of first internal electrodes 16A are electrically connected to the first external electrode 30a. The pair of second internal electrodes 16B are composed of two adjacent second internal electrodes 16b1 and 16b2 that are continuous in the stacking direction x. The pair of second internal electrodes 16B are electrically connected to the second external electrode 30b.

[0082] Furthermore, a pair of first dummy electrodes 25A are positioned at the end (L gap) 27b of the laminate 12C so as to be exposed to the third surface 12c. Also, a pair of second dummy electrodes 25B are positioned at the end (L gap) 27a of the laminate 12C so as to be exposed to the fourth surface 12d.

[0083] A pair of first dummy electrodes 25A is composed of two first dummy electrodes 25a1 and 25a2 that are adjacent to each other in the stacking direction x. Preferably, each of the first dummy electrodes 25a1 and 25a2 constituting the pair of first dummy electrodes 25A is arranged on the same plane as each of the second internal electrodes 16b1 and 16b2 constituting the pair of second internal electrodes 16B, and has the same thickness as each of the second internal electrodes 16b1 and 16b2. The pair of second dummy electrodes 25B is composed of two second dummy electrodes 25b1 and 25b2 that are adjacent to each other in the stacking direction x. Preferably, each of the second dummy electrodes 25b1 and 25b2 constituting the pair of second dummy electrodes 25B is arranged on the same plane as each of the first internal electrodes 16a1 and 16a2 constituting the pair of first internal electrodes 16A, and has the same thickness as each of the first internal electrodes 16a1 and 16a2.

[0084] The multilayer ceramic capacitor 10C according to the modified example 3 shown in Figure 13 produces the same effect as the multilayer ceramic capacitor 10 in Figure 1.

[0085] 3. Manufacturing method of multilayer ceramic capacitors Next, an example of a method for manufacturing a multilayer ceramic capacitor according to this embodiment will be described.

[0086] (Preparation process for ceramic green sheets) First, a ceramic green sheet for the dielectric layer and a conductive paste for the internal electrodes are prepared. The ceramic green sheet and the conductive paste for the internal electrodes contain a binder and an organic solvent. The binder and organic solvent may be known.

[0087] In this case, the ceramic green sheet for the inner dielectric layer region is formed, for example, from a dielectric paste containing Li in CaZrO3. More specifically, this dielectric paste contains at least Ca, Sr or Zr, and Li as its main components. For example, it may have CaZrO3 or SrZrO3 as the dielectric component and contain Li as a sintering aid. In addition, it may also contain Mn, Ti, etc.

[0088] Furthermore, when the dielectric paste for forming the ceramic green sheet for the inner dielectric layer region is mainly composed of CaZrO3, glass components are added in an amount of 2 wt% to 4 wt% relative to the CaZrO3. In this case, the amount of Li contained in the glass components can be 3 wt% to 4 wt%.

[0089] Then, a conductive paste for internal electrodes is printed in a predetermined pattern onto the ceramic green sheet for the inner dielectric layer region, for example, by screen printing or gravure printing. This prepares a ceramic green sheet with the pattern for the first internal electrode formed on it, and a ceramic green sheet with the pattern for the second internal electrode formed on it.

[0090] (Process for obtaining laminated sheets) Next, a predetermined number of ceramic green sheets for the outer layer, which do not have the pattern of the internal electrodes printed on them, are laminated to form the second outer layer portion on the second side. Then, a ceramic green sheet with the pattern of the first internal electrodes printed on it, and a ceramic green sheet with the pattern of the second internal electrodes printed on it, are sequentially laminated on the second outer layer portion to form the structure of the present invention, thereby forming the inner layer portion. A predetermined number of ceramic green sheets for the outer layer, which do not have the pattern of the internal electrodes printed on them, are laminated on this inner layer portion to form the first outer layer portion on the first side. This completes the production of the laminated sheet.

[0091] (Process for obtaining laminated blocks) Next, a laminated block is produced by pressing the laminated sheets in the lamination direction using means such as a hydrostatic press.

[0092] (Process for obtaining stacked chips) Then, the laminated block is cut to a predetermined size, and the laminated chip is cut out.

[0093] (Process for obtaining fired chips) Next, the laminated chips are fired to create fired chips. Specifically, after heating at 200°C to 300°C, the chips are fired in a non-oxidizing atmosphere at a heating rate of 3.33°C / min to 200°C / min, and a maximum firing temperature of 900°C to 1040°C to form fired chips.

[0094] Next, a conductive paste for the base electrode layer, containing metal and glass components, is prepared.

[0095] (Process for forming external electrodes) A conductive paste, which will serve as the base electrode layer, is applied to the third and fourth surfaces of the fired chip, respectively, to form the base electrode layer. The conductive paste is applied to the third and fourth surfaces of the fired chip by methods such as dipping. For example, the conductive paste that will serve as the base electrode layer may mainly consist of Cu as the metal component and contain glass components in an amount of 10 vol% to 20 vol%. In this case, for flattened Cu particles, the D50 is 2 μm to 4 μm, and for spherical particles, the D50 is 0.3 μm to 0.5 μm.

[0096] Next, the fired chip coated with conductive paste is fired to form a fired chip with a base electrode layer. At this time, it is preferable to adjust the firing conditions so that an appropriate amount of Li is contained in the base electrode layer after firing the conductive paste. If firing is performed under conditions that do not contain Li in the base electrode layer, the densification of the base electrode layer will not be promoted, and there is a risk that many defects will occur in the high-temperature load test, such as penetration of the plating solution in the plating process described later or opening of the interface between the internal electrode and the inner dielectric layer. In addition, if the segregation of Li scattered into the base electrode layer is large, or if the amount of Li is too large, the proportion of glass components will increase, and there is a risk that the moisture resistance will decrease. The firing conditions for the fired chip can be, for example, firing in a reducing atmosphere at a temperature of 850°C to 900°C for 0.3 hours to 0.5 hours.

[0097] In addition, in a multilayer ceramic capacitor 10 like this embodiment, where the W dimension is larger than the L dimension, there is a larger contact surface between the laminate 12 and the external electrode 30. Therefore, lithium from within the laminate 12 is more likely to scatter into the external electrode 30 during the external electrode firing process. For this reason, the paste used to form the external electrode 30 and the firing atmosphere for forming the external electrode should be kept within an appropriate range.

[0098] Next, if necessary, plating is applied to the surface of the base electrode layer to form a plating layer. In this embodiment, two plating layers are formed on the surface of the base electrode layer. Specifically, a Ni plating layer and a Sn plating layer are formed on the base electrode layer. Electrolytic plating is preferred as the plating process. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0099] As described above, the multilayer ceramic capacitor 10 according to this embodiment is manufactured.

[0100] 3. Experimental Examples Next, in order to confirm the effect of the multilayer ceramic capacitor according to the present invention described above, multilayer ceramic capacitors were fabricated as experimental samples according to the manufacturing method described above, with varying amounts of Li segregation in the underlying electrode layer, and humidity resistance tests and high-temperature load reliability tests were performed.

[0101] (1) Specifications of the multilayer ceramic capacitor fabricated as a sample for the experimental example Using the manufacturing method according to the above embodiment, multilayer ceramic capacitors, which are samples numbered 1 to 7, were fabricated. • Structure of a multilayer ceramic capacitor: Multilayer ceramic capacitor shown in Figure 1 • Dimensions of the multilayer ceramic capacitor in the first direction: 300 μm • Dimensions of the second direction of the multilayer ceramic capacitor: 600 μm • Dimensions in the stacking direction of multilayer ceramic capacitors: 200 μm • Main component of the internal electrode: Cu • Main component of the inner dielectric layer: CaZrO3 • Main component of the underlying electrode layer: Cu • Thickness of the base electrode layer located in the center of the stacking direction x, which is half the W dimension in the second direction z of the multilayer ceramic capacitor: 20 μm • Plating layer Formation of a two-layer structure consisting of a Ni plating layer and a Sn plating layer. Ni plating layer thickness: approximately 3 μm Sn plating layer thickness: approximately 5 μm

[0102] (2) Method for measuring the magnitude of Li segregation The magnitude of Li segregation in the underlying electrode layer was defined by the presence of Li in a cross-section of the stacking direction x × first direction y, obtained by polishing the multilayer ceramic capacitor for each sample in the second direction z to half of the W dimension in the second direction z, under the condition of a square of 30 μm, and with the interface between the laminate and the underlying electrode layer as the center of the observed image, using TOF.SIMS. The measurement conditions using TOF.SIMS were as follows. • Device name: TOF.SIMS (manufactured by ION-TOF) Primary ion: Bi + • Acceleration voltage: 25kV Secondary ionic polarity: Positive • Number of scans: 32 • Pixel count: 256 pixels x 256 pixels • Measurement area: 30 μm x 30 μm Furthermore, the segregation size of Li is 0.5 μm in area. 2 The above items were counted. For example, if there were three segregated Li regions, the largest Li segregated region was identified, and the size of that Li segregated region was defined as the size of the Li.

[0103] (3) Method of humidity resistance test First, the multilayer ceramic capacitors for each sample were mounted on a wiring board using solder, and their insulation resistance was measured. At this time, the multilayer ceramic capacitors mounted on the wiring boards for each sample were placed in a high-temperature, high-humidity chamber, and a humidity resistance test was conducted by maintaining a 200V DC current applied to the external electrodes of the multilayer ceramic capacitors for each sample for 2000 hours in an environment of 85°C and 85% RH. The insulation resistance of the multilayer ceramic capacitors for each sample was then measured after this humidity resistance test. A sample was considered NG (defective) if the insulation resistance value after the humidity resistance test was more than one order of magnitude lower than the insulation resistance value before the humidity resistance test. There were 100 samples of each type.

[0104] (4) High-temperature load reliability test First, the multilayer ceramic capacitors for each sample were mounted on a wiring board using solder, and their insulation resistance was measured. At this time, the multilayer ceramic capacitors mounted on the wiring boards for each sample were placed in a chamber, and a high-temperature load test was performed by applying a 200V DC current to the external electrodes of the multilayer ceramic capacitors for each sample at a temperature of 150°C for 2000 hours. The insulation resistance of the multilayer ceramic capacitors for each sample was then measured after this high-temperature load test. A sample was considered NG (defective) if the insulation resistance after the high-temperature load test was more than an order of magnitude lower than the insulation resistance before the high-temperature load test. There were 100 samples of each type.

[0105] (5) Results Table 1 shows the results of humidity resistance tests and high-temperature load reliability tests for multilayer ceramic capacitors of each sample from sample number 1 to sample number 7, when the magnitude of segregation of Li contained in the underlying electrode layer was varied.

[0106] Sample No. 7 was defined as a sample that did not contain Li in the underlying electrode layer but contained Li in the laminate. On the other hand, samples No. 1 through No. 6 contained Li in both the underlying electrode layer and the laminate, but the segregation of Li in the underlying electrode layer was greater than the segregation of Li in the laminate.

[0107]

Table 1

[0108] According to Table 1, as the sample numbers go from sample number 1 to sample number 6, the magnitude of the segregation of Li contained in the base electrode layer increases. Therefore, as the sample numbers go from sample number 1 to sample number 6, the difference between the magnitude of the segregation of Li contained in the laminate and the magnitude of the segregation of Li contained in the base electrode layer becomes larger. As a result, it was confirmed that as the magnitude of the segregation of Li contained in the base electrode layer increases, the number of samples that became NG (defective) as a result of the high-temperature load test decreased. On the other hand, in the sample of sample number 7, since there was no segregation of Li in the base electrode layer, as a result of the high-temperature load test, 10 out of 100 samples became NG (defective), which was relatively many.

[0109] When considering the magnitude of the segregation of Li in the samples of sample numbers 1 to 3, as a result of the moisture resistance test, there were no samples that became NG (defective), and good results were obtained. On the other hand, when considering the magnitude of the segregation of Li in the samples of sample numbers 4 to 6, as a result of the moisture resistance test, although the number was small, there were samples that became NG (defective).

[0110] From the above results, in this invention, it was confirmed that the greater the magnitude of the segregation of Li contained in the base electrode layer, the better the results of the high-temperature load reliability test. Also, when the magnitude of the segregation of Li is in the range of 1.0 μm 2 or more and 30.2 μm 2 or less, it was confirmed that the results of the moisture resistance test were also relatively good.

[0111] Note that, as described above, the embodiments of the present invention are disclosed in the above description, but the present invention is not limited thereto.

[0112] In other words, various modifications can be made to the embodiments described above with respect to the mechanism, shape, material, quantity, position or arrangement, etc., without departing from the scope of the technical idea and objectives of the present invention, and these modifications are included in the present invention. [Explanation of Symbols]

[0113] 10, 10A, 10B, 10C Multilayer Ceramic Capacitors 12-layer structure 12a First face 12b Second face 12c Third side 12d Fourth face 12e Fifth side 12f Sixth face 14 Dielectric layer 14a Inner dielectric layer 14b Outer dielectric layer 16 Internal electrode 16a, 16a1, 16a2 First internal electrodes 16b, 16b1, 16b2 Second internal electrodes 16A Pair of first internal electrodes 16B A pair of second internal electrodes 18 Inner layer 20a First side outer layer 20b Second side outer layer 22 Counter electrode section 22a First counter electrode portion 22b Second counter electrode section 24a First extraction electrode section 24b Second extraction electrode section 25 Dummy electrodes 25a, 25a1, 25a2 First dummy electrodes 25b, 25b1, 25b2 Second dummy electrodes 25A pair of dummy electrodes 25B Pair of dummy electrodes 26a, 26b Side 27a, 27b ends 30 External electrode 30a First external electrode 30b Second external electrode 32 Base electrode layer 32a First underlay electrode layer 32b Second base electrode layer 34 Plating layer 34a First plating layer 34b Second plating layer 36 Lower plating layer 36a First lower plating layer 36b Second lower plating layer 38 Upper plating layer 38a First upper plating layer 38b Second upper plating layer x stacking direction y First direction z Second direction

Claims

1. A laminate having a first surface and a second surface facing each other in the stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction, A first external electrode disposed on the third surface of the laminate, A second external electrode disposed on the fourth surface of the laminate, Equipped with, The dimension l of the laminate in the first direction is shorter than the dimension w of the laminate in the second direction. The laminated body is A first internal electrode with one end exposed on the third surface, A second internal electrode, with one end exposed on the fourth surface, An inner dielectric layer on which the first internal electrode and the second internal electrode are arranged, It has, The inner dielectric layer mainly comprises Ca, Sr or Zr and Li. A multilayer ceramic capacitor in which, in at least one of the following regions, a 30 μm square area centered on half the dimension in the stacking direction and the interface between the stack and the first external electrode, and a 30 μm square area centered on half the dimension in the stacking direction and the interface between the stack and the second external electrode, Li segregation exists in the first external electrode and / or the second external electrode, and the magnitude of the Li segregation in the first external electrode and / or the second external electrode is greater than the magnitude of the Li segregation in the inner dielectric layer.

2. The segregation of Li in at least one of the first external electrode and the second external electrode is 1.0 μm. 2 30.2 μm or more 2 The multilayer ceramic capacitor according to claim 1, which is as follows:

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