Electro-optical devices and electronic equipment

Abstract

It supports the miniaturization of electro-optical devices. [Solution] The wiring 251 is provided such that, in a plan view, it includes a line Cen extending along the Y direction between the data lines 14, 14. The data lines 14, 14 are arranged symmetrically with respect to the wiring 251, and the anode wiring leading to the pixel electrode 131 is also arranged symmetrically with respect to the wiring 251. The power supply voltage Vel of the pixel circuit 110 is applied to the wiring 251.

Description

Technical Field

[0001] The present invention relates to an electro-optical device and an electronic device.

Background Art

[0002] An electro-optical device using, for example, an OLED (Organic Light Emitting Diode) as a light-emitting element is known. In the electro-optical device, a pixel circuit including a transistor or the like for flowing a current through the light-emitting element is provided corresponding to each pixel of an image to be displayed. Due to high resolution and high definition, the intervals between adjacent pixel circuits and various wirings become narrow. When the interval between two wirings becomes narrow, a voltage change in one wiring is likely to affect the other wiring, that is, interference is likely to occur. Therefore, a technique has been proposed in which a power supply wiring for supplying current to the light-emitting element is provided in the same wiring layer as the scanning line and extends in the same direction as the scanning line to suppress interference in a direction orthogonal to the scanning line (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In recent years, in electro-optical devices, further higher resolution and higher definition have been required. In particular, there is a strong demand for narrowing the pitch in the horizontal direction parallel to the scanning line, but it is difficult to satisfy this demand while suppressing the above interference.

Means for Solving the Problems

[0005] An electro-optical apparatus according to one aspect of the present disclosure includes: a first light-emitting element having a first anode; a first data line supplying a first data signal to the first light-emitting element; a second light-emitting element having a second anode; a second data line supplying a second data signal to the second light-emitting element; a first transistor circuit controlling the emission of light of the first light-emitting element; a second transistor circuit controlling the emission of light of the second light-emitting element; and a first shielding wire, wherein the first transistor circuit has a first anode line electrically connected to the first anode; the second transistor circuit has a second anode line electrically connected to the second anode; the first shielding wire is positioned between the first data line and the second data line in a plan view, extends along a first direction, the first data line and the second data line are symmetrical with respect to the first shielding wire in a plan view; the first anode line and the second anode line are symmetrical with respect to the first shielding wire in a plan view; and the first shielding wire supplies power to the first transistor circuit and the second transistor circuit. [Brief explanation of the drawing]

[0006] [Figure 1] This is a perspective view showing an electro-optical device according to an embodiment. [Figure 2] This is a block diagram showing the configuration of the main components of an electro-optical device. [Figure 3] This is a circuit diagram showing the configuration of the main components of an electro-optical device. [Figure 4] This is a plan view showing the arrangement of light-emitting elements in an electro-optical device. [Figure 5] This diagram shows the configuration of the pixel circuit in the display area. [Figure 6] This is a timing chart showing the operation of an electro-optical device. [Figure 7] This is a timing chart showing the operation of an electro-optical device. [Figure 8] This is a diagram illustrating the operation of an electro-optical device. [Figure 9] This is a diagram illustrating the operation of an electro-optical device. [Figure 10] It is a diagram for explaining the operation of an electro-optical device. [Figure 11] It is a diagram for explaining the operation of an electro-optical device. [Figure 12] It is a diagram for explaining the operation of an electro-optical device. [Figure 13] It is a diagram for explaining the operation of an electro-optical device. [Figure 14] It is a cross-sectional view of the main part of an electro-optical device. [Figure 15] It is a plan view showing a semiconductor region and the like in an electro-optical device. [Figure 16] It is a plan view showing wirings and the like composed of a first wiring layer in an electro-optical device. [Figure 17] It is a plan view showing wirings and the like composed of a second wiring layer in an electro-optical device. [Figure 18] It is a plan view showing wirings and the like composed of a third wiring layer in an electro-optical device. [Figure 19] It is a plan view showing pixel electrodes in an electro-optical device. [Figure 20] It is a plan view showing a semiconductor region and the like in a comparative example. [Figure 21] It is a plan view showing wirings and the like composed of a first wiring layer in a comparative example. [Figure 22] It is a plan view showing wirings and the like composed of a second wiring layer in a comparative example. [Figure 23] It is a plan view showing wirings and the like composed of a third wiring layer in a comparative example. [Figure 24] It is a plan view showing pixel electrodes in a comparative example. [Figure 25] It is a perspective view showing a head-mounted display using an electro-optical device. [Figure 26] It is a diagram showing the optical configuration of a head-mounted display.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, an electro-optical device according to an embodiment of the present invention will be described with reference to the drawings. In each figure, the dimensions and scales of each part are appropriately different from the actual ones. In addition, the embodiments described below are preferred specific examples, and thus various technically preferable limitations are imposed. However, the scope of the present invention is not limited to these embodiments unless there is a description specifically limiting the present invention in the following description.

[0008] FIG. 1 is a perspective view showing an electro-optical device 10. The electro-optical device 10 is a micro display panel that displays an image, for example, in a head-mounted display or the like. The electro-optical device 10 includes a plurality of pixel circuits and a drive circuit that drives the pixel circuits. The pixel circuit and the drive circuit are integrated on a semiconductor substrate. The semiconductor substrate is typically a silicon substrate, but may be other semiconductor substrates.

[0009] As shown in this figure, the electro-optical device 10 is housed in a frame-shaped case 192 having an opening 191. One end of an FPC (Flexible Printed Circuits) substrate 194 is connected to the electro-optical device 10. A plurality of terminals 196 are provided at the other end of the FPC substrate 194. The plurality of terminals 196 are connected to a host device (not shown). The host device supplies video data to the electro-optical device 10. The video data is data indicating a video to be displayed by the electro-optical device 10.

[0010] In the figure, the X direction indicates the horizontal direction of the display image in the electro-optical device 10, and the Y direction indicates the vertical direction of the display image. Also, the two-dimensional plane defined by the X direction and the Y direction is the substrate surface of the semiconductor substrate. The Z direction is perpendicular to the X direction and the Y direction, and indicates the emission direction of light emitted from a light-emitting element described later.

[0011] FIG. 2 is a block diagram showing the electrical configuration of the electro-optical device 10, and FIG. 3 is a diagram showing the configuration of a main part in the electro-optical device 10. Further, FIG. 4 is a plan view showing the arrangement of pixel circuits excluding the light-emitting element and the arrangement of the light-emitting element in the electro-optical device 10.

[0012] ru. As shown in Figure 2, the electro-optical device 10 includes a control circuit 20, a data signal output circuit 30, a switch group 40, a capacitive element group 50, an initialization circuit 60, an auxiliary circuit 70, a display area 100, and a scan line drive circuit 120.

[0013] In the electro-optical device 10, for example, 540 scan lines 12 are provided extending in the X direction in the figure, and 11520 (=1920 × 3 × 2) data lines 14 are provided extending in the Y direction, and are provided so as to maintain electrical isolation from each other with respect to each scan line 12.

[0014] To distinguish between rows in scan line 12, the rows are referred to as 1, 2, 3, ..., 539, and 540 in the diagram, starting from the top. Note that, to describe scan line 12 generally without specifying a row, an integer i (between 1 and 540) is sometimes used to refer to a row as "row i". Furthermore, to distinguish the columns in data line 14, they are referred to as columns 1, 2, 3, ..., 11520 in the diagram, starting from the left. Data line 14 is grouped into groups of 6 columns. To explain the groups in a general way, if we use an integer j between 1 and 960, then the j-th group from the left contains data line 14 with a total of 6 columns: (6j-5), (6j-4), (6j-3), (6j-2), (6j-1), and (6j).

[0015] In this embodiment, the pixel circuit 110R includes a light-emitting element that includes a red component in the emitted light, the pixel circuit 110G includes a light-emitting element that includes a green component in the emitted light, and the pixel circuit 110B includes a light-emitting element that includes a blue component in the emitted light. When describing pixel circuits 110R, 110G, and 110B in general terms without specifying their colors, the code for the pixel circuit is simply referred to as 110.

[0016] The pixel circuits 110, excluding the light-emitting elements, are arranged in correspondence with the scan lines 12, which are arranged in 540 rows, and the data lines 14, which are arranged in 11,520 columns. At the intersection of the i-th row of scan line 12 and the data lines 14 in columns (6j-5) to (6j), as shown in the left column of Figure 4, six pixel circuits 110R, 110R, 110G, 110G, 110B, and 110B are arranged in a 1x6 arrangement along the X direction. For simplification and distinction in the figure, the pixel circuits 110R, 110R, 110G, 110G, 110B, and 110B, excluding the light-emitting elements, are denoted as R1, R2, G1, G2, B1, and B2, respectively. The area where the pixel circuits 110 are arranged is the display area 100.

[0017] In the figure, the pixel circuit 110 without the light-emitting element is arranged in a 1x6 grid, while the light-emitting element is arranged in a 2x3 grid, as shown in the right column of Figure 4. Therefore, the size in the X direction of the pixel circuit 110 without the light-emitting element is half the size in the X direction of the light-emitting element, and the size in the Y direction of the pixel circuit 110 without the light-emitting element is twice the size in the Y direction of the light-emitting element.

[0018] The pixel circuits 110, excluding the light-emitting elements, are arranged in a matrix of 590 rows vertically and 11520 columns horizontally, while the light-emitting elements are arranged in a matrix of 1080 rows vertically and 5760 columns horizontally. In a planar view, three adjacent light-emitting elements in the X direction correspond to the red pixel circuit 110R, the green pixel circuit 110G, and the blue pixel circuit 110G, respectively, and the color of one dot is represented by additive color mixing of these three colors. Therefore, in this embodiment, an image will be displayed in which color dots are arranged in a matrix of 1080 rows vertically and 1920 columns horizontally.

[0019] Note that pixel circuits 110R, 110G, and 110G represent the red, green, and blue components of a single color pixel in that order, and strictly speaking, they should be called sub-pixel circuits, but for convenience in this explanation, they will be referred to as pixel circuits.

[0020] In Figure 2, the control circuit 20 controls each part based on the video data Vid and control signal Ctrl supplied from the host device. The video data Vid is supplied in synchronization with the synchronization signal and specifies the grayscale level of each pixel in the image to be displayed by the electro-optical device 10, for example, using 8 bits for each RGB component. The synchronization signal includes a vertical synchronization signal that instructs the start of vertical scanning of the video data Vid, a horizontal synchronization signal that instructs the start of horizontal scanning, and a dot clock signal that indicates the timing of one pixel of the video data Vid.

[0021] The control circuit 20 generates control signals Gref, Gcp, / Drst, / Gorst, / Gini, L_Ctr, Sel(1) to Sel(960) and the clock signal Clk as logic signals to control each part. The control circuit 20 also controls the scan line drive circuit 120 based on the vertical synchronization signal included in the control signal Ctrl. Although not shown in Figure 2, the control circuit 20 outputs the control signal / Gcp, which is logically inverted from the control signal Gcp; the control signal / Gref, which is logically inverted from the control signal Gref; and the control signals / Sel(1)~ / Sel(960), which are logically inverted from Sel(1)~Sel(960).

[0022] In these logic signals, the L level is 0V, which is the reference voltage of zero, and the H level is, for example, 6.0V. Furthermore, the control signals / Gel(1) to / Gel(540), which will be described later, take on three levels: L level, H level, and M level. The M level is a level with a value intermediate between the L level and the H level, for example, 4 to 5V.

[0023] The scan line drive circuit 120 is a circuit for driving the pixel circuits 110, which are arranged in a matrix, in units of one row. In addition to the scan signal, it outputs various control signals synchronized with the scan signal, although these are not shown in Figure 3.

[0024] The data signal output circuit 30 outputs a data signal toward the data line 14. More specifically, the data signal output circuit 30 outputs a data signal with a voltage corresponding to the grayscale level of each pixel. In this embodiment, the voltage amplitude of the data signal output from the data signal output circuit 30 is compressed and supplied to the data line 14. Therefore, the compressed data signal also has a voltage corresponding to the grayscale level of the pixel. Furthermore, the data signal output circuit 30 also has the function of parallelizing the video data Vdat supplied serially into multiple phases (in this example, "6" phases, corresponding to the number of columns of data lines 14 that make up the group) and outputting them. For simplicity, the following will be described using "6" phases.

[0025] The data signal output circuit 30 includes a shift register 31, a latch circuit 32, a D / A conversion circuit group 33, and an amplifier group 34. The shift register 31 sequentially transfers the video data Vdat, which is supplied serially in synchronization with the clock signal Clk, and stores one row, or 11,520 pixels, of the pixel circuit 110. In this embodiment, in order to output the video data Vdat in 6 phases in parallel, the shift register 31 sequentially stores the video data Vdat in 6 phases (6 pixels) at a time.

[0026] The latch circuit 32 latches the video data Vdat stored in the shift register 31 in 6-phase units according to the control signal L_Ctr, and outputs the latched video data Vdat in 6-phase parallel conversion according to the control signal L_Ctr.

[0027] The D / A conversion circuit group 33 includes six D / A (Digital to Analog) converters. These six D / A converters convert the six-phase video data Vdat output from the latch circuit 32 into an analog signal. The amplifier group 34 includes six amplifiers. These six amplifiers amplify the six-phase analog signal output from the D / A conversion circuit group 33 and output it as data signals Vd(1) to Vd(6).

[0028] Furthermore, the D / A conversion circuit may be configured such that, for example, a switch and a capacitive element are provided for each bit, and the charging and discharging of the capacitive element is controlled by the switch according to whether each bit is "0" or "1". Also, depending on the configuration of the data signal output circuit 30, the amplifier group 34 is not necessarily required. For example, if the D / A conversion circuit is configured such that a switch and a capacitive element are provided for each bit, and the charging and discharging of the capacitive element is controlled by the switch according to each bit, then the amplifier group 34 does not need to be provided.

[0029] As described later, the control circuit 20 outputs control signals Sel(1) to Sel(960) that are sequentially and exclusively at an H level during the compensation period preceding the write period.

[0030] In Figure 3, the scan line drive circuit 120 supplies scan signals / Gwr(1), / Gwr(2), ..., / Gwr(539), and / Gwr(540) to scan lines 12 of rows 1, 2, 3, ..., 539, and 540 in that order.

[0031] The electro-optical device 10 is provided with a data transfer line 14a that corresponds one-to-one with the data line 14. The switch group 40 is an assembly of transmission gates 45 provided for each data transfer line 14a. Of these, the input terminals of 1920 transmission gates 45 corresponding to the data transfer lines 14a of columns 1, 7, ..., 11515, i.e., column (6j-5), are connected in common. A data signal Vd(1) is supplied to these input terminals in time series for each pixel. Similarly, the input terminals of 1920 transmission gates 45 corresponding to the data transfer lines 14a of columns 2, 8, ..., 11516, i.e., column (6j-4), are connected in common, and data signals Vd(2) are supplied pixel by pixel in time series. Similarly, the input terminals of 1920 transmission gates 45 corresponding to the data transfer lines 14a of columns (6j-3), (6j-2), (6j-1), and (6j) are connected in common, and data signals Vd(3), Vd(4), Vd(5), and Vd(6) are supplied pixel by pixel in time series, respectively. The output terminal of one row of transmission gates 45 is connected to one end of the data transfer line 14a of that row.

[0032] The six transmission gates 45 corresponding to columns (6j-5) to (6j) belonging to the j-th group are turned ON between the input and output terminals when the control signal Sel(j) is at a high level (when the control signal / Sel(j) is at a low level). Note that, due to space limitations, only the first group and a portion of the 960th group are shown in Figure 3, while the other groups are omitted. Also, the transmission gate 45 in Figure 3 is simplified and shown as a simple switch in Figure 2.

[0033] In this explanation, the "on state" of a switch, transistor, or transmission gate refers to a low impedance state where both ends of a switch, the source node and drain node of a transistor, or both ends of a transmission gate are electrically connected. Conversely, the "off state" of a switch, transistor, or transmission gate refers to a high impedance state where both ends of a switch, the source node and drain node, or both ends of a transmission gate are electrically disconnected. Furthermore, in this description, "electrically connected" or simply "connected" means a direct or indirect connection or coupling between two or more elements.

[0034] The capacitive element group 50 is an assembly of capacitive elements 51 provided for each data transfer line 14a. Here, one end of a capacitive element 41 corresponding to a certain row of data transfer lines 14a is connected to one end of the data transfer line 14a, and the other end of the capacitive element 41 is grounded to a constant potential, for example, a reference potential of zero voltage.

[0035] The auxiliary circuit 70 is an assembly of transmission gates 72 and 73 provided in each row, and capacitive elements 74 and 75 provided in each row. Here, the transmission gate 72 corresponding to a certain column is turned ON between its input and output terminals when the control signal Gcp is at an H level (when the control signal / Gcp is at an L level). The input terminal of the transmission gate 72 corresponding to a certain column is connected to the other end of the data transfer line 14a of that column, and the output terminal of the transmission gate 72 corresponding to that column is connected to the output terminal of the transmission gate 73 corresponding to that column, one end of the capacitive element 74 corresponding to that column, and one end of the capacitive element 75 corresponding to that column.

[0036] A transmission gate 73 corresponding to a particular row is turned on between its input and output terminals when the control signal Gref is at a high level (when the control signal / Gref is at a low level). A voltage Vref is applied to the input terminal of the transmission gate 73 corresponding to a particular row. Furthermore, the other end of a capacitive element 75 corresponding to a certain row is grounded to a constant potential, for example, a reference potential of zero voltage. The other end of a capacitive element 74 corresponding to a particular row is connected to one end of a data line 14 corresponding to that row.

[0037] The initialization circuit 60 is an assembly of P-channel MOS type transistors 66, 68 and N-channel MOS type transistors 67, each provided for every data line 14. A control signal / Drst is supplied to the gate electrode of a transistor 66 corresponding to a data line 14 in a given row, a voltage Vel is applied to the source node of the transistor 66, and the drain node of the transistor 66 is connected to the data line 14 in that row. Furthermore, a control signal / Gorst is supplied to the gate electrode of a transistor 67 corresponding to a certain row of data lines 14, a voltage Vorst is applied to the source node of the transistor 67, and the drain node of the transistor 67 is connected to the data line 14 of that row. A control signal / Gini is supplied to the gate electrode of a transistor 68 corresponding to a data line 14 in a given row, a voltage Vini is applied to the source node of the transistor 68, and the drain node of the transistor 68 is connected to the data line 14 in that row.

[0038] Figure 5 shows the configuration of the pixel circuit 110. The configurations of pixel circuits 110R, 110G, and 110B are electrically identical. Therefore, for the purposes of this explanation, we will use the pixel circuit 110 in row i, corresponding to column (6j-5), as a representative example.

[0039] As shown in the figure, the pixel circuit 110 includes P-channel MOS type transistors 121-124, an OLED 130, and a capacitive element 140. In addition, the i-th row pixel circuit 110 receives control signals / Gcmp(i) and / Gel(i) from the scan line drive circuit 120, as well as the scan signal / Gwr(i).

[0040] OLED130 is an example of a light-emitting element, in which a light-emitting layer 132 is sandwiched between a pixel electrode 131 and a common electrode 133. The pixel electrode 131 functions as an anode, and the common electrode 133 functions as a cathode. The pixel electrode 131 is light-reflective, and the common electrode 133 is both light-reflective and light-transmitting. In OLED130, when current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode recombine in the light-emitting layer 132 to generate excitons, and white light is produced.

[0041] In this embodiment, when a color display is achieved, the generated white light resonates in an optical resonator composed of, for example, a reflective layer and a semi-reflective, semi-transparent layer (not shown), and is emitted at a resonant wavelength set to correspond to one of the colors R (red), G (green), or B (blue). A color filter corresponding to the color is provided on the light emission side of the optical resonator, as will be described later. Therefore, the light emitted from the OLED 130 is colored by the optical resonator and color filter before being visible to the observer. Furthermore, if the electro-optical device 10 simply displays a monochrome image consisting only of light and dark areas, the above-mentioned color filter is omitted.

[0042] In the case of transistor 121 of the pixel circuit 110 in row i (6j-5), the gate electrode g is connected to the drain node of transistor 122 and one end of the capacitive element 140, the source node s is connected to the voltage Vel wiring 116, and the drain node d is connected to the source node of transistor 123 and the source node of transistor 124. The other end of the capacitive element 140 is connected to wiring 116 with a constant voltage, for example, voltage Vel. Therefore, the capacitive element 140 maintains the voltage between the gate electrode g and source node s in the transistor 121. The capacitive element 140 may be formed by sandwiching an insulating film between electrodes made of different wiring layers on a semiconductor substrate, as will be described later, or a capacitance parasitic to the gate electrode g of the transistor 121 may be used.

[0043] In the case of the transistor 122 of the pixel circuit 110 in row i (6j-5), the gate electrode is connected to the scan line 12 of row i, and the source node is connected to the data line 14 of the corresponding (6j-5) column. In the transistor 123 of the pixel circuit 110 in row i (6j-5), the control signal / Gcmp(i) is supplied to the gate electrode, and the drain node is connected to the data line 14 of the (6j-5) column. The control signal / Gcmp(i) is supplied from the scan line drive circuit 120 via the control line 117 of row i. In the transistor 124 of the pixel circuit 110 in row i (6j-5), the control signal / Gel(i) is supplied to the gate electrode, and the drain node is connected to the pixel electrode 131, which is the anode of the OLED 130. The control signal / Gel(i) is supplied from the scan line drive circuit 120 via the control line 118 of row i. The common electrode 133, which functions as the cathode of the OLED 130, is connected to a power supply line with voltage Vct. Furthermore, since the electro-optical device 10 is formed on a semiconductor substrate, the substrate potential of the P-channel transistors 121-124 is, for example, defined as voltage Vel.

[0044] Figure 6 is a timing chart illustrating the operation of the electro-optical device 10, and Figure 7 shows an example of the relationship between the scanning signal and the control signal for light emission.

[0045] In the electro-optical device 10, horizontal scanning is performed in the order of rows 1, 2, 3, ..., m, during the period of one frame (V). In this explanation, the duration of one frame (V) refers to the period required to display one frame of the image specified by the video data Vid. The length of one frame is 16.7 milliseconds, which corresponds to one cycle of the vertical synchronization signal if the frequency of the vertical synchronization signal included in the synchronization signal Sync is 60 Hz. The horizontal scan period (H) is the period required to horizontally scan one line. Note that in Figures 5 and 6, the vertical scales showing voltage are not necessarily aligned across all signals.

[0046] The operation of the pixel circuit 110 during the horizontal scanning period (H) in each row is almost identical. Furthermore, the operation of the pixel circuit 110 in columns 1 to 11520 of a row scanned during a given horizontal scanning period (H) is also almost identical. Therefore, the following explanation will focus on the pixel circuit 110 in row i and column (6j-5).

[0047] In the electro-optical device 10, the horizontal scanning period (H) is divided into five periods in chronological order: initialization period (A), (B), (C), compensation period (D), and write period (E). In addition, the operation of the pixel circuit 110 includes an additional light emission period (F) to the above five periods. The light emission period (F) in the i-th row is the period during which the control signal / Gel(i) is at the M level in Figure 7.

[0048] Of the initialization periods (A), (B), and (C), initialization period (A) is the period for setting transistor 121 to the off state and is a period for preparatory processing before initialization period (C). Initialization period (B) is the period for resetting the potential at the anode of OLED 130, and initialization period (C) is the period for applying a voltage to the gate electrode g of transistor 121 to turn on transistor 121 at the start of compensation period (E).

[0049] During the horizontal scanning period (H), in the initialization period (A), the control signals / Gini, / Gorst, / Drst, / Gref, and / Gcp are at the H, H, L, H, and L levels, respectively. Therefore, transistor 68 is in the off state, transistor 67 is in the off state, transistor 66 is in the on state, transmission gate 73 is in the on state, and transmission gate 72 is in the off state. Furthermore, during the initialization period (A) of the horizontal scanning period (H) in which row i is selected, the scanning signal / Gwr(i) is at the L level, the control signal / Gcmp(i) is at the H level, and the control signal / Gel(i) is at the H level. Therefore, in the pixel circuit 110, transistor 122 is in the ON state, and transistors 123 and 124 are in the OFF state.

[0050] Therefore, during the initialization period (A), as shown in Figure 8, the voltage Vref is applied via the transmission gate 73 to one end of the capacitive element 74, one end of the capacitive element 75, and the output terminal of the transmission gate 72. In the pixel circuit 110, the voltage Vel is applied sequentially via the transistor 66, the data line 14, and the transistor 122 to one end of the capacitive element 140 and the gate electrode g of the transistor 121. When the voltage Vel is applied to the gate electrode g, the voltage between the gate electrode g and the source node s becomes zero, so the transistor 121 is forced to turn off, and the current flowing to the OLED 130 is interrupted. Also, since the voltage Vel is applied to the other end of the capacitive element 74 via the data line 14, the capacitive element 74 is charged to the voltage |Vel-Vref|.

[0051] During the horizontal scanning period (H), in the initialization period (B), the control signal / Gini is at the H level, the control signal / Gorst is at the L level, the control signal / Drst is at the H level, the control signal Gref is at the H level, and the control signal Gcp is at the L level. As a result, transistor 68 remains in the off state, transistor 67 changes to the on state, transistor 66 changes to the off state, transmission gate 73 remains in the on state, and transmission gate 72 remains in the off state. Furthermore, during the initialization period (B) of the horizontal scanning period (H) in which row i is selected, the scanning signal / Gwr(i) becomes H level, the control signal / Gcmp(i) becomes L level, and the control signal / Gel(i) becomes L. As a result, in the pixel circuit 110, transistor 122 becomes OFF, and transistors 123 and 124 become ON.

[0052] Therefore, during the initialization period (B), as shown in Figure 9, one end of the capacitive element 74, one end of the capacitive element 75, and the output terminal of the transmission gate 72 are maintained at the voltage Vref. In the pixel circuit 110, the voltage Vorst is applied to the pixel electrode 131, which is the anode of the OLED 130, via transistor 67, data line 14, transistors 123 and 124 in sequence. Since the OLED 130 sandwiches the light-emitting layer 132 between the pixel electrode 131 and the common electrode 133, a capacitive component is parasitic. During the initialization period (B), the voltage Vorst applied to the pixel electrode 131 resets the voltage held by the capacitive component, specifically the voltage corresponding to the current that flowed through the OLED 130 during the light-emitting period (F). The voltage Vorst is the voltage that causes the OLED 130 to stop emitting light, and specifically, it is zero volts, which corresponds to the L level, or a voltage close to zero volts (0 to 1 volt). Furthermore, since the voltage Vorst is applied to the other end of the capacitive element 74 via the data line 14, the capacitive element 74 is charged to the voltage |Vorst-Vref|.

[0053] During the horizontal scanning period (H), in the initialization period (C), the control signal / Gini is at a low level, the control signal / Gorst is at a high level, the control signal / Drst is at a high level, the control signal / Gref is at a high level, and the control signal / Gcp is at a low level. As a result, transistor 68 changes to the ON state, transistor 67 changes to the OFF state, transistor 66 remains in the OFF state, transmission gate 73 remains in the ON state, and transmission gate 72 remains in the OFF state. Furthermore, during the initialization period (C) of the horizontal scanning period (H) in which row i is selected, the scanning signal / Gwr(i) becomes L level, the control signal / Gcmp(i) becomes H level, and the control signal / Gel(i) becomes H level. As a result, in the pixel circuit 110, transistor 122 becomes ON, and transistors 123 and 124 become OFF.

[0054] Therefore, during the initialization period (C), as shown in Figure 10, one end of the capacitive element 74, one end of the capacitive element 75, and the output terminal of the transmission gate 72 are maintained at the voltage Vref. In addition, in the pixel circuit 110, the voltage Vini is applied to one end of the capacitive element 140 and the gate electrode g of the transistor 121, sequentially via the transistor 68, the data line 14, and the transistor 122. Furthermore, since the voltage Vini is applied to the other end of the capacitive element 74 via the data line 14, the capacitive element 74 is charged to the voltage |Vini-Vref|.

[0055] During the horizontal scanning period (H) and the compensation period (D), the control signal / Gini is at the H level, the control signal / Gorst is at the H level, the control signal / Drst is at the H level, the control signal / Gref is at the H level, and the control signal / Gcp is at the L level. As a result, transistor 68 changes to the off state, transistor 67 remains in the off state, transistor 66 remains in the off state, transmission gate 73 remains in the on state, and transmission gate 72 remains in the off state. Furthermore, during the compensation period (D) of the horizontal scanning period (H) in which row i is selected, the scanning signal / Gwr(i) remains at an L level, the control signal / Gcmp(i) changes to an L level, and the control signal / Gel(i) remains at an H level. As a result, in the pixel circuit 110, transistor 122 remains in the ON state, transistor 123 becomes ON, and transistor 124 becomes OFF.

[0056] Therefore, during the compensation period (D), as shown in Figure 11, one end of the capacitive element 74, one end of the capacitive element 75, and the output terminal of the transmission gate 72 are maintained at voltage Vref. In the pixel circuit 110, one end of the capacitive element 140 is held at voltage Vini during the preceding initialization period (C), and therefore maintains a voltage of (Vel-Vini) between the gate electrode g and source node s of the transistor 121. In this state, when transistor 123 is turned on, transistor 121 enters a state where its gate electrode and drain node are connected, i.e., a diode connection state. Therefore, the voltage Vgs between the gate electrode g and source node s of transistor 121 converges to approach the threshold voltage of transistor 121. Here, if we conveniently denote the threshold voltage as Vth, the gate electrode g of transistor 121 converges to approach a voltage (Vel-Vth) corresponding to the threshold voltage Vth.

[0057] Furthermore, at the start of the compensation period (D), it is necessary for current to flow from the source node to the drain node in the diode-connected transistor 121. Therefore, the voltage Vini applied to the gate electrode g during the initialization period (C) prior to the compensation period (D) is: Vini <Vel-Vth They are in that relationship.

[0058] Furthermore, during the compensation period (D), the gate electrode g of transistor 121 is connected to the data line 14 via transistor 122, and the drain node d of transistor 121 is connected to the data line 14 via transistor 123. As a result, the other end of the data line 14 and the capacitive element 74 also converge to approach the voltage (Vel-Vth). Consequently, the capacitive element 74 is charged to approximately the voltage |Vel-Vth-Vref|.

[0059] On the other hand, during the compensation period (D), the control signals Sel(1) to Sel(960) sequentially become H level exclusively. Although omitted in Figure 5, during the compensation period (D), the control signals / Sel(1) to / Sel(960) become L level sequentially exclusively in synchronization with the control signals Sel(1) to Sel(60). Furthermore, the data signal output circuit 30 is a pixel circuit 110 that corresponds to the intersection of the i-th scan line 12 and the j-th group data line 14, when, for example, the control signal Sel(j) among the control signals Sel(1) to Sel(960) reaches a high level, and outputs data signals Vd(1) to Vd(6) of the RGB components of the color represented in the dot represented by the pixel circuit 110. For example, the data signal output circuit 30 outputs the R component (R1) of the dot represented in the i-th row (6j-5) pixel circuit 110R as the data signal Vd(1) during the period when the control signal Sel(j) is at a high level. Also, for example, it outputs the G component (G2) of the dot represented in the i-th row (6j-4) pixel circuit 110G as the data signal Vd(4).

[0060] When the control signals Sel(1) to Sel(960) are sequentially and exclusively set to a high level, the voltage of the data signal corresponding to each pixel is held in the capacitive elements 51 corresponding to the first to 11520th columns. Figure 10 shows the state in which the control signal Sel(j) corresponding to the j-th group to which the pixel circuit 110 belongs becomes high level during the compensation period (D), and the voltage Vdata of the data signal Vd(1) is held in the capacitive element 51.

[0061] During the horizontal scanning period (H) and the write period (E), the control signals / Gini, / Gorst, and / Drst are at an H level, the control signal / Gref is at an L level, and the control signal / Gcp is at an H level. As a result, transistors 68, 67, and 66 remain in the off state, the transmission gate 73 changes to the off state, and the transmission gate 72 changes to the on state. Also, during the write period (E) of the horizontal scanning period (H) in which row i is selected, the scan signal / Gwr(i) remains at an L level, the control signal / Gcmp(i) changes to an H level, and the control signal / Gel(i) remains at an H level. As a result, in the pixel circuit 110, transistor 122 is in the ON state, and transistors 123 and 124 are in the OFF state.

[0062] Therefore, during the write period (E) of the horizontal scanning period (H) in which row i is selected, as shown in Figure 12, one end of the capacitive element 74 changes in accordance with the voltage Vref held in the capacitive element 51, depending on the off state of the transmission gate 73 and the on state of the transmission gate 72. This voltage change propagates through the capacitive element 74 to the gate electrode g via the data line 14 and transistor 122 in sequence. The voltage of the gate electrode g after this change is held in the capacitive element 140.

[0063] As shown in Figure 12, the capacitance of capacitive element 51 is denoted as Cref, the capacitance size of capacitive element 74 is denoted as Cblk, the capacitance size of capacitive element 75 is denoted as Cdt, and the capacitance size of capacitive element 140 is denoted as Cpix. In addition, the voltage of the data signal Vd(1) held in capacitive element 51 during the compensation period (D) is denoted as Vdata. The voltage change ΔV of the gate electrode g from the compensation period (D) to the write period (E) is given by equation (1).

[0064]

number

[0065] In other words, as shown in equation (1), the gate electrode g changes to a value obtained by multiplying the voltage change at one end of the capacitive element 74 (Vdata-Vref) by the coefficient Ka. The coefficient Ka is a coefficient less than "1" and is determined by the capacitance sizes Cref, Cblk, Cdt, and Cpix. In other words, the capacitance sizes Cref, Cblk, Cdt, and Cpix are designed to be of appropriate values ​​so that the coefficient Ka is less than "1". If the coefficient Ka is less than "1", the voltage amplitude from the lowest to the highest value of the data signal voltage Vdata will be compressed according to the coefficient Ka and propagated to the gate electrode g. When the pixel circuit 110 is miniaturized, even a very small change in the voltage Vgs between the gate electrode g and source node s in the transistor 121 can cause a large change in the current flowing through the OLED 130. Even in this case, in this embodiment, the voltage amplitude of the data signal voltage Vdata is compressed according to the coefficient Ka and propagated to the gate electrode g, so that the current flowing through the OLED130 can be controlled with high precision.

[0066] After the writing period (E) ends, the illumination period (F) begins. In this embodiment, from the horizontal scanning period (H) in which the i-th row is selected, through the elapsed period of one frame (V), until the horizontal scanning period (H) in which the i-th row is selected again, the illumination period (F) for the i-th row occurs, for example, four times, as shown in Figure 7. Specifically, after the horizontal scanning period (H) in which the i-th row is selected, four illumination periods (F) in which the control signal / Gel(i) becomes M level occur at approximately equal intervals, and the duration of the periods in which the signal becomes M level is set to be approximately the same length. Furthermore, the illumination period (F) of the i-th row may be continued from the horizontal scanning period (H) in which the i-th row is selected until the horizontal scanning period (H) in which the i-th row is selected again, i.e., the control signal / Gel(i) may be continued at the M level.

[0067] When the control signal / Gel(i) reaches the M level during the light emission period (F), as shown in Figure 13, transistor 121 supplies a current Iel to the OLED 130 that corresponds to the voltage Vgs and is limited by the resistance between the source node and drain node of transistor 124. Consequently, the OLED 130 emits light with a brightness corresponding to the current Iel.

[0068] Note that in Figures 8 to 13, the regions where the capacitive element group 50 and the initialization circuit 60 are provided are not particularly distinguished.

[0069] In this embodiment, the amplitude of the voltage Vdata of the data signal output from the data signal output circuit 30 is compressed via the capacitive element 74 and supplied as a data signal to the gate electrode g in the pixel circuit 110. On the other hand, the configuration compensates for the threshold voltage Vth of transistor 121 during the compensation period (D). Next, we will explain the usefulness of the compensation period (D). In explaining this usefulness, to avoid complicating the formulas, we will assume that the compression ratio of the data signal voltage Vdata is "1", that is, that the data signal voltage Vdata is supplied directly to the data line 14 during the write period (E) after the compensation period (D). Furthermore, we will assume that during the light emission period (F), an L level, not an M level, is applied to the gate electrode of transistor 124, turning on transistor 124, and that the resistance between the source node and the drain node is ideally zero.

[0070] First, the current Iel flowing through the OLED130 during the light emission period (F) can be expressed as shown in equation (2) below.

[0071]

number

[0072]

number

[0073] In equation (3), W is the channel width of transistor 121, L is the channel length of transistor 121, μ is the carrier mobility, and Cox is the capacitance per unit area of ​​the (gate) oxide film in transistor 121.

[0074] In a configuration in which the data signal voltage Vdata is not compressed and the threshold voltage of transistor 121 is not compensated, when the data signal voltage Vdata is directly applied to the gate electrode g of transistor 121, the voltage Vgs between the gate electrode g and the source node s in transistor 121 can be expressed as shown in equation (4) below.

[0075]

number

[0076]

number

[0077] As shown in equation (5), the current Iel is affected by the threshold voltage Vth. Here, due to semiconductor process limitations, the variation in the threshold voltage Vth at transistor 121 is in the range of several mV to tens of mV. When the threshold voltage Vth at transistor 121 varies in the range of several mV to tens of mV, the current Iel may differ by up to 40% between adjacent pixel circuits 110.

[0078] The current-brightness characteristics in the OLED130 are generally linear. Therefore, in a configuration that does not compensate for the threshold voltage Vth, even if the same voltage Vdata data signal is supplied to the two pixel circuits 110 to make the two OLED130s emit light at the same brightness, the actual current flowing through the OLED130s will differ. Consequently, in a configuration that does not compensate for the threshold voltage Vth, the brightness will vary, significantly impairing the display quality.

[0079] During the compensation period (D), if the gate electrode g of transistor 121 is brought to converge towards the voltage (Vel-Vth) and then changed to the voltage Vdata, the voltage Vgs between the gate electrode g and the source node s of transistor 121 can be expressed as shown in equation (6).

number

[0080] In equation (6), the coefficient k2 is determined by the capacitance sizes Cblk and Cpix in a configuration where the data signal voltage Vdata is not compressed (a configuration without the capacitance element 74). When the voltage Vgs is expressed as in equation (6), the current Iel flowing through OLED130 can be expressed as in equation (7).

[0081]

number

[0082] In equation (7), the threshold voltage Vth term is removed, and the current Iel is determined by the data signal voltage Vdata. This makes it possible to suppress the degradation of display quality caused by the threshold voltage Vth of transistor 121. In this embodiment, as shown in equation (1), the voltage amplitude from the lowest to the highest value of the data signal voltage Vdata is actually compressed according to the coefficient Ka and propagated to the gate electrode g. Furthermore, in this embodiment, an M level is supplied to the gate electrode of transistor 124 during the light emission period (F), limiting the current Iel, but this does not change the fact that the degradation of display quality caused by the threshold voltage Vth is suppressed.

[0083] Next, the usefulness of applying an M level to the gate electrode of transistor 124 during the light emission period (F) in this embodiment will be explained. The reason for applying an M level to the gate electrode of transistor 124 is to operate transistor 124 in the saturation region, thereby maintaining constant current characteristics by transistor 121, regardless of the aging of the current-voltage characteristics in OLED 130.

[0084] In detail, when a current Iel flows, the OLED 130 emits light with a brightness corresponding to the current Iel. In this embodiment, the pixel circuit 110 ensures constant current of the current Iel flowing from the wiring 116 to the OLED 130 by maintaining the voltage of the gate electrode g of the transistor 121 with the capacitive element 140.

[0085] However, in the OLED130, the element characteristics change as the light emission time progresses, and the potential of the anode (pixel electrode 131) required to flow a constant current gradually increases. When the potential of the anode in the OLED130 increases, the equilibrium point of the potential in the path from the wiring 116 to the common electrode 133 changes, and the potential of the source node of transistor 124, i.e., the drain node d of transistor 121, rises. When the potential of the drain node d of transistor 121 rises, the voltage between the source node s and the drain node d of transistor 121 also fluctuates, and the current flowing through the drain node of transistor 121 also fluctuates, so as a result, the constant current property of the OLED130 is impaired.

[0086] Therefore, in this embodiment, as a countermeasure against the loss of constant current characteristics due to aging of the OLED130 element characteristics, the transistor 124 is operated in the saturation region. When transistor 124 is operated in the saturation region, even if the anode potential in OLED 130 changes, it is transistor 124 that is directly affected. Transistor 121 is affected by the potential fluctuation at the drain node of transistor 124, but the fluctuation in drain current in the saturation region is minute. Therefore, the effects of the potential fluctuation at the drain node of transistor 121 connected to transistor 124, and consequently the potential fluctuation of the gate electrode due to current leakage, are mitigated.

[0087] In the arrangement shown in Figure 4, the size in the X direction of the pixel circuit 110 excluding the light-emitting element is half the size in the X direction of the light-emitting element, which can become a bottleneck when trying to achieve a narrow pitch, miniaturization, and high resolution in the pixel circuit 110. Therefore, in the electro-optical device 10 according to this embodiment, the structure of the pixel circuit 110 that addresses this issue will be described.

[0088] Figure 14 is a cross-sectional view of the main part of the electro-optical device 10, showing the layered structure of wiring and transistors. Note that Figure 14 is a diagram for a simplified explanation of the wiring layer of the electro-optical device 10 and is not a diagram showing a specific part of the electro-optical device 10 broken off. In the semiconductor substrate constituting the electro-optical device 10, the layers used as conductive layers are, in order from the Z direction as shown in Figure 14, a semiconductor layer 210, a gate electrode layer 220, a first wiring layer 230, a second wiring layer 240, a third wiring layer 250, and a pixel electrode layer 270. For the first wiring layer 230, the second wiring layer 240, and the third wiring layer 250, for example, aluminum or an aluminum-containing alloy is used. The pixel electrode layer 270 is a laminate of a reflective metal layer and a transparent and conductive wire layer. For example, aluminum or an aluminum-containing alloy is used as the reflective metal layer, and for example, indium tin oxide is used as the transparent and conductive wire layer.

[0089] In the detailed description of the invention, the ordinal numbers of the wiring layers (1st, 2nd, 3rd) indicate the order of film formation on the semiconductor substrate, whereas the ordinal numbers of the wiring layers in the claims are used to distinguish between the wiring layers. Therefore, the ordinal numbers of the wiring layers in the detailed description of the invention and the ordinal numbers of the wiring layers in the claims do not necessarily coincide.

[0090] In the semiconductor layer 210, wiring and semiconductor regions are formed, for example, by implanting impurity ions into the p-well region (Well). A gate insulating film 280 is provided between the semiconductor layer 210 and the gate electrode layer 220 in the Z direction. Trench St is provided to demarcate the semiconductor region. The patterning of the gate electrode layer 220 provides electrodes that will serve as the gate electrodes of transistors 121 to 124 and the other end of the capacitive element 140. Electrical contact is established between the electrodes of the semiconductor layer 210 and the electrodes of the gate electrode layer 220 through contact holes opened in the gate insulating film 280.

[0091] In a semiconductor substrate, transistors 121 to 124 function through elements extending in the Z direction up to the gate electrode layer 220. For this reason, as shown in Figure 14, the portion of the electro-optical device 10 up to the gate electrode layer 220 is sometimes conveniently referred to as the substrate 11. The thickness direction of the substrate 11 is the Z direction (or the opposite direction of the Z direction).

[0092] In the first wiring layer 230, the second wiring layer 240, and the third wiring layer 250, wiring, electrodes, etc., are provided by patterning of each layer. Pixel electrodes 131 are provided by patterning of the pixel electrode layer 270.

[0093] A first interlayer insulating film 281 is provided between the gate electrode layer 220 and the first wiring layer 230. Electrical connection is established between the electrode made of the gate electrode layer 220 and the wiring etc. made of the first wiring layer 230 through a contact hole opened in the first interlayer insulating film 281. A second interlayer insulating film 282 is provided between the first wiring layer 230 and the second wiring layer 240. Electrical connection is established between the wiring etc. made of the first wiring layer 230 and the wiring etc. made of the second wiring layer 240 through contact holes opened in the second interlayer insulating film 282. A third interlayer insulating film 283 is provided between the second wiring layer 240 and the third wiring layer 250. Electrical connection is established between the wiring etc. made of the second wiring layer 240 and the wiring etc. made of the third wiring layer 250 through contact holes opened in the third interlayer insulating film 283. A fourth interlayer insulating film 284 is provided between the third wiring layer 250 and the pixel electrode layer 270. Electrical connection is established between the wiring etc. made up of the third wiring layer 260 and the pixel electrode 131 made up of the pixel electrode layer 270 through contact holes opened in the fourth interlayer insulating film 284.

[0094] Figures 15 to 19 are plan views illustrating the specific wiring structure in the electro-optical device 10. More specifically, Figure 15 is a plan view showing the transistor region and wiring formed by the semiconductor layer 210, and the electrodes formed by patterning the gate electrode layer 220. Figure 16 is a plan view showing the wiring formed by patterning the first wiring layer 230. Figure 17 is a plan view showing the wiring formed by patterning the second wiring layer 240. Figure 18 is a plan view showing the wiring formed by patterning the third wiring layer 250. Figure 19 is a plan view showing the pixel electrode 131 formed by patterning the pixel electrode layer 270.

[0095] In Figures 15 to 19, the small-diameter square frames indicate the positions of the contact holes. Regarding the names of each part, ...layer refers to the conductive layer after film formation but before patterning, or a layer that collectively refers to wiring, electrodes, etc., that share the same conductive layer before patterning. ...wire, ...electrode, ...intermediate member refers to those formed by patterning the ...layer, and includes scan lines 12, data lines 14, control lines 117, 118.

[0096] In Figure 15, region 211 is the semiconductor region of transistor 121, and is formed, for example, by implanting impurity ions into the p-well region of the semiconductor substrate. Region 212 is a common semiconductor region of transistors 122 to 124, and is formed by implanting impurity ions, similar to region 211.

[0097] Electrode 221 is the gate electrode of transistor 121. In the figure, the region where electrode 221 and region 211 overlap in a plan view is the channel region of transistor 121. Similarly, electrode 222 is the gate electrode of transistor 122. The region where electrode 222 and region 212 overlap in a plan view is the channel region of transistor 122. Electrode 223 is the gate electrode of transistor 123. The region where electrode 223 and region 212 overlap in a plan view is the channel region of transistor 123. Electrode 224 is the gate electrode of transistor 124. The region where electrode 224 and region 212 overlap in a plan view is the channel region of transistor 124.

[0098] As shown in Figure 15, in two adjacent pixel circuits of the same color along the X direction, the transistors 121-124 and electrodes 221-224 in the two pixel circuits, excluding the light-emitting element, are arranged symmetrically in a plan view with respect to the line Cen that demarcates the two pixel circuits. In this explanation, a plan view refers to the view of the electro-optical device 10 from the opposite direction of the Z-axis.

[0099] As shown in Figure 16, the first wiring layer 230 is patterned to provide wiring 231, scan lines 12, control lines 117, 118, and wiring 232-237. Each of the wirings 231, scan lines 12, and control lines 117 and 118 extends in the X direction and is provided in 540 rows, corresponding to the arrangement of the pixel circuits 110 excluding the light-emitting elements. In other words, the wirings 231, scan lines 12, and control lines 117 and 118 are each provided in common for one row (11,520 pixels) of the pixel circuits 110.

[0100] A voltage Vel is applied to wiring 231 directly or indirectly. For this reason, wiring 231 is wider in the Y direction than the scan lines 12, control lines 117 and 118 which also extend in the X direction, in order to reduce wiring resistance. In addition, as will be described later, wiring 231 is connected via contact holes to wiring provided by the patterning of other second wiring layers 240 and third wiring layers.

[0101] Wiring 232 is a relay wire that leads the drain node of transistor 122 to the gate node of transistor 121. The wiring 231 has portions 231a and 231b that protrude in the Y direction, in addition to portions that extend in the X direction, so as to include the boundary with adjacent pixel circuits in the X direction, and sandwich the wiring 232 on the left and right. In detail, portion 231a is provided to include a dividing line Cen between two adjacent pixel circuits of the same color along the X direction, and portion 23ba is provided to include a dividing line between two adjacent pixel circuits of different colors along the X direction. Therefore, three sides of the wiring 232 connected to the gate node of transistor 121 are shielded by wiring 231, which includes portions 231a and 231b made of the same first wiring layer 230.

[0102] Wiring 233 is a relay wire that leads the drain node of transistor 121 to the source node of transistor 123 and the source node of transistor 124. Wiring 234 is a relay wire that leads the source node of transistor 121 to data line 14. Wiring 235 is a relay wiring that leads wiring 242 of the second wiring layer 240, which will be described next, to the source node of transistor 123 and the source node of transistor 124. Wiring 236 is a relay wire that leads the drain node of transistor 124 to the pixel electrode 131, which is the anode of OLED 130.

[0103] As shown in Figure 16, the wiring 232-236 in two adjacent pixel circuits of the same color along the X direction, excluding the light-emitting element, is arranged symmetrically with respect to line Cen in a plan view.

[0104] As shown in Figure 17, wirings 241 to 244 are provided by patterning the second wiring layer 240. Wiring 241 has, in a plan view, a portion that is wide and extends in the X direction, and a portion that extends in the Y direction so as to include line Cen. A voltage Vel is applied to wiring 241 directly or indirectly, and it is connected to wiring 231 via a contact hole. Furthermore, a portion 241a of the wiring 241 that extends in the Y direction is wider and covers the wiring 232 in a plan view. As a result, the wiring 232 connected to the gate node of transistor 121 is shielded in three directions by the wiring 231 on the same layer, and by portion 241a on the upper layer.

[0105] Wiring 242 is a relay wire that leads wiring 233 to the source node of transistor 123 and the source node of transistor 124. Therefore, the drain node of transistor 121 is connected to the source node of transistor 123 and the source node of transistor 124 via wires 233, 242, and 235 in that order. Wiring 243 is a relay wire that leads wiring 234 to data line 14. Wiring 244 is a relay wire that leads wiring 236 to the pixel electrode 1314.

[0106] As shown in Figure 17, two adjacent pixel circuits of the same color along the X direction, excluding the light-emitting element, have wirings 241-243 arranged symmetrically with respect to line Cen in a plan view.

[0107] As shown in Figure 18, the patterning of the third wiring layer 250 provides wiring 251, 252, 253 and data line 14. The wiring 251 is provided so as to include line Cen in a plan view, and the data line 14 is provided parallel to the wiring 251 and extends in the Y direction. Wiring 252 is provided approximately parallel to the data line 14, but has a portion 252a that bends to avoid wiring 253. Both wiring 251 and 252 are connected to the lower wiring 241 via contact hoses. Therefore, a voltage Vel is applied to both wiring 251 and 252. Wiring 253 is a relay wire that leads wiring 244 to the pixel electrode 131. The data line 14 is connected to the source node of transistor 122 and the drain node of transistor 123 via wirings 243 and 234 in order.

[0108] The data line 14 is sandwiched between wirings 251 and 252 to which voltage Vel is applied. Therefore, the data line 14 is shielded by wirings 251 and 252 on the same layer.

[0109] As shown in Figure 18, the wiring 251, 252 and data line 14 in the two adjacent pixel circuits of the same color along the X direction, excluding the light-emitting element, are arranged symmetrically with respect to line Cen in a plan view.

[0110] As shown in Figure 19, the pixel electrode 131 is provided by patterning the pixel electrode layer 270. The pixel electrode 131 is connected to the drain node of the transistor 124 via wirings 253, 244, and 236 in order. As shown in Figure 19, two adjacent pixel circuits of the same color along the X direction, excluding the light-emitting element, have wirings 251-253 arranged symmetrically with respect to line Cen in a plan view. Furthermore, the pixel electrode 131 is positioned at a shifted position in the Y direction in a plan view relative to the position of the corresponding pixel circuit (excluding the light-emitting element).

[0111] To explain the advantages of the electro-optical apparatus 10 according to this embodiment, an electro-optical apparatus according to a comparative example will be described. Figures 20 to 24 are plan views illustrating the specific wiring structure in the comparative example, and correspond in order to Figures 15 to 19 showing the embodiment. As shown in these figures, in the comparative example, pixel circuits of the same color that are adjacent in the X direction are in the same arrangement, rather than being symmetrically arranged around line Cen as in this embodiment.

[0112] In the comparative example, in a single row of pixel circuits 110, the wiring that is made up of the same wiring layer and extends along the Y direction requires a total of three wires, as shown in Figure 23 or 24: the data line 14 of the third wiring layer, the wiring 251 for applying voltage Vel, and the relay wiring 253. If we consider two adjacent rows of pixel circuits in the X direction, a total of six wires are required. In contrast, in this embodiment, the wiring 251 for applying voltage Vel is provided so as to include line Cen in a plan view and is shared by pixel circuits of the same color and adjacent in the X direction. Therefore, in this embodiment, for two rows of pixel circuits of the same color and adjacent in the X direction, only a total of five wires are needed: two data lines 14, one shared wiring 251, and two wirings 253. In other words, in terms of per row, three pieces are needed in the comparative example, while only 2.5 pieces are needed in this embodiment.

[0113] Therefore, in this embodiment, the number of wires provided along the Y direction in the display area 100 where the pixel circuits 110 are arranged can be reduced, making it easier to achieve a narrow pitch, miniaturization, and high resolution in the pixel circuits 110.

[0114] In this embodiment, a so-called stripe arrangement in which OLED130 light-emitting elements of the same color are arranged in the Y direction was described as an example. However, the embodiment is not limited to this, as long as the pixel circuits, excluding the light-emitting elements, are arranged symmetrically on both sides with respect to a line Cen. For example, this can also be applied to a so-called stripe arrangement where the light-emitting elements are arranged in a 2x2 grid, with two green elements on one diagonal and red and blue elements on the remaining diagonal.

[0115] In this embodiment, OLED130 was used as an example of a light-emitting element, but other light-emitting elements may be used. For example, LEDs, mini-LEDs, micro-LEDs, etc., may be used as light-emitting elements.

[0116] Furthermore, the channel types of transistors 121, 122, 123, and 124 are not limited to the embodiment. Also, these transistors, except for transistor 121, may be replaced with transmission gates as appropriate. Furthermore, the transmission gates 45, 72, and 73 may be replaced with single-channel transistors.

[0117] Next, we will describe electronic devices to which the electro-optical device 10 according to the embodiment is applied. The electro-optical device 10 is suitable for applications requiring small-sized pixels and high-definition display. Therefore, we will explain using a head-mounted display as an example of an electronic device.

[0118] Figure 25 shows the external appearance of the head-mounted display, and Figure 26 shows its optical configuration. First, as shown in Figure 25, the head-mounted display 300 has, externally, the same features as ordinary eyeglasses, including temples 310, a bridge 320, and lenses 301L and 301R. Furthermore, as shown in Figure 26, the head-mounted display 300 is equipped with an electro-optical device 10L for the left eye and an electro-optical device 10R for the right eye near the bridge 320, behind (below in the figure) the lenses 301L and 301R. The image display surface of the electro-optical device 10L is positioned to the left in Figure 26. As a result, the image displayed by the electro-optical device 10L is emitted in the 9 o'clock direction in the figure via the optical lens 302L. The half mirror 303L reflects the image displayed by the electro-optical device 10L in the 6 o'clock direction while transmitting light incident from the 12 o'clock direction. The image display surface of the electro-optical device 10R is positioned to the right, opposite to the electro-optical device 10L. As a result, the image displayed by the electro-optical device 10R is emitted in the 3 o'clock direction in the figure via the optical lens 302R. The half mirror 303R reflects the image displayed by the electro-optical device 10R in the 6 o'clock direction while transmitting light incident from the 12 o'clock direction.

[0119] In this configuration, the wearer of the head-mounted display 300 can observe the images displayed by the electro-optical devices 10L and 10R in a see-through state, superimposed on the outside environment. Furthermore, in this head-mounted display 300, if the left-eye image is displayed by the electro-optical device 10L and the right-eye image is displayed by the electro-optical device 10R, the wearer can perceive the displayed images as if they had depth and three-dimensionality.

[0120] Furthermore, the electronic device including the electro-optical device 10 can be applied not only to the head-mounted display 300, but also to electronic viewfinders in video cameras and interchangeable-lens digital cameras, personal digital assistants, watch displays, and light bulbs in projection projectors.

[0121] From the above description, preferred embodiments of this disclosure can be understood, for example, as follows:

[0122] An electro-optical apparatus according to aspect 1 of the present disclosure includes: a first light-emitting element having a first anode; a first data line supplying a first data signal to the first light-emitting element; a second light-emitting element having a second anode; a second data line supplying a second data signal to the second light-emitting element; a first transistor circuit controlling the emission of light of the first light-emitting element; a second transistor circuit controlling the emission of light of the second light-emitting element; and a first shielding wire, wherein the first transistor circuit has a first anode line electrically connected to the first anode; the second transistor circuit has a second anode line electrically connected to the second anode; the first shielding wire is positioned between the first data line and the second data line in a plan view and extends along a first direction; the first data line and the second data line are symmetrical with respect to the first shielding wire in a plan view; the first anode line and the second anode line are symmetrical with respect to the first shielding wire in a plan view; and the first shielding wire is supplied with power to the first transistor circuit and the second transistor circuit.

[0123] According to the electro-optical apparatus of Embodiment 1, a first shield wire is placed between the first data line and the second data line, thereby suppressing interference between the first data line and the second data line. Furthermore, since the first shielded wire supplies power to both the first and second transistor circuits in common, the amount of wiring is reduced compared to a configuration where power is supplied individually. This makes it easier to narrow the pitch of data lines, etc.

[0124] In addition, the OLED 130 in the pixel circuit 110 located to the left of line Cen is an example of a "first light-emitting element," and the pixel electrode 131, which is the anode of the OLED 130, is an example of a "first anode." The same pixel circuit 110 with the OLED 130 removed is an example of a "first transistor circuit." In the same pixel circuit 110, the path from the drain node of transistor 124 to the pixel electrode 131 via wirings 236, 244, and 253 is an example of a "first anode line." The data line 14 provided in correspondence with the same pixel circuit 110 is an example of a "first data line." The Y direction is an example of the "first direction," and wiring 251 is an example of the "first shielded wire." In addition, the OLED 130 in the pixel circuit 110 located to the right of line Cen is an example of a "second light-emitting element," and the pixel electrode, which is the anode of the OLED 130, is an example of a "second anode." The same pixel circuit 110 with the OLED 130 removed is an example of a "second transistor circuit." In the same pixel circuit 110, the path from the drain node of transistor 124 to the pixel electrode 131 via wirings 236, 244, and 253 is an example of a "second anode line." The data line 14 provided in correspondence with the same pixel circuit 110 is an example of a "second data line." Furthermore, voltage Vel is an example of a "power source".

[0125] In the electro-optical apparatus according to specific embodiment 2 of embodiment 1, the first light-emitting element and the second light-emitting element are adjacent to each other along the first direction. According to the electro-optical apparatus of embodiment 2, the first transistor circuit and the second transistor circuit are arranged symmetrically around a first shielding line along the first direction, but the first light-emitting element and the second light-emitting element are arranged along the first direction, so the size of the first and second light-emitting elements in the direction perpendicular to the first direction can be twice the size of the first and second transistor circuits in the same orthogonal direction.

[0126] An electro-optical apparatus according to another specific embodiment 3 of embodiment 1 further comprises a second shielding wire and a third shielding wire, wherein the first data line is arranged between the first shielding wire and the second shielding wire in a plan view, and the second data line is arranged between the first shielding wire and the third shielding wire in a plan view. According to the electro-optical apparatus of embodiment 3, in a plan view, the first data line is shielded by the first shield line and the second shield line, and the second data line is shielded by the first shield line and the third shield line. Furthermore, the wiring 252 corresponding to the pixel circuit 110 located to the left of line Cen is an example of a "second shielding wire," and the wiring 252 corresponding to the pixel circuit 110 located to the right is an example of a "third shielding wire."

[0127] In the electro-optical apparatus according to a specific embodiment 4 of embodiment 3, the power supply is supplied to the second shield wiring and the third shield wiring.

[0128] An electro-optical apparatus according to another specific embodiment 5 of embodiment 1 further comprises a scan line, the first transistor circuit includes a first transistor that is turned on or off in accordance with the voltage of the scan line, and a second transistor that supplies a current to the first light-emitting element corresponding to the first data signal when the first transistor is turned on, the second transistor circuit includes a third transistor that is turned on or off in accordance with the voltage of the scan line, and a fourth transistor that supplies a current to the second light-emitting element corresponding to the second data signal when the third transistor is turned on. According to the electro-optical apparatus of embodiment 5, the scanning line can be shared by the first transistor circuit and the second transistor circuit. In addition, in the pixel circuit 110 located to the left of line Cen, transistor 122 is an example of a "first transistor," and transistor 121 is an example of a "second transistor." Furthermore, in the pixel circuit 110 located to the right of line Cen, transistor 122 is an example of a "third transistor," and transistor 121 is an example of a "fourth transistor."

[0129] The electronic device relating to Embodiment 6 includes an electro-optical device relating to any of Embodiments 1 to 5. [Explanation of symbols]

[0130] 10... Electro-optical device, 12... Scan line, 14... Data line, 100... Display area, 110... Pixel circuit, 117, 118... Control line, 121~124... Transistor, 130... OLED, 131... Pixel electrode, 230... First wiring layer, 240... Second wiring layer, 250... Third wiring layer, 251, 252... Shield wiring.

Claims

1. A first light-emitting element having a first anode, A first data line that supplies a first data signal to the first light-emitting element, A second light-emitting element having a second anode, A second data line that supplies a second data signal to the second light-emitting element, A first transistor circuit for controlling the light emission of the first light-emitting element, A second transistor circuit for controlling the light emission of the second light-emitting element, First shielded wiring and Includes, The first transistor circuit is, A first anode wire electrically connected to the first anode, It has, The aforementioned second transistor circuit is, A second anode wire electrically connected to the second anode, It has, The first shielded wiring is, In a plan view, it is positioned between the first data line and the second data line, and extends along the first direction. In a plan view, the first data line and the second data line are symmetrical with respect to the first shield wiring. In a plan view, the first anode line and the second anode line are symmetrical with respect to the first shield wiring. The first shield wire is supplied with power to the first transistor circuit and the second transistor circuit. Electro-optical device.

2. The first light-emitting element and the second light-emitting element are adjacent to each other along the first direction. The electro-optical apparatus according to claim 1.

3. Second shielded wiring and Third shielded wiring, It further possesses, The first data line is, In a plan view, it is positioned between the first shield wire and the second shield wire, The second data line is, In a plan view, positioned between the first shield wire and the third shield wire, The electro-optical apparatus according to claim 1.

4. The second shielded wiring and the third shielded wiring include: The aforementioned power supply is supplied. The electro-optical apparatus according to claim 3.

5. It further has scan lines, The first transistor circuit is, A first transistor that turns on or off depending on the voltage of the scan line, A second transistor supplies a current to the first light-emitting element corresponding to the first data signal when the first transistor is in the ON state, Includes, The aforementioned second transistor circuit is, A third transistor which is turned on or off in accordance with the voltage of the scan line, A fourth transistor supplies a current to the second light-emitting element corresponding to the second data signal when the third transistor is in the ON state, The electro-optical apparatus according to claim 1, including the following:

6. An electronic device having an electro-optical device according to any one of claims 1 to 5.

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