Display panel and display device including the same

Abstract

The present invention relates to a display panel and a display device including the same. [Solution] The present invention includes a first drive unit configured to supply current to a first light-emitting element when each subpixel of a display panel is input with a pixel drive voltage, a first pixel data voltage, and a plurality of gate signals; a second drive unit configured to supply current to a second light-emitting element when the pixel drive voltage, a second pixel data voltage, and a plurality of gate signals are input; and a shared switch unit comprising a plurality of transistors electrically connected to the first drive unit and the second drive unit, configured to receive the first pixel data voltage and the second pixel data voltage.

Description

Technical Field

[0001] The present invention relates to a display panel with a variable viewing angle and a display device including the same.

Background Art

[0002] Viewing angle variable technology is applied to display devices. The viewing angle variable technology can show video content and visual information reproduced on the display device only to users within a narrow viewing angle range or to a plurality of users existing within a wide viewing angle range.

[0003] While the future car market such as electric vehicles and autonomous driving vehicles is expanding, the demand for vehicle display devices is increasing rapidly. Research is underway on a method of dividing the screen of a vehicle display device and controlling a part of the screen at a narrow viewing angle and another part at a wide viewing angle. In this technology, personal content and information that can be seen only by a specific user are displayed on pixels driven at a narrow viewing angle, and shared content that can be seen by many users together can be displayed on pixels driven at a wide viewing angle. In order to embody this, pixel technology that can freely control each pixel at a narrow viewing angle and a wide viewing angle is required.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention aims to solve the above-mentioned necessities and / or problems.

[0005] The present invention provides a display device that can separate the viewing angles of pixel data of different contents without adding channels of a data driving unit for each pixel and can enhance the privacy protection function.

[0006] The problems of the present invention are not limited to the problems mentioned above, and further problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] A display panel according to one embodiment of the present invention includes a plurality of data lines, a plurality of gate lines, a plurality of power lines, a plurality of mode selection lines, and a plurality of subpixels. Each of the subpixels includes a first light-emitting element; a second light-emitting element; a first drive unit that receives a pixel drive voltage, a first pixel data voltage, and a plurality of gate signals and supplies current to the first light-emitting element; a second drive unit that receives the pixel drive voltage, a second pixel data voltage, and a plurality of gate signals and supplies current to the second light-emitting element; and a shared switch unit that supplies the first pixel data voltage to the first drive unit and the second pixel data voltage to the second drive unit.

[0008] A display device according to one embodiment of the present invention includes the display panel; a data drive unit that supplies data voltage to data lines; and a gate drive unit that supplies gate signals to gate lines.

[0009] The present invention allows for adjustment of the pixel viewing angle according to the user's environment and the need to protect the privacy of personal content. Therefore, the present invention provides a display device that not only enables low power consumption and process optimization, but also allows for the separation of pixel data for personal content and pixel data for shared content in each pixel, thereby enhancing privacy protection.

[0010] This invention can protect privacy by reproducing videos of personal content, where privacy protection is required, with a narrow viewing angle, without interfering with the viewing of shared content videos.

[0011] This invention allows for the reproduction of shared content video at a wide viewing angle and personal content video at a narrow viewing angle within a single pixel. Therefore, when wide-viewing-angle and narrow-viewing-angle video are displayed together on a pixel, it prevents some pixels from appearing black, i.e., black.

[0012] The present invention makes it possible to reproduce shared content and personal content at different viewing angles in pixels without increasing the number of data lines and data drive channels.

[0013] The effects of the present invention are not limited to those mentioned above, and any further effects not mentioned will be clearly understood by those skilled in the art from the description of the claims. [Brief explanation of the drawing]

[0014] [Figure 1] This is a block diagram showing a display device according to one embodiment of the present invention. [Figure 2a] This figure shows an example of a gate drive unit. [Figure 2b] This figure shows an example of a gate drive unit. [Figure 2c] This figure shows an example of a gate drive unit. [Figure 3] This is a circuit diagram showing a pixel circuit according to one embodiment of the present invention. [Figure 4] This figure shows an example of lenses placed in subpixels. [Figure 5] Figure 3 is a circuit diagram showing a detailed example of the pixel circuit. [Figure 6] This waveform diagram shows the gate signals applied to the pixel circuit shown in Figure 5 during the first refresh frame period, the second refresh frame period, and the skip frame period. [Figure 7] This waveform diagram shows an example of a gate signal applied to the pixel circuit shown in Figure 5 during the first refresh frame period. [Figure 8a]It is a circuit diagram showing step by step the operation of the pixel circuit shown in FIG. 5 during the first refresh frame period. [Figure 8b] It is a circuit diagram showing step by step the operation of the pixel circuit shown in FIG. 5 during the first refresh frame period. [Figure 8c] It is a circuit diagram showing step by step the operation of the pixel circuit shown in FIG. 5 during the first refresh frame period. [Figure 8d] It is a circuit diagram showing step by step the operation of the pixel circuit shown in FIG. 5 during the first refresh frame period. [Figure 8e] It is a circuit diagram showing step by step the operation of the pixel circuit shown in FIG. 5 during the first refresh frame period. [Figure 9] It is a waveform diagram showing an example of a gate signal applied to the pixel circuit shown in FIG. 5 during the second refresh frame period. [Figure 10a] It is a circuit diagram showing step by step the operation of the pixel circuit shown in FIG. 5 during the second refresh frame period. [Figure 10b] It is a circuit diagram showing step by step the operation of the pixel circuit shown in FIG. 5 during the second refresh frame period. [Figure 10c] It is a circuit diagram showing step by step the operation of the pixel circuit shown in FIG. 5 during the second refresh frame period. [Figure 10d] It is a circuit diagram showing step by step the operation of the pixel circuit shown in FIG. 5 during the second refresh frame period. [Figure 10e] It is a circuit diagram showing step by step the operation of the pixel circuit shown in FIG. 5 during the second refresh frame period. [Figure 11] It is a circuit diagram showing a pixel circuit and a switch section according to another embodiment of the present invention. [Figure 12] It is a circuit diagram showing a pixel circuit and a switch section according to still another embodiment of the present invention. <I [Figure 13]These waveform diagrams show the gate signals applied to the pixel circuits shown in Figures 11 and 12 during the first refresh frame period, the second refresh frame period, and the skip frame period. [Figure 14a] This is a circuit diagram illustrating the step-by-step operation of the pixel circuit shown in Figure 11 during the first refresh frame period. [Figure 14b] This is a circuit diagram illustrating the step-by-step operation of the pixel circuit shown in Figure 11 during the first refresh frame period. [Figure 14c] This is a circuit diagram illustrating the step-by-step operation of the pixel circuit shown in Figure 11 during the first refresh frame period. [Figure 14d] This is a circuit diagram illustrating the step-by-step operation of the pixel circuit shown in Figure 11 during the first refresh frame period. [Figure 14e] This is a circuit diagram illustrating the step-by-step operation of the pixel circuit shown in Figure 11 during the first refresh frame period. [Figure 15a] This is a circuit diagram illustrating the step-by-step operation of the pixel circuit shown in Figure 11 during the second refresh frame period. [Figure 15b] This is a circuit diagram illustrating the step-by-step operation of the pixel circuit shown in Figure 11 during the second refresh frame period. [Figure 15c] This is a circuit diagram illustrating the step-by-step operation of the pixel circuit shown in Figure 11 during the second refresh frame period. [Figure 15d] This is a circuit diagram illustrating the step-by-step operation of the pixel circuit shown in Figure 11 during the second refresh frame period. [Figure 15e] This is a circuit diagram illustrating the step-by-step operation of the pixel circuit shown in Figure 11 during the second refresh frame period. [Figure 16a] This circuit diagram shows the step-by-step operation of the pixel circuit shown in Figure 11 during the skip frame period. [Figure 16b] This circuit diagram shows the step-by-step operation of the pixel circuit shown in Figure 11 during the skip frame period. [Modes for carrying out the invention]

[0015] The advantages and features of the present invention, as well as methods for achieving them, will become clearer with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and can be embodied in a variety of different forms, and these embodiments are provided merely to complete the disclosure of the present invention and to fully inform those who are ordinary skill in the art to which the invention pertains.

[0016] The shapes, sizes, proportions, angles, numbers, etc., disclosed in the drawings illustrating embodiments of the present invention are illustrative only, and the present invention is not limited to what is shown in the drawings. Throughout the specification, the same reference numerals refer to substantially the same components. Furthermore, in describing the present invention, if a specific description of related prior art is deemed to unnecessarily obscure the gist of the invention, such detailed description will be omitted.

[0017] Wherever "equipped with," "includes," "possesses," etc., are used as referred to herein, other parts can be added unless "only" or "solely" is used. When a component is expressed in the singular, it may be interpreted as plural unless otherwise explicitly stated.

[0018] When interpreting the constituent elements, they shall be interpreted as including a margin of error, even if not explicitly stated otherwise.

[0019] When describing the positional and interconnected relationships between two components, such as "on top of," "above," "below," "next to," "connect or couple," or "crossing or intersecting," one or more other components may be interposed between those components unless otherwise specified, such as "immediately" or "directly."

[0020] When describing a temporal sequence, such as "after," "following," "next," or "before," the absence of "immediately" or "directly" suggests that the events may not be continuous on a timeline.

[0021] While terms such as "first," "second," etc., may be used to distinguish components, the function and structure of these components are not limited by the ordinal numbers preceding them or by the names of the components.

[0022] The following embodiments can be partially or entirely combined or linked with one another, allowing for a variety of technically interconnected and driven configurations. Each embodiment can be implemented independently of the others or in conjunction with one another.

[0023] In the display device of the present invention, the pixel circuit and the gate drive circuit may include a plurality of transistors. The transistors may be oxide TFTs (Thin Film Transistors) containing oxide semiconductors or LTPSTFTs containing low-temperature polysilicon (LTPS).

[0024] A transistor is a three-electrode device consisting of a gate, source, and drain. The source is the electrode that supplies carriers to the transistor. Within the transistor, carriers flow out from the source. The drain is the electrode through which carriers exit the transistor. In a transistor, the carrier flow is from the source to the drain. In an n-channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain. In an n-channel transistor, the direction of current is from the drain to the source. In a p-channel transistor, since the carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain may change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following explanation, the source and drain of the transistor will be referred to as the first and second electrodes.

[0025] The gate signal can swing between the gate-on voltage and the gate-off voltage. A transistor turns on in response to the gate-on voltage and turns off in response to the gate-off voltage. For an n-channel transistor, the gate-on voltage can be the gate-high voltage (VGH) and the gate-off voltage can be the gate-low voltage (VGL). For a p-channel transistor, the gate-on voltage can be the gate-low voltage (VGL) and the gate-off voltage can be the gate-high voltage (VGH).

[0026] Various embodiments of the present invention will be described in detail below with reference to the attached drawings.

[0027] Referring to Figure 1, a display device according to one embodiment of the present invention includes a display panel 100 and a display panel driving circuit for writing pixel data to the pixels of the display panel 100. The display device also includes a power supply unit 150.

[0028] The display panel 100 may be, but is not limited to, a rectangular panel having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. For example, the display panel 100 may be an irregularly shaped panel in which at least a portion is curved or elliptical.

[0029] The display area AA of the display panel 100 includes a pixel array for displaying the input video. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 that intersect with the data lines 102, and pixels arranged in a matrix. The display panel 100 may further include a plurality of power lines. The power lines are connected to constant voltage nodes of the pixel circuit and supply the constant voltage necessary to drive the pixels 101 to the pixels 101. The power lines may be represented by stripe or mesh wiring and connected in common to the pixels 101 of the display panel 100.

[0030] Each of the pixels 101 may be divided into a red subpixel, a green subpixel, and a blue subpixel for the embodiment of color. Each pixel may further contain a white subpixel. Each subpixel includes a pixel circuit that drives first and second light-emitting elements that selectively emit light according to the selected viewing angle mode. The light-emitting elements may be, but are not limited to, OLEDs (Organic Light Emitting Diodes) or micro-LEDs (Light Emitting Diodes). Hereafter, pixels may be interpreted as subpixels.

[0031] Display area AA includes multiple pixel lines L1 to Ln. Each of the pixel lines L1 to Ln contains a line of pixels arranged along the X-axis in the pixel array of the display panel 100. Pixels 101 arranged in one pixel line can share a gate line 103. Subpixels arranged along the Y-axis can share the same data line 102. One horizontal period is the time obtained by dividing one frame period by the total number of pixel lines L1 to Ln.

[0032] A touch sensor for sensing touch input may be placed on the display panel 100. The touch sensor may be an on-cell type or an add-on type placed on the display panel 100, or it may be implemented as an in-cell type touch sensor embedded in the pixel array.

[0033] The display panel 100 can be implemented as an opaque or transparent display panel. A transparent display panel can be applied to a transparent display device in which an image is displayed on the screen and the actual object behind the display panel is visible. The display panel 100 can be manufactured from a flexible display panel that can be bent flexibly.

[0034] The power supply unit 150 receives an input voltage from the host system 200 and outputs the voltage necessary to drive the pixels 101 of the display panel 100 and the display panel drive circuit. For this purpose, the power supply unit 150 may include a DC-DC converter. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. Through the DC-DC converter, the power supply unit 150 can output constant voltages (or DC voltages) such as gate high voltage, gate low voltage, pixel drive voltage, cathode voltage, initialization voltage, and IC drive voltage for the display panel drive circuit. The gate high voltage and gate low voltage can be supplied to the level shifter 140 and the gate drive unit 120. Voltages such as the pixel drive voltage, cathode voltage, and initialization voltage can be supplied to the pixels 101 through a power line commonly connected to the pixels 101.

[0035] The power supply unit 150 may further include a gamma voltage generation unit. The gamma voltage generation unit receives a high-potential reference voltage and a low-potential reference voltage as inputs and outputs multiple gamma reference voltages divided at predetermined intervals on a preset gamma curve, for example, a 2.2 gamma curve. The gamma reference voltages are supplied to the data drive unit 110. In the data drive unit 110, the gamma reference voltages are divided by a voltage divider circuit and subdivided into gradation voltages. The gamma voltage generation unit may be implemented by a programmable gamma circuit that can adjust the voltage of each gamma reference voltage according to the digital data. The timing controller 130, host system 200, or another external device can update the digital data stored in the register of the programmable gamma circuit via a communication interface.

[0036] The display panel drive circuit writes pixel data of the input video to the pixels 101 of the display panel 100 under the control of the timing controller 130. The display panel drive circuit includes a data drive unit 110 and a gate drive unit 120. The display panel drive circuit may further include a touch sensor drive unit for driving a touch sensor. The touch sensor drive unit is omitted in Figure 1. The data drive unit 110 and the touch sensor drive unit can be integrated into a single drive IC.

[0037] The data drive unit 110 receives pixel data of the input video, which is received as a digital signal from the timing controller 130, and outputs a data voltage. The input video may be video data containing various types of content, such as personal content and shared content. The data drive unit 110 can receive a gamma reference voltage and generate a gradation-specific gamma compensation voltage through a voltage divider circuit. The gradation-specific gamma compensation voltage is supplied to a digital-to-analog converter (DAC) located in each channel of the data drive unit 110. The data drive unit 110 samples and latches the pixel data, and then inputs the digital data to the DAC. The DAC converts the pixel data into a gamma compensation voltage and outputs a pixel data voltage.

[0038] The gate drive unit 120 may be formed in the display panel 100 together with the circuit elements and wiring of the display area AA. The gate drive unit 120 may be positioned on at least one non-display area NA on the left and right sides outside the display area AA in the display panel 100, or at least a portion of it may be positioned within the display area AA.

[0039] The gate drive unit 120 is positioned in the non-display areas NA on both sides of the display panel 100, flanking the display area AA, and can supply gate pulses to the gate line 103 using a double-feeding method. In another embodiment, the gate drive unit 120 is positioned on at least one side of the non-display areas NA on the left and right sides of the display panel 100, and can supply gate signals to the gate line 103 using a single-feeding method. The gate drive unit 120 sequentially outputs gate signal pulses to the gate line 103 under the control of the timing controller 130. The gate drive unit 120 can sequentially supply these signals to the gate line 103 by shifting the gate signal pulses using a shift register or edge trigger.

[0040] The timing controller 130 receives digital video data of the input video and timing signals synchronized with this data from the host system 200. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, etc. The vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted because the vertical and horizontal periods can be determined by counting the data enable signal DE. The horizontal synchronization signal Hsync and the data enable signal DE have a period of 1 horizontal period (1H).

[0041] The timing controller 130 can control the pixels 101 and the display panel drive circuit by generating data timing control signals to control the operation timing of the data drive unit 110, gate timing control signals to control the operation timing of the gate drive unit 120, and mode selection signals to control the viewing angle mode of each pixel 101, based on the timing signals Vsync, Hsync, and DE received from the host system 200. The timing controller 130 can synchronize the data drive unit 110 and the gate drive unit 120 by controlling the operation timing of the display panel drive circuit.

[0042] The gate timing control signal output from the timing controller 130 can be input to the shift register of the gate drive unit 120 via the level shifter 140. The level shifter 140 can convert the voltage level of the gate timing signal received from the timing controller 130 into a swing width between the gate low voltage and the gate high voltage and supply it to the gate drive unit 120. The clock signal output from the level shifter 140 includes the start signal and the clock, and can independently control the rising edge, gate on voltage interval, and falling edge of each gate signal.

[0043] The host system 200 can scale the video signal from the video source to match the resolution of the display panel 100 and transmit it to the timing controller 130 along with a timing signal. The host system 200 can transmit a mode signal that controls the viewing angle, along with a flag signal that indicates the presence or absence of data containing personal content requiring privacy protection, to the timing controller 130. The timing controller 130 can control the gate signal output from the gate drive unit 120 in the viewing angle mode selected by the mode signal from the host system 200, and control the data drive unit 110 in the selected viewing angle mode. The timing controller 130 can output a mode selection signal in response to the mode signal from the host system 200.

[0044] When multiple gate signals are applied to each pixel, the gate drive unit 120 may include multiple gate drive units. The gate signals may include the first scan signals SCAN1(1) to SCAN1(n), the second scan signals SCAN2(1) to SCAN2(n), the third scan signals SCAN3(1) to SCAN3(n), the fourth scan signals SCAN4(1) to SCAN4(n), the fifth scan signals SCAN5(1) to SCAN5(n), the sixth scan signals SCAN6(1) to SCAN6(n), the first light emission signals EM1(1) to EM1(n), and the second EM signals EM2(1) to EM2(n), which are input to the pixel circuit through multiple gate lines, as shown in Figures 2a to 2c. In this case, the gate drive unit 120 consists of a first gate drive unit 121 that outputs the first scan signals SCAN1(1) to SCAN1(n), a second gate drive unit 122 that outputs the second scan signals SCAN2(1) to SCAN2(n), a third gate drive unit 123 that outputs the third scan signals SCAN3(1) to SCAN3(n), a fourth gate drive unit 124 that outputs the fourth scan signals SCAN4(1) to SCAN4(n), and a fifth scan signal It may include a fifth gate drive unit 125 that outputs signals SCAN5(1) to SCAN5(n), a sixth gate drive unit 126 that outputs sixth scan signals SCAN6(1) to SCAN6(n), a seventh gate drive unit 127 that outputs first EM signals EM1(1) to EM1(n), an eighth gate drive unit 128 that outputs second EM signals EM2(1) to EM2(n), and a ninth gate drive unit 129 that outputs third EM signals EM3(1) to EM3(n). In (ni) shown in Figures 2a to 2c, i is a positive integer smaller than n.

[0045] Each of the gate drive units 121 to 129 can be input to start signals VST1 to VST9 and clock signals S1CLK to E3CLK. Each of the gate drive units 121 to 129 includes a plurality of signal transmission units ST1 to ST9 that are connected in cascade. The signal transmission units ST1 to ST9 of the gate drive units 121 to 129 receive the start signals VST1 to VST9 and the clock signals S1CLK to E3CLK as inputs, and sequentially output the pulses of the gate signals SCAN1(1) to SCAN1(n), SCAN2(1) to SCAN2(n), SCAN3(1) to SCAN3(n), SCAN4(1) to SCAN4(n), SCAN5(1) to SCAN5(n), SCAN6(1) to SCAN6(n), EM1(1) to EM1(n), EM2(1) to EM2(n), and EM3(1) to EM3(n). Depending on the viewing angle mode of the subpixel, the waveforms of the gate signals SCAN1(1)~SCAN1(n), SCAN2(1)~SCAN2(n), SCAN3(1)~SCAN3(n), SCAN4(1)~SCAN4(n), SCAN5(1)~SCAN5(n), SCAN6(1)~SCAN6(n), EM1(1)~EM1(n), EM2(1)~EM2(n), and EM3(1)~EM3(n) may change as shown in Figure 6. The timing controller 130 can vary the start signals VST1 to VST9 and the clock signals S1CLK to E3CLK according to the viewing angle mode of the subpixel, and control the waveforms of the gate signals SCAN1(1) to SCAN1(n), SCAN2(1) to SCAN2(n), SCAN3(1) to SCAN3(n), SCAN4(1) to SCAN4(n), SCAN5(1) to SCAN5(n), SCAN6(1) to SCAN6(n), EM1(1) to EM1(n), EM2(1) to EM2(n), and EM3(1) to EM3(n) in accordance with the selected viewing angle mode.

[0046] Figure 3 is a circuit diagram showing a pixel circuit according to one embodiment of the present invention. Figure 4 is a diagram showing an example of lenses arranged in subpixels.

[0047] Referring to Figures 3 and 4, each subpixel of the display panel 100 includes a first light-emitting element EL1, a second light-emitting element EL2, a first drive unit 10, a second drive unit 20, and a shared switch unit 30.

[0048] The first and second light-emitting elements EL1 and EL2 may, but are not limited to, an OLED (Organic Light Emitting Diode) or a micro-LED (Light Emitting Diode). The first light-emitting element EL1 can be driven and emit light in a first viewing angle mode. When the first light-emitting element EL1 emits light, the light from the first light-emitting element EL1 can be diffused through the first lens 42 and emitted at a wide viewing angle. The second light-emitting element EL2 can be driven and emit light in a second viewing angle mode. When the second light-emitting element EL2 emits light, the light from the second light-emitting element EL2 can be focused through the second lens 44 and emitted at a narrow viewing angle.

[0049] The first drive unit 10 receives the pixel drive voltage EVDD, the first pixel data voltage Vdata, and the gate signals SCAN1(n), SCAN4(n), and EM2(n) as inputs, and supplies current to the first light-emitting element EL1 to drive the first light-emitting element EL1. The first drive unit 10 may include a first capacitor and a plurality of transistors. The second drive unit 20 receives the pixel drive voltage EVDD, the second pixel data voltage Vdata, and the gate signals SCAN5(n), SCAN6(n), and EM3(n) as inputs, and supplies current to the second light-emitting element EL2 to drive the second light-emitting element EL2. The second drive unit 20 may include a second capacitor and a plurality of transistors.

[0050] The shared switch unit 30 includes a plurality of transistors that are electrically connected to the first drive unit 10 and the second drive unit 20. The shared switch unit 30 receives the first pixel data voltage and the second pixel data voltage as inputs, and also receives gate signals SCAN2(n), SCAN3(n), SCAN3(n+1), and EM1(n) as inputs, and selectively transmits the data voltage Vdata to the first drive unit 10 and the second drive unit 20.

[0051] Referring to Figure 3, the first lens 42 is a wide-viewing-angle lens positioned on the first light-emitting element EL1. The first lens 42 overlaps with the light-emitting area of ​​the first light-emitting element EL1. The first lens 42 may be embodied as a semi-cylindrical lens to limit the vertical viewing angle and widen the horizontal viewing angle. The first lens 42 is long in the left-right direction (or X-axis direction) and narrow in the vertical direction (Y-axis direction) of the display panel 100. The first lens 42 focuses the light from the first light-emitting element EL1 in the vertical direction and diffuses it to a wide viewing angle in the left-right direction, so that the light from the first light-emitting element EL1 travels with a wide viewing angle in the left-right direction.

[0052] The second lens 44 is a narrow-field-of-view lens positioned on the second light-emitting element EL2. The second lens 44 overlaps with the light-emitting region of the second light-emitting element EL2. The second lens 44 may be a hemispherical lens that is thicker in the center and becomes thinner towards the edges in the vertical and horizontal directions. The second lens 44 focuses the light from the second light-emitting element EL2 so that the light emitted from the second light-emitting element EL2 travels with a narrow field of view in the vertical and horizontal directions.

[0053] The first and second lenses 42 and 44 may be, but are not limited to, a transparent medium or a transparent insulating layer pattern arranged within the display panel 100. The first and second lenses 42 and 44 can limit the vertical viewing angle of the pixels, preventing the phenomenon in which light from the pixels is reflected from the vehicle's windshield and the display screen is visible.

[0054] The display panel drive circuit can be driven at a variable refresh rate (VRR) under the control of the timing controller 130 or the host system 200. For example, the timing controller 130 can analyze the input video and reduce the refresh rate when the input video does not change for a preset time, thereby reducing the power consumption of the display device. For example, under the control of the timing controller 130, the display panel drive circuit can reduce the refresh rate of pixels P when a still image is input for a certain period of time or longer, thereby controlling the data writing cycle of pixels P and reducing the power consumption of the display device. When the display device is operating in standby mode or in response to a user command, the drive circuit of the display panel 100 may have a lower refresh rate. The refresh rate may also be lower on the AOD (Always On Display) screen. The AOD screen is a part of the pixel area of ​​the display area AA where simplified information, such as battery level and time, is displayed in standby mode.

[0055] The timing controller 130 or the host system 200 can control the display panel drive circuit to control the viewing angle of a pixel by a first viewing angle during the first frame period. The timing controller 130 or the host system 200 can control the display panel drive circuit to control the viewing angle of a pixel by a second viewing angle during the second frame period. The timing controller 130 or the host system 200 can change the viewing angle of each pixel using a variable refresh rate. In this case, the first frame period may be a pixel drive period with a high refresh rate, and the second frame period may be a pixel drive period with a relatively low refresh rate, but is not limited to this. The refresh rate may be the frequency of the refresh frame in which data is written to the pixel. When writing pixel data for a typical video to a pixel, the pixel data can be written to the pixel at a refresh rate of 60Hz or 120Hz or higher. When the aforementioned slow drive event occurs, the system enters a slow drive mode, and the pixel data can be written to the pixel at a refresh rate lower than 60Hz, for example, a frequency of 1Hz to 10Hz. When the refresh rate is 1 Hz, pixel data is written to the pixel during one refresh frame period per second, and 119 frame periods may be skip frame periods or blank periods in which no pixel data is written and the data voltage charged during the previous refresh frame period is maintained. When the refresh rate is 120 Hz, pixel data can be written to the pixel during 120 refresh frame periods per second.

[0056] Figure 5 is a circuit diagram showing in detail an example of the pixel circuit shown in Figure 3. The pixel circuit shown in Figure 5 may be a subpixel pixel circuit located in the nth (where n is a natural number) pixel line. Figure 6 is a waveform diagram showing the gate signal applied to the pixel circuit shown in Figure 5 during the first refresh frame period, the second refresh frame period, and the skip frame period.

[0057] Referring to Figures 5 and 6, the pixel circuit is connected to a data line to which the pixel data voltage Vdata is applied, and to gate lines to which the gate signals SCAN1(n) to SCAN6(n), EM1(n), EM2(n), and EM3(n) are applied.

[0058] The pixel circuit may be connected to power supply nodes to which constant voltages are applied, such as a first constant voltage node to which the pixel drive voltage EVDD is applied, a second constant voltage node to which the cathode voltage EVSS is applied, a third constant voltage node to which the initialization voltage Vini is applied, a fourth constant voltage node to which the anode reset voltage VAR is applied, and a fifth constant voltage node to which the on-bias voltage VOBS is applied. The cathode voltage EVSS may be the pixel ground voltage. On the display panel 100, the power supply lines to which the constant voltage nodes are connected may be connected in common to all pixels.

[0059] The pixel drive voltage EVDD and cathode voltage EVSS can be set to voltages that allow the drive transistor DT1 to operate in the saturation region. The pixel drive voltage EVDD can be set to a voltage between 2V and 4V, and the cathode voltage EVSS can be set to a voltage between -9V and -7V, but is not limited to these values.

[0060] The anode reset voltage VAR can be, but is not limited to, a voltage between -13V and -10V. For example, the anode reset voltage VAR can be separated by subpixel color. The anode reset voltage VAR can initialize the anode electrodes of the light-emitting elements EL1 and EL2. The on-bias voltage VOBS can be, but is not limited to, a voltage between 4V and 6V. The on-bias voltage VOBS can improve the hysteresis of the drive transistor DT1 by changing the direction of the current flowing through it.

[0061] The initialization voltage Vini may be set to a voltage lower than the lower limit voltage of the data voltage Vdata and higher than the cathode voltage EVSS, but is not limited to this. For example, the data voltage Vdata may have a dynamic range (DynamICrange) between 2V and 6V. Within this dynamic range, the voltage level of the data voltage Vdata may be selected according to the grayscale value of the pixel data. In this case, the initialization voltage Vini may be set to a voltage between -6V and -3V, but is not limited to this.

[0062] The gate signals SCAN1(n) to SCAN6(n), EM1(n), EM2(n), and EM3(n) may include pulses that swing between the gate high voltage VGH and the gate low voltage VGL. The gate high voltage VGH of the gate signals SCAN1(n) to SCAN6(n), EM1(n), EM2(n), and EM3(n) may be set to a voltage higher than the pixel drive voltage EVDD, and the gate low voltage VGL may be set to a voltage lower than the cathode voltage EVSS. For example, the gate high voltage may be set to a voltage between 5V and 10V, and the gate low voltage may be set to a voltage between -18V and -10V.

[0063] The first drive unit 10 includes a first drive transistor DT1, a first switch transistor T1, a second switch transistor T2, a third switch transistor T3, and a first capacitor Cst1. The first drive transistor DT1 and the third switch transistor T3 may, but are not limited to, p-channel LTPSTFTs with good on-current characteristics. The first and second switch transistors T1 and T2 may, but are not limited to, n-channel oxideTFTs with low off-current characteristics. Off-current is the leakage current that flows through the semiconductor channel of a transistor in the off state.

[0064] The first drive transistor DT1 drives the first light-emitting element EL1 during the first refresh frame period RFR1 by generating a current in accordance with the gate-source voltage Vgs. The first drive transistor DT1 includes a gate electrode connected to the first node n1, a first electrode connected to the second node n2, and a second electrode connected to the third node n3. The first capacitor Cst1 is connected between the first constant voltage node to which the pixel drive voltage EVDD is applied and the first node n1.

[0065] The first light-emitting element EL1 can emit light when driven by a current from the first drive transistor DT1. The anode electrode of the first light-emitting element EL1 is connected to the fourth node n4, and the cathode electrode is connected to the second constant voltage node to which the cathode voltage EVSS is applied.

[0066] The first switch transistor T1 is connected between the first node n1 and the third node n3. The first switch transistor T1 can be turned on in response to the gate high voltage VGH of the first scan signal SCAN1(n) and turned off in response to the gate low voltage VGL. When the first switch transistor T1 is turned on, the first node n1 is electrically connected to the third node n3. The first switch transistor T1 includes a gate electrode connected to the first gate line to which the first scan signal SCAN1(n) is applied, a first electrode connected to the first node n1, and a second electrode connected to the third node n3.

[0067] The second switch transistor T2 is connected between the first node n1 and the third constant voltage node to which the initialization voltage Vini is applied. The second switch transistor T2 can be turned on in response to the gate high voltage VGH of the fourth scan signal SCAN4(n) and turned off in response to the gate low voltage. When the second switch transistor T2 is turned on, the initialization voltage Vini is applied to the first node n1. The second switch transistor T2 includes a gate electrode connected to the fourth gate line to which the fourth scan signal SCAN4(n) is applied, a first electrode connected to the first node n1, and a second electrode to which the initialization voltage Vini is applied.

[0068] The third switch transistor T3 is connected between the third node n3 and the fourth node n4. The third switch transistor T3 can be turned on in response to the gate low voltage VGL of the second EM signal EM2(n). When the third switch transistor T3 is turned on, the third node n3 can be electrically connected to the fourth node n4. The third switch transistor T3 includes a gate electrode connected to the eighth gate line to which the second EM signal EM2(n) is applied, a first electrode connected to the third node n3, and a second electrode connected to the fourth node n4.

[0069] The second drive unit 20 includes a second drive transistor DT2, a fourth switch transistor T4, a fifth switch transistor T5, a sixth switch transistor T6, and a second capacitor Cst2. The second drive transistor DT2 and the sixth switch transistor T6 may, but are not limited to, p-channel LTPSTFTs. The fourth and fifth switch transistors T4 and T5 may, but are not limited to, n-channel OxideTFTs.

[0070] The second drive transistor DT2 drives the second light-emitting element EL2 during the second refresh frame period RFR2 by generating a current in accordance with the gate-source voltage Vgs. The second drive transistor DT2 includes a gate electrode connected to the fifth node n5, a first electrode connected to the second node n2, and a second electrode connected to the sixth node n6. The second capacitor Cst2 is connected between the first constant voltage node to which the pixel drive voltage EVDD is applied and the fifth node n5.

[0071] The second light-emitting element EL2 can emit light when driven by the current from the second drive transistor DT2. The anode electrode of the second light-emitting element EL2 is connected to the seventh node n7, and the cathode electrode is connected to the second constant voltage node to which the cathode voltage EVSS is applied.

[0072] The fourth switch transistor T4 is connected between the fifth node n5 and the sixth node n6. The fourth switch transistor T4 can be turned on in response to the gate high voltage VGH of the fifth scan signal SCAN5(n) and turned off in response to the gate low voltage VGL. When the fourth switch transistor T4 is turned on, the fifth node n5 is electrically connected to the sixth node n6. The fourth switch transistor T4 includes a gate electrode connected to the fifth gate line to which the fifth scan signal SCAN5(n) is applied, a first electrode connected to the fifth node n5, and a second electrode connected to the sixth node n6.

[0073] The fifth switch transistor T5 is connected between the fifth node n5 and the third constant voltage node to which the initialization voltage Vini is applied. The fifth switch transistor T5 can be turned on in response to the gate high voltage VGH of the sixth scan signal SCAN6(n) and turned off in response to the gate low voltage VGL. When the fifth switch transistor T5 is turned on, the initialization voltage Vini is applied to the fifth node n5. The fifth switch transistor T5 includes a gate electrode connected to the sixth gate line to which the sixth scan signal SCAN6(n) is applied, a first electrode connected to the fifth node n5, and a second electrode to which the initialization voltage Vini is applied.

[0074] The sixth switch transistor T6 is connected between the sixth node n6 and the seventh node n7. The sixth switch transistor T6 can be turned on in response to the gate low voltage VGL of the third EM signal EM3(n) and turned off in response to the gate high voltage VGH. When the sixth switch transistor T6 is turned on, the sixth node n6 can be electrically connected to the seventh node n7. The sixth switch transistor T6 includes a gate electrode connected to the ninth gate line to which the third EM signal EM3(n) is applied, a first electrode connected to the sixth node n6, and a second electrode connected to the seventh node n7.

[0075] The shared switch section 30 includes the 7th switch transistor T7, the 8th switch transistor T8, the 9th switch transistor T9, the 10th switch transistor T10, and the 11th switch transistor T11. The 7th to 11th switch transistors T7 to T11 can be, but are not limited to, p-channel LTPSTFTs.

[0076] During the first refresh frame period (RFR1), the first pixel data voltage is applied to the data line DL. During the second refresh frame period (RFR2), the second pixel data voltage is applied to the data line DL. Therefore, pixel data with different content can be sequentially written to subpixels through a single data line DL.

[0077] The seventh switch transistor T7 is connected between the data line DL to which the data voltage Vdata is applied and the second node n2. The seventh switch transistor T7 can be turned on in response to the gate low voltage VGL of the second scan signal SCAN2(n) and turned off in response to the gate high voltage VGH. When the seventh switch transistor T7 is turned on, the data line DL to which the pixel data voltage Vdata is applied is electrically connected to the second node n2, and the data voltage Vdata is applied to the second node n2. The seventh switch transistor T7 includes a gate electrode connected to the second gate line to which the second scan signal SCAN2(n) is applied, a first electrode connected to the data line DL, and a second electrode connected to the second node n2.

[0078] The eighth switch transistor T8 is connected between the second node n2 and the fifth constant voltage node to which the on-bias voltage VOBS is applied. The eighth switch transistor T8 can be turned on in response to the gate low voltage VGL of the scan signal SCAN3(n) of 3-1 and turned off in response to the gate high voltage VGH. When the eighth switch transistor T8 is turned on, the on-bias voltage VOBS is applied to the second node n2. The eighth switch transistor T8 includes a gate electrode connected to the gate line of 3-1 to which the scan signal SCAN3(n) of 3-1 is applied, a first electrode connected to the second node n2, and a second electrode to which the on-bias voltage VOBS is applied.

[0079] The ninth switch transistor T9 is connected between a first constant voltage node to which the pixel drive voltage EVDD is applied and a second node n2. The ninth switch transistor T9 can be turned on in response to the gate low voltage VGL of the first EM signal EM1(n) and turned off in response to the gate high voltage VGH. When the ninth switch transistor T9 is turned on, the pixel drive voltage EVDD is applied to the second node n2. The ninth switch transistor T9 includes a gate electrode connected to the seventh gate line to which the first EM signal EM1(n) is applied, a first electrode connected to the first constant voltage node, and a second electrode connected to the second node n2.

[0080] The tenth switch transistor T10 is connected between the fourth node n4 and the fourth constant voltage node to which the anode reset voltage VAR is applied. The tenth switch transistor T10 can be turned on in response to the gate low voltage VGL of the scan signal SCAN3(n+1) of the third-second node and turned off in response to the gate high voltage VGH. When the tenth switch transistor T10 is turned on, the anode reset voltage VAR is applied to the fourth node n4. The tenth switch transistor T10 includes a gate electrode connected to the gate line of the third-second node to which the scan signal SCAN3(n+1) of the third-second node is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the fourth constant voltage node.

[0081] The 11th switch transistor T11 is connected between the 7th node n7 and the 4th constant voltage node to which the anode reset voltage VAR is applied. The 11th switch transistor T11 can be turned on in response to the gate low voltage VGL of the 3-2 scan signal SCAN3(n+1) and turned off in response to the gate high voltage VGH. When the 11th switch transistor T11 is turned on, the anode reset voltage VAR is applied to the 7th node n7. The 11th switch transistor T11 includes a gate electrode connected to the 3-2 gate line to which the 3-2 scan signal SCAN3(n+1) is applied, a first electrode connected to the 7th node n7, and a second electrode connected to the 4th constant voltage node.

[0082] The pulses of the scan signal SCAN3(n) (3-1) and the scan signal SCAN3(n+1) (3-2) are sequentially generated as the gate low voltage VGL. The pulse of the scan signal SCAN3(n) (3-1) is applied from the pixel of the nth pixel line to the gate electrode of the eighth switch transistor T8, and from the (n-1)th pixel line to the gate electrodes of the tenth and eleventh switch transistors T10 and T11. Subsequently, the pulse of the scan signal SCAN3(n+1) (3-2) is applied from the pixel of the nth pixel line to the gate electrodes of the tenth and eleventh switch transistors T10 and T11, and from the (n+1)th pixel line to the gate electrode of the eighth switch transistor T8. Therefore, in each pixel line, the tenth and eleventh switch transistors T10 and T11 can be turned on after the eighth switch transistor T8 has been turned on.

[0083] Referring to Figure 6, the first refresh frame period RFR1 is the frame period during which the first pixel data voltage Vdata is charged to the first capacitor Cst1. The first pixel data may be data for shared content reproduced at a wide viewing angle. The second refresh frame period RFR2 is the frame period during which the second pixel data voltage Vdata is charged to the second capacitor Cst2. The second pixel data may be data for personal content or content where privacy protection is required. The skip frame period SFR is the period during which, when the refresh rate is lower than 60Hz in low-speed drive mode, the data voltage that was charged to the first capacitor Cst1 or the second capacitor Cst2 in the previous refresh frame period is maintained without charging a new data voltage. A pulse of the second scan signal SCAN2(n), which is synchronized with the pixel data voltage Vdata, is applied to the pixel circuit during the first and second refresh frame periods RFR1 and RFR2, but not during the skip frame period SFR.

[0084] During the first refresh frame period (RFR1), the second refresh frame period (RFR2), and the skip frame period (SFR), one or more of the light-emitting elements EL1 and EL2 can emit light after the capacitors Cst1 and Cst2 have been programmed with pixel data. During the first refresh frame period (RFR1), after a subpixel has been programmed with the first pixel data, one or more of the light-emitting elements EL1 and EL2 of the subpixel can emit light during the emission period of the first refresh frame. During the second refresh frame period (RFR2), after a subpixel has been programmed with the second pixel data, one or more of the light-emitting elements EL1 and EL2 of the subpixel can emit light. During the skip frame period (SFR), one or more of the light-emitting elements EL1 and EL2 of the subpixel can emit light without updating the pixel data. During the first refresh frame period RFR1, the second refresh frame period RFR2, and the skip frame period SFR, the light-emitting elements EL1 and EL2 can be selectively driven in accordance with the data voltage charged to capacitors Cst1 and Cst2 and the second and third EM signals EM2(n) and EM3(n).

[0085] During the first refresh frame period RFR1, the second refresh frame period RFR2, and the skip frame period SFR, when the third switch transistor T3 is turned on in response to the second EM signal EM2(n), a current generated according to the gate-source voltage of the first drive transistor DT1 charged in the first capacitor Cst1 is supplied to the first light-emitting element EL1, allowing the first pixel data to be reproduced with a wide viewing angle. When the sixth switch transistor T6 is turned on in response to the third EM signal EM3(n), a current generated according to the gate-source voltage of the second drive transistor DT2 charged in the second capacitor Cst2 is supplied to the second light-emitting element EL2, allowing the second pixel data to be reproduced with a narrow viewing angle.

[0086] In low-speed drive mode, after the first pixel data is written to the pixel during the first refresh frame period (RFR1), the second pixel data may be written to the pixel during the second refresh frame period (RFR2). The third through 120th frame periods are controlled as skip frame periods, during which no pixel data is written, and subpixels can be driven by the voltage stored in capacitors Cst1 and Cst2.

[0087] Figures 7 to 8e show the stepwise operation of the pixel circuit during the first refresh frame period. Figure 7 is a waveform diagram showing an example of a gate signal applied to the pixel circuit shown in Figure 5 during the first refresh frame period. Figures 8a to 8e are circuit diagrams showing the stepwise operation of the pixel circuit shown in Figure 5 during the first refresh frame period. In Figures 8a to 8e, "X" indicates an off-state transistor, and the arrows are current paths.

[0088] Referring to Figures 7 to 8e, the first refresh frame period RFR1 may include the first period P11, the second period P12, the third period P13, the fourth period P14, and the fifth period P15. During the first refresh frame period RFR1, the voltages of the fifth and sixth scan signals SCAN5(n) and SCAN6(n) input to the second drive unit 20 may be the gate low voltage VGL, and the voltage of the third EM signal EM3(n) may be the gate high voltage VGH. In this case, during the first refresh frame period RFR1, the switch transistors T4, T5, and T6 of the second drive unit 20 remain in the off state.

[0089] During the first period P11, the voltages of the first, fourth, fifth, and sixth scan signals SCAN1(n), SCAN4(n), SCAN5(n), and SCAN6(n) are the gate low voltage VGL. The voltages of the third-first and third-second scan signals SCAN3(n) and SCAN3(n+1) are generated as sequentially shifted gate low voltage VGL pulses during the first period P11. The voltage of the second scan signal SCAN2(n) is the gate high voltage VGH during the first period P11. The voltages of the EM signals EM1(n), EM2(n), and EM3(n) are the gate high voltage VGH during the first period P11. Therefore, during the first period P11, as shown in Figure 8a, the 8th, 10th, and 11th switch transistors T8, T10, and T11 are turned on, an on-bias voltage VOBS is applied to the second node n2, and an anode reset voltage VAR is applied to the 4th and 7th nodes n4 and n7.

[0090] During the first period P11, as shown in Figure 8a, the switch transistors T1 to T6 of the first and second drive units 10 and 20, the seventh switch transistor T7, and the ninth switch transistor T9 are turned off in response to the gate off voltage VGH or VGL. During the first period P11, the drive transistors DT1 and DT2 may be turned on, but since the third and sixth switch transistors T3 and T6 are in the off state, no current can be supplied to the light-emitting elements EL1 and EL2. Also, since the voltage difference between the anode reset voltage VAR and the cathode voltage EVSS is smaller than the threshold voltage of the light-emitting elements EL1 and EL2, the light-emitting elements EL1 and EL2 do not emit light during the first period P11.

[0091] During the second period P12, the voltages of the fifth and sixth scan signals SCAN5(n) and SCAN6(n) are the gate low voltage VGL, while the voltages of the other gate signals (SCAN1(n), SCAN2(n), SCAN3(n), SCAN3(n+1), SCAN4(n), EM1(n), EM2(n), and EM3(n)) are the gate high voltage VGH. Therefore, during the second period P12, as shown in Figure 8b, the first and second switch transistors T1 and T2 are turned on, and the initialization voltage Vini is applied to the first and third nodes n1 and n3, while the other switch transistors T3 to T11 are in the off state. During the second period P12, the light-emitting elements EL1 and EL2 are in the off state and therefore do not emit light.

[0092] During the third period P13, the voltage of the second scan signal SCAN2(n) is generated as a pulse of gate low voltage VGL, synchronized with the first pixel data voltage Vdata. During the third period P13, the voltages of the first and third scan signals SCAN1(n), SCAN3(n), SCAN3(n+1) and the EM signals EM1(n), EM2(n), EM3(n) are gate high voltage VGH, and the voltage of the fourth scan signal SCAN4(n) is gate low voltage VGL. During the third period P13, the voltages of the fifth and sixth scan signals SCAN5(n), SCAN6(n) maintain gate low voltage VGL. As shown in Figure 8c, when the seventh switch transistor T7 is turned on in response to the gate-low voltage VGL of the second scan signal SCAN2(n), the first pixel data voltage Vdata is applied to the second node n2, and the data voltage Vdata is also applied to the first and third nodes n1 and n3 through the ON-state first drive transistor DT1. When the third period P13 ends, the voltage at the second node n2 is the data voltage Vdata, and the voltages at the first and third nodes n1 and n3 are the data voltage Vdata plus the threshold voltage Vth of the first drive transistor DT1. During the third period P13, the fourth and seventh nodes n4 and n7 are in a floating state, and the light-emitting elements EL1 and EL2 are in an OFF state and therefore do not emit light.

[0093] During the fourth period P14, the voltages of the first, fourth, fifth, and sixth scan signals SCAN1(n), SCAN4(n), SCAN5(n), and SCAN6(n) are the gate low voltage VGL. The voltages of the third-first and third-second scan signals SCAN3(n) and SCAN3(n+1) are generated as sequentially shifted gate low voltage VGL pulses during the fourth period P14. The voltage of the second scan signal SCAN2(n) is the gate high voltage VGH during the fourth period P14. The voltages of the EM signals EM1(n), EM2(n), and EM3(n) are the gate high voltage VGH during the fourth period P14. Therefore, during the fourth period P14, as shown in Figure 8d, the 8th, 10th, and 11th switch transistors T8, T10, and T11 are turned on, the on-bias voltage VOBS is applied to the second node n2, and the anode reset voltage VAR is applied to the 4th and 7th nodes n4 and n7. During the fourth period P14, the switch transistors T1 to T6 of the first and second drive units 10 and 20, the 7th switch transistor T7, and the 9th switch transistor T9 are turned off.

[0094] During the fifth period P15, the first, fourth, fifth, and sixth scan signals SCAN1(n), SCAN4(n), SCAN5(n), and SCAN6(n) have a gate low voltage VGL, while the voltages of the second and third scan signals SCAN2(n), SCAN3(n), and SCAN3(n+1) have a gate high voltage VGH. During the fifth period P15, the voltages of the first and second EM signals EM1(n) and EM2(n) may be a gate low voltage VGL, and the third EM signal EM3(n) may have a gate high voltage VGH. In this case, as shown in Figure 8e, during the fifth period P15, the third and ninth switch transistors T3 and T9 are turned on, forming a current path between the pixel drive voltage EVDD and the first light-emitting element EL1, allowing the first light-emitting element EL1 to emit light. At this time, the current generated according to the gate-source voltage Vgs of the first drive transistor DT1 charged in the first capacitor Cst1 allows the first light-emitting element EL1 to emit light at a brightness corresponding to the grayscale value of the first pixel data. During the fifth period P15, the other switch transistors T1, T2, T4~T8, T10, and T11 may be in the off state, except for the third and ninth switch transistors T3 and T9.

[0095] During the fifth period P15, the voltages of the first, second, and third EM signals EM1(n), EM2(n), and EM3(n) may be the gate low voltage VGL. In this case, during the fifth period P15, the third, sixth, and ninth switch transistors T3, T6, and T9 are turned on, and the first light-emitting element EL1 can emit light due to the current generated according to the gate-source voltage Vgs of the first drive transistor DT1 charged in the first capacitor Cst1, and the second light-emitting element EL2 can emit light due to the current generated according to the gate-source voltage Vgs of the second drive transistor DT2 charged in the second capacitor Cst2. As a result, in a single pixel circuit, the first pixel data can be reproduced with a wide viewing angle, and the second pixel data can be reproduced with a narrow viewing angle.

[0096] Figures 9 to 10e illustrate the stepwise operation of the pixel circuit during the second refresh frame period. Figure 9 is a waveform diagram showing an example of a gate signal applied to the pixel circuit shown in Figure 5 during the second refresh frame period. Figures 10a to 10e are circuit diagrams illustrating the stepwise operation of the pixel circuit shown in Figure 5 during the second refresh frame period. In Figures 10a to 10e, "X" indicates an off-state transistor, and the arrows represent the current path.

[0097] Referring to Figures 9 to 10e, the second refresh frame period RFR2 may include the first period P21, the second period P22, the third period P23, the fourth period P24, and the fifth period P25. During the second refresh frame period RFR2, the voltages of the first and fourth scan signals SCAN1(n) and SCAN4(n) input to the first drive unit 10 may be the gate low voltage VGL, and the voltage of the second EM signal EM2(n) may be the gate high voltage VGH. In this case, during the second refresh frame period RFR2, the switch transistors T1, T2, and T3 of the first drive unit 10 remain in the off state.

[0098] During the first period P21, the voltages of the first, fourth, fifth, and sixth scan signals SCAN1(n), SCAN4(n), SCAN5(n), and SCAN6(n) are the gate low voltage VGL. The voltages of the third-first and third-second scan signals SCAN3(n) and SCAN3(n+1) are generated as sequentially shifted gate low voltage VGL pulses during the first period P21. The voltage of the second scan signal SCAN2(n) is the gate high voltage VGH during the first period P21. The voltages of the EM signals EM1(n), EM2(n), and EM3(n) are the gate high voltage VGH during the first period P21. Therefore, during the first period P21, as shown in Figure 10a, the 8th, 10th, and 11th switch transistors T8, T10, and T11 are turned on, the on-bias voltage VOBS is applied to the second node n2, and the anode reset voltage VAR is applied to the 4th and 7th nodes n4 and n7.

[0099] During the first period P21, as shown in Figure 10a, the switch transistors T1 to T6 of the first and second drive units 10 and 20, the seventh switch transistor T7, and the ninth switch transistor T9 are turned off in response to the gate off voltage VGH or VGL. During the first period P21, the drive transistors DT1 and DT2 may be turned on, but since the third and sixth switch transistors T3 and T6 are in the off state, no current can be supplied to the light-emitting elements EL1 and EL2. Also, since the voltage difference between the anode reset voltage VAR and the cathode voltage EVSS is smaller than the threshold voltage of the light-emitting elements EL1 and EL2, the light-emitting elements EL1 and EL2 do not emit light during the first period P11.

[0100] During the second period P22, the voltages of the first and fourth scan signals SCAN1(n) and SCAN4(n) are the gate low voltage VGL, while the voltages of the other gate signals SCAN2(n), SCAN3(n), SCAN3(n+1), SCAN5(n), SCAN6(n), EM1(n), EM2(n), and EM3(n) are the gate high voltage VGH. Therefore, during the second period P22, as shown in Figure 10b, the fourth and fifth switch transistors T4 and T5 are turned on, and the initialization voltage Vini is applied to the fifth and sixth nodes n5 and n6, while the other switch transistors T1, T2, T3, T6~T11 are in the off state. During the second period P22, the light-emitting elements EL1 and EL2 are in the off state and therefore do not emit light.

[0101] During the third period P23, the voltage of the second scan signal SCAN2(n) is generated as a pulse of gate low voltage VGL synchronized with the second pixel data voltage Vdata. During the third period P23, the voltages of the third and fifth scan signals SCAN3(n), SCAN3(n+1), SCAN5(n) and the EM signals EM1(n), EM2(n), EM3(n) are gate high voltage VGH, and the voltage of the sixth scan signal SCAN6(n) is gate low voltage VGL. During the third period P23, the voltages of the first and fourth scan signals SCAN1(n), SCAN4(n) maintain gate low voltage VGL. As shown in Figure 10c, when the seventh switch transistor T7 is turned on in response to the gate-low voltage VGL of the second scan signal SCAN2(n), the second pixel data voltage Vdata is applied to the second node n2, and through the ON-state second drive transistor DT2, the data voltage Vdata is also applied to the fifth and sixth nodes n5 and n6. When the third period P23 ends, the voltage at the second node n2 is the data voltage Vdata, and the voltages at the fifth and sixth nodes n5 and n6 are the data voltage Vdata plus the threshold voltage Vth of the second drive transistor DT2. During the third period P23, the fourth and seventh nodes n4 and n7 are in a floating state, and the light-emitting elements EL1 and EL2 are in an OFF state and therefore do not emit light.

[0102] During the fourth period P24, the voltages of the first, fourth, fifth, and sixth scan signals SCAN1(n), SCAN4(n), SCAN5(n), and SCAN6(n) are the gate low voltage VGL. The voltages of the third-first and third-second scan signals SCAN3(n) and SCAN3(n+1) are generated as sequentially shifted gate low voltage VGL pulses during the fourth period P24. The voltage of the second scan signal SCAN2(n) is the gate high voltage VGH during the fourth period P24. The voltages of the EM signals EM1(n), EM2(n), and EM3(n) are the gate high voltage VGH during the fourth period P24. Therefore, during the fourth period P24, as shown in Figure 10d, the 8th, 10th, and 11th switch transistors T8, T10, and T11 are turned on, the on-bias voltage VOBS is applied to the second node n2, and the anode reset voltage VAR is applied to the 4th and 7th nodes n4 and n7. During the fourth period P24, the switch transistors T1 to T6 of the first and second drive units 10 and 20, the 7th switch transistor T7, and the 9th switch transistor T9 are turned off.

[0103] During the fifth period P25, the voltages of the first, fourth, fifth, and sixth scan signals SCAN1(n), SCAN4(n), SCAN5(n), and SCAN6(n) are the gate low voltage VGL, and the voltages of the second and third scan signals SCAN2(n), SCAN3(n), and SCAN3(n+1) are the gate high voltage VGH. During the fifth period P25, the voltages of the first and third EM signals EM1(n) and EM3(n) are the gate low voltage VGL, and the second EM signal EM2(n) is the gate high voltage VGH. In this case, during the fifth period P25, as shown in Figure 10e, the sixth and ninth switch transistors T6 and T9 are turned on, forming a current path between the pixel drive voltage EVDD and the second light-emitting element EL2, allowing the second light-emitting element EL2 to emit light. At this time, the current generated according to the gate-source voltage Vgs of the second drive transistor DT2 charged in the second capacitor Cst2 allows the second light-emitting element EL2 to emit light at a brightness corresponding to the grayscale value of the second pixel data. During the fifth period P25, the other switch transistors T1~T5, T7, T8, T10, and T11 may be in the off state, except for the sixth and ninth switch transistors T6 and T9.

[0104] During the fifth period P25, the voltages of the first, second, and third EM signals EM1(n), EM2(n), and EM3(n) may be the gate low voltage VGL. In this case, during the fifth period P25, the third, sixth, and ninth switch transistors T3, T6, and T9 are turned on, and the first light-emitting element EL1 can light up due to the current generated according to the gate-source voltage Vgs of the first drive transistor DT1 charged in the first capacitor Cst1, and the second light-emitting element EL2 can light up due to the current generated according to the gate-source voltage Vgs of the second drive transistor DT2 charged in the second capacitor Cst2. As a result, in a single pixel circuit, the first pixel data can be reproduced with a wide viewing angle, and the second pixel data can be reproduced with a narrow viewing angle.

[0105] When the pixel refresh rate is low, a preset park voltage Vpark may be applied to the data line to compensate for the brightness fluctuations of the pixels, as shown in Figures 11 to 16b. The park voltage Vpark may be applied to data lines connected to non-driven drive units in the pixel circuit. The park voltage Vpark may be set to a voltage between 2V and 5V, but is not limited to this range. The higher the brightness, the greater the IRDrop of the pixel drive voltage EVDD applied to the subpixel, so the optimal park voltage Vpark for preventing flicker may be set to a lower voltage. Conversely, as the brightness decreases, the IRDrop of the pixel drive voltage EVDD decreases, so the park voltage Vpark may be set to a higher voltage. For example, when the brightness of the display panel is 450 nits during a refresh frame period, the park voltage Vpark applied to the data line during the next skip frame period may increase to 2.1V. When the brightness of the display panel is 200 nits during a refresh frame period, the park voltage Vpark applied to the data line during the next skip frame period may increase to 2.5V. When the brightness of the display panel is 20 nits during the refresh frame period, the park voltage Vpark applied to the data line during the next skip frame period may increase to 2.9V, where brightness can be the average brightness.

[0106] Figures 11 and 12 show an embodiment of a pixel circuit and a data switch section in which the viewing angle can be changed and a park voltage can be applied. In this embodiment, components that are substantially the same as those in the pixel circuit shown in Figure 5 are denoted by the same reference numerals, and redundant explanations thereof are omitted.

[0107] Referring to Figure 11, each subpixel of the display panel 100 includes a first drive unit 10 that drives a first light-emitting element EL1, a second drive unit 20 that drives a second light-emitting element EL2, a shared switch unit 30 connected to the first drive unit 10 and the second drive unit 20, and a data switch unit 40 connected to the shared switch unit 30.

[0108] The first drive unit 10 includes a first drive transistor DT1, a first switch transistor T1, a second switch transistor T2, a third switch transistor T3, and a first capacitor Cst1. In the first viewing angle mode, the first light-emitting element EL1 can emit light by being driven by a current generated according to the gate-source voltage of the first drive transistor DT1 charged in the first capacitor Cst1. When the first light-emitting element EL1 emits light, the light can propagate over a wide viewing angle.

[0109] The second drive unit 20 includes a second drive transistor DT2, a fourth switch transistor T4, a fifth switch transistor T5, a sixth switch transistor T6, and a second capacitor Cst2. The second drive transistor DT2 includes a gate electrode connected to the fifth node n5, a first electrode connected to the eighth node n8, and a second electrode connected to the sixth node n6. In the second viewing angle mode, the second light-emitting element EL2 can emit light by being driven by a current generated according to the gate-source voltage of the second drive transistor DT2 charged in the second capacitor Cst2. When the second light-emitting element EL2 emits light, the light can propagate in a narrow viewing angle.

[0110] The shared switch section 30 includes the 7th to 13th switch transistors T27 to T33. The 7th to 13th switch transistors T27 to T33 may, but are not limited to, p-channel LTPSTFTs.

[0111] The gate drive unit 120 may include a gate drive unit that outputs a second-first scan signal SCAN2(n) for controlling the seventh switch transistor T27, and a gate drive unit that outputs a second-second scan signal SCAN2'(n) for controlling the eighth switch transistor T28. The second-first scan signal SCAN2(n) may include a pulse of gate low voltage VGL generated during the first refresh frame period RFR1, as shown in Figure 13. The second-second scan signal SCAN2'(n) may include a pulse of gate low voltage VGL generated during the second refresh frame period RFR2, as shown in Figure 13.

[0112] Under the control of the timing controller 130, the data switch unit 40 can apply the pixel data voltage Vdata to the first data line DL1 and the park voltage Vpark to the second data line DL2 during the first refresh frame period RFR1. The data switch unit 40 can apply the pixel data voltage Vdata to the second data line DL2 and the park voltage Vpark to the first data line DL1 during the second refresh frame period RFR2. The data switch unit 40 can apply the park voltage Vpark to the first and second data lines DL1 and DL2 during the skip frame period SFR.

[0113] The seventh switch transistor T27 is connected between the first data line DL1 and the second node n2. The seventh switch transistor T27 can be turned on in response to the gate low voltage VGL of the second-first scan signal SCAN2(n) and turned off in response to the gate high voltage VGH. When the seventh switch transistor T27 is turned on, the first data line DL1 is electrically connected to the second node n2. The seventh switch transistor T27 includes a gate electrode connected to the second-first gate line to which the second-first scan signal SCAN2(n) is applied, a first electrode connected to the first data line DL1, and a second electrode connected to the second node n2.

[0114] The eighth switch transistor T28 is connected between the second data line DL2 and the eighth node n8. The eighth switch transistor T28 can be turned on in response to the gate low voltage VGL of the second scan signal SCAN2'(n) and turned off in response to the gate high voltage VGH. When the eighth switch transistor T28 is turned on, the second data line DL2 is electrically connected to the eighth node n8. The eighth switch transistor T28 includes a gate electrode connected to the second gate line to which the second scan signal SCAN2'(n) is applied, a first electrode connected to the second data line DL2, and a second electrode connected to the eighth node n8.

[0115] The ninth switch transistor T29 is connected between the second node n2 and the fifth constant voltage node to which the on-bias voltage VOBS is applied. The ninth switch transistor T29 can be turned on in response to the gate low voltage VGL of the scan signal SCAN3(n) of 3-1 and turned off in response to the gate high voltage VGH. When the ninth switch transistor T29 and the eleventh switch transistor T31 are turned on, the on-bias voltage VOBS is applied to the second and eighth nodes n2 and n8. The ninth switch transistor T29 includes a gate electrode connected to the gate line of 3-1 to which the scan signal SCAN3(n) of 3-1 is applied, a first electrode connected to the second node n2, and a second electrode to which the on-bias voltage VOBS is applied.

[0116] The tenth switch transistor T30 is connected between a first constant voltage node to which the pixel drive voltage EVDD is applied and a second node n2. The tenth switch transistor T30 can be turned on in response to the gate low voltage VGL of the first EM signal EM1(n) and turned off in response to the gate high voltage VGH. When the tenth switch transistor T30 and the eleventh switch transistor T31 are turned on, the pixel drive voltage EVDD is applied to the second and eighth nodes n2 and n8. The tenth switch transistor T30 includes a gate electrode connected to the seventh gate line to which the first EM signal EM1(n) is applied, a first electrode connected to the first constant voltage node, and a second electrode connected to the second node n2.

[0117] The 11th switch transistor T31 is connected between the second node n2 and the eighth node n8 and can be turned on in response to the gate low voltage VGL of the first scan signal SCAN1(n) and turned off in response to the gate high voltage VGH. When the 11th switch transistor T31 is turned on, the second node n2 is electrically connected to the eighth node n8. The 11th switch transistor T31 includes a gate electrode connected to the first gate line to which the first scan signal SCAN1(n) is applied, a first electrode connected to the second node n2, and a second electrode connected to the eighth node n8.

[0118] The first switch transistor T1 and the eleventh switch transistor T31 are represented by different types of transistors and can operate in opposite directions in response to pulses of the first scan signal SCAN1(n). For example, as shown in Figures 14a to 14e, when the first switch transistor T1 is turned off, the eleventh switch transistor T31 can be turned on. When the first switch transistor T1 is turned on, the eleventh switch transistor T31 can be turned off.

[0119] When the 12th switch transistor T32 is turned on, an anode reset voltage VAR is applied to the 4th node n4. The 12th switch transistor T32 includes a gate electrode connected to the 3-2 gate line to which the 3-2 scan signal SCAN3(n+1) is applied, a first electrode connected to the 4th node n4, and a second electrode connected to the 4th constant voltage node to which the anode reset voltage VAR is applied.

[0120] When the 13th switch transistor T33 is turned on, an anode reset voltage VAR is applied to the 7th node n7. The 13th switch transistor T33 includes a gate electrode connected to the 3-2 gate line to which the 3-2 scan signal SCAN3(n+1) is applied, a first electrode connected to the 7th node n7, and a second electrode connected to the 4th constant voltage node.

[0121] The data switch section 40 includes first to eighth transistors M1 to M8. The first to eighth transistors M1 to M8 may, but are not limited to, be embodied by a p-channel LTPSTFT that turns on in response to a gate low voltage VGL and turns off in response to a gate high voltage VGH. The data switch section 40 may be integrated into a drive IC on which the data drive section 110 is integrated, or it may be located in the non-display area NA of the display panel 100. Each of the transistors M1 to M8 of the data switch section 40 can be turned on / off under the control of the timing controller 130. The level shifter 140 can output swinging selection signals SEL1 to SEL4 between the gate low voltage VGL and the gate high voltage VGH in response to a clock input from the timing controller 130.

[0122] The first and second transistors M1 and M2 are connected in series between the first input node IN1 and the first data line DL1. The data voltage Vdata or park voltage Vpark output from the first channel of the data drive unit 110 may be applied to the first input node IN1. In other embodiments, the park voltage Vpark may be output from the power supply unit 150. The first transistor M1 may be turned on in response to the gate low voltage VGL of the first selection signal SEL1. When the first transistor M1 is turned on, the first input node IN1 is electrically connected to the first electrode of the second transistor M2. The first transistor M1 includes a gate electrode connected to the first selection line to which the first selection signal SEL1 is applied, a first electrode connected to the first input node IN1, and a second electrode connected to the first electrode of the second transistor M2.

[0123] The second transistor M2 can be turned on in response to the gate low voltage VGL of the third selection signal SEL3. When the second transistor M2 is turned on, the second electrode of the first transistor M1 is electrically connected to the first data line DL1. The second transistor M2 includes a gate electrode connected to the third selection line to which the third selection signal SEL3 is applied, a first electrode connected to the second electrode of the first transistor M1, and a second electrode connected to the first data line DL1.

[0124] The third and fourth transistors M3 and M4 are connected in series between the second input node IN2 and the first data line DL1. A data voltage Vdata or a park voltage Vpark output from the second channel of the data drive unit 110 may be applied to the second input node IN2. The park voltage Vpark may also be output from the power supply unit 150. The third transistor M3 may be turned on in response to the gate low voltage VGL of the second selection signal SEL2. When the third transistor M3 is turned on, the second input node IN2 is electrically connected to the first electrode of the fourth transistor M4. The third transistor M3 includes a gate electrode connected to the second selection line to which the second selection signal SEL2 is applied, a first electrode connected to the second input node IN2, and a second electrode connected to the first electrode of the fourth transistor M4.

[0125] The fourth transistor M4 can be turned on in response to the gate low voltage VGL of the fourth selection signal SEL4. When the fourth transistor M4 is turned on, the second electrode of the third transistor M3 is electrically connected to the first data line DL1. The fourth transistor M4 includes a gate electrode connected to the fourth selection line to which the fourth selection signal SEL4 is applied, a first electrode connected to the second electrode of the third transistor M3, and a second electrode connected to the first data line DL1.

[0126] The fifth and sixth transistors M5 and M6 are connected in series between the first input node IN1 and the second data line DL2. The fifth transistor M5 can be turned on in response to the gate low voltage VGL of the second selection signal SEL2. When the fifth transistor M5 is turned on, the first input node IN1 is electrically connected to the first electrode of the sixth transistor M6. The fifth transistor M5 includes a gate electrode connected to the second selection line to which the second selection signal SEL2 is applied, a first electrode connected to the first input node IN1, and a second electrode connected to the first electrode of the sixth transistor M6.

[0127] The sixth transistor M6 can be turned on in response to the gate low voltage VGL of the third selection signal SEL3. When the sixth transistor M6 is turned on, the second electrode of the fifth transistor M5 is electrically connected to the second data line DL2. The sixth transistor M6 includes a gate electrode connected to the third selection line to which the third selection signal SEL3 is applied, a first electrode connected to the second electrode of the fifth transistor M5, and a second electrode connected to the second data line DL2.

[0128] The seventh and eighth transistors M7 and M8 are connected in series between the second input node IN2 and the second data line DL2. The seventh transistor M7 can be turned on in response to the gate low voltage VGL of the first selection signal SEL1. When the seventh transistor M7 is turned on, the second input node IN2 is electrically connected to the first electrode of the eighth transistor M8. The seventh transistor M7 includes a gate electrode connected to the first selection line to which the first selection signal SEL1 is applied, a first electrode connected to the second input node IN2, and a second electrode connected to the first electrode of the eighth transistor M8.

[0129] The eighth transistor M8 can be turned on in response to the gate low voltage VGL of the fourth selection signal SEL4. When the eighth transistor M8 is turned on, the second electrode of the seventh transistor M7 is electrically connected to the second data line DL2. The eighth transistor M8 includes a gate electrode connected to the fourth selection line to which the fourth selection signal SEL4 is applied, a first electrode connected to the second electrode of the seventh transistor M7, and a second electrode connected to the second data line DL2.

[0130] Referring to Figure 12, each subpixel of the display panel 100 includes a first drive unit 10 that drives a first light-emitting element EL1, a second drive unit 20 that drives a second light-emitting element EL2, a shared switch unit 30 connected to the first drive unit 10 and the second drive unit 20, and a data switch unit 40 connected to the shared switch unit 30. The first drive unit 10, the second drive unit 20, and the data switch unit 40 are substantially the same as the pixel circuit shown in Figure 11.

[0131] The first drive transistor DT1 includes a gate electrode connected to the first node n1, a first electrode connected to the second node n2, and a second electrode connected to the third node n3, and generates a current to drive the first light-emitting element EL1. The second drive transistor DT2 includes a gate electrode connected to the fifth node n5, a first electrode connected to the second node n2, and a second electrode connected to the sixth node n6, and generates a current to drive the second light-emitting element EL2.

[0132] The shared switch section 30 includes the 7th to 12th switch transistors T37 to T42. The 7th to 12th switch transistors T37 to T42 may, but are not limited to, p-channel LTPSTFTs.

[0133] The seventh switch transistor T37 is connected between the first data line DL1 and the second node n2. The seventh switch transistor T37 can be turned on in response to the gate low voltage VGL of the scan signal SCAN2(n) 2-1. When the seventh switch transistor T37 is turned on, the first data line DL1 is electrically connected to the second node n2. The eighth switch transistor T38 is connected between the second data line DL2 and the second node n2. The eighth switch transistor T38 can be turned on in response to the gate low voltage VGL of the scan signal SCAN2'(n) 2-2. When the eighth switch transistor T38 is turned on, the second data line DL2 is electrically connected to the second node n2.

[0134] The seventh switch transistor T37 includes a gate electrode connected to the second-first gate line to which the second-first scan signal SCAN2(n) is applied, a first electrode connected to the first data line DL1, and a second electrode connected to the second node n2. The eighth switch transistor T28 includes a gate electrode connected to the second-second gate line to which the second-second scan signal SCAN2'(n) is applied, a first electrode connected to the second data line DL2, and a second electrode connected to the second node n2.

[0135] The ninth switch transistor T39 is connected between the second node n2 and the fifth constant voltage node to which the on-bias voltage VOBS is applied. The ninth switch transistor T39 can be turned on in response to the gate low voltage VGL of the scan signal SCAN3(n) of 3-1. When the ninth switch transistor T39 is turned on, the on-bias voltage VOBS is applied to the second node n2. The ninth switch transistor T29 includes a gate electrode connected to the gate line of 3-1 to which the scan signal SCAN3(n) of 3-1 is applied, a first electrode connected to the second node n2, and a second electrode to which the on-bias voltage VOBS is applied.

[0136] The tenth switch transistor T40 is connected between the first constant voltage node to which the pixel drive voltage EVDD is applied and the second node n2. The tenth switch transistor T40 is turned on in response to the gate low voltage VGL of the first EM signal EM1(n) and applies the pixel drive voltage EVDD to the second node n2.

[0137] When the 11th switch transistor T41 is turned on, an anode reset voltage VAR is applied to the 4th node n4. The 11th switch transistor T41 includes a gate electrode connected to the gate line of the 3-2 to which the scan signal SCAN3(n+1) of the 3-2 is applied, a first electrode connected to the 4th node n4, and a second electrode connected to the 4th constant voltage node to which the anode reset voltage VAR is applied.

[0138] When the 12th switch transistor T42 is turned on, an anode reset voltage VAR is applied to the 7th node n7. The 12th switch transistor T42 includes a gate electrode connected to the 3-2 gate line to which the 3-2 scan signal SCAN3(n+1) is applied, a first electrode connected to the 7th node n7, and a second electrode connected to the 4th constant voltage node.

[0139] In the following, we will explain the operation of the pixel circuit shown in Figure 11 by linking Figures 13 to 16. Although there is a difference between the pixel circuits shown in Figure 11 and Figure 12 in the presence or absence of the 11th switch transistor T31, which selectively connects the second node n2 and the eighth node n8, the other operations are substantially the same, so we will omit the explanation of the operation of the pixel circuit shown in Figure 12.

[0140] Figure 13 is a waveform diagram showing the gate signals applied to the pixel circuits shown in Figures 11 and 12 during the first refresh frame period, the second refresh frame period, and the skip frame period. Figures 14a to 14d are circuit diagrams showing the stepwise operation of the pixel circuit shown in Figure 11 during the first refresh frame period. Figures 15a to 15e are circuit diagrams showing the stepwise operation of the pixel circuit shown in Figure 11 during the second refresh frame period. Figures 16a and 16b are circuit diagrams showing the stepwise operation of the pixel circuit shown in Figure 11 during the skip frame period. In Figures 14a to 16b, "X" indicates an off-state transistor, and the arrows represent the current path.

[0141] Referring to Figures 13 to 14e, the first refresh frame period RFR1 may include the first period P11, the second period P12, the third period P13, the fourth period P14, and the fifth period P15. During the first refresh frame period RFR1, the voltages of the fifth and sixth scan signals SCAN5(n) and SCAN6(n) input to the second drive unit 20 may be the gate low voltage VGL, and the voltage of the second scan signal SCAN2'(n) may be the gate high voltage VGH. In this case, during the first refresh frame period RFR1, the switch transistors T4, T5, and T6 of the second drive unit 20 and the eighth switch transistor T28 remain in the off state.

[0142] During the first period P11 of the first refresh frame period RFR1, the voltages of the first, fourth, fifth, and sixth scan signals SCAN1(n), SCAN4(n), SCAN5(n), and SCAN6(n) are the gate low voltage VGL. The voltages of the third-first and third-second scan signals SCAN3(n) and SCAN3(n+1) are generated as sequentially shifted pulses of the gate low voltage VGL during the first period P11. The voltages of the second-first scan signal SCAN2(n) and the second-second scan signal SCAN2'(n) are the gate high voltage VGH during the first period P11. The voltages of the EM signals EM1(n), EM2(n), and EM3(n) are the gate high voltage VGH during the first period P11. Therefore, during the first period P11, as shown in Figure 14a, the 9th, 11th, 12th, and 13th switch transistors T29, T31, T32, and T33 are turned on, the on-bias voltage VOBS is applied to the 2nd and 8th nodes n2 and n8, and the anode reset voltage VAR is applied to the 4th and 7th nodes n4 and n7.

[0143] During the first period P11, as shown in Figure 14a, the switch transistors T1 to T6 of the first and second drive units 10 and 20, as well as the seventh switch transistor T27, the eighth switch transistor T28, and the tenth switch transistor T30, are turned off in response to the gate off voltage VGH or VGL. During the first period P11, the light-emitting elements EL1 and EL2 do not emit light.

[0144] During the second period P12 of the first refresh frame period RFR1, the voltages of the fifth and sixth scan signals SCAN5(n) and SCAN6(n) are the gate low voltage VGL, while the voltages of the other gate signals SCAN1(n), SCAN2(n), SCAN2'(n), SCAN3(n), SCAN3(n+1), SCAN4(n), EM1(n), EM2(n), and EM3(n) are the gate high voltage VGH. Therefore, during the second period P12, as shown in Figure 14b, the first and second switch transistors T1 and T2 are turned on, and the initialization voltage Vini is applied to the first and third nodes n1 and n3, while the other switch transistors T3 to T33 are in the off state. During the second period P12, the light-emitting elements EL1 and EL2 do not emit light.

[0145] During the third period P13 of the first refresh frame period RFR1, the data switch unit 40 supplies a first pixel data voltage Vdata to the first data line DL1 and a park voltage Vpark to the second data line DL2. The selection signals SEL1 to SEL4 that control transistors M1 to M8 of the data switch unit 40 may be maintained from the time they are updated in the third period P13 until the second period P12 of the next refresh frame period RFR1. In other embodiments, during periods other than the third periods P13 and P23 of the refresh frame periods RFR1 and RFR2, and the first and second periods P31 and P32 of the skip frame period SFR, the voltages of the selection signals SEL1 to SEL4 may be maintained at a gate low voltage VGL that turns on transistors M1 to M8, or a gate high voltage VGH that turns off transistors M1 to M8.

[0146] During the third period P13, the first, third, and fourth selection signals SEL1, SEL3, and SEL4 are gate low voltages VGL, and the second selection signal SEL2 is gate high voltage VGH. As a result, as shown in Figure 14c, the first, second, seventh, and eighth transistors M1, M2, M7, and M8 are turned on, and the first pixel data voltage Vdata is applied to the first data line DL1, and the park voltage Vpark is applied to the second data line DL2.

[0147] During the third period P13, the voltage of the second-first scan signal SCAN2(n) is generated as a pulse of gate low voltage VGL synchronized with the first pixel data voltage Vdata. During the third period P13, the voltages of the first, second-second, and third scan signals SCAN1(n), SCAN2'(n), SCAN3(n), SCAN3(n+1) and the EM signals EM1(n), EM2(n), EM3(n) are gate high voltage VGH. During the third period P13, the voltages of the fourth, fifth, and sixth scan signals SCAN4(n), SCAN5(n), SCAN6(n) maintain gate low voltage VGL. As shown in Figure 14c, when the seventh switch transistor T27 is turned on in response to the gate-low voltage VGL of the second-first scan signal SCAN2(n), the first pixel data voltage Vdata is applied to the second node n2, and the data voltage Vdata is also applied to the first and third nodes n1 and n3 through the on-state first drive transistor DT1. When the third period P13 ends, the voltage at the second node n2 is the data voltage Vdata, and the voltages at the first and third nodes n1 and n3 are the data voltage Vdata plus the threshold voltage Vth of the first drive transistor DT1. During the third period P13, the light-emitting elements EL1 and EL2 do not emit light.

[0148] During the fourth period P14 of the first refresh frame period RFR1, the voltages of the first, fourth, fifth, and sixth scan signals SCAN1(n), SCAN4(n), SCAN5(n), and SCAN6(n) are the gate low voltage VGL. The voltages of the third-first and third-second scan signals SCAN3(n) and SCAN3(n+1) are generated as sequentially shifted pulses of the gate low voltage VGL during the fourth period P14. The voltages of the second-first scan signal SCAN2(n) and the second-second scan signal SCAN2'(n) are the gate high voltage VGH during the fourth period P14. The voltages of the EM signals EM1(n), EM2(n), and EM3(n) are the gate high voltage VGH during the fourth period P14. Therefore, during the fourth period P14, as shown in Figure 14d, the ninth, eleventh, twelfth, and thirteenth switch transistors T29, T31, T32, and T33 are turned on, the on-bias voltage VOBS is applied to the second and eighth nodes n2 and n8, and the anode reset voltage VAR is applied to the fourth and seventh nodes n4 and n7.

[0149] During the fourth period P14, as shown in Figure 14d, the switch transistors T1 to T6 of the first and second drive units 10 and 20, as well as the seventh switch transistor T27, the eighth switch transistor T28, and the tenth switch transistor T30, are turned off in response to the gate off voltage VGH or VGL. During the fourth period P14, the light-emitting elements EL1 and EL2 do not emit light.

[0150] During the fifth period P15 of the first refresh frame period RFR1, the first, fourth, fifth, and sixth scan signals SCAN1(n), SCAN4(n), SCAN5(n), and SCAN6(n) have a gate low voltage VGL, and the voltages of the second and third scan signals SCAN2(n), SCAN2'(n), SCAN3(n), and SCAN3(n+1) have a gate high voltage VGH. During the fifth period P15, the voltages of the first and second EM signals EM1(n) and EM2(n) have a gate low voltage VGL, and the third EM signal EM3(n) may have a gate high voltage VGH. In this case, during the fifth period P15, the third and tenth switch transistors T3 and T30 can be turned on and emit light. At this time, the current generated according to the gate-source voltage Vgs of the first drive transistor DT1 charged in the first capacitor Cst1 allows the first light-emitting element EL1 to emit light with a brightness corresponding to the grayscale value of the first pixel data. During the fifth period P15, the other switch transistors T1, T2, T4~T6, T27, T28, T29, T31~T33 may be in the off state, except for the third and tenth switch transistors T3 and T30.

[0151] During the fifth period P15, the voltages of the first, second, and third EM signals EM1(n), EM2(n), and EM3(n) may be the gate low voltage VGL. In this case, as shown in Figure 14e, during the fifth period P15, the third, sixth, and tenth switch transistors T3, T6, and T30 are turned on, and the first light-emitting element EL1 can emit light due to the current generated in accordance with the gate-source voltage Vgs of the first drive transistor DT1 charged in the first capacitor Cst1, and the second light-emitting element EL2 can emit light due to the current generated in accordance with the gate-source voltage Vgs of the second drive transistor DT2 charged in the second capacitor Cst2. As a result, in a single pixel circuit, the first pixel data can be reproduced with a wide viewing angle, and the second pixel data can be reproduced with a narrow viewing angle.

[0152] Referring to Figures 13 and 15a to 15e, the second refresh frame period RFR2 may include the first period P21, the second period P22, the third period P23, the fourth period P24, and the fifth period P25. During the second refresh frame period RFR2, the voltages of the first and fourth scan signals SCAN1(n) and SCAN4(n) input to the first drive unit 10 may be the gate low voltage VGL, and the voltage of the second scan signal SCAN2(n) may be the gate high voltage VGH. In this case, during the second refresh frame period RFR2, the switch transistors T1, T2, and T3 of the first drive unit 10 and the seventh switch transistor T27 remain in the off state.

[0153] During the first period P21 of the second refresh frame period RFR2, the voltages of the first, fourth, fifth, and sixth scan signals SCAN1(n), SCAN4(n), SCAN5(n), and SCAN6(n) are the gate low voltage VGL. The voltages of the third-first and third-second scan signals SCAN3(n) and SCAN3(n+1) are generated as sequentially shifted gate low voltage VGL pulses during the first period P21. The voltages of the second-first scan signal SCAN2(n) and the second-second scan signal SCAN2'(n) are the gate high voltage VGH during the first period P21. The voltages of the EM signals EM1(n), EM2(n), and EM3(n) are the gate high voltage VGH during the first period P21. Therefore, during the first period P21, as shown in Figure 15a, the 9th, 11th, 12th, and 13th switch transistors T29, T31, T32, and T33 are turned on, the on-bias voltage VOBS is applied to the 2nd and 8th nodes n2 and n8, and the anode reset voltage VAR is applied to the 4th and 7th nodes n4 and n7.

[0154] During the first period P21, as shown in Figure 14a, the switch transistors T1 to T6 of the first and second drive units 10 and 20, as well as the seventh switch transistor T27, the eighth switch transistor T28, and the tenth switch transistor T30, are turned off in response to the gate off voltage VGH or VGL. During the first period P21, the light-emitting elements EL1 and EL2 do not emit light.

[0155] During the second refresh frame period (RFR2), period P22, the voltages of the first and fourth scan signals SCAN1(n) and SCAN4(n) are the gate low voltage VGL, while the voltages of the other gate signals SCAN2(n), SCAN2'(n), SCAN3(n), SCAN3(n+1), SCAN5(n), SCAN6(n), EM1(n), EM2(n), and EM3(n) are the gate high voltage VGH. Therefore, during period P22, as shown in Figure 15b, the fourth and fifth switch transistors T4 and T5 are turned on, and the initialization voltage Vini is applied to the fifth and sixth nodes n5 and n6, while the other switch transistors T1, T2, T3, T6~T33 are in the off state. During period P22, the light-emitting elements EL1 and EL2 do not emit light.

[0156] During the third period P23 of the second refresh frame period RFR2, the data switch unit 40 supplies the second pixel data voltage Vdata to the second data line DL2 and the park voltage Vpark to the first data line DL1.

[0157] During the third period P23, the second, third, and fourth selection signals SEL2, SEL3, and SEL4 have a gate low voltage VGL, and the first selection signal SEL1 has a gate high voltage VGH. As a result, as shown in Figure 15c, the third, fourth, fifth, and sixth transistors M3, M4, M5, and M6 are turned on, and the second pixel data voltage Vdata is applied to the second data line DL2, and the park voltage Vpark is applied to the first data line DL1.

[0158] During the third period P23, the voltage of the second-second scan signal SCAN2'(n) is generated as a pulse of gate low voltage VGL synchronized with the second pixel data voltage Vdata. During the third period P23, the voltages of the fifth, second-first, and third scan signals SCAN5(n), SCAN2(n), SCAN3(n), SCAN3(n+1) and the EM signals EM1(n), EM2(n), EM3(n) are gate high voltage VGH. During the third period P13, the voltages of the first, fourth, and sixth scan signals SCAN1(n), SCAN4(n), SCAN6(n) maintain gate low voltage VGL. As shown in Figure 15c, when the eighth switch transistor T28 is turned on in response to the gate-low voltage VGL of the second scan signal SCAN2'(n), the second pixel data voltage Vdata is applied to the eighth node n8, and through the on-state second drive transistor DT2, the data voltage Vdata is also applied to the fifth and sixth nodes n5 and n6. When the third period P23 ends, the voltage at the eighth node n8 is the data voltage Vdata, and the voltages at the fifth and sixth nodes n5 and n6 are the data voltage Vdata plus the threshold voltage Vth of the second drive transistor DT2. During the third period P23, the light-emitting elements EL1 and EL2 do not emit light.

[0159] During the fourth period P24 of the second refresh frame period RFR2, the voltages of the first, fourth, fifth, and sixth scan signals SCAN1(n), SCAN4(n), SCAN5(n), and SCAN6(n) are the gate low voltage VGL. The voltages of the third-first and third-second scan signals SCAN3(n) and SCAN3(n+1) are generated as sequentially shifted gate low voltage VGL pulses during the fourth period P24. The voltages of the second-first scan signal SCAN2(n) and the second-second scan signal SCAN2'(n) are the gate high voltage VGH during the fourth period P14. The voltages of the EM signals EM1(n), EM2(n), and EM3(n) are the gate high voltage VGH during the fourth period P24. Therefore, during the fourth period P24, as shown in Figure 15d, the ninth, eleventh, twelfth, and thirteenth switch transistors T29, T31, T32, and T33 are turned on, the on-bias voltage VOBS is applied to the second and eighth nodes n2 and n8, and the anode reset voltage VAR is applied to the fourth and seventh nodes n4 and n7.

[0160] During the fourth period P24, as shown in Figure 15d, the switch transistors T1 to T6 of the first and second drive units 10 and 20, as well as the seventh switch transistor T27, the eighth switch transistor T28, and the tenth switch transistor T30 are turned off in response to the gate off voltage VGH or VGL. During the fourth period P24, the light-emitting elements EL1 and EL2 do not emit light.

[0161] During the fifth period P25 of the second refresh frame period RFR2, the first, fourth, fifth, and sixth scan signals SCAN1(n), SCAN4(n), SCAN5(n), and SCAN6(n) have a gate low voltage VGL, and the voltages of the second and third scan signals SCAN2(n), SCAN2'(n), SCAN3(n), and SCAN3(n+1) have a gate high voltage VGH. During the fifth period P25, the voltages of the first and third EM signals EM1(n) and EM3(n) may be a gate low voltage VGL, and the second EM signal EM2(n) may have a gate high voltage VGH. In this case, during the fifth period P25, the sixth and tenth switch transistors T6 and T30 can be turned on and emit light. At this time, the current generated according to the gate-source voltage Vgs of the second drive transistor DT2 charged in the second capacitor Cst2 allows the second light-emitting element EL2 to emit light at a brightness corresponding to the grayscale value of the second pixel data. During the fifth period P25, the other switch transistors T1-T5, T27, T28, T29, T31-T33 may be in the off state, except for the sixth and tenth switch transistors T6 and T30.

[0162] During the fifth period P25, the voltages of the first, second, and third EM signals EM1(n), EM2(n), and EM3(n) may be the gate low voltage VGL. In this case, as shown in Figure 15e, during the fifth period P25, the third, sixth, and tenth switch transistors T3, T6, and T30 are turned on, and the first light-emitting element EL1 lights up due to the current generated according to the gate-source voltage Vgs of the first drive transistor DT1 charged in the first capacitor Cst1, and the second light-emitting element EL2 lights up due to the current generated according to the gate-source voltage Vgs of the second drive transistor DT2 charged in the second capacitor Cst2. As a result, in a single pixel circuit, the first pixel data can be reproduced with a wide viewing angle, and the second pixel data can be reproduced with a narrow viewing angle.

[0163] Referring to Figures 13, 16a, and 16b, the skip frame period SFR may include a first period P31, a second period P32, and a third period P33. During the period between the first period P31 and the second period P32, all switch transistors T1-T33 may be turned off, and the main nodes n1-n7 may be floating.

[0164] During the first and second periods P31 and P32 of the skip frame period SFR, the voltages of the first, fourth, fifth, and sixth scan signals SCAN1(n), SCAN4(n), SCAN5(n), and SCAN6(n) are the gate low voltage VGL, and the voltages of the second scan signals SCAN2(n), SCAN2'(n) and EM signals EM1, EM2, and EM3 may be the gate high voltage VGH. The voltages of the third-first and third-second scan signals SCAN3(n) and SCAN3(n+1) are generated during the first period P31 as pulses of gate low voltage VGL that are sequentially shifted. Therefore, during the first and second periods P31 and P32, the switch transistors T1 to T6, the seventh switch transistor T27, the eighth switch transistor T28, and the tenth switch transistor T30 of the first and second drive units 10 and 20 are turned off. During the first and second periods P31 and P32, as shown in Figure 16a, the 9th, 11th, 12th, and 13th switch transistors T29, T31, T32, and T33 are turned on, the on-bias voltage VOBS is applied to the second and 8th nodes n2 and n8, and the anode reset voltage VAR is applied to the 4th and 7th nodes n4 and n7.

[0165] During the third period P33 of the skip frame period SFR, the first, fourth, fifth, and sixth scan signals SCAN1(n), SCAN4(n), SCAN5(n), and SCAN6(n) have a gate low voltage VGL, while the voltages of the second and third scan signals SCAN2(n), SCAN2'(n), SCAN3(n), and SCAN3(n+1) have a gate high voltage VGH. During the third period P33, the voltages of the first and second EM signals EM1(n) and EM2(n) may be a gate low voltage VGL, and the third EM signal EM3(n) may have a gate high voltage VGH. In this case, during the third period P33, the third and tenth switch transistors T3 and T30 can be turned on and emit light. At this time, the current generated according to the gate-source voltage Vgs of the first drive transistor DT1 charged in the first capacitor Cst1 causes the first light-emitting element EL1 to emit light with a brightness corresponding to the grayscale value of the first pixel data. Conversely, during the third period P33, the voltages of the first and third EM signals EM1(n) and EM3(n) may be the gate low voltage VGL, and the second EM signal EM2(n) may be the gate high voltage VGH. In this case, during the third period P33, the sixth and tenth switch transistors T6 and T30 can be turned on and emit light. At this time, the current generated according to the gate-source voltage Vgs of the second drive transistor DT2 charged in the second capacitor Cst2 causes the second light-emitting element EL2 to emit light with a brightness corresponding to the grayscale value of the second pixel data.

[0166] During the third period P33, the voltages of the first, second, and third EM signals EM1(n), EM2(n), and EM3(n) may be the gate low voltage VGL. In this case, as shown in Figure 16b, during the third period P33, the third, sixth, and tenth switch transistors T3, T6, and T30 are turned on, and the first light-emitting element EL1 can emit light due to the current generated according to the gate-source voltage Vgs of the first drive transistor DT1 charged in the first capacitor Cst1, and the second light-emitting element EL2 can emit light due to the current generated according to the gate-source voltage Vgs of the second drive transistor DT2 charged in the second capacitor Cst2. As a result, in a single pixel circuit, the first pixel data can be reproduced with a wide viewing angle, and the second pixel data can be reproduced with a narrow viewing angle.

[0167] The display devices according to embodiments of the present invention can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, sliding devices, variable devices, electronic organizers, e-books, PMPs (portable multimedia players), PDAs (personal digital assistants), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigation systems, in-vehicle display devices, theater display devices, televisions, wallpaper devices, signage devices, game consoles, notebook computers, monitors, cameras, camcorders, and home appliances, etc. Furthermore, one or more display devices according to embodiments can be applied to organic light-emitting illumination devices or inorganic light-emitting illumination devices.

[0168] Since the contents of the specification described above—the problem to be solved, the means of solving the problem, and the effects—do not specify the essential features of the claims, the scope of rights of the claims is not limited by the matters described in the specification.

[0169] While embodiments of the present invention have been described in more detail above with reference to the attached drawings, the present invention is not necessarily limited to these embodiments and can be implemented in various modified forms without departing from the technical concept of the present invention. Therefore, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. Accordingly, the embodiments described above should be understood as illustrative in all respects and not limiting. [Explanation of Symbols]

[0170] 10: First drive unit 20: Second drive unit 30: Shared switch section 40: Data switch section 42: First lens 44: Second lens 100: Display Panel 110: Data-driven unit 120: Gate drive unit 130: Timing Controller 140: Level Shifter 150: Power supply section DL: Dataline Vdata: Data voltage Vpark: Park Voltage SCAN1~SCAN6: Scan signals EM1~EM3:EM signal SEL1~SEL4: Selection signals EL1, EL2: Light-emitting elements T1~T42, DT1, DT2, M1~M8: Transistors Cst1, Cst2: Capacitors Vdata: Data voltage

Claims

1. It includes multiple data lines, multiple gate lines, multiple power lines, multiple mode selection lines, and multiple subpixels, Each of the aforementioned subpixels is, First light-emitting element, The second light-emitting element, A first drive unit is configured to receive a pixel drive voltage, a first pixel data voltage, and a plurality of gate signals as inputs and to supply current to the first light-emitting element, A second drive unit is configured to receive the aforementioned pixel drive voltage, second pixel data voltage, and a plurality of gate signals, and to supply current to the second light-emitting element. A display panel including a shared switch unit configured to supply the first pixel data voltage to the first drive unit and the second pixel data voltage to the second drive unit.

2. A wide-angle lens superimposed on the light-emitting region of the first light-emitting element, and The display panel according to claim 1, further comprising a narrow-viewing-angle lens superimposed on the light-emitting region of the second light-emitting element.

3. The first drive unit is, A first drive transistor comprising a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, configured to drive the first light-emitting element during a first refresh frame period, A first constant voltage node to which the pixel driving voltage is applied, and a first capacitor connected between the first node, A first switch transistor, connected between the first node and the third node, is turned on in response to the gate high voltage of the first scan signal and turned off in response to the gate low voltage of the first scan signal. A second switch transistor is connected between the first node and a third constant voltage node to which an initialization voltage is applied, and is turned on in response to the gate high voltage of the fourth scan signal and turned off in response to the gate low voltage of the fourth scan signal, and The system includes a third switch transistor connected between the third node and the fourth node, which is turned on in response to the gate low voltage of the second light-emitting signal and turned off in response to the gate high voltage of the second light-emitting signal. The display panel according to claim 1, wherein the first light-emitting element includes an anode electrode connected to the fourth node and a cathode electrode connected to a second constant voltage node to which a cathode voltage is applied.

4. The second drive unit is, A second drive transistor comprising a gate electrode connected to the fifth node, a first electrode connected to the second or eighth node, and a second electrode connected to the sixth node, configured to drive the second light-emitting element during the second refresh frame period, A second capacitor is connected between the first constant voltage node and the fifth node. A fourth switch transistor is connected between the fifth node and the sixth node, and is turned on in response to the gate high voltage of the fifth scan signal and turned off in response to the gate low voltage of the fifth scan signal. A fifth switch transistor is connected between the fifth node and the third constant voltage node, and is turned on in response to the gate high voltage of the sixth scan signal and turned off in response to the gate low voltage of the sixth scan signal, and The system includes a sixth switch transistor, which is connected between the sixth node and the seventh node, and is turned on in response to the gate low voltage of the third light-emitting signal and turned off in response to the gate high voltage of the third light-emitting signal. The display panel according to claim 3, wherein the second light-emitting element includes an anode electrode connected to the seventh node and a cathode electrode connected to the second constant voltage node.

5. The shared switch section is, A seventh switch transistor is connected between the corresponding data line and the second node, and is turned on in response to the gate low voltage of the second scan signal and turned off in response to the gate high voltage of the second scan signal. An eighth switch transistor is connected between the second node and a fifth constant voltage node to which an on-bias voltage is applied, and is turned on in response to the gate low voltage of the scan signal of the third-first node and turned off in response to the gate high voltage of the scan signal of the third-first node. A ninth switch transistor is connected between the first constant voltage node and the second node, and is turned on in response to the gate low voltage of the first light-emitting signal and turned off in response to the gate high voltage of the first light-emitting signal. A tenth switch transistor is connected between the fourth node and a fourth constant voltage node to which an anode reset voltage is applied, and is turned on in response to the gate low voltage of the scan signal of the third-second node and turned off in response to the gate high voltage of the scan signal of the third-second node, and The system includes an eleventh switch transistor, which is connected between the seventh node and the fourth constant voltage node, and is turned on in response to the gate low voltage of the scan signal of the third-second node and turned off in response to the gate high voltage of the scan signal of the third-second node. The pulses of the scan signal 3-1 and the scan signal 3-2 are sequentially generated as the gate low voltage. During the first refresh frame period, the first pixel data voltage is applied to the data line, and during the second refresh frame period, the second pixel data voltage is applied to the data line. The display panel according to claim 4, wherein the shared switch unit receives the first pixel data voltage and the second pixel data voltage through a single data line.

6. The shared switch section is, A seventh switch transistor is connected between the first data line and the second node, and is turned on in response to the gate low voltage of the scan signal of the second-first, and turned off in response to the gate high voltage of the scan signal of the second-first. An eighth switch transistor is connected between the second data line and the eighth node, and is turned on in response to the gate low voltage of the second scan signal and turned off in response to the gate high voltage of the second scan signal. A ninth switch transistor is connected between the second node and a fifth constant voltage node to which an on-bias voltage is applied, and is turned on in response to the gate low voltage of the scan signal of the third-first node and turned off in response to the gate high voltage of the scan signal of the third-first node. A tenth switch transistor is connected between the first constant voltage node and the second node, and is turned on in response to the gate low voltage of the first light-emitting signal and turned off in response to the gate high voltage of the first light-emitting signal. An eleventh switch transistor, connected between the second node and the eighth node, is turned on in response to the gate low voltage of the first scan signal and turned off in response to the gate high voltage of the first scan signal. A twelfth switch transistor is connected between the fourth node and a fourth constant voltage node to which an anode reset voltage is applied, and is turned on in response to the gate low voltage of the scan signal of the third-second node and turned off in response to the gate high voltage of the scan signal of the third-second node, and The system includes a 13th switch transistor, which is connected between the 7th node and the 4th constant voltage node, and is turned on in response to the gate low voltage of the scan signal of the 3-2, and turned off in response to the gate high voltage of the scan signal of the 3-2, The pulses of the scan signal 3-1 and the scan signal 3-2 are sequentially generated as the gate low voltage. When the first switch transistor is turned off, the eleventh switch transistor is turned on, and when the first switch transistor is turned on, the eleventh switch transistor is turned off. The display panel according to claim 4, wherein the shared switch unit receives the first pixel data voltage and the second pixel data voltage through a single data line.

7. The shared switch section is, A seventh switch transistor is connected between the first data line and the second node, and is turned on in response to the gate low voltage of the scan signal of the second-first, and turned off in response to the gate high voltage of the scan signal of the second-first. An eighth switch transistor is connected between the second data line and the second node, and is turned on in response to the gate low voltage of the second-2 scan signal and turned off in response to the gate high voltage of the second-2 scan signal. A ninth switch transistor is connected between the second node and a fifth constant voltage node to which an on-bias voltage is applied, and is turned on in response to the gate low voltage of the scan signal of the third-first node and turned off in response to the gate high voltage of the scan signal of the third-first node. A tenth switch transistor is connected between the first constant voltage node and the second node, and is turned on in response to the gate low voltage of the first light-emitting signal and turned off in response to the gate high voltage of the first light-emitting signal. An eleventh switch transistor is connected between the fourth node and a fourth constant voltage node to which an anode reset voltage is applied, and is turned on in response to the gate low voltage of the scan signal of the third-second node and turned off in response to the gate high voltage of the scan signal of the third-second node, and The system includes a 12th switch transistor, which is connected between the 7th node and the 4th constant voltage node, and is turned on in response to the gate low voltage of the scan signal of the 3-2, and turned off in response to the gate high voltage of the scan signal of the 3-2, The display panel according to claim 4, wherein the pulses of the scan signal 3-1 and the scan signal 3-2 are sequentially generated as the gate low voltage.

8. The display panel according to claim 6 or 7, further comprising a data switch unit configured to apply the first pixel data voltage to the first data line and the park voltage to the second data line during the first refresh frame period, and to apply the second pixel data voltage to the second data line and the park voltage to the first data line during the second refresh frame period.

9. The aforementioned data switch unit is First and second transistors are connected in series between the first input node and the first data line. Third and fourth transistors are connected in series between the second input node and the first data line. Fifth and sixth transistors are connected in series between the first input node and the second data line, and The system includes seventh and eighth transistors connected in series between the second input node and the second data line, The first and seventh transistors are turned on in accordance with the gate-on voltage of the first selection signal and turned off in accordance with the gate-off voltage of the first selection signal. The third and fifth transistors are turned on in response to the gate-on voltage of the second selection signal and turned off in response to the gate-off voltage of the second selection signal. The second and sixth transistors are turned on in response to the gate-on voltage of the third selection signal and turned off in response to the gate-off voltage of the third selection signal. The display panel according to claim 8, wherein the fourth and eighth transistors are turned on in response to the gate-on voltage of the fourth selection signal and turned off in response to the gate-off voltage of the fourth selection signal.

10. A display panel including multiple data lines, multiple gate lines, multiple power lines, and multiple subpixels. A data drive unit configured to supply data voltage to the data line, and Includes a gate drive unit configured to supply a gate signal to the gate line, Each of the aforementioned subpixels is, First light-emitting element, Second light-emitting element, A first drive unit is configured to receive a pixel drive voltage, a first pixel data voltage, and a plurality of gate signals as inputs and to supply current to the first light-emitting element, A second drive unit is configured to receive the aforementioned pixel drive voltage, second pixel data voltage, and a plurality of gate signals, and to supply current to the second light-emitting element. A display device comprising: a shared switch unit configured to supply the first pixel data voltage to the first drive unit and to supply the first pixel data voltage to the second drive unit.

11. A wide-angle lens superimposed on the light-emitting region of the first light-emitting element, and The display device according to claim 10, further comprising a narrow-viewing-angle lens superimposed on the light-emitting region of the second light-emitting element.

12. The first drive unit is, A first drive transistor comprising a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, configured to drive the first light-emitting element during a first refresh frame period, A first constant voltage node to which the pixel driving voltage is applied, and a first capacitor connected between the first node, A first switch transistor, connected between the first node and the third node, is turned on in response to the gate high voltage of the first scan signal and turned off in response to the gate low voltage of the first scan signal. A second switch transistor is connected between the first node and a third constant voltage node to which an initialization voltage is applied, and is turned on in response to the gate high voltage of the fourth scan signal and turned off in response to the gate low voltage of the fourth scan signal, and The system includes a third switch transistor connected between the third node and the fourth node, which is turned on in response to the gate low voltage of the second light-emitting signal and turned off in response to the gate high voltage of the second light-emitting signal. The display device according to claim 11, wherein the first light-emitting element includes an anode electrode connected to the fourth node and a cathode electrode connected to a second constant voltage node to which a cathode voltage is applied.

13. The second drive unit is, A second drive transistor comprising a gate electrode connected to the fifth node, a first electrode connected to the second or eighth node, and a second electrode connected to the sixth node, configured to drive the second light-emitting element during the second refresh frame period, A second capacitor is connected between the first constant voltage node and the fifth node. A fourth switch transistor is connected between the fifth node and the sixth node, and is turned on in response to the gate high voltage of the fifth scan signal and turned off in response to the gate low voltage of the fifth scan signal. A fifth switch transistor is connected between the fifth node and the third constant voltage node, and is turned on in response to the gate high voltage of the sixth scan signal and turned off in response to the gate low voltage of the sixth scan signal, and The system includes a sixth switch transistor, which is connected between the sixth node and the seventh node, and is turned on in response to the gate low voltage of the third light-emitting signal and turned off in response to the gate high voltage of the third light-emitting signal. The display device according to claim 12, wherein the second light-emitting element includes an anode electrode connected to the seventh node and a cathode electrode connected to the second constant voltage node.

14. The shared switch section is, A seventh switch transistor is connected between the data line and the second node, and is turned on in response to the gate low voltage of the second scan signal and turned off in response to the gate high voltage of the second scan signal. An eighth switch transistor is connected between the second node and a fifth constant voltage node to which an on-bias voltage is applied, and is turned on in response to the gate low voltage of the scan signal of the third-first node and turned off in response to the gate high voltage of the scan signal of the third-first node. A ninth switch transistor is connected between the first constant voltage node and the second node, and is turned on in response to the gate low voltage of the first light-emitting signal and turned off in response to the gate high voltage of the first light-emitting signal. A tenth switch transistor is connected between the fourth node and a fourth constant voltage node to which an anode reset voltage is applied, and is turned on in response to the gate low voltage of the scan signal of the third-second node and turned off in response to the gate high voltage of the scan signal of the third-second node, and The system includes an eleventh switch transistor, which is connected between the seventh node and the fourth constant voltage node, and is turned on in response to the gate low voltage of the scan signal of the third-second node, and turned off in response to the gate high voltage of the scan signal of the third-second node, The pulses of the scan signal 3-1 and the scan signal 3-2 are sequentially generated as the gate low voltage. The display device according to claim 13, wherein the first pixel data voltage is applied to the data line during the first refresh frame period, and the second pixel data voltage is applied to the data line during the second refresh frame period.

15. The display device according to claim 14, wherein one or more of the first light-emitting element and the second light-emitting element emit light during at least one of the first refresh frame period, the second refresh frame period, and the skip frame period in which there is no pixel data update.

16. The shared switch section is, A seventh switch transistor is connected between the first data line and the second node, and is turned on in response to the gate low voltage of the scan signal of the second-first, and turned off in response to the gate high voltage of the scan signal of the second-first. An eighth switch transistor is connected between the second data line and the eighth node, and is turned on in response to the gate low voltage of the second scan signal and turned off in response to the gate high voltage of the second scan signal. A ninth switch transistor is connected between the second node and a fifth constant voltage node to which an on-bias voltage is applied, and is turned on in response to the gate low voltage of the scan signal of the third-first node and turned off in response to the gate high voltage of the scan signal of the third-first node. A tenth switch transistor is connected between the first constant voltage node and the second node, and is turned on in response to the gate low voltage of the first light-emitting signal and turned off in response to the gate high voltage of the first light-emitting signal. An eleventh switch transistor, connected between the second node and the eighth node, is turned on in response to the gate low voltage of the first scan signal and turned off in response to the gate high voltage of the first scan signal. A twelfth switch transistor is connected between the fourth node and a fourth constant voltage node to which an anode reset voltage is applied, and is turned on in response to the gate low voltage of the scan signal of the third-second node and turned off in response to the gate high voltage of the scan signal of the third-second node, and The system includes a 13th switch transistor, which is connected between the 7th node and the 4th constant voltage node, and is turned on in response to the gate low voltage of the scan signal of the 3-2, and turned off in response to the gate high voltage of the scan signal of the 3-2, The pulses of the scan signal 3-1 and the scan signal 3-2 are sequentially generated as the gate low voltage. The display device according to claim 13, wherein when the first switch transistor is turned off, the eleventh switch transistor is turned on, and when the first switch transistor is turned on, the eleventh switch transistor is turned off.

17. The shared switch section is, A seventh switch transistor is connected between the first data line and the second node, and is turned on in response to the gate low voltage of the scan signal of the second-first, and turned off in response to the gate high voltage of the scan signal of the second-first. An eighth switch transistor is connected between the second data line and the second node, and is turned on in response to the gate low voltage of the second-2 scan signal and turned off in response to the gate high voltage of the second-2 scan signal. A ninth switch transistor is connected between the second node and a fifth constant voltage node to which an on-bias voltage is applied, and is turned on in response to the gate low voltage of the scan signal of the third-first node and turned off in response to the gate high voltage of the scan signal of the third-first node. A tenth switch transistor is connected between the first constant voltage node and the second node, and is turned on in response to the gate low voltage of the first light-emitting signal and turned off in response to the gate high voltage of the first light-emitting signal. An eleventh switch transistor is connected between the fourth node and a fourth constant voltage node to which an anode reset voltage is applied, and is turned on in response to the gate low voltage of the scan signal of the third-second node and turned off in response to the gate high voltage of the scan signal of the third-second node, and The system includes a 12th switch transistor, which is connected between the 7th node and the 4th constant voltage node, and is turned on in response to the gate low voltage of the scan signal of the 3-2, and turned off in response to the gate high voltage of the scan signal of the 3-2, The display device according to claim 13, wherein the pulses of the scan signal 3-1 and the scan signal 3-2 are sequentially generated as the gate low voltage.

18. The display device according to claim 16 or 17, wherein one or more of the first light-emitting element and the second light-emitting element emit light during at least one of the first refresh frame period, the second refresh frame period, and the skip frame period in which there is no pixel data update.

19. The display device according to claim 16 or 17, further comprising a data switch unit configured to apply the first pixel data voltage to the first data line and the park voltage to the second data line during the first refresh frame period, and to apply the second pixel data voltage to the second data line and the park voltage to the first data line during the second refresh frame period.

20. The aforementioned data switch unit is First and second transistors are connected in series between the first input node and the first data line. Third and fourth transistors are connected in series between the second input node and the first data line. Fifth and sixth transistors are connected in series between the first input node and the second data line, and The system includes seventh and eighth transistors connected in series between the second input node and the second data line, The first and seventh transistors are turned on in accordance with the gate-on voltage of the first selection signal and turned off in accordance with the gate-off voltage of the first selection signal. The third and fifth transistors are turned on in response to the gate-on voltage of the second selection signal and turned off in response to the gate-off voltage of the second selection signal. The second and sixth transistors are turned on in response to the gate-on voltage of the third selection signal and turned off in response to the gate-off voltage of the third selection signal. The display device according to claim 19, wherein the fourth and eighth transistors are turned on in accordance with the gate-on voltage of the fourth selection signal and turned off in accordance with the gate-off voltage of the fourth selection signal.

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