Indication device

Abstract

To provide a display device that includes a transistor using an oxide semiconductor layer in which fluctuations in transistor characteristics are suppressed. [Solution] The display device includes a gate electrode, an oxide semiconductor layer superimposed on the gate electrode, a first insulating layer located on the oxide semiconductor layer and containing an organic insulating material, a pixel electrode on the first insulating layer, a first connecting electrode electrically connected to the pixel electrode and in contact with the first insulating layer, and a second connecting electrode between the oxide semiconductor layer and the first connecting electrode that electrically connects the oxide semiconductor layer and the first connecting electrode, wherein the first connecting electrode contains a transparent conductive oxide and the second connecting electrode contains a metallic material.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a display device using an oxide semiconductor film. [Background technology]

[0002] In recent years, development of transistors using oxide semiconductor films (hereinafter sometimes referred to as "OS transistors" for convenience) has been progressing (see, for example, Patent Documents 1 and 2). Like transistors using amorphous silicon films (hereinafter sometimes referred to as "a-Si transistors" for convenience), OS transistors have a simple structure and are formed using low-temperature processes. OS transistors are known to have higher mobility and very low off-current than a-Si transistors. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2014-146819 [Patent Document 2] Japanese Patent Publication No. 2015-159315 [Overview of the project] [Problems that the invention aims to solve]

[0004] Using OS transistors with low off-current characteristics in high-resolution display devices such as head-mounted displays can reduce power consumption and enable longer operating times. However, high-resolution display devices require increasing the number of pixels while maintaining the aperture ratio, which can lead to problems unique to high-resolution displays. For example, the processing precision of the display device can limit the pattern and structure of the film, resulting in a problem where OS transistors tend to exhibit depletion-type transistor characteristics in high-resolution display devices using OS transistors.

[0005] One aspect of one embodiment of the present invention aims to provide a display device including a transistor that uses an oxide semiconductor layer in which fluctuations in transistor characteristics are suppressed, in view of the above-mentioned problems. Another aspect of one embodiment of the present invention aims to provide an array substrate for the said display device. [Means for solving the problem]

[0006] A display device according to one embodiment of the present invention includes a gate electrode, an oxide semiconductor layer superimposed on the gate electrode, a first insulating layer located on the oxide semiconductor layer and containing an organic insulating material, a pixel electrode on the first insulating layer, a first connecting electrode electrically connected to the pixel electrode and in contact with the first insulating layer, and a second connecting electrode that electrically connects the oxide semiconductor layer and the first connecting electrode between the oxide semiconductor layer and the first connecting electrode, wherein the first connecting electrode contains a transparent conductive oxide and the second connecting electrode contains a metallic material.

[0007] A display device according to one embodiment of the present invention includes a gate electrode, an oxide semiconductor layer superimposed on the gate electrode, a first insulating layer located on the oxide semiconductor layer and containing an organic insulating material, a pixel electrode on the first insulating layer, and a first connecting electrode in contact with the first insulating layer and electrically connecting the oxide semiconductor layer and the pixel electrode, wherein the oxide semiconductor layer is separated into at least two regions between the gate electrode and the first connecting electrode, the at least two regions are electrically connected by a second connecting electrode, the first connecting electrode contains a transparent conductive oxide, and the second connecting electrode contains a metallic material.

[0008] A display device according to one embodiment of the present invention includes a gate electrode, an oxide semiconductor layer superimposed on the gate electrode, a first insulating layer located on the oxide semiconductor layer and containing an organic insulating material, a pixel electrode on the first insulating layer, a first connecting electrode in contact with the oxide semiconductor layer, and a second connecting electrode covering the first connecting electrode so that it does not come into contact with the first insulating layer, and electrically connecting the first connecting electrode and the pixel electrode, wherein the first connecting electrode contains a transparent conductive oxide, and the second connecting electrode contains a metallic material. [Brief explanation of the drawing]

[0009] [Figure 1] It is a schematic plan view showing an outline of a display device according to an embodiment of the present invention. [Figure 2] It is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention. [Figure 3] It is a circuit diagram showing a pixel circuit of a pixel of a display device according to an embodiment of the present invention. [Figure 4] It is a schematic cross-sectional view showing a configuration of an array substrate of a display device according to an embodiment of the present invention. [Figure 5] It is a schematic plan view showing a configuration of an array substrate of a display device according to an embodiment of the present invention. [Figure 6] In an array substrate of a display device according to an embodiment of the present invention, it is a plan view for explaining a layout of each layer. [Figure 7] In an array substrate of a display device according to an embodiment of the present invention, it is a plan view for explaining a layout of each layer. [Figure 8] In an array substrate of a display device according to an embodiment of the present invention, it is a plan view for explaining a layout of each layer. [Figure 9] In a display device according to an embodiment of the present invention, it is a plan view for explaining a layout of each layer. [Figure 10] In an array substrate of a display device according to an embodiment of the present invention, it is a plan view for explaining a layout of each layer. [Figure 11] In an array substrate of a display device according to an embodiment of the present invention, it is a plan view for explaining a layout of each layer. [Figure 12] In an array substrate of a display device according to an embodiment of the present invention, it is a plan view for explaining a layout of each layer. [Figure 13] In an array substrate of a display device according to an embodiment of the present invention, it is a plan view for explaining a layout of each layer. [Figure 14] In an array substrate of a display device according to an embodiment of the present invention, it is a plan view for explaining a layout of each layer. [Figure 15]This is a plan view illustrating the layout of each layer in an array substrate of a display device according to one embodiment of the present invention. [Figure 16] This is a plan view illustrating the layout of each layer in an array substrate of a display device according to one embodiment of the present invention. [Figure 17] This is a plan view illustrating the layout of each layer in an array substrate of a display device according to one embodiment of the present invention. [Figure 18] This is a schematic cross-sectional view showing the configuration of the array substrate of a display device according to one embodiment of the present invention. [Figure 19] This is a schematic plan view showing the configuration of the array substrate of a display device according to one embodiment of the present invention. [Figure 20] This is a schematic cross-sectional view showing the configuration of the array substrate of a display device according to one embodiment of the present invention. [Figure 21] This is a schematic plan view showing the configuration of the array substrate of a display device according to one embodiment of the present invention. [Modes for carrying out the invention]

[0010] Embodiments of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art could easily conceive by appropriately modifying the configuration of the embodiments while maintaining the spirit of the invention are naturally included within the scope of the present invention. In order to make the explanation clearer, the drawings may schematically represent the width, thickness, and shape of the components compared to the actual embodiments. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and drawings, components similar to those described above with respect to previously shown figures are denoted by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0011] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upward." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downward." Thus, for the sake of explanation, the terms "up" and "downward" are used, but the vertical relationship between the substrate and the oxide semiconductor layer may be arranged in the opposite direction to that shown in the illustration. Furthermore, the expression "oxide semiconductor layer on the substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer, and other components may be placed between the substrate and the oxide semiconductor layer. Upward or downward refers to the stacking order in a structure in which multiple layers are stacked. When referring to a pixel electrode above the oxide semiconductor layer, the positional relationship between the oxide semiconductor layer and the pixel electrode may not overlap in a plan view. On the other hand, when referring to a pixel electrode vertically above the oxide semiconductor layer, it means a positional relationship in which the semiconductor device and the pixel electrode overlap in a plan view. A plan view refers to viewing from a direction perpendicular to the surface of the substrate.

[0012] In this specification, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A, B, and C, unless otherwise explicitly stated. Furthermore, these expressions do not exclude cases where α includes other components.

[0013] In this specification, "display device" refers to a structure that displays images using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or to a structure in which other optical components (e.g., polarizing members, backlights, touch panels, etc.) are attached to a display cell. The "electro-optical layer" may include liquid crystal layers, electroluminescent (EL) layers, electrochromic (EC) layers, and electrophoretic layers, as long as there is no technical inconsistency. Therefore, in each embodiment, a liquid crystal display device including a liquid crystal layer is described as an example of a display device, but the structure in the embodiment can be applied to other display devices including the electro-optical layers described above.

[0014] In this specification, the terms "membrane" and "layer" may be interchangeable as appropriate.

[0015] Furthermore, the following embodiments can be combined with each other, provided that no technical inconsistencies arise.

[0016] <First Embodiment> Referring to Figures 1 to 17, the configuration of the display device 10 according to one embodiment of the present invention will be described.

[0017] [1. Overview of the display device 10] Figure 1 is a schematic plan view showing an overview of a display device 10 according to one embodiment of the present invention. As shown in Figure 1, the display device 10 includes an array substrate 300, a sealing material 400, a counter substrate 500, a flexible printed circuit board (FPC) 600, and an IC chip 700. The array substrate 300 and the counter substrate 500 are arranged facing each other and are bonded together by the sealing material 400. The sealing material 400 is provided on the outer periphery of the counter substrate 500, and liquid crystal is sealed in the space surrounded by the array substrate 300, the counter substrate 500, and the sealing material 400. That is, a liquid crystal area 22 is formed inside the sealing area 24 where the sealing material 400 is provided. In the liquid crystal area 22, a plurality of pixels 310 are provided on the array substrate 300. The plurality of pixels 310 are arranged in a matrix in a first direction D1 (hereinafter sometimes referred to as the "column direction") and a second direction D2 (hereinafter sometimes referred to as the "row direction") that intersects the first direction D1. The first direction D1 and the second direction D2 may be orthogonal. In addition, in the liquid crystal region 22, a color filter is provided on the opposing substrate 500 so as to correspond to a plurality of pixels 310. The plurality of pixels 310 are defined as red pixels R, green pixels G, and blue pixels B according to the color of the color filter.

[0018] The display device 10 has a backlight unit on the back of the array substrate 300. When light emitted from the backlight unit passes through the liquid crystal area 22, the transmitted light is modulated by the liquid crystal sealed in the liquid crystal area 22 at each pixel 310, and an image is displayed in the liquid crystal area 22. In the following, the area in the liquid crystal area 22 where multiple pixels 310 of the array substrate 300 are provided may be referred to as the image display area.

[0019] The FPC 600 is located in the terminal region 26 of the array substrate 300, which is exposed from the opposing substrate 500. That is, the terminal region 26 is located outside the seal region 24. The IC chip 700 is located on the FPC 600 and supplies signals to each of the multiple pixels 310 to drive the pixel circuit. In the following, the seal region 24 and the terminal region 26 may be referred to as the frame region.

[0020] [2. Circuit configuration of the display device 10] Figure 2 is a block diagram showing the circuit configuration of a display device 10 according to one embodiment of the present invention. As shown in Figure 2, a source driver circuit 320 is provided on the array substrate 300 adjacent to the liquid crystal region 22 in a first direction D1, and a gate driver circuit 330 is provided on the array substrate 300 adjacent to the liquid crystal region 22 in a second direction D2. That is, the source driver circuit 320 and the gate driver circuit 330 are provided in the seal region 24. However, the area in which the source driver circuit 320 and the gate driver circuit 330 are provided is not limited to the seal region 24, but may be an area outside of the plurality of pixels 310 within the liquid crystal region 22.

[0021] Source wiring 321 extends from source driver circuit 320 in a first direction D1 and is electrically connected to the pixel circuits of multiple pixels 310 arranged in the first direction D1. Gate wiring 331 extends from gate driver circuit 330 in a second direction D2 and is electrically connected to the pixel circuits of multiple pixels 310 arranged in the second direction D2.

[0022] A terminal section 333 is provided in the terminal area 26. The terminal section 333 and the source driver circuit 320 are electrically connected via a connecting wire 341. Similarly, the terminal section 333 and the gate driver circuit 330 are electrically connected via a connecting wire 341. Signals from external devices are input to the source driver circuit 320 and the gate driver circuit 330 via the FPC 600 and the terminal section 333 provided in the terminal area 26. This drives each pixel circuit of the multiple pixels 310.

[0023] [3. Pixel circuit of pixel 310] Figure 3 is a circuit diagram showing the pixel circuit of a pixel 310 of a display device 10 according to one embodiment of the present invention. As shown in Figure 3, the pixel circuit includes elements such as a transistor 800, a retaining capacitor 890, and a liquid crystal element 410. As will be described in detail later, one electrode of the retaining capacitor 890 is a pixel electrode PTCO, and the other electrode is a common electrode CTCO (see Figure 4). Similarly, one electrode of the liquid crystal element 410 is a pixel electrode PTCO, and the other electrode is a common electrode CTCO (see Figure 4). The transistor 800 includes a first gate electrode 810, a first source electrode 830, and a first drain electrode 840. The first source electrode 830 and the first drain electrode 840 function as a source and drain, respectively, but these functions may be interchangeable. The first gate electrode 810 is electrically connected to the gate wiring 331. The first source electrode 830 is electrically connected to the source wiring 321. The first drain electrode 840 is electrically connected to the retaining capacitor 890 and the liquid crystal element 410.

[0024] [4. Configuration of the array substrate 300] In this embodiment, an OS transistor is used as the transistor 800 described above. That is, the pixel circuit includes an OS transistor provided on the array substrate 300. Therefore, the configuration of the array substrate 300 will be described below with reference to Figures 4 to 16.

[0025] [4-1. Components of the array substrate 300] Figure 4 is a schematic cross-sectional view showing the configuration of the array substrate 300 of a display device 10 according to one embodiment of the present invention. Note that Figure 4 is a cross-sectional view illustrating the layer structure of the array substrate 300, where peripheral circuits and pixel circuits are adjacent to each other. However, the pixel circuits and peripheral circuits are actually spaced apart, as they are located within the image display area and frame area, respectively. Furthermore, in Figure 4, the apertures (contact holes) of the pixel circuits are primarily shown to illustrate the connection relationships of each layer, while only a portion of the transparent area (aperture area) contributing to the display is shown.

[0026] As shown in Figure 4, the array substrate 300 includes multiple components such as transistor Tr1 and transistors Tr2-1 and Tr2-2 (hereinafter, when these are not specifically distinguished, they may be referred to as "transistor Tr2"), which are provided on the substrate SUB. Specifically, the array substrate 300 includes transistor Tr1, transistors Tr2-1 and 2-2, wiring W, connecting electrode ZTCO, pixel electrode PTCO, common auxiliary electrode CMTL, and common electrode CTCO. Here, TCO is an abbreviation for Transparent Conductive Oxide. Transistor Tr1 is a transistor included in the pixel circuit. Transistor Tr2 is a transistor included in peripheral circuits such as the source driver circuit 320 or the gate driver circuit 330.

[0027] [4-2. Configuration of Transistor Tr1] As shown in Figure 4, transistor Tr1 includes oxide semiconductor layers OS1 and OS2 (hereinafter, unless otherwise distinguished, these may be referred to as "oxide semiconductor layer OS"), a gate insulating layer GI1, and a gate electrode GL1-1. In other words, transistor Tr1 is an OS transistor. The gate electrode GL1-1 is superimposed on the oxide semiconductor layer OS. The gate insulating layer GI1 is provided between the oxide semiconductor layer OS and the gate electrode GL1-1. In this embodiment, a top-gate type transistor is exemplified in which the oxide semiconductor layer OS is provided on the substrate SUB side of the gate electrode GL1-1, but a configuration in which a bottom-gate type transistor is applied in which the positional relationship between the gate electrode GL1-1 and the oxide semiconductor layer OS is reversed is also possible.

[0028] The oxide semiconductor layer OS is defined as oxide semiconductor layers OS1 and OS2 based on conductivity. Oxide semiconductor layer OS1 is superimposed on gate electrode GL1-1. Oxide semiconductor layer OS1 functions as a semiconductor layer and switches between a conductive state and a non-conductive state depending on the voltage supplied to gate electrode GL1-1. That is, oxide semiconductor layer OS1 functions as the channel region of transistor Tr1. On the other hand, oxide semiconductor layers OS2, located on either side of oxide semiconductor layer OS1, function as conductive layers. That is, oxide semiconductor layer OS2 functions as the source region and drain region. Oxide semiconductor layers OS1 and OS2 are a single continuous layer. For example, by adding impurities to oxide semiconductor layer OS1, which functions as a semiconductor layer, it is possible to form oxide semiconductor layer OS2, which has low resistance and functions as a conductive layer.

[0029] A gate insulating layer GI1 is provided on the oxide semiconductor layer OS. A gate electrode GL1-1 and a connecting electrode GL1-2 are provided on the gate insulating layer GI1. The gate electrode GL1-1 and the connecting electrode GL1-2 are the same layer formed by patterning a single deposited conductive film (where the single conductive film may have a single-layer structure or a multilayer structure). Therefore, the gate electrode GL1-1 and the connecting electrode GL1-2 have the same material and structure. As will be described in detail later, metallic materials are used for the gate electrode GL1-1 and the connecting electrode GL1-2. As described above, the gate electrode GL1-1 is provided superimposed on the oxide semiconductor layer OS1. On the other hand, the connecting electrode GL1-2 is electrically connected to one side of the oxide semiconductor layer OS2 via an opening GCON provided in the gate insulating layer GI1. The connecting electrode GL1-2 is in contact with the oxide semiconductor layer OS at the bottom of the opening GCON.

[0030] An insulating layer IL2 is provided on the gate electrode GL1-1. A wiring W1 is provided on the insulating layer IL2. The wiring W1 is electrically connected to the other side of the oxide semiconductor layer OS2 via an aperture WCON provided in the insulating layer IL2 and the gate insulating layer GI1. Data signals related to the grayscale of the pixels are transmitted to the wiring W1. An insulating layer IL3 is provided on the insulating layer IL2 and the wiring W1. Note that the wiring W1 is not in contact with the insulating layer IL1. A connecting electrode ZTCO is provided on the insulating layer IL3. As will be described in detail later, a transparent conductive oxide is used as the connecting electrode ZTCO. The connecting electrode ZTCO is electrically connected to the connecting electrode GL1-2 via an aperture ZCON provided in the insulating layers IL3 and IL2.

[0031] An insulating layer IL4 is provided on the connecting electrode ZTCO. The insulating layer IL4 mitigates the step created by the structure provided below it. In other words, the insulating layer IL4 functions as a planarization film. A pixel electrode PTCO is provided on the insulating layer IL4. As will be described in detail later, a transparent conductive oxide is used as the pixel electrode PTCO. The pixel electrode PTCO is electrically connected to the connecting electrode ZTCO via an opening PCON provided in the insulating layer IL4.

[0032] An insulating layer IL5 is provided on the pixel electrode PTCO. A common auxiliary electrode CMTL and a common electrode CTCO are provided on the insulating layer IL5. As will be described in detail later, a metallic material and a transparent conductive oxide are used as the common auxiliary electrode CMTL and the common electrode, respectively. The electrical resistance of the common auxiliary electrode CMTL is lower than that of the common electrode CTCO. The common auxiliary electrode CMTL also functions as a light-shielding layer. For example, the common auxiliary electrode CMTL suppresses the occurrence of color mixing by shielding light from adjacent pixels. A spacer SP is provided on the common electrode CTCO.

[0033] Spacers SP are provided for some of the pixels. For example, spacers SP may be provided for any one of the red, green, and blue pixels. However, spacers SP may be provided for all pixels. The height of spacers SP is half the height of the cell gap. Spacers are also provided on the opposing substrate, and the spacers on the opposing substrate and the spacers SP described above overlap in a plan view. It is also possible to apply a configuration in which the height of spacers SP matches the cell gap. Furthermore, as shown in Figure 4, the spacers are filled into the opening PCON and protrude toward the opposing substrate, but it is also possible to apply a configuration in which the opening PCON is simply filled with a filler.

[0034] A light-shielding layer LS is provided between the transistor Tr1 and the substrate SUB. In this embodiment, light-shielding layers LS1 and LS2 are provided as the light-shielding layer LS. However, the light-shielding layer LS may be formed from only one of the light-shielding layers LS1 and LS2. In a plan view, the light-shielding layer LS is provided so as to overlap the gate electrode GL1-1 and the oxide semiconductor layer OS. That is, in a plan view, the light-shielding layer LS is provided so as to overlap the oxide semiconductor layer OS1. The light-shielding layer LS suppresses light incident from the substrate SUB side from reaching the oxide semiconductor layer OS1. When a conductive layer is used as the light-shielding layer LS, the oxide semiconductor layer OS1 may be controlled by applying a voltage to the light-shielding layer LS. When a voltage is applied to the light-shielding layer LS, the light-shielding layer LS and the gate electrode GL1-1 may be connected in the peripheral region of the pixel circuit. In a plan view, the aperture GCON is provided so as not to overlap with the light-shielding layer LS.

[0035] [4-3. Configuration of Transistor Tr2] Transistor Tr2 comprises a p-type transistor Tr2-1 and an n-type transistor Tr2-2. For example, transistor Tr2 is a transistor containing polycrystalline silicon (poly-Si), but is not limited to this.

[0036] Both the p-type transistor Tr2-1 and the n-type transistor Tr2-2 have a gate electrode GL2, a gate insulating layer GI2, and semiconductor layers S1, S2, and S3 (hereinafter, when these are not distinguished, they may be referred to as "semiconductor layer S"). The semiconductor layer S is located below the oxide semiconductor layer OS. If transistor Tr2 is a transistor containing polycrystalline silicon, then the semiconductor layer S contains silicon. The gate electrode GL2 faces the semiconductor layer S. The gate insulating layer GI2 is located between the semiconductor layer S and the gate electrode GL2. In this embodiment, a bottom-gate type transistor is exemplified in which the gate electrode GL2 is located on the substrate SUB side of the semiconductor layer S, but a top-gate type transistor in which the positional relationship between the semiconductor layer S and the gate electrode GL2 is reversed may also be used.

[0037] The semiconductor layer S of the p-type transistor Tr2-1 includes semiconductor layers S1 and S2. The semiconductor layer S of the n-type transistor Tr2-2 includes semiconductor layers S1, S2, and S3. Semiconductor layer S1 is a semiconductor layer in the region that overlaps with the gate electrode GL2 in a plan view. Semiconductor layer S1 functions as the channel of transistor Tr2-1. Semiconductor layer S2 functions as a conductive layer. Semiconductor layer S3 functions as a conductive layer with higher resistance than semiconductor layer S2. Semiconductor layer S3 suppresses hot carrier degradation by attenuating hot carriers that penetrate toward semiconductor layer S1.

[0038] An insulating layer IL1 and a gate insulating layer GI1 are provided on a semiconductor layer S. In transistor Tr2, the gate insulating layer GI1 simply functions as an interlayer film. Wiring W2 is provided on these insulating layers. Wiring W2 is connected to the semiconductor layer S through openings provided in insulating layer IL1 and gate insulating layer GI1. An insulating layer IL2 is provided on wiring W2. Wiring W1 is provided on insulating layer IL2. Wiring W1 is connected to wiring W2 through openings provided in insulating layer IL2.

[0039] The gate electrode GL2 and the light-shielding layer LS2 are the same layer. The wiring W2 and the gate electrode GL1-1 are the same layer. "Same layer" means that multiple components are formed by patterning a single layer.

[0040] [4-4. Planar layout of array substrate 300] Figure 5 is a schematic plan view showing the configuration of the array substrate 300 of the display device 10 according to one embodiment of the present invention. Figures 6 to 17 are plan views illustrating the layout of each layer in the array substrate 300 of the display device 10 according to one embodiment of the present invention. In Figure 5, the pixel electrode PTCO, common auxiliary electrode CMTL, common electrode CTCO, and spacer SP are omitted. The planar layouts of the pixel electrode PTCO, common auxiliary electrode CMTL, and common electrode CTCO are shown in Figures 15 to 17, respectively.

[0041] As shown in Figures 5 and 6, the light-shielding layer LS extends in a first direction D1 and is provided in common to pixels located in the first direction D1. The shape of the light-shielding layer LS differs depending on the pixel. In this embodiment, a protrusion PJT is provided that extends in a second direction D2 intersecting the first direction D1 from a part of the light-shielding layer LS extending in the first direction D1. As shown in Figure 9, the light-shielding layer LS is provided in a region that includes the region where the gate electrode GL1-1 and the oxide semiconductor layer OS overlap in a plan view. Note that the gate electrode GL1-1 can also be called the "gate line".

[0042] As shown in Figures 5, 7, and 9, the oxide semiconductor layer OS extends in the second direction D2. The gate electrode GL1-1 extends in the first direction D1 and intersects with the oxide semiconductor layer OS. The pattern of the gate electrode GL1-1 is located inside the pattern of the light-shielding layer LS.

[0043] As shown in Figures 5, 8, and 9, the aperture GCON is located near the lower end of the pattern of the oxide semiconductor layer OS. The aperture GCON is located in a region that overlaps with the pattern of the oxide semiconductor layer OS, but does not overlap with the gate electrode GL1-1. The aperture GCON is located in a region that overlaps with the connecting electrode GL1-2. The connecting electrode GL1-2 has an island-like pattern that covers the aperture GCON and overlaps with the oxide semiconductor layer OS. Therefore, the connecting electrode GL1-2 is in contact with the oxide semiconductor layer OS via the aperture GCON.

[0044] As shown in Figures 5 and 10, the aperture WCON is located near the upper edge of the oxide semiconductor layer OS pattern, in a region that overlaps with the wiring W1. The main portion of the oxide semiconductor layer OS pattern extends in the second direction D2 between adjacent wiring W1s. The remaining portion of the oxide semiconductor layer OS pattern extends from the main portion toward the region of the aperture WCON in directions oblique to the first direction D1 and the second direction D2.

[0045] As shown in Figures 5 and 11, multiple wirings W1 extend in the second direction D2. When it is necessary to distinguish and explain two adjacent wirings, the two adjacent wirings W1 are referred to as the first wiring W1-1 and the second wiring W1-2. In this case, the main portion of the oxide semiconductor layer OS can be said to extend in the second direction D2 between the first wiring W1-1 and the second wiring W1-2, and intersect with the gate electrode GL1-1.

[0046] As shown in Figures 5, 12, and 13, the aperture ZCON is located near the lower end of the pattern of the oxide semiconductor layer OS. The aperture ZCON is located in a region that overlaps with the pattern of the oxide semiconductor layer OS, but does not overlap with the gate electrode GL1-1. The aperture ZCON is located in a region that overlaps with the connecting electrode GL1-2 and ZTCO. The connecting electrode ZTCO overlaps with the aperture ZCON and the connecting electrode GL1-2 between the first wiring W1-1 and the second wiring W1-2. Therefore, the connecting electrode ZTCO is in contact with the connecting electrode GL1-2 via the aperture ZCON. Note that the connecting electrode ZTCO is not in contact with the oxide semiconductor layer OS.

[0047] As shown in Figures 5, 14, and 15, the aperture PCON is provided near the upper end of the pattern of the connecting electrode ZTCO. The aperture PCON is provided in a region that overlaps with the pattern of the gate electrode GL1-1 and the pattern of the connecting electrode ZTCO. The aperture PCON is provided in a region that overlaps with the pixel electrode PTCO. The pixel electrode PTCO overlaps with the gate electrode GL1-1, the oxide semiconductor layer OS, and the connecting electrode ZTCO between the first wiring W1-1 and the second wiring W1-2. Therefore, the pixel electrode PTCO is in contact with the connecting electrode ZTCO via the aperture PCON that overlaps with the gate electrode GL1-1.

[0048] As shown in Figure 16, the common auxiliary electrode CMTL is arranged in a grid pattern, overlapping with a portion of the pixel electrode PTCO of each of the multiple pixels, and an aperture OP is formed at a position opposite each pixel electrode PTCO. Specifically, the common auxiliary electrode CMTL is provided in common to multiple pixels without being divided within the image display area, and overlaps with the aperture PCON of each pixel, as well as with a portion of the edge of each pixel electrode PTCO. Therefore, in the aperture PCON, the common auxiliary electrode CMTL overlaps with the pixel electrode PTCO. In addition, the common auxiliary electrode CMTL overlaps with the gate electrode GL1-1 in a plan view. On the other hand, the common auxiliary electrode CMTL is opened so that the pixel electrode PTCO, including the aperture ZCON, is exposed. That is, the aperture ZCON (first contact area CON1) is included in the display area. Note that the display area here refers to the area in which the user can see the light from the pixel when viewed on a pixel-by-pixel basis. For example, areas that are shielded by a metal layer and in which the user cannot see the light are not included in the display area. In other words, the display area described above is sometimes referred to as the "light-transmitting area (or aperture area)."

[0049] As shown in Figure 17, the common electrode CTCO is provided in common for multiple pixels without being divided, at least within the image display area. The common electrode CTCO overlaps with the pixel electrode PTCO. The common electrode CTCO has a slit SL in the region corresponding to each aperture OP. The slit SL has a curved shape (a vertically elongated S-shape). The tip of the slit SL has a shape in which the width decreases perpendicular to the direction of extension of the tip. Furthermore, one tip of the slit SL overlaps with the common auxiliary electrode CMTL within the aperture PCON and also overlaps with the pixel electrode PTCO. The other tip of the slit SL is located within the aperture OP but does not overlap with the pixel electrode PTCO.

[0050] [4-5. Materials of each component of the array substrate 300] As the substrate SUB, a rigid substrate having light transmittance and no flexibility, such as a glass substrate, a quartz substrate, or a sapphire substrate, can be used. On the other hand, when the substrate SUB needs to have flexibility, a flexible substrate containing resin and having flexibility, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, can be used as the substrate SUB. In order to improve the heat resistance of the substrate SUB, impurities may be introduced into the above resin.

[0051] As the gate electrodes GL1-1 and GL2, the connection electrode GL1-2, the wirings W1 and W2, the light-shielding layer LS, and the common auxiliary electrode CMTL, a metal material can be used. For example, as the metal material, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), or silver (Ag), or an alloy or compound thereof is used. As the members such as the above electrodes, the above metal material may be used in a single layer or in a laminated form.

[0052] For example, as the gate electrodes GL1-1 and the connection electrode GL1-2, a laminated structure of Ti / Al / Ti is used. In the present embodiment, the cross-sectional shape of the pattern end portion of the gate electrodes GL1-1 and the connection electrode GL1-2 having the above laminated structure is a forward taper shape.

[0053] As the gate insulating layers GI1 and GI2 and the insulating layers IL1 to IL5, a general insulating material can be used. For example, as the insulating layers IL1 to IL3 and IL5, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon nitride oxide (SiN x O y ), aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ), aluminum nitride oxide (AlN x Oy ), or aluminum nitride (AlN x Inorganic insulating materials such as ) can be used. As these insulating layers, insulating layers with few defects can be used. As insulating layer IL4, organic insulating materials such as polyimide resin, acrylic resin, epoxy resin, silicone resin, fluororesin, or siloxane resin can be used. The above insulating materials may be used as a single layer or in a laminated form as components such as the insulating layer.

[0054] As an example of the insulating layer mentioned above, the gate insulating layer GI1 is made of SiO with a thickness of 100 nm. x The following is used. SiO2 with a total thickness of 600nm to 700nm is used as the insulating layer IL1. x / SiN x / SiO x The gate insulating layer GI2 is made of SiO with a total thickness of 60-100 nm. x / SiN x The insulating layer IL2 is made of SiO with a total thickness of 300 nm to 500 nm. x / SiN x / SiO x The insulating layer IL3 is made of SiO with a total thickness of 200 nm to 500 nm. x (Single layer), SiN x (Single layer) or a lamination thereof is used. A polyimide resin with a thickness of 2 μm to 4 μm is used as the insulating layer IL4. SiN with a thickness of 50 nm to 150 nm is used as the insulating layer IL5. x (Single layer) is used.

[0055] Here, SiO x N y and AlO x N y These are silicon and aluminum compounds that contain nitrogen (N) in a smaller proportion (x>y) than oxygen (O). x O y and AlN x O y These are silicon and aluminum compounds that contain oxygen in a smaller proportion (x > y) than nitrogen.

[0056] As the oxide semiconductor layer OS, an oxide semiconductor having semiconductor properties can be used. The oxide semiconductor layer OS is translucent. For example, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) can be used. In particular, an oxide semiconductor having a composition ratio of In:Ga:Zn:O = 1:1:1:4 can be used. However, the oxide semiconductor containing In, Ga, Zn, and O used in this embodiment is not limited to the above composition, and oxide semiconductors with different compositions can also be used. For example, the ratio of In may be increased to improve mobility. Also, the ratio of Ga may be increased to increase the band gap and reduce the effect of light irradiation.

[0057] Other elements may be added to the oxide semiconductor containing In, Ga, Zn, and O. For example, metallic elements such as Al or Sn may be added to the oxide semiconductor. In addition to the oxide semiconductors mentioned above, oxide semiconductors containing In and Ga (IGO), oxide semiconductors containing In and Zn (IZO), oxide semiconductors containing In, Sn, and Zn (ITZO), or oxide semiconductors containing In and W may be used as the oxide semiconductor layer OS. The oxide semiconductor layer OS may be amorphous or crystalline. The oxide semiconductor layer OS may be a mixed phase of amorphous and crystalline materials.

[0058] A transparent conductive layer is used as the connecting electrode ZTCO, the pixel electrode PTCO, and the common electrode CTCO. As the transparent conductive layer, a mixture of indium oxide and tin oxide (ITO) or a mixture of indium oxide and zinc oxide (IZO) can be used. Other materials may also be used as the transparent conductive layer.

[0059] The display device 10 according to this embodiment has been described above. Generally, in an OS transistor, when moisture (or hydrogen) that has entered from the outside diffuses into the channel region, the OS transistor acquires depletion-type transistor characteristics. As a result of diligent research, the inventors have found that a transparent conductive oxide film in contact with the planarization film easily diffuses the water contained in the planarization film. That is, when the oxide semiconductor layer and the planarization film are connected by a conductive oxide film, the conductive oxide film becomes a water diffusion path, and the water contained in the planarization film diffuses through the conductive oxide film to the oxide semiconductor layer. Furthermore, the inventors have found that a metal film in contact with the conductive oxide film functions as a so-called water diffusion prevention layer that blocks water.

[0060] In the array substrate 300 of the display device 10, the connecting electrode ZTCO, which is electrically connected to the pixel electrode PTCO and in contact with the insulating layer IL4 that functions as a planarization film, contains a transparent conductive oxide. Therefore, during the heat treatment in the manufacturing process of the display device 10, which is performed after the formation of the insulating layer IL4, water contained in the insulating layer IL4 diffuses into the connecting electrode ZTCO. However, the oxide semiconductor layer OS (more specifically, the oxide semiconductor layer OS2) is electrically connected to the connecting electrode ZTCO via the connecting electrode GL1-2, which contains a metallic material. That is, the oxide semiconductor layer OS is not in contact with the insulating layer IL4. In addition, the connecting electrode GL1-2 functions as a water diffusion prevention layer. Therefore, since the diffusion of water from the insulating layer IL4 to the oxide semiconductor layer OS is blocked, fluctuations in the transistor characteristics of the OS transistors are suppressed in the display device 10. As a result, the variation in the transistor characteristics of the multiple OS transistors included in the display device 10 is also reduced, thus improving the manufacturing yield of the display device 10.

[0061] The display device 10 according to this embodiment is a high-definition display device having a configuration in which the aperture PCON of the insulating layer IL4 on which the pixel electrode PTCO is provided is superimposed on the gate electrode GL1-2. Since such a high-definition display device requires high transparency, many transparent conductive oxide films are arranged, and the configuration of the array substrate 300 is particularly effective. Furthermore, it goes without saying that the configuration of the array substrate 300 is effective not only for application to high-definition display devices but also for application to transparent display devices that require high transparency.

[0062] <Second Embodiment> Referring to Figures 18 and 19, the configuration of the array substrate 300A of the display device 10 according to one embodiment of the present invention will be described. In the following, when the configuration of the array substrate 300A is the same as that of the array substrate 300 of the first embodiment, the description of its configuration may be omitted.

[0063] Figure 18 is a schematic cross-sectional view showing the configuration of the array substrate 300A of the display device 10 according to one embodiment of the present invention. Figure 19 is a schematic plan view showing the configuration of the array substrate 300A of the display device 10 according to one embodiment of the present invention.

[0064] In the array substrate 300A, the GCON aperture is provided in the gate insulating layer GI1 and the oxide semiconductor layer OS2 so as to separate the oxide semiconductor layer OS2 into two regions. One region of the separated oxide semiconductor layer OS2 (hereinafter referred to as the "first region of the oxide semiconductor layer OS2") is connected to the oxide semiconductor layer OS1. The oxide semiconductor layer OS2 is exposed at the side of the GCON aperture, and the insulating layer IL1 is exposed at the bottom of the GCON aperture. In addition, the ZCON aperture is provided in the insulating layers IL3 and IL2 and the gate insulating layer GI1 in the array substrate 300A. At the bottom of the ZCON aperture, the other region of the separated oxide semiconductor layer OS2 (hereinafter referred to as the "second region of the oxide semiconductor layer OS2") is exposed.

[0065] In a plan view, the connecting electrode GL1-2, formed as the same layer as the gate electrode GL1-1, is positioned to cover the opening GCON. Since the sides of the opening GCON expose not only the side surface of the first region of the oxide semiconductor layer OS2 but also the side surface of the second region of the oxide semiconductor layer OS2, the connecting electrode GL1-2 is electrically connected to the first and second regions of the oxide semiconductor layer OS2 via the opening GCON. In other words, the first and second regions of the oxide semiconductor layer OS2, separated by the opening GCON, are electrically connected to each other via the connecting electrode GL1-2. To put it another way, the connecting electrode GL-2 spatially separates the first and second regions of the oxide semiconductor layer OS2 and electrically connects the first and second regions of the oxide semiconductor layer OS2.

[0066] Furthermore, in a plan view, the connecting electrode ZTCO formed on the insulating layer IL3 is positioned to cover the aperture ZCON. That is, the connecting electrode ZTCO is electrically connected to the second region of the oxide semiconductor layer OS2 via the aperture ZCON. The connecting electrode ZTCO is electrically connected to the pixel electrode PTCO, but the connecting electrode ZTCO is in contact with the insulating layer IL4 which contains an organic insulating material. Therefore, during the heat treatment in the manufacturing process of the display device 10, which is performed after the formation of the insulating layer IL4, water contained in the insulating layer IL4 is diffused into the connecting electrode ZTCO.

[0067] In the array substrate 300A, the connecting electrode ZTCO is in contact with the second region of the oxide semiconductor layer OS2. Therefore, water contained in the insulating layer IL4 diffuses through the connecting electrode ZTCO into the second region of the oxide semiconductor layer OS2. However, the first and second regions of the oxide semiconductor layer OS2 are not in direct contact, and a connecting electrode GL1-2 containing a metallic material is provided between them. Therefore, even if water contained in the insulating layer IL4 diffuses into the second region of the oxide semiconductor layer OS2, it is blocked by the connecting electrode GL1-2 and hardly diffuses into the first region of the oxide semiconductor layer OS2. In other words, even in the array substrate 300A, the connecting electrode GL1-2 can function as a water diffusion prevention layer.

[0068] As described above, in the array substrate 300A of the display device 10 according to this embodiment, the oxide semiconductor layer OS2 is separated into two regions by the connecting electrode GL1-2, thereby blocking the diffusion of water contained in the insulating layer IL4. Therefore, the water contained in the insulating layer IL4 does not diffuse to the oxide semiconductor layer OS1. Consequently, the diffusion of water from the insulating layer IL4 to the oxide semiconductor layer OS1, which functions as a channel region, is blocked, and thus fluctuations in the transistor characteristics of the OS transistors are suppressed in the display device 10 according to this embodiment. As a result, the variation in the transistor characteristics of the multiple OS transistors contained in the display device 10 is also reduced, improving the manufacturing yield of the display device 10.

[0069] In this embodiment, a configuration in which the oxide semiconductor layer OS2 is separated into two regions has been described, but the number of regions in which the oxide semiconductor layer OS is separated does not need to be more than two.

[0070] <Third Embodiment> Referring to Figures 20 and 21, the configuration of the array substrate 300B of the display device 10 according to one embodiment of the present invention will be described. In the following, if the configuration of the array substrate 300B is the same as that of the array substrate 300 of the first embodiment or the array substrate 300A of the second embodiment, the description of that configuration may be omitted.

[0071] Figure 20 is a schematic cross-sectional view showing the configuration of the array substrate 300B of the display device 10 according to one embodiment of the present invention. Figure 21 is a schematic plan view showing the configuration of the array substrate 300B of the display device 10 according to one embodiment of the present invention.

[0072] Unlike array substrates 300 and 300A, array substrate 300B does not have apertures GCON in the gate insulating layer GI1 and the oxide semiconductor layer OS2. Furthermore, similar to array substrate 300A, array substrate 300B has apertures ZCON in the insulating layers IL3 and IL2 and the gate insulating layer GI1. Also, in array substrate 300B, a connecting electrode ZMTL containing a metallic material is provided on top of the connecting electrode ZTCO. More specifically, the connecting electrode ZMTL is provided between the connecting electrode ZTCO and the pixel electrode PTCO, electrically connecting the connecting electrode ZTCO and the pixel electrode PTCO.

[0073] In a plan view, the connecting electrode ZMTL, formed on the connecting electrode ZTCO that is in contact with the oxide semiconductor layer OS2, is provided so as to cover the connecting electrode ZTCO. Therefore, the connecting electrode ZTCO is not in contact with the insulating layer IL4 which contains an organic insulating material. In other words, in the array substrate 300B, the connecting electrode ZMTL spatially separates the connecting electrode ZTCO from the insulating layer IL4. As a result, water contained in the insulating layer IL4 is blocked by the connecting electrode ZMTL and hardly diffuses into the connecting electrode ZTCO. Thus, in the array substrate 300B, the connecting electrode ZMTL can function as a water diffusion prevention layer.

[0074] As described above, in the array substrate 300B of the display device 10 according to this embodiment, the connecting electrode ZMTL is provided covering the connecting electrode ZTCO so that the connecting electrode ZTCO does not come into contact with the insulating layer IL4. Therefore, water contained in the insulating layer IL4 does not diffuse into the connecting electrode ZMTL that comes into contact with the oxide semiconductor layer OS. Consequently, the diffusion of water from the insulating layer IL4 to the oxide semiconductor layer OS1 is blocked, and therefore, fluctuations in the transistor characteristics of the OS transistors are suppressed in the display device 10 according to this embodiment. As a result, the variation in the transistor characteristics of the multiple OS transistors included in the display device 10 is also reduced, and the manufacturing yield of the display device 10 is improved.

[0075] The embodiments described above as embodiments of the present invention can be combined and implemented as appropriate, insofar as they do not contradict each other. Furthermore, devices based on the display devices of each embodiment, in which a person skilled in the art has added, deleted, or modified components, or added, omitted, or modified processes, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0076] Any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0077] 10: Display device, 22: Liquid crystal area, 24: Seal area, 26: Terminal area, 300, 300A, 300B: Array substrate, 310: Pixel, 320: Source driver circuit, 321: Source wiring, 330: Gate driver circuit, 331: Gate wiring, 333: Terminal section, 341: Connection wiring, 400: Seal material, 410: Liquid crystal element, 500: Opposing substrate, 600: Flexible printed circuit board, 700: Chip, 800: Transistor, 810: First gate electrode, 830: First source electrode, 840: First drain electrode, 890: Holding capacitance, CMTL: Common auxiliary electrode, CON1: First contact area, CON2: Second contact area, CTCO: Common electrode, GI1, GI2: Gate insulating layer, GL1, GL2: Gate electrode, IL1~IL6: Insulating layer, LS: Light-shielding layer, OP: Aperture, OS: Oxide semiconductor layer, PCON, WCON, ZCON: Aperture, PJT: Protrusion, PTCO: Pixel electrode, S: Semiconductor layer, SL: Slit, SP: Spacer, SUB: Substrate, Tr1, Tr2: Transistor, W: Wiring, ZMTL, ZTCO: Connecting electrode

Claims

1. Terminal gate and, An oxide semiconductor layer superimposed on the aforementioned gate electrode, A first insulating layer located on the oxide semiconductor layer and containing an organic insulating material, The pixel electrode on the first insulating layer, A first connecting electrode is electrically connected to the pixel electrode and is in contact with the first insulating layer, The oxide semiconductor layer and the first connecting electrode are further provided with a second connecting electrode that electrically connects the oxide semiconductor layer and the first connecting electrode, The first connecting electrode comprises a transparent conductive oxide, The second connecting electrode is a display device containing a metallic material.

2. Terminal gate and, An oxide semiconductor layer superimposed on the aforementioned gate electrode, A first insulating layer located on the oxide semiconductor layer and containing an organic insulating material, The pixel electrode on the first insulating layer, It includes a first connecting electrode that is in contact with the first insulating layer and electrically connects the oxide semiconductor layer and the pixel electrode, The oxide semiconductor layer is separated into at least two regions between the gate electrode and the first connecting electrode. The two regions are electrically connected by a second connecting electrode. The first connecting electrode comprises a transparent conductive oxide, The second connecting electrode is a display device containing a metallic material.

3. The display device according to claim 1 or claim 2, wherein the second connecting electrode is in the same layer as the gate electrode.

4. Terminal gate and, An oxide semiconductor layer superimposed on the aforementioned gate electrode, A first insulating layer located on the oxide semiconductor layer and containing an organic insulating material, The pixel electrode on the first insulating layer, A first connecting electrode in contact with the oxide semiconductor layer, The first connecting electrode covers the first connecting electrode so that it does not come into contact with the first insulating layer, and includes a second connecting electrode that electrically connects the first connecting electrode and the pixel electrode, The first connecting electrode comprises a transparent conductive oxide, The second connecting electrode is a display device containing a metallic material.

5. The first insulating layer includes an opening in which the pixel electrode is provided, In a plan view, the aperture is superimposed on the gate electrode, as described in claim 1, claim 2, or claim 4.

6. moreover, The gate insulating layer between the gate electrode and the oxide semiconductor layer, The second insulating layer on the gate electrode, The display device according to claim 1, claim 2, or claim 4, further comprising: a wiring on the second insulating layer that is in contact with the oxide semiconductor layer through openings provided in the second insulating layer and the gate insulating layer.

7. The display device according to claim 6, wherein the wiring includes a metallic material.

8. The display device according to claim 6, wherein the wiring is not in contact with the first insulating layer.

9. Furthermore, the display device according to claim 1, claim 2, or claim 4, further comprising a transistor including a semiconductor layer provided below the oxide semiconductor layer.

10. The display device according to claim 9, wherein the semiconductor layer includes silicon.

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