Capacitor mounting board

Abstract

This invention provides a capacitor mounting board that allows capacitors to be placed in close proximity to ICs without removing some of the conductive bumps on the power supply BGA. [Solution] The capacitor mounting board 1 comprises a board 10, (M × N) power supply lands 43, 47, and (M-1) × (N-1) capacitors 50, each arranged in a region surrounded by adjacent (2 × 2) power supply lands 43, 47. Each capacitor 50 has a first main surface S51, a second main surface S52, a first side surface S53 and a third side surface S55, a second side surface S54 and a fourth side surface S56, and is located at least on the first main surface S51, has multiple electrode terminals, is rectangular in shape on the first main surface S51 and the second main surface S52, and the side of the first main surface S51 on the side of the first side surface S53 and the side on the side of the third side surface S55 are arranged to be inclined at 45 degrees ± 5 degrees with respect to a straight line L extending in the first direction X on the second main surface S12 of the board 10.

Description

Technical Field

[0006] , ,

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[0001] The present invention relates to a capacitor mounting substrate.

Background Art

[0002] Patent Document 1 discloses a wiring board on which a capacitor is mounted. This wiring board has an IC mounted on the first main surface side and is mounted on a mother board on the second main surface side via a BGA (Ball Grid Array). Also, in this wiring board, the capacitor is mounted as a decoupling capacitor for the power supply of the IC. Specifically, in the wiring board, on the second main surface side, a capacitor is arranged in place of some of the conductor bumps of the BGA. Thereby, the decoupling capacitor can be arranged in the immediate vicinity of the IC, and the decoupling effect (high-frequency voltage fluctuation suppression effect) of the power supply of the IC can be improved.

[0003] Patent Document 2 discloses, as an example of such a capacitor, a multilayer multi-terminal capacitor.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, if some of the conductor bumps of the power supply BGA of the wiring board are removed in order to arrange the capacitor in the immediate vicinity of the IC, the current in the remaining power supply conductor bumps increases, and there is a possibility of disconnection due to electromigration or the like.

[0006] The present invention aims to provide a capacitor mounting board that allows capacitors to be placed in close proximity to ICs without removing some of the conductive bumps on a power supply BGA. [Means for solving the problem]

[0007] The capacitor mounting substrate according to the present invention comprises a substrate having a first substrate main surface on which an IC is mounted and a second substrate main surface on which a power supply BGA for connection to a motherboard is arranged, and power supply lands for the power supply BGA, wherein (M × N) power supply lands are arranged two-dimensionally in a first direction and a second direction that intersect each other on the second substrate main surface of the substrate, where M and N are integers of 2 or more, and (M-1) × (N-1) capacitors are arranged in regions on the second substrate main surface of the substrate that are surrounded by (2 × 2) adjacent power supply lands in the first direction and the second direction of the (M × N) power supply lands. Each of the (M-1) × (N-1) capacitors has a first capacitor main surface facing the second main surface of the substrate, a second capacitor main surface opposite to the first capacitor main surface, a first capacitor side surface and a third capacitor side surface opposite to each other, and a second capacitor side surface and a fourth capacitor side surface opposite to each other, and has a plurality of electrode terminals arranged on at least the first capacitor main surface and connected to the second main surface of the substrate, and is rectangular in shape on the first capacitor main surface and the second capacitor main surface, and the side on the first capacitor side surface and the side on the third capacitor side surface of the first capacitor main surface are arranged to be inclined at 45 degrees ± 5 degrees with respect to a straight line extending in the first direction on the second main surface of the substrate.

[0008] Another capacitor mounting board according to the present invention comprises a board having a first main board surface on which an IC is mounted and a second main board surface on which a power supply BGA for connection to a motherboard is arranged, and power supply lands for the power supply BGA, wherein (M × N) power supply lands are arranged two-dimensionally in a first direction and a second direction intersecting each other on the second main board surface of the board, where M and N are integers of 2 or more, and (M-1) × (N-1) capacitors are arranged in regions surrounded by (2 × 2) power supply lands adjacent to each other in the first direction and the second direction of the (M × N) power supply lands as seen from the second main board surface of the board. The board has a core layer and two build-up layers arranged on the first main board surface side and the second main board surface side of the core layer, respectively, and each including a power supply wiring layer. Each of the (M-1) × (N-1) capacitors is embedded in the core layer of the substrate and has a first capacitor main surface facing the build-up layer on the first main surface side of the substrate, a second capacitor main surface opposite to the first capacitor main surface, a first capacitor side and a third capacitor side opposite to each other, and a second capacitor side and a fourth capacitor side opposite to each other, and has a plurality of electrode terminals arranged at least on the first capacitor main surface and connected to the power supply wiring layer of the build-up layer on the first main surface side of the substrate, and is rectangular in shape on the first capacitor main surface and the second capacitor main surface, and the side on the first capacitor side and the side on the third capacitor side of the first capacitor main surface are arranged to be inclined at 45 degrees ± 5 degrees with respect to a straight line extending in the first direction on the second main surface of the substrate. [Effects of the Invention]

[0009] According to the present invention, in a capacitor mounting board, a capacitor can be placed in close proximity to an IC without removing some of the conductive bumps of the power supply BGA. [Brief explanation of the drawing]

[0010] [Figure 1]This is a schematic cross-sectional view of the capacitor mounting board according to the first embodiment, and is a schematic cross-sectional view of line II shown in Figure 2. [Figure 2] This is a schematic diagram of the back surface of the capacitor mounting board according to the first embodiment, and is a schematic diagram of the back surface along line II-II shown in Figure 1. [Figure 3] This is a schematic cross-sectional view showing the internal structure of the capacitor mounting board according to the first embodiment, and is a schematic cross-sectional view taken along line III-III shown in Figure 4. [Figure 4] This is a schematic diagram of the back surface of the capacitor mounting board according to the first embodiment, and is a schematic diagram of the back surface along the IV-IV line shown in Figure 3. [Figure 5] This is a schematic diagram of the back surface of the capacitor mounting board according to the second embodiment, and is a schematic diagram of the back surface corresponding to the IV-IV line shown in Figure 3. [Figure 6] This is a schematic surface diagram of a capacitor in a capacitor mounting board according to the second embodiment. [Figure 7] This is a schematic surface diagram of a capacitor in a capacitor mounting board according to the second embodiment. [Figure 8] This is a schematic cross-sectional view showing the internal structure of the capacitor mounting board according to the third embodiment, and is a schematic cross-sectional view corresponding to line III-III shown in Figure 4. [Figure 9] This is a schematic cross-sectional view showing the internal structure of the capacitor mounting board according to the fourth embodiment, and is a schematic cross-sectional view of the line IX-IX shown in Figures 11 to 13. [Figure 10] Figures 11 to 13 are schematic cross-sectional diagrams showing the internal structure of the capacitor mounting board according to the fourth embodiment, and are schematic cross-sectional diagrams of line XX. [Figure 11] This is a schematic diagram of the back surface of the capacitor mounting board according to the fourth embodiment, and is a schematic diagram of the back surface along the line X1-X1 shown in Figures 9 to 10. [Figure 12] This is a schematic diagram of the back surface of the capacitor mounting board according to the fourth embodiment, and is a schematic diagram of the back surface along the line X1I-X1I shown in Figures 9 to 10. [Figure 13]It is a schematic diagram of the back surface of the substrate in the capacitor mounting substrate according to the fourth embodiment, and is a schematic diagram of the back surface on the X1II-X1II line shown in FIGS. 9 to 10. [Figure 14] It is a schematic cross-sectional view showing the internal structure of the substrate in the capacitor mounting substrate according to the fourth embodiment, and is a schematic cross-sectional view of the X-X line shown in FIGS. 11 to 13.

Mode for Carrying Out the Invention

[0011] Hereinafter, an example of an embodiment of the present invention will be described with reference to the accompanying drawings. In each drawing, the same or corresponding parts will be denoted by the same reference numerals.

[0012] (First Embodiment) FIG. 1 is a schematic cross-sectional view of a capacitor mounting substrate according to the first embodiment, and is a schematic cross-sectional view of the I-I line shown in FIG. 2. FIG. 2 is a schematic diagram of the back surface of the capacitor mounting substrate according to the first embodiment, and is a schematic diagram of the back surface on the II-II line shown in FIG. 1. FIG. 3 is a schematic cross-sectional view showing the internal structure of the substrate in the capacitor mounting substrate according to the first embodiment, and is a schematic cross-sectional view of the III-III line shown in FIG. 4. FIG. 4 is a schematic diagram of the back surface of the substrate in the capacitor mounting substrate according to the first embodiment, and is a schematic diagram of the back surface on the IV-IV line shown in FIG. 3.

[0013] In FIGS. 1 to 4 and the drawings described later, the power supply lines (VDD, GND) are illustrated, and the signal lines are not illustrated. Further, hereinafter, the power supply lines (VDD, GND) will be described, and the description of the signal lines will be omitted.

[0014] The capacitor mounting substrate 1 shown in FIGS. 1 and 2 is a package substrate used for an IC package. The capacitor mounting substrate 1 includes a substrate 10 and a plurality of capacitors 50.

[0015] On the first main surface S11 of the substrate 10, i.e., the first main surface S11 of the capacitor mounting substrate 1, ICs such as processors are mounted via conductive bumps B1. The IC packages are mounted on the motherboard MB via a power supply BGA, and as a result, a power supply BGA, i.e., a power supply conductive bump B2, for connection to the motherboard MB is placed on the second main surface S12 of the substrate 10, i.e., the second main surface S12 of the capacitor mounting substrate 1.

[0016] As a result, as shown by the arrow in Figure 1, the DC current supplied from the voltage regulator is supplied to the IC via the motherboard MB, power supply BGA (power supply conductor bump B2), capacitor mounting board 1, and conductor bump B1. In addition, the AC current of the IC's power supply flows to the capacitor 50 via conductor bump B1 and capacitor mounting board 1, suppressing high-frequency voltage fluctuations and high-frequency noise of the IC's power supply.

[0017] As shown in Figure 3, the substrate 10 has a core layer 20 and two build-up layers 30 and 40.

[0018] The core layer 20 has multiple through-holes that penetrate from the first main surface S1 to the second main surface S2, specifically through-holes 21 for the first potential (e.g., VDD) and through-holes 25 for the second potential (e.g., GND).

[0019] The build-up layer 30 is located on the first main surface S1 side of the core layer 20. The build-up layer 30 includes two or more wiring layer pairs, specifically wiring layer pairs of a first potential (e.g., VDD) wiring layer 31 and a second potential (e.g., GND) wiring layer 35. The build-up layer 30 also includes multiple conductor vias, specifically multiple first potential (e.g., VDD) conductor vias 32 and multiple second potential (e.g., GND) conductor vias 36. Furthermore, the first main surface S11 of the build-up layer 30 has multiple power supply lands (power supply pads), specifically multiple first potential (e.g., VDD) lands 33 and multiple second potential (e.g., GND) lands 37.

[0020] The first potential conductor via 32 includes conductor vias stacked from the first potential land 33 to each of two or more first potential wiring layers 31, and conductor vias stacked from the first potential land 33 to the first potential through-hole 21. The second potential conductor via 36 includes conductor vias stacked from the second potential land 37 to each of two or more second potential wiring layers 35, and conductor vias stacked from the second potential land 37 to the second potential through-hole 25.

[0021] As a result, the first potential land 33, the first potential wiring layer 31 in two or more wiring layer pairs, and the first potential through-hole 21 are electrically connected by the first potential conductor via 32. In addition, the second potential land 37, the second potential wiring layer 35 in two or more wiring layer pairs, and the second potential through-hole 25 are electrically connected by the second potential conductor via 36.

[0022] Furthermore, by including a conductor via 32 for the first potential that is stacked from the land 33 for the first potential to the through-hole 21 for the first potential, and a conductor via 36 for the second potential that is stacked from the land 37 for the second potential to the through-hole 25 for the second potential, the shortest possible DC current path can be achieved, thereby minimizing resistance.

[0023] The build-up layer 40 is located on the second main surface S2 side of the core layer 20. The build-up layer 40 includes two or more wiring layer pairs, specifically wiring layer pairs of a first potential (e.g., VDD) wiring layer 41 and a second potential (e.g., GND) wiring layer 45. The build-up layer 40 also includes multiple conductor vias, specifically multiple first potential (e.g., VDD) conductor vias 42 and multiple second potential (e.g., GND) conductor vias 46. Furthermore, the second main surface S12 of the build-up layer 40 has multiple power supply lands (power supply pads), specifically multiple first potential (e.g., VDD) lands 43 and multiple second potential (e.g., GND) lands 47.

[0024] The first potential conductor via 42 includes conductor vias stacked from the first potential land 43 to each of two or more first potential wiring layers 41, and conductor vias stacked from the first potential land 43 to the first potential through-hole 21. The second potential conductor via 46 also includes conductor vias stacked from the second potential land 47 to each of two or more second potential wiring layers 45, and conductor vias stacked from the second potential land 47 to the second potential through-hole 25.

[0025] As a result, the first potential land 43, the first potential wiring layer 41 in two or more wiring layer pairs, and the first potential through-hole 21 are electrically connected by the first potential conductor via 42. In addition, the second potential land 47, the second potential wiring layer 45 in two or more wiring layer pairs, and the second potential through-hole 25 are electrically connected by the second potential conductor via 46.

[0026] Furthermore, by including a conductor via 42 for the first potential that is stacked from the land 43 for the first potential to the through-hole 21 for the first potential, and a conductor via 46 for the second potential that is stacked from the land 47 for the second potential to the through-hole 25 for the second potential, the shortest possible DC current path can be achieved, thereby minimizing resistance.

[0027] Furthermore, the second main surface S12 of the build-up layer 40 has multiple capacitor lands, specifically multiple first potential (e.g., VDD) lands 44 and multiple second potential (e.g., GND) lands 48.

[0028] The first potential conductor via 42 includes conductor vias stacked from the first potential land 44 to each of two or more first potential wiring layers 41, and conductor vias stacked from the first potential land 44 to the first potential through-hole 21. The second potential conductor via 46 also includes conductor vias stacked from the second potential land 48 to each of two or more second potential wiring layers 45, and conductor vias stacked from the second potential land 48 to the second potential through-hole 25.

[0029] As a result, the first potential land 44, the first potential wiring layer 41 in two or more wiring layer pairs, and the first potential through-hole 21 are electrically connected by the first potential conductor via 42. In addition, the second potential land 48, the second potential wiring layer 45 in two or more wiring layer pairs, and the second potential through-hole 25 are electrically connected by the second potential conductor via 46.

[0030] Furthermore, by including a conductor via 42 for the first potential that is stacked from the land 44 for the first potential to the through-hole 21 for the first potential, and a conductor via 46 for the second potential that is stacked from the land 48 for the second potential to the through-hole 25 for the second potential, the shortest possible distance for the AC current path through the capacitor 50 can be achieved, resulting in low ESL (Equivalent Series Inductance). In addition, the mutual inductance between the AC current paths can be maximized.

[0031] Examples of materials for the core layer 20 include known materials such as glass epoxy, and examples of materials for the build-up layers 30 and 40 include known materials such as epoxy resin. Examples of materials for the power supply lands 33, 37, 43, 47, capacitor lands 44, 48, wiring layers 31, 35, 41, 45, conductor vias 32, 36, 42, 46, and through-holes 21, 25 include known metallic materials such as Cu.

[0032] As shown in Figure 2, (M × N) power supply lands (power supply pads) 43, 47 for the power supply BGA are arranged on the second main surface S12 of the substrate 10. The (M × N) power supply lands 43, 47 are arranged in a two-dimensional manner at equal intervals (e.g., 1 mm intervals) in a first direction X and a second direction Y that intersect each other on the second main surface S12 of the substrate 10. Here, M and N are integers of 2 or greater.

[0033] As described above, the (M × N) power supply lands 43, 47 include a land 43 for a first potential (e.g., VDD) and a land 47 for a second potential (e.g., GND). The first potential lands 43 and the second potential lands 47 are arranged alternately in the first direction X and the second direction Y.

[0034] Furthermore, (M-1) × (N-1) capacitors 50 are arranged on the second main surface S12 of the substrate 10. The (M-1) × (N-1) capacitors 50 are arranged on the second main surface S12 of the substrate 10 in regions enclosed by (2 × 2) adjacent power supply lands 43, 47 in the first direction X and second direction Y of (M × N) power supply lands 43, 47.

[0035] The capacitor 50 is a multi-terminal capacitor with two or more terminals, preferably four or more terminals. As shown in Figures 1 and 2, the capacitor 50 has a first main surface S51 facing the second main surface S12 of the substrate 10, a second main surface S52 opposite the first main surface S51, a first side surface S53 and a third side surface S55 opposite each other, and a second side surface S54 and a fourth side surface S56 opposite each other.

[0036] Multiple electrode terminals, specifically a first electrode terminal (e.g., VDD) 51 and a second electrode terminal (e.g., GND) 52, are arranged on at least the first main surface S51 of the capacitor 50. The first electrode terminal 51 is connected to a first potential land 44 on the second main surface S12 of the substrate 10 via a conductor bump B3. The second electrode terminal 52 is connected to a second potential land 48 on the second main surface S12 of the substrate 10 via a conductor bump B3 (see Figure 3).

[0037] On the other hand, the first electrode terminal 51 and the second electrode terminal 52 are not located on the first side surface S53, the second side surface S54, the third side surface S55, and the fourth side surface S56 of the capacitor 50. This makes it possible to suppress short circuits between the electrode terminals of the capacitor 50 and the power supply conductor bumps B2 due to the spread of the BGA, i.e., the adjacent power supply conductor bumps B2.

[0038] The capacitor 50 has a rectangular shape, preferably a square shape, on the first main surface S51 and the second main surface S52. The capacitor 50 is positioned such that the center of the first main surface S51 is located in the center of the region surrounded by adjacent (2x2) power supply lands. Furthermore, the capacitor 50 is positioned such that the edge on the first side surface S53 and the edge on the third side surface S55 of the first main surface S51 are inclined at 45 degrees ± 5 degrees, preferably 45 degrees, with respect to the straight line L extending in the first direction X on the second main surface S12 of the substrate 10.

[0039] Examples of such capacitors 50 include known Si capacitors and multilayer capacitors (see Patent Document 2).

[0040] As shown in Figure 4, the capacitor 50 includes a first capacitor 55 and a second capacitor 56. The first capacitor 55 and the second capacitor 56 are arranged alternately in the first direction X and the second direction Y. The first capacitor 55 and the second capacitor 56 have different assignments (allocation and arrangement) of the first potential (VDD) and the second potential (GND). For example, the first capacitor 55 has more first electrode terminals 51 than second electrode terminals 52. The second capacitor 56 has fewer first electrode terminals 51 than second electrode terminals 52. The total number of electrode terminals 51 and 52 of the first capacitor 55 is the same as the total number of electrode terminals 51 and 52 of the second capacitor 56.

[0041] This reduces the imbalance between the number of electrode terminals for the first potential (VDD) and the number of electrode terminals for the second potential (GND), thereby achieving a lower impedance in the AC current path through the capacitor 50.

[0042] As described above, according to the capacitor mounting board 1 of the first embodiment, the capacitor 50 is arranged on the back side of the board 10 opposite to the IC mounting side. This allows the decoupling capacitor to be placed in close proximity to the IC, thereby improving the decoupling effect (high-frequency voltage fluctuation suppression effect) and high-frequency noise suppression effect of the IC's power supply. More specifically, the high-frequency current (AC current) loop through the capacitor 50 can be made as short as possible, low impedance of the high-frequency current (AC current) loop can be achieved, and high-frequency voltage fluctuation suppression and high-frequency noise suppression of the IC's power supply can be achieved.

[0043] Furthermore, according to the capacitor mounting board 1 of the first embodiment, the capacitor 50 is positioned at an angle of, for example, 45 degrees in the region enclosed by adjacent (2x2) power supply lands 43, 47 in the (MxN) power supply lands 43, 47. This allows the capacitor 50 to be placed in close proximity to the IC without removing some of the conductor bumps B2 of the power supply BGA. Therefore, by removing some of the conductor bumps B2 of the power supply BGA, the current in the remaining power supply conductor bumps B2 increases, and disconnection of the power supply conductor bumps B2 due to electromigration or the like can be avoided.

[0044] In the first embodiment described above, an underfill may be interposed between the capacitor 50 and the substrate 10, more specifically, between the first main surface S51 of the capacitor 50 and the second main surface S12 of the substrate 10. Examples of underfill materials include epoxy resin.

[0045] In this way, the interposition of underfill between the capacitor 50 and the substrate 10 further suppresses short circuits between the electrode terminals of the capacitor 50 and the power supply conductor bumps B2 caused by the spread of BGA, i.e., the adjacent power supply conductor bumps B2. In addition, the adhesive strength of the underfill can increase the adhesive strength between the capacitor 50 and the substrate 10.

[0046] (Second Embodiment) The capacitor mounting board 1 of the second embodiment differs from the capacitor mounting board 1 of the first embodiment in the configuration of the capacitor 50.

[0047] Figure 5 is a schematic diagram of the back surface of the capacitor mounting board according to the second embodiment, and is a schematic diagram of the back surface corresponding to the IV-IV line shown in Figure 3. Figures 6 and 7 are schematic diagrams of the front surface of the capacitor in the capacitor mounting board according to the second embodiment.

[0048] As shown in Figures 5 and 6, the electrode terminals 51 and 52 on the first main surface S51 of the capacitor 50 are arranged in a staggered pattern. Specifically, in the capacitor 50, if the direction along the first side surface S53 and the third side surface S55 is defined as the third direction D3, and the direction along the second side surface S54 and the fourth side surface S56 is defined as the fourth direction D4, then in the third direction D3, electrode terminals of the same potential are lined up, and in the fourth direction D4, an odd number of electrode terminals of different potentials are lined up alternately. Furthermore, if the spacing between adjacent electrode terminals in the third direction D3 is defined as 1 pitch, then the power supply terminals of different potentials adjacent to each other in the fourth direction D4 are shifted by half a pitch relative to the third direction D3.

[0049] As shown in Figure 5, in capacitor 50, the power assignment of the electrode terminal closest to the first side surface S53 is the same as the power assignment of the conductor bump adjacent to the first side surface S53 in the BGA. Similarly, the power assignment of the electrode terminal closest to the second side surface S54 is the same as the power assignment of the conductor bump adjacent to the second side surface S54 in the BGA. Furthermore, the power assignment of the electrode terminal closest to the third side surface S55 is the same as the power assignment of the conductor bump adjacent to the third side surface S55 in the BGA. Also, the power assignment of the electrode terminal closest to the fourth side surface S56 is the same as the power assignment of the conductor bump adjacent to the fourth side surface S56 in the BGA. Note that power assignment refers to a first potential (e.g., VDD) and a second potential (e.g., GND).

[0050] The capacitor mounting board 1 of this second embodiment also offers the same advantages as the capacitor mounting board 1 of the first embodiment.

[0051] Furthermore, according to the capacitor mounting board 1 of the second embodiment, in the capacitor 50, the power supply assignment of the outermost electrode terminal among the electrode terminals is the same as the power supply assignment of the conductor bump adjacent to that side in the BGA. This further suppresses short circuits between the electrode terminals of the capacitor 50 and the power supply conductor bumps B2 due to the expansion of the BGA, i.e., the adjacent power supply conductor bumps B2.

[0052] In the second embodiment described above, as shown in Figure 7, the electrode terminals 51 and 52 may be positioned closer to the center of the capacitor 50, that is, the electrode terminals 51 and 52 may be positioned further inside the capacitor 50. Specifically, in the capacitor 50, the electrode terminal closest to the first side surface S53 is positioned at a predetermined distance from the conductor bump (end) adjacent to the first side surface S53 of the BGA. The electrode terminal closest to the second side surface S54 is positioned at a predetermined distance from the conductor bump (end) adjacent to the second side surface S54 of the BGA. The electrode terminal closest to the third side surface S55 is positioned at a predetermined distance from the conductor bump (end) adjacent to the third side surface S55 of the BGA. The electrode terminal closest to the fourth side surface S56 is positioned at a predetermined distance from the conductor bump (end) adjacent to the fourth side surface S56 of the BGA.

[0053] The specified distance is, for example, 170 μm or more when the BGA pitch is 1 mm and the diameter of the conductor bump in the BGA is 500 μm.

[0054] According to this, it is possible to further suppress short circuits between the electrode terminals of the capacitor 50 and the power supply conductor bump B2 due to the spread of the BGA, i.e., the adjacent power supply conductor bump B2.

[0055] (Third embodiment) The capacitor mounting board 1 of the third embodiment differs from the capacitor mounting board 1 of the first embodiment in the placement position of the capacitor 50.

[0056] Figure 8 is a schematic cross-sectional view showing the internal structure of the capacitor mounting board according to the third embodiment, and is a schematic cross-sectional view corresponding to line III-III shown in Figure 4.

[0057] As shown in Figure 8, the second main surface S12 of the substrate 10 may have (M-1) × (N-1) recesses 12, each located in a region surrounded by (2 × 2) adjacent power supply lands 43, 47 in the first direction X and second direction Y of the (M × N) power supply lands 43, 47. (M-1) × (N-1) capacitors 50 are embedded in each of the (M-1) × (N-1) recesses 12.

[0058] Each of the (M-1) × (N-1) recesses 12 in the build-up layer 40 on the second main surface S12 side of the substrate 10 reaches a portion of the multiple pairs of the first potential wiring layer 41 and the second potential wiring layer 45, but does not reach at least one pair of the multiple pairs of the first potential wiring layer 41 and the second potential wiring layer. In other words, the recesses 12 are formed in the build-up layer 40 such that at least one pair of the multiple pairs of the first potential wiring layer 41 and the second potential wiring layer remains. This ensures that conductive paths in the first direction X and the second direction Y are secured in the build-up layer 40.

[0059] According to this third embodiment of the capacitor mounting board 1, the same advantages as those of the first embodiment of the capacitor mounting board 1 can be obtained.

[0060] Furthermore, according to the capacitor mounting substrate 1 of the third embodiment, the capacitor 50 is embedded in a recess 12 on the second main surface S12 of the substrate 10. This further suppresses short circuits between the electrode terminals of the capacitor 50 and the power supply conductor bumps B2 due to the spread of the BGA, i.e., the adjacent power supply conductor bumps B2. In addition, the high-frequency current (AC current) loop through the capacitor 50 can be further shortened, low impedance of the high-frequency current (AC current) loop can be achieved, and high-frequency voltage fluctuations and high-frequency noise of the IC power supply can be suppressed.

[0061] In the third embodiment described above, the recess 12 in which the capacitor 50 is embedded may be filled with a molding material. Examples of molding materials include epoxy resin.

[0062] In this way, by filling the recess 12 in which the capacitor 50 is embedded with molding material, it is possible to further suppress short circuits between the electrode terminals of the capacitor 50 and the power supply conductor bump B2 caused by the expansion of the BGA, i.e., the adjacent power supply conductor bump B2. In addition, the adhesive strength of the molding material can increase the adhesive strength between the capacitor 50 and the substrate 10.

[0063] Alternatively, the entire capacitor 50 may be embedded in the recess 12. This ensures that the entire capacitor 50 is covered with the molding material, further suppressing short circuits between the electrode terminals of the capacitor 50 and the power supply conductor bump B2.

[0064] (Fourth Embodiment) The capacitor mounting board 1 of the fourth embodiment differs from the capacitor mounting board 1 of the first embodiment in the placement position of the capacitors 50.

[0065] Figure 9 is a schematic cross-sectional view showing the internal structure of the capacitor mounting substrate according to the fourth embodiment, and is a schematic cross-sectional view along the line IX-IX shown in Figures 11 to 13. Figures 10 and 14 are schematic cross-sectional views showing the internal structure of the capacitor mounting substrate according to the fourth embodiment, and are schematic cross-sectional views along the line XX shown in Figures 11 to 13. Figure 11 is a schematic back surface view of the capacitor mounting substrate according to the fourth embodiment, and is a schematic back surface view along the line X1-X1 shown in Figures 9 to 10. Figure 12 is a schematic back surface view of the capacitor mounting substrate according to the fourth embodiment, and is a schematic back surface view along the line X1I-X1I shown in Figures 9 to 10. Figure 13 is a schematic back surface view of the capacitor mounting substrate according to the fourth embodiment, and is a schematic back surface view along the line X1II-X1II shown in Figures 9 to 10.

[0066] As shown in Figure 9, in the fourth embodiment as well, the core layer 20 of the substrate 10 has a plurality of through-holes that penetrate from the first main surface S1 to the second main surface S2, specifically through-holes 21 for the first potential (e.g., VDD) and through-holes 25 for the second potential (e.g., GND).

[0067] Furthermore, as shown in Figure 10, the core layer 20 has a plurality of first potential conductor vias 22 that extend from the first electrode terminals 51 of the first main surface S51 of each of the (M-1) × (N-1) capacitors 50 to the build-up layer 30 on the first main surface S11 side of the core layer 20. In addition, the core layer 20 has a plurality of second potential conductor vias 26 that extend from the second electrode terminals 52 of the first main surface S51 of each of the (M-1) × (N-1) capacitors 50 to the build-up layer 30 on the first main surface S11 side of the core layer 20.

[0068] This makes it possible to shorten the AC current path through capacitor 50, thereby achieving low ESL (Equivalent Series Inductance).

[0069] Furthermore, the core layer 20 has a plurality of first potential conductor vias 23 that extend from the first electrode terminals 51 of the second main surface S52 of each of the (M-1) × (N-1) capacitors 50 to the build-up layer 40 on the second main surface S12 side of the core layer 20. Furthermore, the core layer 20 has a plurality of second potential conductor vias 27 that extend from the second electrode terminals 52 of the second main surface S52 of each of the (M-1) × (N-1) capacitors 50 to the build-up layer 40 on the second main surface S52 side of the core layer 20.

[0070] Furthermore, in the capacitor 50, the first electrode terminal 51 of the first main surface S51 penetrates through to the first electrode terminal 51 of the second main surface S52, and the second electrode terminal 52 of the first main surface S51 penetrates through to the second electrode terminal 52 of the second main surface S52.

[0071] As a result, the first potential conductor vias 42 and 23, the through vias of the capacitor 50, and the first potential conductor vias 22 and 32, and the second potential conductor vias 46 and 27, the through vias of the capacitor 50, and the second potential conductor vias 26 and 36 become DC current paths, thereby achieving low impedance in the DC current path.

[0072] In the fourth embodiment, the build-up layer 30 of the substrate 10 includes two or more wiring layer pairs, specifically wiring layer pairs of a first potential (e.g., VDD) wiring layer 31 and a second potential (e.g., GND) wiring layer 35. The build-up layer 30 also includes a plurality of conductor vias, specifically a plurality of first potential (e.g., VDD) conductor vias 32 and a plurality of second potential (e.g., GND) conductor vias 36. Furthermore, the first main surface S11 of the build-up layer 30 has a plurality of power supply lands (power supply pads), specifically a plurality of first potential (e.g., VDD) lands 33 and a plurality of second potential (e.g., GND) lands 37.

[0073] The first potential conductor via 32 includes conductor vias stacked from the first potential land 33 to each of two or more first potential wiring layers 31, and conductor vias stacked from the first potential land 33 to the first potential through-hole 21. The second potential conductor via 36 includes conductor vias stacked from the second potential land 37 to each of two or more second potential wiring layers 35, and conductor vias stacked from the second potential land 37 to the second potential through-hole 25.

[0074] As a result, the first potential land 33, the first potential wiring layer 31 in two or more wiring layer pairs, and the first potential through-hole 21 are electrically connected by the first potential conductor via 32. In addition, the second potential land 37, the second potential wiring layer 35 in two or more wiring layer pairs, and the second potential through-hole 25 are electrically connected by the second potential conductor via 36.

[0075] Furthermore, by including a conductor via 32 for the first potential that is stacked from the land 33 for the first potential to the through-hole 21 for the first potential, and a conductor via 36 for the second potential that is stacked from the land 37 for the second potential to the through-hole 25 for the second potential, the shortest possible DC current path can be achieved, thereby minimizing resistance.

[0076] Furthermore, the build-up layer 30 has a plurality of first potential conductor vias 32 that connect the first potential wiring layer 31 in two or more wiring layer pairs to each of the plurality of first potential conductor vias 22 in the core layer 20. Furthermore, the build-up layer 30 has a plurality of second potential conductor vias 36 that connect the second potential wiring layer 35 in two or more wiring layer pairs to each of the plurality of second potential conductor vias 26 in the core layer 20.

[0077] As a result, the first electrode terminal 51 on the first main surface S51 side of the capacitor 50 and the first potential wiring layer 31 of the build-up layer 30 are electrically connected by the first potential conductor via 22 of the core layer 20 and the first potential conductor via 32 of the build-up layer 30. In addition, the second electrode terminal 52 on the first main surface S51 side of the capacitor 50 and the second potential wiring layer 35 of the build-up layer 30 are electrically connected by the second potential conductor via 26 of the core layer 20 and the second potential conductor via 36 of the build-up layer 30.

[0078] In the fourth embodiment as well, the build-up layer 40 of the substrate 10 includes two or more wiring layer pairs, specifically wiring layer pairs of a first potential (e.g., VDD) wiring layer 41 and a second potential (e.g., GND) wiring layer 45. The build-up layer 40 also includes a plurality of conductor vias, specifically a plurality of first potential (e.g., VDD) conductor vias 42 and a plurality of second potential (e.g., GND) conductor vias 46. Furthermore, a plurality of power supply lands (power supply pads), specifically a plurality of first potential (e.g., VDD) lands 43 and a plurality of second potential (e.g., GND) lands 47, are arranged on the second main surface S12 of the build-up layer 40.

[0079] The first potential conductor via 42 includes conductor vias stacked from the first potential land 43 to each of two or more first potential wiring layers 41, and conductor vias stacked from the first potential land 43 to the first potential through-hole 21. The second potential conductor via 46 also includes conductor vias stacked from the second potential land 47 to each of two or more second potential wiring layers 45, and conductor vias stacked from the second potential land 47 to the second potential through-hole 25.

[0080] As a result, the first potential land 43, the first potential wiring layer 41 in two or more wiring layer pairs, and the first potential through-hole 21 are electrically connected by the first potential conductor via 42. In addition, the second potential land 47, the second potential wiring layer 45 in two or more wiring layer pairs, and the second potential through-hole 25 are electrically connected by the second potential conductor via 46.

[0081] Furthermore, by including a conductor via 42 for the first potential that is stacked from the land 43 for the first potential to the through-hole 21 for the first potential, and a conductor via 46 for the second potential that is stacked from the land 47 for the second potential to the through-hole 25 for the second potential, the shortest possible DC current path can be achieved, thereby minimizing resistance.

[0082] Furthermore, the build-up layer 40 has a plurality of first potential conductor vias 42 that connect the first potential wiring layers 41 in two or more wiring layer pairs to each of the plurality of first potential conductor vias 23 in the core layer 20. Furthermore, the build-up layer 40 has a plurality of second potential conductor vias 46 that connect the second potential wiring layers 45 in two or more wiring layer pairs to each of the plurality of second potential conductor vias 27 in the core layer 20.

[0083] The first potential conductor via 42 includes conductor vias stacked from the first potential conductor via 23 in the core layer 20 to the first potential wiring layer 41 closest to the second main surface S12. The second potential conductor via 46 includes conductor vias stacked from the second potential conductor via 27 in the core layer 20 to the second potential wiring layer 45 closest to the second main surface S12.

[0084] As a result, the first electrode terminal 51 on the second main surface S52 side of the capacitor 50 and the first potential wiring layer 41 of the build-up layer 40 are electrically connected by the first potential conductor via 23 of the core layer 20 and the first potential conductor via 42 of the build-up layer 40. In addition, the second electrode terminal 52 on the second main surface S52 side of the capacitor 50 and the second potential wiring layer 45 of the build-up layer 40 are electrically connected by the second potential conductor via 27 of the core layer 20 and the second potential conductor via 46 of the build-up layer 40.

[0085] Furthermore, by including a conductor via 42 for the first potential that is stacked from the first potential conductor via 23 in the core layer 20 to the first potential wiring layer 41 on the second main surface S12 side, and a conductor via 46 for the second potential that is stacked from the second potential conductor via 27 in the core layer 20 to the second potential wiring layer 45 on the second main surface S12 side, the shortest possible distance for the AC current path through the capacitor 50 can be achieved, resulting in low ESL (Equivalent Series Inductance). In addition, the mutual inductance between the AC current paths can be maximized.

[0086] In the fourth embodiment, (M-1) × (N-1) capacitors 50 are embedded in the core layer 20 of the substrate 10. The (M-1) × (N-1) capacitors 50 are each located in regions enclosed by (2 × 2) adjacent power lands 43, 47 in the first direction X and second direction Y, as viewed from the second main surface S12 of the substrate 10.

[0087] The first main surface S51 of the capacitor 50 faces the build-up layer 30 on the first main surface S11 side of the substrate 10, and the second main surface S52 of the capacitor 50 faces the build-up layer 40 on the second main surface S12 side of the substrate 10.

[0088] Multiple electrode terminals, specifically a first electrode terminal (e.g., VDD) 51 and a second electrode terminal (e.g., GND) 52, are arranged on the first main surface S51 of the capacitor 50. The first electrode terminal 51 on the first main surface S51 is connected to the first potential conductor via 32 and the first potential wiring layer 31 of the build-up layer 30 via the first potential conductor via 22 of the core layer 20. The second electrode terminal 52 on the first main surface S51 is connected to the second potential conductor via 36 and the second potential wiring layer 35 of the build-up layer 30 via the second potential conductor via 26 of the core layer 20 (see Figure 10).

[0089] Furthermore, the second main surface S52 of the capacitor 50 also has multiple electrode terminals, specifically a first electrode terminal (e.g., VDD) 51 and a second electrode terminal (e.g., GND) 52. The first electrode terminal 51 on the second main surface S52 is connected to the first potential conductor via 42 and the first potential wiring layer 41 of the build-up layer 40 via the first potential conductor via 23 of the core layer 20. The second electrode terminal 52 on the second main surface S52 is connected to the second potential conductor via 46 and the second potential wiring layer 45 of the build-up layer 40 via the second potential conductor via 27 of the core layer 20 (see Figure 10).

[0090] In the fourth embodiment, the capacitor 50 is rectangular, preferably square, on the first main surface S51 and the second main surface S52. The capacitor 50 is positioned such that the center of the first main surface S51 is located in the center of the region surrounded by adjacent (2x2) power supply lands. Furthermore, the capacitor 50 is positioned such that the edge on the first side surface S53 and the edge on the third side surface S55 of the first main surface S51 are inclined at 45 degrees ± 5 degrees, preferably 45 degrees, with respect to a straight line L extending in the first direction X on the second main surface S12 of the substrate 10.

[0091] Furthermore, capacitor 50 includes a first capacitor 55 and a second capacitor 56. The first capacitor 55 and the second capacitor 56 are arranged alternately in the first direction X and the second direction Y. The first capacitor 55 and the second capacitor 56 have different assignments (allocation and arrangement) of the first potential (VDD) and the second potential (GND). For example, the first capacitor 55 has more first electrode terminals 51 than second electrode terminals 52. The second capacitor 56 has fewer first electrode terminals 51 than second electrode terminals 52. Note that the total number of electrode terminals 51 and 52 of the first capacitor 55 is the same as the total number of electrode terminals 51 and 52 of the second capacitor 56.

[0092] This reduces the imbalance between the number of electrode terminals for the first potential (VDD) and the number of electrode terminals for the second potential (GND), thereby achieving a lower impedance in the AC current path through the capacitor 50.

[0093] This fourth embodiment of the capacitor mounting board 1 also has the same advantages as the first embodiment of the capacitor mounting board 1.

[0094] In the capacitor mounting substrate 1 of the fourth embodiment described above, as shown in Figure 14, the capacitor 50 may be configured not to have electrode terminals 51 and 52 on the second main surface S52. In this case, the core layer 20 described above does not have conductive vias 23 and 27.

[0095] Although embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above, and various modifications and variations are possible.

[0096] Furthermore, the present invention may also take the following forms. <1> A substrate having a first main surface on which ICs are mounted, and a second main surface on which a power supply BGA for connection to a motherboard is arranged, A power supply land for a power supply BGA, comprising (M × N) power supply lands arranged two-dimensionally in a first direction and a second direction intersecting each other on the second main surface of the substrate, where M and N are integers of 2 or more. On the second main surface of the substrate, (M-1) × (N-1) capacitors are arranged in the region enclosed by (2 × 2) power supply lands adjacent to each other in the first and second directions in the (M × N) power supply lands, Equipped with, Each of the (M-1) × (N-1) capacitors is The substrate has a first capacitor main surface facing the second main surface of the substrate, a second capacitor main surface opposite to the first main surface of the substrate, a first capacitor side surface and a third capacitor side surface that are opposite to each other, and a second capacitor side surface and a fourth capacitor side surface that are opposite to each other. It has a plurality of electrode terminals arranged at least on the main surface of the first capacitor and connected to the main surface of the second substrate of the substrate, The main surface of the first capacitor and the main surface of the second capacitor are rectangular in shape. The edges on the side of the first capacitor and the side of the third capacitor on the main surface of the first capacitor are arranged such that they are inclined at 45 degrees ± 5 degrees with respect to a straight line extending in the first direction on the main surface of the second substrate of the substrate. Capacitor mounting board.

[0097] <2> The (M × N) power supply lands are arranged at equal intervals in the first and second directions on the second main surface of the substrate. Each of the (M-1) × (N-1) capacitors is The main surface of the first capacitor and the main surface of the second capacitor are square in shape. The edges on the side of the first capacitor and the side of the third capacitor on the main surface of the first capacitor are arranged to be inclined at 45 degrees with respect to a straight line extending in the first direction on the main surface of the second substrate of the substrate. The first capacitor is positioned such that the center of its main surface is located in the center of the region enclosed by the adjacent (2x2) power supply lands. <1> Capacitor mounting board as described above.

[0098] <3> In each of the (M-1) × (N-1) capacitors, the plurality of electrode terminals are not arranged on the first capacitor side, the second capacitor side, the third capacitor side, and the fourth capacitor side. <1> or <2> Capacitor mounting board as described above.

[0099] <4> The (M × N) power supply lands include first potential lands and second potential lands arranged alternately in the first and second directions. The number of electrode terminals on the main surface of the first capacitor in each of the (M-1) × (N-1) capacitors is 4 or more, and includes a first electrode terminal for the first potential and a second electrode terminal for the second potential. <1> ~ <3> A capacitor mounting board as described in any of the following.

[0100] <5> The (M-1) × (N-1) capacitors include a first capacitor having more first electrode terminals than the number of second electrode terminals, and a second capacitor having fewer first electrode terminals than the number of second electrode terminals. The number of electrode terminals of the first capacitor and the number of electrode terminals of the second capacitor are the same. The first capacitor and the second capacitor are arranged alternately in the first and second directions. <4> Capacitor mounting board as described above.

[0101] <6> In each of the (M-1) × (N-1) capacitors, the plurality of electrode terminals on the main surface of the first capacitor are arranged in a staggered pattern. <4> Capacitor mounting board as described above.

[0102] <7> In each of the (M-1) × (N-1) capacitors, The power supply assignment for the electrode terminal closest to the first capacitor among the plurality of electrode terminals is the same as the power supply assignment for the conductor bump adjacent to the first capacitor side of the power supply BGA. The power supply assignment for the electrode terminal closest to the second capacitor among the plurality of electrode terminals is the same as the power supply assignment for the conductor bump adjacent to the second capacitor side of the power supply BGA. The power supply assignment for the electrode terminal closest to the third capacitor among the plurality of electrode terminals is the same as the power supply assignment for the conductor bump adjacent to the third capacitor side of the power supply BGA. The power supply assignment for the electrode terminal closest to the fourth capacitor among the plurality of electrode terminals is the same as the power supply assignment for the conductor bump adjacent to the fourth capacitor side of the power supply BGA. <6> Capacitor mounting board as described above.

[0103] <8> In each of the (M-1) × (N-1) capacitors, The electrode terminal closest to the first capacitor side among the plurality of electrode terminals is positioned at a predetermined distance from the conductor bump adjacent to the side of the first capacitor in the power supply BGA. The electrode terminal closest to the second capacitor side among the plurality of electrode terminals is positioned at a predetermined distance from the conductor bump adjacent to the side of the second capacitor in the power supply BGA. The electrode terminal closest to the third capacitor among the plurality of electrode terminals is positioned at a predetermined distance from the conductor bump adjacent to the side of the third capacitor in the power supply BGA. The electrode terminal closest to the fourth capacitor among the plurality of electrode terminals is positioned at a predetermined distance from the conductor bump adjacent to the fourth capacitor side of the power supply BGA. <5> or <6> Capacitor mounting board as described above.

[0104] <9> The substrate comprises a core layer and two build-up layers disposed on the first substrate main surface side and the second substrate main surface side of the core layer, Each of the two build-up layers includes two or more wiring layer pairs of a first potential wiring layer and a second potential wiring layer. <4> ~ <8> A capacitor mounting board as described in any of the following.

[0105] <10> The build-up layer on the main surface side of the second substrate of the core layer is, A plurality of first potential conductor vias connecting the first potential wiring layer in the two or more pairs of wiring layers and each of the first potential lands in the (M × N) power supply lands, A plurality of second potential conductor vias connecting the second potential wiring layer in the two or more pairs of wiring layers and each of the second potential lands in the (M × N) power supply lands, It has, The plurality of first potential conductor vias include stacked conductor vias, The plurality of second potential conductor vias include stacked conductor vias, <9> Capacitor mounting board as described above.

[0106] <11> On the second main surface of the substrate, (M-1) × (N-1) sets of capacitor lands are arranged for the plurality of electrode terminals of the (M-1) × (N-1) capacitors. Each set of capacitor lands in the (M-1)×(N-1) set includes a capacitor land for the first potential and a capacitor land for the second potential. The build-up layer on the main surface side of the second substrate of the core layer is, A plurality of first potential conductor vias connecting the first potential wiring layer in the wiring layer pair closest to the core layer among the two or more wiring layer pairs, and each of the first potential capacitor lands in each of the (M-1) × (N-1) sets of capacitor lands, A plurality of second potential conductor vias connecting the second potential wiring layer in the wiring layer pair closest to the core layer among the two or more wiring layer pairs, and each of the second potential capacitor lands in each of the (M-1) × (N-1) sets of capacitor lands, It has, The plurality of first potential conductor vias connected to the first potential capacitor land include stacked conductor vias. Multiple second potential conductor vias connected to the second potential capacitor land include stacked conductor vias. <10> Capacitor mounting board as described above.

[0107] <12> On the main surface of the second substrate, there are (M-1) × (N-1) recesses arranged in the region surrounded by (2 × 2) power supply lands adjacent to each other in the first and second directions among the (M × N) power supply lands, Each of the (M-1) × (N-1) recesses has (M-1) × (N-1) capacitors embedded in it. <9> ~ <11> A capacitor mounting board as described in any of the following.

[0108] <13> Each of the (M-1) × (N-1) depressions reaches a portion of the multiple pairs of the first potential wiring layer (VDD) and the second potential wiring layer (GND) in the build-up layer on the main surface side of the second substrate, but does not reach at least one pair of the multiple pairs of the first potential wiring layer (VDD) and the second potential wiring layer (GND). <12> Capacitor mounting board as described above.

[0109] <14> A substrate having a first main surface on which ICs are mounted, and a second main surface on which a power supply BGA for connection to a motherboard is arranged, A power supply land for a power supply BGA, comprising (M × N) power supply lands arranged two-dimensionally in a first direction and a second direction intersecting each other on the second main surface of the substrate, where M and N are integers of 2 or more. Viewed from the second main surface of the substrate, (M-1) × (N-1) capacitors are arranged in the region enclosed by (2 × 2) adjacent power supply lands in the first and second directions of the (M × N) power supply lands, Equipped with, The substrate comprises a core layer and two build-up layers, one on the first substrate main surface side and the other on the second substrate main surface side of the core layer, each including a power supply wiring layer. Each of the (M-1) × (N-1) capacitors is Embedded in the core layer of the substrate, The substrate has a first capacitor main surface facing the build-up layer on the first main surface side of the substrate, a second capacitor main surface opposite to the first capacitor main surface, a first capacitor side surface and a third capacitor side surface that are opposite to each other, and a second capacitor side surface and a fourth capacitor side surface that are opposite to each other. It has at least a plurality of electrode terminals arranged on the main surface of the first capacitor and connected to the power supply wiring layer of the build-up layer on the main surface side of the substrate, The main surface of the first capacitor and the main surface of the second capacitor are rectangular in shape. The edges on the side of the first capacitor and the side of the third capacitor on the main surface of the first capacitor are arranged such that they are inclined at 45 degrees ± 5 degrees with respect to a straight line extending in the first direction on the main surface of the second substrate of the substrate. Capacitor mounting board.

[0110] <15> The (M × N) power supply lands are arranged at equal intervals in the first and second directions on the second main surface of the substrate. Each of the (M-1) × (N-1) capacitors is The main surface of the first capacitor and the main surface of the second capacitor are square in shape. The edges on the side of the first capacitor and the side of the third capacitor on the main surface of the first capacitor are arranged to be inclined at 45 degrees with respect to a straight line extending in the first direction on the main surface of the second substrate of the substrate. The first capacitor is positioned such that the center of its main surface is located in the center of the region enclosed by the adjacent (2x2) power supply lands. <14> Capacitor mounting board as described above.

[0111] <16> The (M × N) power supply lands include first potential lands and second potential lands arranged alternately in the first and second directions. The number of electrode terminals on the main surface of the first capacitor in each of the (M-1) × (N-1) capacitors is 4 or more, and includes a first electrode terminal for the first potential and a second electrode terminal for the second potential. <14> or <15> Capacitor mounting board as described above.

[0112] <17> The (M-1) × (N-1) capacitors include a first capacitor having more first electrode terminals than the number of second electrode terminals, and a second capacitor having fewer first electrode terminals than the number of second electrode terminals. The number of electrode terminals of the first capacitor and the number of electrode terminals of the second capacitor are the same. The first capacitor and the second capacitor are arranged alternately in the first and second directions. <16> Capacitor mounting board as described above.

[0113] <18> Each of the two build-up layers has two or more pairs of first potential wiring layers and second potential wiring layers as the power supply wiring layers. <16> Capacitor mounting board as described above.

[0114] <19> The build-up layer on the main surface side of the second substrate of the core layer is, A plurality of first potential conductor vias connecting the first potential wiring layer in the two or more pairs of wiring layers and each of the first potential lands in the (M × N) power supply lands, A plurality of second potential conductor vias connecting the second potential wiring layer in the two or more pairs of wiring layers and each of the second potential lands in the (M × N) power supply lands, It has, The plurality of first potential conductor vias include stacked conductor vias, The plurality of second potential conductor vias include stacked conductor vias, <18> Capacitor mounting board as described above.

[0115] <20> The aforementioned core layer is A plurality of first potential-generating one-side core conductor vias extending from the first electrode terminal on the main surface of each of the (M-1) × (N-1) capacitors to the build-up layer on the main surface side of the core layer, A plurality of second potential-generating one-side core conductor vias extending from the second electrode terminal on the main surface of each of the (M-1) × (N-1) capacitors to the build-up layer on the main surface side of the core layer, It has, The build-up layer on the main surface side of the first substrate of the core layer is, A plurality of first potential capacitor conductor vias connecting the first potential wiring layer in the two or more pairs of wiring layers to each of the plurality of first potential one-side core conductor vias, A plurality of second potential capacitor conductor vias connecting the second potential wiring layer in the two or more pairs of wiring layers to each of the plurality of second potential one-side core conductor vias, Having, <18> Capacitor mounting board as described above.

[0116] <21> The aforementioned core layer is A plurality of first potential-generating other-side core conductor vias extending from the first electrode terminal on the main surface of each of the (M-1) × (N-1) capacitors to the build-up layer on the main surface side of the core layer, A plurality of second potential-generating other-side core conductor vias extending from the second electrode terminal on the main surface of each of the (M-1) × (N-1) capacitors to the build-up layer on the main surface side of the core layer, It further possesses, The build-up layer on the main surface side of the second substrate of the core layer is, A plurality of first potential capacitor conductor vias connecting the first potential wiring layer in the wiring layer pair closest to the second substrate main surface among the two or more wiring layer pairs, and each of the plurality of first potential other-side core conductor vias, A plurality of second potential capacitor conductor vias connecting the second potential wiring layer in the wiring layer pair closest to the second substrate main surface among the two or more wiring layer pairs, and each of the plurality of second potential other-side core conductor vias, It has, The plurality of first potential capacitor conductor vias in the build-up layer on the main surface side of the second substrate of the core layer include stacked conductor vias. The plurality of second potential capacitor conductor vias in the build-up layer on the main surface side of the second substrate of the core layer include stacked conductor vias. <20> Capacitor mounting board as described above. [Explanation of Symbols]

[0117] 1 Capacitor mounting board 10 circuit boards 12 indentations 20 core layers 21 Through-hole for the first potential 22,23 Conductor via for the first potential 25 Through-hole for second potential 26,27 Conductor vias for the second potential 30,40 Build-up layer 31,41 Wiring layer for first potential 32,42 Conductor vias for the first potential 33,43 First potential land (power supply land) 34,44 First potential land (capacitor land) 35,45 Wiring layer for second potential 36,46 Conductor vias for the second potential 37,47 Second potential land (power supply land) 38,48 Second potential land (capacitor land) 50 Capacitors 51 1st electrode terminal 52 2nd electrode terminal 55 First Capacitor 56. Second Capacitor B1 IC Conductor Bump B2 Power supply conductor bump (Power supply BGA) B3 Conductor bump for capacitor S11 First main surface (first substrate main surface) S12 Second main surface (second substrate main surface) S51 First main surface (First capacitor main surface) S52 Second main surface (Second capacitor main surface) S53 First side (First capacitor side) S54 Second side (Second capacitor side) S55 Third side (Third capacitor side) S56 Fourth side (Fourth capacitor side)

Claims

1. A circuit board having a first main surface on which ICs are mounted, and a second main surface on which a power supply BGA for connection to a motherboard is arranged, A power supply land for a power supply BGA, comprising (M × N) power supply lands arranged two-dimensionally in a first direction and a second direction intersecting each other on the second main surface of the substrate, where M and N are integers of 2 or more. On the second main surface of the substrate, (M-1) × (N-1) capacitors are arranged in the region surrounded by (2 × 2) power supply lands adjacent to each other in the first and second directions in the (M × N) power supply lands, Equipped with, Each of the (M-1) × (N-1) capacitors is The substrate has a first capacitor main surface facing the second main surface of the substrate, a second capacitor main surface facing the first main surface, a first capacitor side surface and a third capacitor side surface facing each other, and a second capacitor side surface and a fourth capacitor side surface facing each other. It has a plurality of electrode terminals arranged at least on the main surface of the first capacitor and connected to the main surface of the second substrate of the substrate, The main surface of the first capacitor and the main surface of the second capacitor are rectangular in shape. The edges on the side surface of the first capacitor and the edges on the side surface of the third capacitor are arranged such that they are inclined at 45 degrees ± 5 degrees with respect to a straight line extending in the first direction on the main surface of the second substrate of the substrate. Capacitor mounting board.

2. The (M × N) power supply lands are arranged at equal intervals in the first and second directions on the second main surface of the substrate. Each of the (M-1) × (N-1) capacitors is The main surface of the first capacitor and the main surface of the second capacitor are square in shape. The edges on the side of the first capacitor and the side of the third capacitor on the main surface of the first capacitor are arranged to be inclined at 45 degrees with respect to a straight line extending in the first direction on the main surface of the second substrate of the substrate. The first capacitor is positioned such that the center of its main surface is located in the center of the region enclosed by the adjacent (2x2) power supply lands. A capacitor mounting board according to claim 1.

3. In each of the (M-1) × (N-1) capacitors, the plurality of electrode terminals are not arranged on the first capacitor side, the second capacitor side, the third capacitor side, and the fourth capacitor side. A capacitor mounting board according to claim 1.

4. The (M × N) power supply lands include first potential lands and second potential lands arranged alternately in the first and second directions. The plurality of electrode terminals on the main surface of the first capacitor in each of the (M-1) × (N-1) capacitors are four or more, and include a first electrode terminal for the first potential and a second electrode terminal for the second potential. A capacitor mounting board according to claim 1.

5. The (M-1) × (N-1) capacitors include a first capacitor having more first electrode terminals than the number of second electrode terminals, and a second capacitor having fewer first electrode terminals than the number of second electrode terminals. The number of electrode terminals of the first capacitor and the number of electrode terminals of the second capacitor are the same. The first capacitor and the second capacitor are arranged alternately in the first and second directions. The capacitor mounting board according to claim 4.

6. In each of the (M-1) × (N-1) capacitors, the plurality of electrode terminals on the main surface of the first capacitor are arranged in a staggered pattern. The capacitor mounting board according to claim 4.

7. In each of the (M-1) × (N-1) capacitors, The power supply assignment for the electrode terminal closest to the first capacitor among the plurality of electrode terminals is the same as the power supply assignment for the conductor bump adjacent to the first capacitor side of the power supply BGA. The power supply assignment for the electrode terminal closest to the second capacitor among the plurality of electrode terminals is the same as the power supply assignment for the conductor bump adjacent to the second capacitor side of the power supply BGA. The power supply assignment for the electrode terminal closest to the third capacitor among the plurality of electrode terminals is the same as the power supply assignment for the conductor bump adjacent to the third capacitor side of the power supply BGA. The power supply assignment for the electrode terminal closest to the fourth capacitor among the plurality of electrode terminals is the same as the power supply assignment for the conductor bump adjacent to the fourth capacitor side of the power supply BGA. The capacitor mounting board according to claim 6.

8. In each of the (M-1) × (N-1) capacitors, The electrode terminal closest to the first capacitor side among the plurality of electrode terminals is positioned at a predetermined distance from the conductor bump adjacent to the side of the first capacitor in the power supply BGA. The electrode terminal closest to the second capacitor side among the plurality of electrode terminals is positioned at a predetermined distance from the conductor bump adjacent to the side of the second capacitor in the power supply BGA. The electrode terminal closest to the third capacitor among the plurality of electrode terminals is positioned at a predetermined distance from the conductor bump adjacent to the side of the third capacitor in the power supply BGA. The electrode terminal closest to the fourth capacitor among the plurality of electrode terminals is positioned at a predetermined distance from the conductor bump adjacent to the side of the fourth capacitor in the power supply BGA. A capacitor mounting board according to claim 5 or 6.

9. The substrate comprises a core layer and two build-up layers disposed on the first substrate main surface side and the second substrate main surface side of the core layer, respectively. Each of the two build-up layers includes two or more wiring layer pairs of a first potential wiring layer and a second potential wiring layer. The capacitor mounting board according to claim 4.

10. The build-up layer on the main surface side of the second substrate of the core layer is, A plurality of first potential conductor vias connecting the first potential wiring layer in the two or more pairs of wiring layers and each of the first potential lands in the (M × N) power supply lands, A plurality of second potential conductor vias connecting the second potential wiring layer in the two or more pairs of wiring layers and each of the second potential lands in the (M × N) power supply lands, It has, The plurality of first potential conductor vias include stacked conductor vias, The plurality of second potential conductor vias include stacked conductor vias. The capacitor mounting board according to claim 9.

11. On the second main surface of the substrate, (M-1) × (N-1) sets of capacitor lands are arranged for the plurality of electrode terminals of the (M-1) × (N-1) capacitors. Each set of capacitor lands in the (M-1) × (N-1) set includes a capacitor land for the first potential and a capacitor land for the second potential. The build-up layer on the main surface side of the second substrate of the core layer is, A plurality of first potential conductor vias connecting the first potential wiring layer in the wiring layer pair closest to the core layer among the two or more wiring layer pairs, and each of the first potential capacitor lands in each of the (M-1) × (N-1) sets of capacitor lands, A plurality of second potential conductor vias connecting the second potential wiring layer in the wiring layer pair closest to the core layer among the two or more wiring layer pairs, and each of the second potential capacitor lands in each of the (M-1) × (N-1) sets of capacitor lands, It has, The plurality of first potential conductor vias connected to the first potential capacitor land include stacked conductor vias. Multiple second potential conductor vias connected to the second potential capacitor land include stacked conductor vias. The capacitor mounting board according to claim 10.

12. On the main surface of the second substrate, there are (M-1) × (N-1) recesses arranged in the region surrounded by (2 × 2) power supply lands adjacent to each other in the first and second directions in the (M × N) power supply lands, Each of the (M-1) × (N-1) recesses has (M-1) × (N-1) capacitors embedded in it. The capacitor mounting board according to claim 9.

13. Each of the (M-1) × (N-1) depressions reaches a portion of the multiple pairs of the first potential wiring layer and the second potential wiring layer in the build-up layer on the main surface side of the second substrate, but does not reach at least one pair of the multiple pairs of the first potential wiring layer and the second potential wiring layer. The capacitor mounting board according to claim 12.

14. A circuit board having a first main surface on which ICs are mounted, and a second main surface on which a power supply BGA for connection to a motherboard is arranged, A power supply land for a power supply BGA, comprising (M × N) power supply lands arranged two-dimensionally in a first direction and a second direction intersecting each other on the second main surface of the substrate, where M and N are integers of 2 or more. Viewed from the second main surface of the substrate, (M-1) × (N-1) capacitors are arranged in the region surrounded by (2 × 2) adjacent power supply lands in the first and second directions of the (M × N) power supply lands, Equipped with, The substrate comprises a core layer and two build-up layers, one on the first substrate main surface side and the other on the second substrate main surface side of the core layer, each including a power supply wiring layer. Each of the (M-1) × (N-1) capacitors is Embedded in the core layer of the substrate, The substrate has a first capacitor main surface facing the build-up layer on the first main surface side of the substrate, a second capacitor main surface facing the first capacitor main surface, a first capacitor side surface and a third capacitor side surface facing each other, and a second capacitor side surface and a fourth capacitor side surface facing each other. It has at least a plurality of electrode terminals arranged on the main surface of the first capacitor and connected to the power supply wiring layer of the build-up layer on the main surface side of the substrate, The main surface of the first capacitor and the main surface of the second capacitor are rectangular in shape. The edges on the side surface of the first capacitor and the edges on the side surface of the third capacitor are arranged such that they are inclined at 45 degrees ± 5 degrees with respect to a straight line extending in the first direction on the main surface of the second substrate of the substrate. Capacitor mounting board.

15. The (M × N) power supply lands are arranged at equal intervals in the first and second directions on the second main surface of the substrate. Each of the (M-1) × (N-1) capacitors is The main surface of the first capacitor and the main surface of the second capacitor are square in shape. The edges on the side of the first capacitor and the side of the third capacitor on the main surface of the first capacitor are arranged to be inclined at 45 degrees with respect to a straight line extending in the first direction on the main surface of the second substrate of the substrate. The first capacitor is positioned such that the center of its main surface is located in the center of the region enclosed by the adjacent (2x2) power supply lands. A capacitor mounting board according to claim 14.

16. The (M × N) power supply lands include first potential lands and second potential lands arranged alternately in the first and second directions. The plurality of electrode terminals on the main surface of the first capacitor in each of the (M-1) × (N-1) capacitors are four or more, and include a first electrode terminal for the first potential and a second electrode terminal for the second potential. A capacitor mounting board according to claim 14.

17. The (M-1) × (N-1) capacitors include a first capacitor having more first electrode terminals than the number of second electrode terminals, and a second capacitor having fewer first electrode terminals than the number of second electrode terminals. The number of electrode terminals of the first capacitor and the number of electrode terminals of the second capacitor are the same. The first capacitor and the second capacitor are arranged alternately in the first and second directions. A capacitor mounting board according to claim 16.

18. Each of the two build-up layers has two or more pairs of first potential wiring layers and second potential wiring layers as the power supply wiring layers. A capacitor mounting board according to claim 16.

19. The build-up layer on the main surface side of the second substrate of the core layer is, A plurality of first potential conductor vias connecting the first potential wiring layer in the two or more pairs of wiring layers and each of the first potential lands in the (M × N) power supply lands, A plurality of second potential conductor vias connecting the second potential wiring layer in the two or more pairs of wiring layers and each of the second potential lands in the (M × N) power supply lands, It has, The plurality of first potential conductor vias include stacked conductor vias, The plurality of second potential conductor vias include stacked conductor vias. The capacitor mounting board according to claim 18.

20. The aforementioned core layer is A plurality of first potential-generating one-side core conductor vias extending from the first electrode terminal on the main surface of each of the (M-1) × (N-1) capacitors to the build-up layer on the main surface side of the first substrate of the core layer, A plurality of second potential-generating one-side core conductor vias extending from the second electrode terminal on the main surface of each of the (M-1) × (N-1) capacitors to the build-up layer on the main surface side of the first substrate of the core layer, It has, The build-up layer on the main surface side of the first substrate of the core layer is, A plurality of first potential capacitor conductor vias connecting the first potential wiring layer in the two or more pairs of wiring layers to each of the plurality of first potential one-side core conductor vias, A plurality of second potential capacitor conductor vias connecting the second potential wiring layer in the two or more pairs of wiring layers to each of the plurality of second potential one-side core conductor vias, Having, The capacitor mounting board according to claim 18.

21. The aforementioned core layer is A plurality of first potential-generating other-side core conductor vias extending from the first electrode terminal on the main surface of each of the (M-1) × (N-1) capacitors to the build-up layer on the main surface side of the core layer, A plurality of second potential-generating other-side core conductor vias extending from the second electrode terminal on the main surface of each of the (M-1) × (N-1) capacitors to the build-up layer on the main surface side of the core layer, It further possesses, The build-up layer on the main surface side of the second substrate of the core layer is, A plurality of first potential capacitor conductor vias connecting the first potential wiring layer in the wiring layer pair closest to the second substrate main surface among the two or more wiring layer pairs, and each of the plurality of first potential other-side core conductor vias, A plurality of second potential capacitor conductor vias connecting the second potential wiring layer in the wiring layer pair closest to the second substrate main surface among the two or more wiring layer pairs, and each of the plurality of second potential other-side core conductor vias, It has, The plurality of first potential capacitor conductor vias in the build-up layer on the main surface side of the second substrate of the core layer include stacked conductor vias. The plurality of second potential capacitor conductor vias in the build-up layer on the main surface side of the second substrate of the core layer include stacked conductor vias. The capacitor mounting board according to claim 20.

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