3D storage device with bit-line transistors

Abstract

The present invention relates to circuits, integrated chips, and methods for operating integrated chips, and more specifically, to a three-dimensional DRAM device including a bit-line transistor that selectively connects bit lines to a sense amplifier. This can improve the amplitude of the signal detected by the sense amplifier during memory cell readout, facilitating accurate reading of the memory cell. [Solution] The circuit includes a first bit line, a second bit line, a first word line, a second word line, a first memory cell, a second memory cell, a first sense amplifier, a first bit line transistor, and a second bit line transistor. The first memory cell is connected to the first bit line and the first word line. The second memory cell is connected to the second bit line and the second word line. The first sense amplifier has a first terminal. The first bit line transistor selectively connects the first bit line to the first terminal of the first sense amplifier. The second bit line transistor selectively connects the second bit line to the first terminal of the first sense amplifier.

Description

Background Art

[0001] Two-dimensional (2D) memory arrays are widely used in electronic devices, including, for example, NOR flash memory arrays, NAND flash memory arrays, dynamic random access memory (DRAM) arrays, and the like. However, 2D memory arrays have reached the limit of size reduction and are approaching the limit in memory density. Three-dimensional (3D) memory arrays are promising candidates for improving memory density and include, for example, 3D DRAM flash memory arrays, 3D NOR flash memory arrays, 3D NAND flash memory arrays, and the like.

Summary of the Invention

Problems to be Solved by the Invention

[0002] The present invention relates to a circuit, an integrated chip, and an operation method of an integrated chip, and more specifically, to a three-dimensional dynamic random access memory (DRAM) device including a bit line transistor that selectively connects a bit line to a sense amplifier.

Means for Solving the Problems

[0003] According to an embodiment of the present invention, a circuit includes a first bit line and a second bit line, a first word line and a second word line, a first memory cell connected to the first bit line and the first word line, a second memory cell connected to the second bit line and the second word line, a first sense amplifier having a first terminal, a first bit line transistor that selectively connects the first bit line to the first terminal of the first sense amplifier, and a second bit line transistor that selectively connects the second bit line to the first terminal of the first sense amplifier.

[0004] According to one embodiment of the present invention, the integrated chip includes a semiconductor substrate, a first sense amplifier arranged along the semiconductor substrate, a first bit line arranged at intervals on the semiconductor substrate, a second bit line arranged at intervals on the first bit line, a first word line arranged at intervals on the semiconductor substrate, a second word line arranged at intervals on the first word line, a first memory cell arranged at intervals on the semiconductor substrate and connected to the first bit line and the first word line, a second memory cell arranged at intervals on the first memory cell and connected to the second bit line and the second word line, a first bit line transistor arranged at intervals on the semiconductor substrate and spaced laterally from the first memory cell, and a second bit line transistor arranged at intervals on the first bit line transistor and spaced laterally from the second memory cell. A first conductive interconnect is connected to the first sense amplifier. The first bit line transistor includes a first source / drain electrode connected to the first bit line and a second source / drain electrode connected to the first conductive interconnect. The second bit-line transistor includes a first source / drain electrode connected to the second bit line and a second source / drain electrode connected to the first conductive interconnect.

[0005] According to one embodiment of the present invention, the operation method of the integrated chip is to provide a first switch line voltage to the control terminal of the first bit line transistor, causing the first bit line transistor to connect the first bit line to the first terminal of the first sense amplifier, wherein the first memory cell is connected to the first bit line and the first word line, and to provide a second switch line voltage to the control terminal of the second bit line transistor, causing the second bit line transistor to disconnect the second bit line from the first terminal of the first sense amplifier, wherein the second memory cell is connected to the second bit line and the second word line, and the first bit line transistor This includes providing a precharge voltage to the first bit line in response to providing a first switch line voltage to the control terminal of the second bit line transistor and providing a second switch line voltage to the control terminal of the second bit line transistor; providing a first word line voltage to the first word line in response to providing a precharge voltage to the first bit line and asserting the first word line voltage; determining the change from the precharge voltage on the first bit line in response to asserting the first word line; and determining the value stored in the first memory cell based on the change from the precharge voltage on the first bit line. [Effects of the Invention]

[0006] By reducing the total capacitance at the first terminal of the sense amplifier, the amplitude of the signal sensed by the first sense amplifier when reading the first memory cell can be improved, thereby making it easier to accurately read the first memory cell. [Brief explanation of the drawing]

[0007] The aspects of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not depicted to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for the sake of clarity in the discussion. [Figure 1]The diagrams show some embodiments of a three-dimensional dynamic random access memory (DRAM) device that includes a bit-line transistor that selectively connects the bit line to a sense amplifier. [Figure 2] Figure 1 shows timing diagrams for several embodiments of read and / or write operations for reading and / or writing to the first memory cell of the 3D DRAM device. [Figure 3] Figure 1 shows flowcharts of several embodiments of methods for reading and / or writing memory cells in a 3D DRAM device. [Figure 4] Figure 1 shows cross-sectional views of several embodiments of an integrated chip including a 3D DRAM device. [Figure 5] The schematics of several embodiments of the 3D DRAM device shown in Figure 1, which further includes complementary bit lines, are also shown. [Figure 6] Figure 1 shows circuit diagrams of several embodiments of the 3D DRAM device, further including a second sense amplifier. [Figure 7] Figure 6 shows three-dimensional diagrams of several embodiments of the 3D DRAM device. [Figure 8] Figure 4 shows cross-sectional views of various embodiments of the integrated chip. [Figure 9] Figure 4 shows cross-sectional views of various embodiments of the integrated chip. [Figure 10] Figure 4 shows cross-sectional views of various embodiments of the integrated chip. [Figure 11] Figure 4 shows cross-sectional views of various embodiments of the integrated chip. [Figure 12] Figure 4 shows cross-sectional views of various embodiments of the integrated chip. [Figure 13] Circuit diagrams of several embodiments of the sense amplifier are shown. [Figure 14] Cross-sectional views of several embodiments of a method for forming an integrated chip that includes a 3D DRAM device having bit-line transistors that selectively connect bit lines to sense amplifiers are shown. [Figure 15]Cross-sectional views of several embodiments of a method for forming an integrated chip that includes a 3D DRAM device having bit-line transistors that selectively connect bit lines to sense amplifiers are shown. [Figure 16] Cross-sectional views of several embodiments of a method for forming an integrated chip that includes a 3D DRAM device having bit-line transistors that selectively connect bit lines to sense amplifiers are shown. [Figure 17] Cross-sectional views of several embodiments of a method for forming an integrated chip that includes a 3D DRAM device having bit-line transistors that selectively connect bit lines to sense amplifiers are shown. [Figure 18] Cross-sectional views of several embodiments of a method for forming an integrated chip that includes a 3D DRAM device having bit-line transistors that selectively connect bit lines to sense amplifiers are shown. [Figure 19] Cross-sectional views of several embodiments of a method for forming an integrated chip that includes a 3D DRAM device having bit-line transistors that selectively connect bit lines to sense amplifiers are shown. [Figure 20] Cross-sectional views of several embodiments of a method for forming an integrated chip that includes a 3D DRAM device having bit-line transistors that selectively connect bit lines to sense amplifiers are shown. [Modes for carrying out the invention]

[0008] The following disclosure provides many different embodiments or examples for carrying out different features of the subject matter provided. For the sake of brevity of the invention, specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. For example, forming a first feature on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features, and the first and second features do not need to be in direct contact. Furthermore, the invention may repeat reference numerals and / or words in various examples. This repetition is for the sake of brevity and clarity and does not in itself define the relationships between the various embodiments and / or configurations discussed.

[0009] Furthermore, spatially relative terms such as “down,” “below,” “underside,” “up,” and “top” may be used in this specification to facilitate the description of the relationship between one element or feature and another, as shown in the figures. These spatially relative terms are intended to encompass different orientations of the device during use or operation, in addition to the orientation shown in the figures. The device may also be oriented in other directions (90-degree rotation or other directions), and the spatially relative descriptions used herein may be interpreted accordingly.

[0010] A dynamic random access memory (DRAM) device includes a sense amplifier, a first bit line, a second bit line, a first word line, and a second word line. The DRAM device includes a first memory cell connected to the first bit line and the first word line. The DRAM device includes a second memory cell connected to the second bit line and the second word line. The second bit line is spaced on the first bit line, the second word line is spaced on the first word line, and the second memory cell is spaced on the first memory cell, resulting in a three-dimensional arrangement that improves the memory density of the DRAM device.

[0011] In some devices, to reduce the number of sense amplifiers in a DRAM device, a first bit line and a second bit line are connected to a first terminal of the sense amplifier in a "shared" bit line arrangement. However, this shared bit line arrangement can make it difficult to accurately read memory cells in a three-dimensional DRAM device. For example, the first bit line has a first parasitic capacitance, and the second bit line has a second parasitic capacitance. In the shared bit line arrangement, since both the parasitic capacitance of the first bit line and the parasitic capacitance of the second bit line are connected to the first terminal of the sense amplifier, the total capacitance at the first terminal of the sense amplifier may increase. As a result, the amplitude of the signal detected by the first sense amplifier during the reading of the memory cell may decrease (e.g., the read margin may decrease), making it difficult to accurately read the memory cell. Further, as the number of bit lines connected to the first terminal of the sense amplifier increases, the total capacitance of the first terminal of the sense amplifier increases, making it difficult to accurately read the memory cell.

[0012] In various embodiments of the present invention, a three-dimensional DRAM device includes a first bit line transistor that selectively connects a first bit line to a first terminal of a sense amplifier, and a second bit line transistor that selectively connects a second bit line to the first terminal of the sense amplifier, improving the read performance of memory cells on the first and second bit lines. For example, during the reading and / or writing of the first memory cell, the first bit line transistor connects the first bit line to the first terminal of the sense amplifier, and the second bit line transistor separates the second bit line from the first terminal of the first sense amplifier. Thus, during the reading and / or writing of the first memory cell, the second bit line transistor can separate the parasitic capacitance on the second bit line from the first terminal of the sense amplifier, thereby reducing the total capacitance at the first terminal of the sense amplifier. By reducing the total capacitance at the first terminal of the sense amplifier, the amplitude of the signal sensed by the first sense amplifier during the reading of the first memory cell can be improved (e.g., the read margin can be improved), making it easier to accurately read the first memory cell.

[0013] FIG. 1 shows a circuit diagram 100 of some embodiments of a three-dimensional dynamic random access memory (DRAM) device including bit line transistors that selectively connect bit lines to sense amplifiers.

[0014] The DRAM device includes a first bit line 102, a second bit line 104, a first word line 106, and a second word line 108. The DRAM device includes a first memory cell 110 and a second memory cell 118. The first memory cell 110 is connected to the first bit line 102 and the first word line 106. The first memory cell 110 includes a first memory cell transistor 112 and a first memory cell capacitor 114. The first memory cell transistor 112 selectively connects the first memory cell capacitor 114 to the first bit line 102. The second memory cell 118 is connected to the second bit line 104 and the second word line 108. The second memory cell 118 includes a second memory cell transistor 120 and a second memory cell capacitor 122. The second memory cell transistor 120 selectively connects the second memory cell capacitor 122 to the second bit line 104.

[0015] The DRAM device includes a first sense amplifier 124 having a first terminal 124a. The DRAM device further includes a first bit line transistor 126 and a second bit line transistor 128. The first bit line transistor 126 selectively connects the first bit line 102 to the first terminal 124a of the first sense amplifier 124. The second bit line transistor 128 selectively connects the second bit line 104 to the first terminal 124a of the first sense amplifier 124.

[0016] For example, when reading and / or writing to the first memory cell 110, the first bit line transistor 126 connects the first bit line 102 to the first terminal 124a of the first sense amplifier 124, and the second bit line transistor 128 disconnects the second bit line from the first terminal 124a of the first sense amplifier 124. Therefore, when reading and / or writing to the first memory cell, the second bit line transistor 128 can disconnect the parasitic capacitance 132 on the second bit line 104 from the first terminal 124a of the first sense amplifier 124, thereby reducing the total capacitance at the first terminal 124a of the first sense amplifier 124. By reducing the total capacitance at the first terminal 124a of the first sense amplifier 124, the signal detected by the first sense amplifier 124 when reading the first memory cell 110 can be improved (for example, the read margin can be improved). As a result, the likelihood of accurately reading the first memory cell 110 can be improved. Furthermore, although the bit-line transistor has capacitance, this capacitance is substantially smaller than the parasitic capacitance isolated from the first terminal 124a of the first sense amplifier 124 by the bit-line transistor during reading and / or writing.

[0017] Similarly, when reading and / or writing to the second memory cell 118, the second bit line transistor 128 connects the second bit line to the first terminal 124a of the first sense amplifier 124, and the first bit line transistor 126 separates the first bit line 102 from the first terminal 124a of the first sense amplifier 124, thereby separating the parasitic capacitance 130 on the first bit line 102 from the first terminal 124a of the first sense amplifier 124 and reducing the total capacitance at the first terminal 124a of the first sense amplifier 124.

[0018] The first bit line transistor 126 has a first terminal 126a, a second terminal 126b, and a control terminal 126c. The first terminal 126a is connected to the first bit line 102. The second terminal 126b is connected to the first terminal 124a of the first sense amplifier 124. The control terminal 126c is connected to the first switch line 134.

[0019] The second bit line transistor 128 has a first terminal 128a, a second terminal 128b, and a control terminal 128c. The first terminal 128a is connected to the second bit line 104. The second terminal 128b is connected to the first terminal 124a of the first sense amplifier 124. The control terminal 128c is connected to the second switch line 136.

[0020] The DRAM device includes a first word line drive circuit 138 having a first output terminal 138a connected to a first word line 106 and a second output terminal 138b connected to a first switch line 134. The first word line drive circuit 138 drives the first word line 106 and the first switch line 134 (e.g., by providing voltage). The DRAM device also includes a second word line drive circuit 140 having a first output terminal 140a connected to a second word line 108 and a second output terminal 140b connected to a second switch line 136. The second word line drive circuit 140 drives the second word line 108 and the second switch line 136.

[0021] The first memory cell transistor 112 has a first terminal 112a, a second terminal 112b, and a control terminal 112c. The first memory cell capacitor 114 has a first terminal 114a and a second terminal 114b. The first terminal 112a of the first memory cell transistor 112 is connected to the first bit line 102. The second terminal 112b of the first memory cell transistor 112 is connected to the first terminal 114a of the first memory cell capacitor 114. The control terminal 112c of the first memory cell transistor 112 is connected to the first word line 106. The second terminal 114b of the first memory cell capacitor 114 is connected to the reference voltage terminal 116 (e.g., ground).

[0022] The second memory cell transistor 120 has a first terminal 120a, a second terminal 120b, and a control terminal 120c. The second memory cell capacitor 122 has a first terminal 122a and a second terminal 122b. The first terminal 120a of the second memory cell transistor 120 is connected to the second bit line 104. The second terminal 120b of the second memory cell transistor 120 is connected to the first terminal 122a of the second memory cell capacitor 122. The control terminal 120c of the second memory cell transistor 120 is connected to the second word line 108. The second terminal 122b of the second memory cell capacitor 122 is connected to the reference voltage terminal 116 (e.g., ground).

[0023] Figure 2 shows timing diagrams 200 for several embodiments of read and / or write operations for reading and / or writing to the first memory cell 110 of the 3D DRAM device in Figure 1.

[0024] At the first time point T1, the first word line drive circuit 138 provides the first switch line voltage VS1 (e.g., a "high" voltage) to the first switch line 134 via its output terminal 138b, asserting the first switch line 134. In response, the first bit line transistor 126 turns on, and the first bit line 102 is connected to the first terminal 124a of the first sense amplifier 124. Furthermore, at the first time point T1, the second word line drive circuit 140 provides the second switch line voltage VS0 (e.g., a "low" voltage) to the second switch line 136 via its output terminal 140b. In response, the second bit line transistor 128 turns off (or remains off), and the second bit line 104 is disconnected from the first terminal 124a of the first sense amplifier 124. In response to the first bit line transistor 126 connecting the first bit line 102 to the first terminal 124a of the first sense amplifier 124 (and the second bit line transistor 128 disconnecting the second bit line 104 from the first terminal 124a of the first sense amplifier 124), the first sense amplifier 124 provides a precharge voltage VP (e.g., standby voltage) to the first bit line 102 via the first terminal 124a.

[0025] At the second time point T2, in response to the first bit line 102 being precharged to the precharge voltage VP, the first word line drive circuit 138 asserts the first word line 106 by providing the first word line voltage VW1 (e.g., a "high" voltage) to the first word line 106 via the output terminal 138a. In response, the first memory cell transistor 112 turns on, and the first bit line 102 is connected to the first memory cell capacitor 114. In response, the first memory cell capacitor 114 discharges to or charges the first bit line 102 according to the charge of the first memory cell capacitor 114 (indicating the value stored in the first memory cell capacitor 114). In response, the first sense amplifier 124 detects (e.g., determines) a change in voltage from the precharge voltage VP on the first bit line 102, and determines (e.g., reads the first memory cell 110) the value stored in the first memory cell 110 based on the voltage change on the first bit line 102.

[0026] For example, if the first memory cell capacitor 114 is charged (e.g., the voltage at the first terminal 114a is greater than the precharge voltage VP), indicating that a first value (e.g., logic 1) is stored in the first memory cell 110, then, as shown in segment 202, in response to the first memory cell transistor 112 connecting the first bit line 102 to the first memory cell capacitor 114, the voltage on the first bit line 102 increases (e.g., from the precharge voltage VP to the first change voltage VΔ1). The first sense amplifier 124 detects the increase in voltage on the first bit line 102 and determines that the value stored in the first memory cell 110 is a first value (e.g., logic 1).

[0027] Conversely, if the first memory cell capacitor 114 is discharged (for example, the voltage at the first terminal 114a is lower than the precharge voltage (e.g., ground)), indicating that the first memory cell 110 stores a second value (e.g., logic 0), then, as shown in segment 204, the voltage on the first bit line 102 decreases (e.g., from the precharge voltage VP to the second changing voltage VΔ2) in response to the first memory cell transistor 112 connecting the first bit line 102 to the first memory cell capacitor 114. The first sense amplifier 124 detects the decrease in voltage on the first bit line 102 and determines that the value stored in the first memory cell 110 is the second value (e.g., logic 0).

[0028] At the third time T3, in response to the first sense amplifier 124 determining the value stored in the first memory cell 110, the first sense amplifier 124 provides a write voltage to the first bit line 102 (via the first terminal 124a) for writing to the first memory cell 110. For example, to write a first value (e.g., logic 1) to the first memory cell 110, the first sense amplifier 124 provides a first write voltage VB1 (e.g., a voltage higher than the precharge voltage VP) to the first bit line 102 (via the first terminal 124a), as shown in segments 206 and 208. In response, the first memory cell capacitor 114 is charged to the first write voltage VB1. Conversely, in order to write a second value (e.g., logic 0) to the first memory cell 110, the first sense amplifier 124 provides a second write voltage VB0 (e.g., a voltage lower than the precharge voltage VP) to the first bit line 102 (via the first terminal 124a), as shown in segments 210 and 212. In response, the first memory cell capacitor 114 is discharged.

[0029] At the fourth time T4, in response to writing to the first memory cell 110, the first word line drive circuit 138 provides the first word line 106 with a second word line voltage VW0 (e.g., a "low" voltage) via the output terminal 138a, deasserting the first word line 106.

[0030] In the fifth time T5, in response to the deassertion of the first word line 106, the first sense amplifier 124 provides a precharge voltage VP (e.g., standby voltage) to the first bit line 102 via the first terminal 124a.

[0031] At the sixth time T6, in response to the first sense amplifier 124 returning the first bit line 102 to the precharge voltage VP, the first word line drive circuit 138 provides the second switch line voltage VS0 (e.g., the "low" voltage) to the first switch line 134 via the output terminal 138b. In response, the first bit line transistor 126 turns off, and the first bit line 102 is isolated from the first terminal 124a of the first sense amplifier 124.

[0032] Figure 3 shows a flowchart 300 of several embodiments of the method for reading and / or writing memory cells of the three-dimensional DRAM device of Figure 1. Although the flowchart 300 is illustrated and described as a series of operations or events, it should be understood that the order of the illustrated operations or events should not be interpreted in an restrictive sense. For example, some operations may occur in a different order than those illustrated and / or described herein, and / or concurrently with other operations or events. Furthermore, not all illustrated operations are necessary to carry out one or more aspects or embodiments of the description herein. Furthermore, one or more operations shown herein may be performed in one or more separate operations and / or phases.

[0033] In block 302, a memory cell to be read from and / or written to is selected, and the bit line connected to the selected memory cell is identified. For example, if the first memory cell 110 is selected, the first bit line 102 is identified.

[0034] In block 304, the switch line corresponding to the identified bit line is identified, and the identified switch line is asserted. For example, if the first switch line 134 is identified, the first word line drive circuit 138 asserts the first switch line 134. In response, the first bit line transistor 126 turns on, and the first bit line 102 is connected to the first terminal 124a of the first sense amplifier 124.

[0035] In block 306, the identified bit lines are precharged. For example, the first sense amplifier 124 provides a precharge voltage to the first bit line 102 via the first bit line transistor 126.

[0036] In block 308, the word line connected to the selected memory cell is identified, and the identified word line is asserted. For example, if the first word line 106 is identified, the first word line drive circuit 138 asserts the first word line 106. In response, the first memory cell transistor 112 turns on, and the first bit line 102 is connected to the first memory cell capacitor 114.

[0037] In block 310, changes in the precharge voltage of the identified bit line are detected. For example, the first sense amplifier 124 detects changes in the precharge voltage of the first bit line 102.

[0038] In block 312, the value stored in the selected memory cell is determined based on the change from the precharge voltage on the identified bit line. For example, the first sense amplifier 124 determines the value stored in the first memory cell 110 based on the change from the precharge voltage on the first bit line 102.

[0039] In block 314, a write voltage is provided to the identified bit line. For example, the first sense amplifier 124 provides a write voltage to the first bit line 102 via the first bit line transistor 126, charging or discharging the first memory cell capacitor 114 to write to the first memory cell 110.

[0040] In block 316, the identified word line is de-assert. For example, the first word line drive circuit 138 de-asserts the first word line 106.

[0041] In block 318, a precharge voltage is provided to the identified bit line. For example, the first sense amplifier 124 provides a precharge voltage to the first bit line 102 via the first bit line transistor 126.

[0042] In block 320, the identified switch line is deasserted. For example, the first word line drive circuit 138 deassers the first switch line 134. In response, the first bit line transistor 126 turns off, and the first bit line 102 is decoupled (e.g., isolated) from the first terminal 124a of the first sense amplifier 124.

[0043] Figure 4 shows cross-sectional views 400 of several embodiments of an integrated chip including the three-dimensional DRAM device of Figure 1.

[0044] The integrated chip includes a semiconductor substrate 402. Word line drive circuits (e.g., 138, 140) and a first sense amplifier 124 are arranged along the semiconductor substrate 402. For example, in some embodiments, the word line drive circuits (e.g., 138, 140) and the first sense amplifier 124 include a transistor 404 along the semiconductor substrate 402. The transistor 404 includes a source / drain 406 and a gate 408. In some embodiments, the word line drive circuits (e.g., 138, 140) and the first sense amplifier 124 further include conductive interconnects 412 and 414, respectively, located within a dielectric structure 410 on the semiconductor substrate 402. In some embodiments, one or more of the conductive interconnects 414 form a first terminal 124a of the first sense amplifier 124. In some embodiments, the conductive interconnects form an output terminal of the word line drive circuit.

[0045] The first memory cell 110, the second memory cell 118, the first bit line 102, the second bit line 104, the first word line 106, and the second word line 108 are located within the dielectric structure 410 and spaced above the word line driving circuits (e.g., 138, 140) and the first sense amplifier 124, which are arranged along the semiconductor substrate 402. For example, the first memory cell capacitor 114 includes a first electrode layer 442 (corresponding to the first terminal 114a), a second electrode layer 446 (corresponding to the second terminal 114b), and an insulating layer 444 between the first electrode layer 442 and the second electrode layer 446. Furthermore, the first memory cell transistor 112 includes a first source / drain electrode 428 (corresponding to terminal 112a), a second source / drain electrode 430 (corresponding to terminal 112b); a channel layer 426 extending from the first source / drain electrode 428 to the second source / drain electrode 430; a gate electrode 422 between the first source / drain electrode 428 and the second source / drain electrode 430 (corresponding to control terminal 112c); and a gate dielectric layer 424 between the channel layer 426 and the gate electrode 422. In some embodiments, the first word line 106 is either the gate electrode 422 or forms the gate electrode 422. The gate electrode 422 is connected to the first word line drive circuit 138 by a conductive interconnect 416. The first source / drain electrode 428 extends from the channel layer 426 to the first bit line 102. The second source / drain electrode 430 extends from the channel layer 426 to the first electrode layer 442 of the first memory cell capacitor 114. The second electrode layer 446 of the first memory cell capacitor 114 is connected to the reference voltage terminal 116 by a conductive interconnect 447.

[0046] Similarly, the second memory cell capacitor 122 includes a first electrode layer 474 (corresponding to terminal 122a), a second electrode layer 478 (corresponding to terminal 122b), and an insulating layer 476 between the first electrode layer 474 and the second electrode layer 478. Furthermore, the second memory cell transistor 120 includes a first source / drain electrode 460 (corresponding to terminal 120a); a second source / drain electrode 462 (corresponding to terminal 120b); a channel layer 458 extending from the first source / drain electrode 460 to the second source / drain electrode 462; a gate electrode 454 between the first source / drain electrode 460 and the second source / drain electrode 462 (corresponding to control terminal 120c); and a gate dielectric layer 456 between the channel layer 458 and the gate electrode 454. In some embodiments, the second word line 108 is the gate electrode 454 or forms the gate electrode 454. The gate electrode 454 is connected to the second word line drive circuit 140 by a conductive interconnect 448. The first source / drain electrode 460 extends from the channel layer 458 to the second bit line 104. The second source / drain electrode 462 extends from the channel layer 458 to the first electrode layer 474 of the second memory cell capacitor 122.

[0047] The second memory cell 118 is arranged on the first memory cell 110 at vertical intervals (for example, along axis 101z). The second bit line 104 is arranged on the first bit line 102 at vertical intervals. The second word line 108 is arranged on the first word line 106 at vertical intervals.

[0048] The first bit-line transistor 126, the second bit-line transistor 128, the first switch line 134, and the second switch line 136 are located within a dielectric structure 410 and spaced above the word line drive circuits (e.g., 138, 140) and the first sense amplifier 124, which are arranged along the semiconductor substrate 402. For example, the first bit-line transistor 126 includes a first source / drain electrode 438 (corresponding to terminal 126a); a second source / drain electrode 440 (corresponding to terminal 126b); a channel layer 436 extending from the first source / drain electrode 438 to the second source / drain electrode 440; and a gate electrode 432 (corresponding to control terminal 126c) between the first source / drain electrode 438 and the second source / drain electrode 440. A gate dielectric layer 434 is provided between the channel layer 436 and the gate electrode 432. In some embodiments, the first switch line 134 is the gate electrode 432 or forms the gate electrode 432. The gate electrode 432 is connected to the first word line drive circuit 138 by a conductive interconnect 418. The first source / drain electrode 438 extends from the channel layer 436 to the first bit line 102. The second source / drain electrode 440 extends from the channel layer 436 to a conductive wire 421, which is connected to the first terminal 124a of the first sense amplifier 124 by a conductive interconnect 420.

[0049] Similarly, the second bit line transistor 128 includes a first source / drain electrode 470 (corresponding to terminal 128a); a second source / drain electrode 472 (corresponding to terminal 128b); a channel layer 468 extending from the first source / drain electrode 470 to the second source / drain electrode 472; a gate electrode 464 between the first source / drain electrode 470 and the second source / drain electrode 472 (corresponding to control terminal 128c); and a gate dielectric layer 466 between the channel layer 468 and the gate electrode 464. In some embodiments, the second switch line 136 is either the gate electrode 464 or forms the gate electrode 464. The gate electrode 464 is connected to the second word line drive circuit 140 by a conductive interconnect 450. The first source / drain electrode 470 extends from the channel layer 468 to the second bit line 104. The second source / drain electrode 472 extends from the channel layer 468 to the conductive 453, which is connected to the first terminal of the first sense amplifier 124 by conductive interconnects (e.g., 452, 421, 420).

[0050] The second switch line 136 is positioned vertically on the first switch line 134 (for example, along axis 101z). The first bit line transistor 126 is positioned laterally from the first memory cell transistor 112 (for example, along axis 101x). The second bit line transistor 128 is positioned laterally from the second memory cell transistor 120 (for example, along axis 101x) and vertically from the first bit line transistor 126.

[0051] In some embodiments, the semiconductor substrate 402 comprises silicon or other suitable semiconductor material. In some embodiments, the source / drain 406 is a doped region of the semiconductor substrate 402. In some embodiments, the source / drain may refer to the source or drain individually or collectively, depending on the context. In some embodiments, the gate 408 comprises polysilicon, tungsten, titanium, tantalum, or other suitable material. In some embodiments, the dielectric layer of the dielectric structure 410 comprises silicon oxide, silicon nitride, silicon carbide, hafnium oxide, aluminum oxide, or other suitable material. In some embodiments, the conductive interconnects (e.g., 412, 414, 416, 418, 420, 421, 447, 448, 450, 452, 453) comprises metals such as tungsten, aluminum, copper, or other suitable material. In some embodiments, the word lines, bit lines, and switch lines comprise metals such as tungsten, aluminum, copper, or other suitable material. In some embodiments, the gate dielectric layer comprises silicon oxide, hafnium oxide, or other suitable dielectric material. In some embodiments, the channel layer comprises a semiconductor such as silicon, or other suitable semiconductor material. In some embodiments, the source / drain electrodes comprise a metal such as gold, tungsten, aluminum, copper, or other suitable material. In some embodiments, the electrode layer of the memory cell capacitor comprises a metal such as gold, tungsten, aluminum, copper, or other suitable material. In some embodiments, the insulating layer of the memory cell capacitor comprises a dielectric such as silicon oxide, hafnium oxide, or other suitable dielectric material.

[0052] Figure 5 shows circuit diagrams of several embodiments of the three-dimensional DRAM device of Figure 1, further including complementary bit lines selectively connected to the first sense amplifier 124.

[0053] For example, a DRAM device includes a first complementary bit line 502 and a second complementary bit line 504. A memory cell 510 is connected to the first complementary bit line 502 and a word line 506. The memory cell 510 includes a memory cell transistor 512 and a memory cell capacitor 514. The memory cell transistor 512 selectively connects the memory cell capacitor 514 to the first complementary bit line 502. A memory cell 518 is connected to the second complementary bit line 504 and a word line 508. The memory cell 518 includes a memory cell transistor 520 and a memory cell capacitor 522. The memory cell transistor 520 selectively connects the memory cell capacitor 522 to the second complementary bit line 504.

[0054] The DRAM device further includes a first complementary bit line transistor 526 and a second complementary bit line transistor 528. The first complementary bit line transistor 526 selectively connects the first complementary bit line 502 to the second terminal 124b of the first sense amplifier 124. The second complementary bit line transistor 528 selectively connects the second complementary bit line 504 to the second terminal 124b of the first sense amplifier 124.

[0055] The first complementary bit line transistor 526 has a first terminal 526a, a second terminal 526b, and a control terminal 526c. The first terminal 526a is connected to the first complementary bit line 502. The second terminal 526b is connected to the second terminal 124b of the first sense amplifier 124. The control terminal 526c is connected to the switch line 534.

[0056] The second complementary bit line transistor 528 has a first terminal 528a, a second terminal 528b, and a control terminal 528c. The first terminal 528a is connected to the second complementary bit line 504. The second terminal 528b is connected to the second terminal 124b of the first sense amplifier 124. The control terminal 528c is connected to the switch line 536.

[0057] The word line drive circuit 538 has a first output terminal 538a connected to the word line 506 and a second output terminal 538b connected to the switch line 534. The word line drive circuit 538 drives the word line 506 and the switch line 534. The word line drive circuit 540 has a first output 540a connected to the word line 508 and a second output 540b connected to the switch line 536. The word line drive circuit 540 drives the word line 508 and the switch line 536.

[0058] When reading from and / or writing to the first memory cell 110, the first word line drive circuit 138 asserts the first switch line 134, and the word line drive circuit 538 asserts the switch line 534. In response, the first bit line transistor 126 connects the first bit line 102 to the first terminal 124a of the first sense amplifier 124, and the first complementary bit line transistor 526 connects the first complementary bit line 502 to the second terminal 124b of the first sense amplifier 124 (while the second bit line transistor 128 disconnects the second bit line from the first terminal 124a of the first sense amplifier 124, and the second complementary bit line transistor 528 disconnects the second complementary bit line 504 from the second terminal 124b of the first sense amplifier 124). Next, the first sense amplifier 124 provides precharge voltages to the first bit line 102 and the first complementary bit line 502. Next, the first word line drive circuit 138 asserts the first word line 106. In response, the first sense amplifier 124 detects (e.g., determines) a change in the precharge voltage on the first bit line 102 by comparing the voltage on the first bit line 102 with the precharge voltage on the first complementary bit line 502.

[0059] Figure 6 shows circuit diagrams of several embodiments of the three-dimensional DRAM device of Figure 1, further including a second sense amplifier 624.

[0060] The DRAM device includes additional memory cells along the first word line 106 and the second word line 108. For example, a third memory cell 610 is connected to the first word line 106 and the third bit line 602. The third memory cell 610 includes a third memory cell transistor 612 and a third memory cell capacitor 614. The third memory cell transistor 612 selectively connects the third memory cell capacitor 614 to the third bit line 602. Furthermore, a fourth memory cell 618 is connected to the second word line 108 and the fourth bit line 604. The fourth memory cell 618 includes a fourth memory cell transistor 620 and a fourth memory cell capacitor 622. The fourth memory cell transistor 620 selectively connects the fourth memory cell capacitor 622 to the fourth bit line 604.

[0061] The DRAM device includes additional memory cells along the first bit line 102 and the second bit line 104. For example, a fifth memory cell 650 is connected to the first bit line 102 and the third word line 606. The fifth memory cell 650 includes a fifth memory cell transistor 652 and a fifth memory cell capacitor 654. The fifth memory cell transistor 652 selectively connects the fifth memory cell capacitor 654 to the first bit line 102. Furthermore, a sixth memory cell 658 is connected to the second bit line 104 and the fourth word line 608. The sixth memory cell 658 includes a sixth memory cell transistor 660 and a sixth memory cell capacitor 662. The sixth memory cell transistor 660 selectively connects the sixth memory cell capacitor 662 to the second bit line 104. The third word line 606 is connected to the output terminal 138c of the first word line drive circuit 138. The fourth word line 608 is connected to the output terminal 140c of the second word line drive circuit 140.

[0062] The DRAM device includes additional memory cells along the third bit line 602 and the fourth bit line 604. For example, the seventh memory cell 670 is connected to the third bit line 602 and the third word line 606. The seventh memory cell 670 includes the seventh memory cell transistor 672 and the seventh memory cell capacitor 674. The seventh memory cell transistor 672 selectively connects the seventh memory cell capacitor 674 to the third bit line 602. Furthermore, the eighth memory cell 678 is connected to the fourth bit line 604 and the fourth word line 608. The eighth memory cell 678 includes the eighth memory cell transistor 680 and the eighth memory cell capacitor 682. The eighth memory cell transistor 680 selectively connects the eighth memory cell capacitor 682 to the fourth bit line 604.

[0063] The DRAM device includes additional sense amplifiers and bit line transistors depending on the number of bit lines. For example, the DRAM device includes a second sense amplifier 624, a third bit line transistor 626 that selectively connects a third bit line 602 to the first terminal 624a of the second sense amplifier 624, and a fourth bit line transistor 628 that selectively connects a fourth bit line 604 to the first terminal 624a of the second sense amplifier 624.

[0064] The third bit line transistor 626 has a first terminal 626a, a second terminal 626b, and a control terminal 626c. The first terminal 626a is connected to the third bit line 602. The second terminal 626b is connected to the first terminal 624a of the second sense amplifier 624. The control terminal 626c is connected to the first switch line 134. Thus, the first word line drive circuit 138 drives the control terminal 126c of the first bit line transistor 126 and the control terminal 626c of the third bit line transistor 626 via its output terminal 138b.

[0065] The fourth bit line transistor 628 has a first terminal 628a, a second terminal 628b, and a control terminal 628c. The first terminal 628a is connected to the fourth bit line 604. The second terminal 628b is connected to the first terminal 624a of the second sense amplifier 624. The control terminal 628c is connected to the second switch line 136. Thus, the second word line drive circuit 140 drives the control terminal 628c of the second bit line transistor 128 and the control terminal 628c of the fourth bit line transistor 628 via the output terminal 140b.

[0066] During reading and / or writing to the first memory cell 110, the first word line drive circuit 138 asserts the first switch line 134. In response, the first bit line transistor 126 and the third bit line transistor 626 turn on, connecting the first bit line 102 to the first terminal 124a of the first sense amplifier 124 and the third bit line 602 to the first terminal 624a of the second sense amplifier 624. During reading and / or writing to the first memory cell 110, the second switch line 136 is not asserted. Therefore, the second bit line transistor 128 and the fourth bit line transistor 628 are off, and the second bit line 104 (and parasitic capacitance 132) is isolated from the first terminal 124a of the first sense amplifier 124, and the fourth bit line 604 (and parasitic capacitance 632) is isolated from the first terminal 624a of the second sense amplifier 624.

[0067] Similarly, when reading from and / or writing to the second memory cell 118, the second word line drive circuit 140 asserts the second switch line 136. In response, the second bit line transistor 128 and the fourth bit line transistor 628 turn on, connecting the second bit line 104 to the first terminal 124a of the first sense amplifier 124 and the fourth bit line 604 to the first terminal 624a of the second sense amplifier 624. When reading from and / or writing to the second memory cell 118, the first switch line 134 is not asserted. Therefore, the first bit line transistor 126 and the third bit line transistor 626 are off, and the first bit line 102 (and parasitic capacitance 130) is isolated from the first terminal 124a of the first sense amplifier 124 and the third bit line 602 (and parasitic capacitance 630) is isolated from the first terminal 624a of the second sense amplifier 624.

[0068] In some embodiments, the first word line drive circuit 138 includes a decoder 684 (e.g., a logic circuit) and drivers 686, 688, and 690 connected to the decoder 684. For example, the input (unlabeled) of driver 686 is connected to the first output (unlabeled) of decoder 684, and the output of driver 686 is connected to the first switch line 134. The input (unlabeled) of driver 688 is connected to the second output (unlabeled) of decoder 684, and the output (unlabeled) of driver 688 is connected to the first word line 106. The input (unlabeled) of driver 690 is connected to the third output (not shown) of decoder 684, and the output (unlabeled) of driver 690 is connected to the third word line 606. Similarly, the second word line drive circuit 140 includes a decoder 692 and drivers 694, 696, and 698. Drivers 694, 696, and 698 are connected to decoder 692, second switch line 136, second word line 108, and fourth word line 608, as shown in the diagram.

[0069] In some embodiments, the first sense amplifier 124 includes a detection circuit 603, an equalization circuit, and a precharge circuit 605. For example, the first terminal (unlabeled) of the detection circuit 603 and the first terminal (unlabeled) of the equalization and precharge circuit 605 are connected to the first terminal 124a of the first sense amplifier 124. Similarly, the second sense amplifier 624 includes a detection circuit 607 and an equalize and precharge circuit 609 connected to the first terminal 624a of the second sense amplifier 624.

[0070] Figure 7 shows three-dimensional figures 700 of several embodiments of the three-dimensional DRAM device of Figure 6.

[0071] The third memory cell capacitor 614 includes a first electrode layer 702, a second electrode layer 706, and an insulating layer 704 between the first electrode layer 702 and the second electrode layer 706. Furthermore, the third memory cell transistor 612 includes a first source / drain electrode 708, a second source / drain electrode 710, a channel layer 712, a gate electrode (e.g., a first word line 106), and a gate dielectric layer 714. The first source / drain electrode 708 extends from the channel layer 712 to the third bit line 602. The second source / drain electrode 710 extends from the channel layer 712 to the first electrode layer 702 of the third memory cell capacitor 614.

[0072] Similarly, the fourth memory cell capacitor 622 includes a first electrode layer 716, a second electrode layer 720, and an insulating layer 718 between the first electrode layer 716 and the second electrode layer 720. Furthermore, the fourth memory cell transistor 620 includes a first source / drain electrode 722, a second source / drain electrode 724, a channel layer 726, a gate electrode (e.g., a second word line 108), and a gate dielectric layer 728. The first source / drain electrode 722 extends from the channel layer 726 to the fourth bit line 604. The second source / drain electrode 724 extends from the channel layer 726 to the first electrode layer 716 of the fourth memory cell capacitor 622.

[0073] The third bit-line transistor 626 includes a first source / drain electrode 730, a second source / drain electrode 732, a channel layer 734, a gate electrode (e.g., a first switch line 134), and a gate dielectric layer 736. The first source / drain electrode 730 extends from the channel layer 734 to the third bit-line 602. The second source / drain electrode 732 extends from the channel layer 734 to a conductive line 738 (connected to the second sense amplifier 624 by a conductive interconnect).

[0074] The fourth bit line transistor 628 includes a first source / drain electrode 740, a second source / drain electrode 742, a channel layer 744, a gate electrode (e.g., a second switch line 136), and a gate dielectric layer 746. The first source / drain electrode 740 extends from the channel layer 744 to the fourth bit line 604. The second source / drain electrode 742 extends from the channel layer 744 to a conductive line 748 (connected to the second sense amplifier 624 by a conductive interconnect).

[0075] Word lines (e.g., 106, 108) and switch lines (e.g., 134, 136) extend in a first direction (e.g., along axis 101y). Bit lines (e.g., 102, 104, 602, 604) extend in a second direction perpendicular to the first direction (e.g., along axis 101x).

[0076] The second bit line 104 is positioned vertically on the first bit line 102 (for example, along axis 101z) at a spacing. The fourth bit line 604 is positioned vertically on the third bit line 602 at a spacing. The third bit line 602 is positioned laterally from the first bit line 102 in the first direction (for example, along axis 101y). The fourth bit line 604 is positioned laterally from the second bit line 104 in the first direction.

[0077] The second word line 108 is positioned vertically on the first word line 106 (for example, along axis 101Z) at a distance. The second switch line 136 is positioned vertically on the first switch line 134 at a distance. The first switch line 134 is positioned laterally from the first word line 106 in the second direction (for example, along axis 101x). The second switch line 136 is positioned laterally from the second word line 108 in the second direction.

[0078] The second memory cell transistor 120 is positioned vertically on the first memory cell transistor 112 (for example, along axis 101Z). The fourth memory cell transistor 620 is positioned vertically on the third memory cell transistor 612. The third memory cell transistor 612 is positioned laterally from the first memory cell transistor 112 in a first direction (for example, along axis 101Y). The fourth memory cell transistor 620 is positioned laterally from the second memory cell transistor 120 in a first direction.

[0079] The second memory cell transistor 122 is positioned vertically on the first memory cell capacitor 114 (for example, along axis 101Z). The fourth memory cell capacitor 622 is positioned vertically on the third memory cell transistor 614. The third memory cell capacitor 614 is positioned laterally from the first memory cell capacitor 114 in the first direction (for example, along axis 101y). The fourth memory cell capacitor 622 is positioned laterally from the second memory cell capacitor 122 in the first direction.

[0080] The second bit-line transistor 128 is positioned vertically above the first bit-line transistor 126 (for example, along axis 101z). The fourth bit-line transistor 628 is positioned vertically above the third bit-line transistor 626. The third bit-line transistor 626 is positioned laterally above the first bit-line transistor 126 in the first direction (for example, along axis 101y). The fourth bit-line transistor 628 is positioned laterally above the second bit-line transistor 128 in the first direction.

[0081] Figures 8 to 12 show cross-sectional views 800 to 1200 of various embodiments of the integrated chip shown in Figure 4.

[0082] In some embodiments (for example, as shown in Figure 8), the memory cell capacitor is a planar metal-insulator-metal (MIM) capacitor. For example, the second electrode layer 446, the insulator layer 444, and the first electrode layer 442 of the first memory cell capacitor 114 are each substantially planar. The second electrode layer 446 is located on top of the insulator layer 444, and the insulator layer 444 is located on top of the first electrode layer 442.

[0083] In some embodiments (for example, as shown in Figure 9), the memory cell capacitor is a cylindrical capacitor or a trench capacitor. For example, the first electrode layer 442 of the first memory cell capacitor 114 has a lower portion and a side portion extending upward from the lower portion. An insulating layer 444 covers the top surface and side walls of the first electrode layer 442. A second electrode layer 446 covers the side walls and top surface of the insulating layer 444. The first electrode layer 442 laterally surrounds the insulating layer 444, and the insulating layer 444 laterally surrounds the second electrode layer 446.

[0084] In some embodiments (for example, as shown in Figure 10), the memory cell capacitor is a pillar-type capacitor. For example, the first electrode layer 442 of the first memory cell capacitor 114 has a lower portion and a pillar portion extending upward from the lower portion. The second electrode layer 446 has an upper portion and a pillar portion extending downward from the upper portion. The pillar portions of the first electrode layer 442 and the second electrode layer 446 intersect each other. An insulating layer 444 extends between the first electrode layer 442 and the second electrode layer 446.

[0085] In some embodiments (for example, as shown in Figure 8), the memory cell transistors and bit line transistors are bottom-gate transistors. For example, the gate dielectric layer 424 of the first memory cell transistor 112 is located on the gate electrode 422 (e.g., the first word line 106) of the first memory cell transistor 112. The channel layer 426 is located on the gate dielectric layer 424. The source / drain electrodes (e.g., 428, 430) are located on the channel layer 426. Similarly, the gate dielectric layer 434 of the first bit line transistor 126 is located on the gate electrode 432 (e.g., the first switch line 134) of the first bit line transistor 126. The channel layer 436 is located on the gate dielectric layer 434. The source / drain electrodes 438, 440 are located on the channel layer 436. In some such embodiments, the bit line is located on the corresponding memory cell transistor and bit line transistor.

[0086] In some embodiments (for example, as shown in Figure 11), the memory cell transistors and bit line transistors are top-gate transistors. For example, the gate dielectric layer 424 of the first memory cell transistor 112 is located above the channel layer 426 of the first memory cell transistor 112. The gate electrode 422 (e.g., the first word line 106) is located above the gate dielectric layer 424. The source / drain electrodes 428, 430 are located above the channel layer 426 and opposite the gate electrode 422. Similarly, the gate dielectric layer 434 of the first bit line transistor 126 is located above the channel layer 436 of the first bit line transistor 126. The gate electrode 432 (e.g., the first switch line 134) is located above the gate dielectric layer 434. The source / drain electrodes 438, 440 are located above the channel layer 436 and opposite the gate electrode 432.

[0087] In some embodiments (for example, as shown in Figure 12), the memory cell transistors and bit line transistors are vertical channel transistors (e.g., gate-all-around transistors). For example, the gate dielectric layer 424 of the first memory cell transistor 112 laterally surrounds the channel layer 426 of the first memory cell transistor 112. The gate electrode 422 (e.g., the first word line 106) laterally surrounds the gate dielectric layer 424. The first source / drain electrode 428 is located below the channel layer 426, and the second source / drain electrode 430 is located above the channel layer 426. Similarly, the gate dielectric layer 434 of the first bit line transistor 126 laterally surrounds the channel layer 436 of the first bit line transistor 126. The gate electrode 432 (e.g., the first switch line 134) laterally surrounds the gate dielectric layer 434. The first source / drain electrode 438 is located below the channel layer 436, and the second source / drain electrode 440 is located above the channel layer 436. In some such embodiments, the bit line is located below the corresponding memory cell transistor and bit line transistor.

[0088] Figure 13 shows circuit diagrams 1300 of several embodiments of the first sense amplifier 124.

[0089] The first sense amplifier 124 includes a detection circuit 603 and an equalize precharge circuit 605. The detection circuit 603 includes a first transistor 1302, a second transistor 1304, a third transistor 1306, a fourth transistor 1308, a fifth transistor 1310, and a sixth transistor 1312, connected as shown in the figure. The terminal (unlabeled) of the first transistor 1302 is connected to the first power supply voltage terminal 1314 (e.g., VDD). The control terminal (unlabeled) of the first transistor 1302 is connected to the input terminal 124c of the first sense amplifier 124. The control terminal of the sixth transistor 1312 is connected to the input terminal 124d of the first sense amplifier 124.

[0090] The equalize precharge circuit 605 includes a first transistor 1316, a second transistor 1318, and a third transistor 1320, connected as shown in the figure. The terminals of transistor 1316 and transistor 1318 are connected to a second power supply voltage terminal 1322 (e.g., VDD / 2). In some embodiments, the voltage supplied to the second power supply voltage terminal 1322 is half the voltage supplied to the first power supply voltage terminal 1314. The control terminals of transistor 1316, transistor 1318, and transistor 1320 are connected to the input terminal 124e of the first sense amplifier 124.

[0091] In some embodiments, transistors 1302, 1304, and 1306 are of type 1 (e.g., N-channel metal-oxide-semiconductor field-effect transistors, MOSFETs), and transistors 1308, 1310, and 1312 are of type 2 (e.g., P-channel MOSFETs). In some embodiments, transistors 1316, 1318, and 1320 are of type 1.

[0092] Figures 14–20 show cross-sectional views 1400–2000 of several embodiments of a method for forming an integrated chip including a three-dimensional DRAM device with bit-line transistors that selectively connect bit lines to sense amplifiers. Although Figures 14–20 are described in relation to the method, it should be understood that the structures disclosed in Figures 14–20 are not limited to such a method and may exist independently as structures separate from the method.

[0093] As shown in the cross-sectional view 1400 of Figure 14, the sense amplifier (e.g., sense amplifier 124) and the word line drive circuit (e.g., word line drive circuit 138) are formed along the semiconductor substrate 402. For example, the transistor 404 is formed along the semiconductor substrate 402. Furthermore, conductive interconnects (e.g., interconnects 412, 414) are formed on the semiconductor substrate 402 and within the dielectric layers 410-1, 410-2 of the dielectric structure 410.

[0094] As shown in the cross-sectional view 1500 of Figure 15, dielectric layers 410-3 and 410-4 of the dielectric structure 410 are formed on a semiconductor substrate 402. Conductive interconnects (e.g., wiring 418, 420) are formed within dielectric layer 410-3. Dielectric layer 410-4 is etched to form word line openings 1502 and switch line openings 1504. In some embodiments, a mask layer 1506 is formed on dielectric layer 410-4 and etched based on the mask layer 1506. In some embodiments, etching includes a dry etching process such as a plasma etching process, a reactive ion etching process, an ion beam etching process, or other suitable process. In some embodiments, the mask layer 1506 includes a photoresist, a hard mask material, or other suitable material.

[0095] In some embodiments, the switch line opening 1504 is substantially identical to the word line opening 1502. Therefore, no additional process steps or additional masks are required to form the switch line opening 1504. Consequently, the formation of the switch line opening 1504 does not substantially increase the cost of forming the integrated chip.

[0096] As shown in the cross-sectional view 1600 of Figure 16, word lines (e.g., word lines 106, 606) are formed in the word line opening 1502, and a switch line (e.g., first switch line 134) is formed in the switch line opening 1504. Conductive material (e.g., copper, tungsten, aluminum, or other suitable material) is deposited in the openings by, for example, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or other suitable process. Furthermore, a planarization process (e.g., a chemical mechanical planarization process, a planar etching process, or other suitable process) is performed on the conductive material to further define the word lines and switch lines.

[0097] In some embodiments, the switch wires are formed from the same material as the word wires. Therefore, no additional process steps or materials are required to form the switch wires. Consequently, the formation of the switch wires does not substantially increase the cost of forming the integrated chip.

[0098] As shown in the cross-sectional view 1700 of Figure 17, the gate dielectric material layer 1702 is deposited on the word lines (e.g., word lines 106, 606) and switch lines (e.g., switch line 134), as well as on the dielectric layer 410-4. Furthermore, the channel material layer 1704 is deposited on top of the gate dielectric material layer 1702. In some embodiments, the gate dielectric material layer 1702 comprises silicon oxide, hafnium oxide, or other suitable material and is deposited by a CVD process, a PVD process, and an ALD process, or other suitable process. In some embodiments, the channel material layer 1704 comprises silicon or other suitable semiconductor material and is deposited by an epitaxial growth process, a CVD process, a PVD process, and an ALD process, or other suitable process.

[0099] As shown in the cross-sectional view 1800 of Figure 18, the channel material layer 1704 and the gate dielectric material layer 1702 are etched to form individual channel layers (e.g., channel layers 426, 436) and individual gate dielectric layers (e.g., gate dielectric layers 424, 434). In some embodiments, a mask layer 1802 is formed on the channel material layer 1704 and etched based on the mask layer 1802. In some embodiments, the etching includes a dry etching process or other suitable process. In some embodiments, the mask layer 1802 includes a photoresist, a hard mask material, or other suitable material.

[0100] In some embodiments, the size and shape of the channel layer and gate dielectric layer of a switch-line transistor are substantially the same as those of a memory cell transistor. Therefore, no additional process steps or additional masks are required to form the channel layer and gate dielectric layer of a switch-line transistor. Furthermore, since the channel layer and gate dielectric layer of a switch-line transistor are formed from the same material as the channel layer and gate dielectric layer of a memory cell transistor, no additional process steps or additional materials are required to form a switch-line transistor. Thus, the formation of the channel layer and gate dielectric layer of a switch-line transistor does not substantially increase the cost of forming an integrated chip.

[0101] As shown in the cross-sectional view 1900 of Figure 19, the dielectric layers 410-5, 410-6, and 410-7 of the dielectric structure 410 are formed on the channel layer, the source / drain electrodes (e.g., source / drain electrodes 428, 430, 438, 440) are formed on the channel layer, the bit line (e.g., first bit line 102) is formed on the source / drain electrodes, and the memory cell capacitor (e.g., memory cell capacitors 114, 654) is formed on the memory cell transistors (e.g., memory cell transistors 112, 652). For example, the source / drain electrode 428 is formed on the channel layer 426, and the source / drain electrode 438 is formed on the channel layer 436. Furthermore, the first bit line 102 is formed on the source / drain electrodes 428 and 438. Furthermore, the source / drain electrode 430 is formed on the channel layer 426, and the first memory cell capacitor 114 is formed on the source / drain electrode 430.

[0102] As shown in the cross-sectional view 2000 of Figure 20, additional word lines (e.g., word lines 108, 608), bit lines (e.g., second bit line 104), memory cell transistors (e.g., memory cell transistors 120, 660), memory cell capacitors (e.g., memory cell capacitors 122, 662), switch lines (e.g., second switch line 136), bit line transistors (e.g., second bit line transistor 128), and the like are formed on the semiconductor substrate 402 and within the dielectric structure 410.

[0103] Therefore, the present invention relates to a three-dimensional dynamic random access memory (DRAM) device that includes a bit-line transistor for selectively connecting bit lines to a sense amplifier.

[0104] Accordingly, in some embodiments, the present invention relates to a circuit comprising a first bit line, a second bit line, a first word line, a second word line, a first memory cell, a second memory cell, a first sense amplifier, a first bit line transistor, and a second bit line transistor. The first memory cell is connected to the first bit line and the first word line. The second memory cell is connected to the second bit line and the second word line. The first sense amplifier has a first terminal. The first bit line transistor selectively connects the first bit line to the first terminal of the first sense amplifier. The second bit line transistor selectively connects the second bit line to the first terminal of the first sense amplifier.

[0105] In other embodiments, the present invention relates to an integrated chip comprising a semiconductor substrate, a first sense amplifier, a first bit line, a second bit line, a first word line, a second word line, a first memory cell, a second memory cell, a first bit line transistor, and a second bit line transistor. The first sense amplifier is arranged along the semiconductor substrate. A first conductive interconnect is connected to the first sense amplifier. The first bit lines are spaced apart on the semiconductor substrate. The second bit lines are spaced apart on the first bit lines. The first word lines are spaced apart on the semiconductor substrate. The second word lines are spaced apart on the first word lines. The first memory cells are spaced apart on the semiconductor substrate and connected to the first bit line and the first word line. The second memory cells are spaced apart on the first memory cells and connected to the second bit line and the second word line. The first bit line transistor is spaced apart on the semiconductor substrate and spaced laterally from the first memory cell. The first bit line transistor includes a first source / drain electrode connected to the first bit line and a second source / drain electrode connected to the first conductive interconnect. The second bit-line transistor is spaced above the first bit-line transistor and spaced laterally from the second memory cell. The second bit-line transistor includes a first source / drain electrode connected to the second bit line and a second source / drain electrode connected to the first conductive interconnect.

[0106] In yet another embodiment, the present invention relates to a method comprising providing a first switch line voltage to the control terminal of a first bit line transistor to cause the first bit line transistor to connect the first bit line to the first terminal of a first sense amplifier. A first memory cell is connected to a first bit line and a first word line. The method comprises providing a second switch line voltage to the control terminal of a second bit line transistor to cause the second bit line transistor to disconnect the second bit line from the first terminal of the first sense amplifier. A second memory cell is connected to a second bit line and a second word line. The method comprises providing a precharge voltage to the first bit line in response to providing a first switch line voltage to the control terminal of the first bit line transistor and providing a second switch line voltage to the control terminal of the second bit line transistor. The method comprises providing a first word line voltage to the first word line in response to providing a precharge voltage to the first bit line to assert the first word line. The method comprises determining a change from the precharge voltage on the first bit line in response to asserting the first word line. This method includes determining the value stored in the first memory cell based on the change from the precharge voltage on the first bit line.

[0107] The above outlines some features of embodiments so that those skilled in the art may better understand aspects of the present invention. Those skilled in the art should understand that the present invention can be readily used as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent configurations do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present invention. [Industrial applicability]

[0108] The present invention relates to a circuit, an integrated chip, and a method for operating the integrated chip, and more specifically to a three-dimensional DRAM device including a bit-line transistor that selectively connects bit lines to a sense amplifier. [Explanation of Symbols]

[0109] 100, 500, 600, 1300: Circuit diagram 101x, 101y, 101z: axis 102: 1st bit line 104: 2nd bit line 106: First Word Line 108: Second Word Line 110: First cell 112: First memory cell transistor 112a, 114a, 120a, 122a, 124a, 126a, 128a, 526a, 528a, 624a, 626a, 628a: First terminal 112b, 114b, 120b, 122b, 124b, 126b, 128b, 526b, 528b, 626b, 628b: Second terminal 112c, 120c, 126c, 128c, 526c, 528c, 626c, 628c: Control terminals 114: First memory cell capacitor 116: Reference voltage terminal 118: Second memory cell 120: Second memory cell transistor 122: Second memory cell capacitor 124: First Sense Amplifier 124c, 124d, 124e: Input terminals 126: 1st bit line transistor 128: Second bit-line transistor 130, 132, 630, 632: Parasitic capacitance 134: First switch wire 136: Second switch wire 138: First word line drive circuit 138a, 140a, 538a: First output terminal 138b, 140b, 538b: Second output terminals 138c, 140c: Output terminals 140: Second word line drive circuit 200: Timing Diagram 300: Flowchart 302, 304, 306, 308, 310, 312, 314, 316, 318, 320: Block 400, 800, 900, 1000, 1100, 1200, 1400, 1500, 1600, 1700, 1800, 1900, 2000: Cross-sectional view 402: Semiconductor substrate 404: Transistor 406: Source / Drain 408: Gate 410: Dielectric structure 410-1, 410-2, 410-3, 410-4, 410-5, 410-6, 410-7: Dielectric layer 412, 414, 416, 418, 420, 447, 448, 450, 452: Conductive interconnections 421, 453, 738, 748: Conductive wires 422, 432, 454, 464: Gates 424, 434, 456, 466, 714, 728, 736, 746: Gate dielectric layer 426, 436, 458, 468, 712, 726, 734, 744: Channel layer 428, 438, 460, 470, 708, 722, 730, 740: First source / drain electrodes 430, 440, 462, 472, 710, 724, 732, 742: Second source / drain electrodes 442, 474, 702, 716: First electrode layer 444, 476, 704, 718: Insulating layer 446, 478, 706, 720: Second electrode layer 502: First complementary bit line 504: Second complementary bit line 506, 508: Word lines 510, 518: Memory cells 512, 520: Memory cell transistors 514, 522: Memory cell capacitors 526: First complementary bit-line transistor 528: Second-phase complementary bit-line transistor 534, 536: Switch wires 538, 540: Word line drive circuit 540a: First output 540b: Second output 602: Third bit line 603, 607: Detection circuit 604: 4th bit line 605, 609: Equalize / Precharge Circuit 606: Third Word Line 608: Fourth Word Line 610: Third memory cell 612: Third memory cell transistor 614: Third memory cell capacitor 618: 4th memory cell 620: Fourth memory cell transistor 622: Fourth memory cell capacitor 624: Second Sense Amplifier 626: Third bit line transistor 628: 4th bit line transistor 650: Fifth memory cell 652: Fifth memory cell transistor 654: Fifth memory cell capacitor 658: 6th memory cell 660: Sixth memory cell transistor 662: 6th memory cell capacitor 670: 7th memory cell 672: 7th memory cell transistor 674: 7th Memory Cell Capacitor 678: 8th Memory Cell 680: 8th memory cell transistor 682: 8th memory cell capacitor 684, 692: Decoder 686, 688, 690, 694, 696, 698: Drivers 700: 3D diagram 1302, 1316: First transistor 1304, 1318: Second transistor 1306, 1320: Third transistor 1308: 4th transistor 1310: Fifth transistor 1312: 6th transistor 1314: First power supply voltage terminal 1322: Second power supply voltage terminal 1502: Word line opening 1504: Switch wire opening 1506, 1802: Mask layer 1702: Gate dielectric material layer 1704: Channel material layer T1: 1st time T2: Second time T3: 3rd time T4: 4th time T5: 5th time T6: 6th time VB0: Second write voltage VB1: First write voltage VP: Precharge Voltage VS0: Second switch line voltage VS1: First switch line voltage VW0: Second word line voltage VW1: First word line voltage VΔ1: First changing voltage VΔ2: Second changing voltage

Claims

1. The first bit line and the second bit line, The first word line and the second word line, A first memory cell connected to the first bit line and the first word line, A second memory cell connected to the second bit line and the second word line, A first sense amplifier having a first terminal, A first bit line transistor that selectively connects the first bit line to the first terminal of the first sense amplifier, A second bit line transistor selectively connects the second bit line to the first terminal of the first sense amplifier, A circuit that includes this.

2. The third bit line and the fourth bit line, A third memory cell connected to the third bit line and the first word line, A fourth memory cell connected to the fourth bit line and the second word line, A second sense amplifier having a first terminal, A third bit line transistor that selectively connects the third bit line to the first terminal of the second sense amplifier, A fourth bit line transistor selectively connects the fourth bit line to the first terminal of the second sense amplifier, The circuit according to claim 1, further comprising:

3. The control terminal of the first bit line transistor and the first switch line connected to the control terminal of the third bit line transistor, The control terminal of the second bit line transistor and the second switch line connected to the control terminal of the fourth bit line transistor, The circuit according to claim 2, further comprising:

4. A first word line drive circuit having a first output terminal connected to the first word line and a second output terminal connected to the first switch line, A second word line drive circuit having a first output terminal connected to the second word line and a second output terminal connected to the second switch line, The circuit according to claim 3, further comprising:

5. The first terminal of the first bit line transistor is connected to the first bit line, and the second terminal of the first bit line transistor is connected to the first terminal of the first sense amplifier. The first terminal of the second bit line transistor is connected to the second bit line, and the second terminal of the second bit line transistor is connected to the first terminal of the first sense amplifier. The first terminal of the third bit line transistor is connected to the third bit line, and the second terminal of the third bit line transistor is connected to the first terminal of the second sense amplifier. The first terminal of the fourth bit line transistor is connected to the fourth bit line, and the second terminal of the fourth bit line transistor is connected to the first terminal of the second sense amplifier. The circuit according to claim 3.

6. The first complementary bit line and the second complementary bit line, The third word line and the fourth word line, A third memory cell connected to the first complementary bit line and the third word line, A fourth memory cell connected to the second complementary bit line and the fourth word line, A third bit line transistor selectively connects the first complementary bit line to the second terminal of the first sense amplifier, A fourth bit line transistor selectively connects the second complementary bit line to the second terminal of the first sense amplifier, The circuit according to claim 1, further comprising:

7. The first memory cell includes a first memory cell transistor and a first memory cell capacitor, the first memory cell transistor having a first terminal connected to the first bit line, a second terminal connected to the first terminal of the first memory cell capacitor, and a control terminal connected to the first word line. The first bit line transistor has a first terminal connected to the first bit line, a second terminal connected to the first terminal of the first sense amplifier, and a control terminal connected to the first switch line. The circuit according to claim 1.

8. The third word line and the fourth word line, A third memory cell connected to the first bit line and the third word line, A fourth memory cell connected to the second bit line and the fourth word line, The circuit according to claim 1, further comprising:

9. Semiconductor substrate and A first sense amplifier is arranged along the semiconductor substrate, and a first conductive interconnect is connected to the first sense amplifier, A first bit line is arranged at intervals on the semiconductor substrate, A second bit line is placed at intervals on the first bit line, A first word line is arranged at intervals on the semiconductor substrate, A second word line is placed at intervals along the first word line, A first memory cell is arranged at intervals on the semiconductor substrate and connected to the first bit line and the first word line, A second memory cell is arranged at intervals on the first memory cell and connected to the second bit line and the second word line, A first bit line transistor is arranged at intervals on the semiconductor substrate and at intervals laterally from the first memory cell, and the first bit line transistor includes a first source / drain electrode connected to the first bit line and a second source / drain electrode connected to the first conductive interconnect, A second bit line transistor, spaced apart on the first bit line transistor and spaced laterally from the second memory cell, comprising a first source / drain electrode connected to the second bit line and a second source / drain electrode connected to the first conductive interconnect, An integrated chip, including

10. A second sense amplifier arranged along the semiconductor substrate, wherein a second conductive interconnection is connected to the second sense amplifier, A third bit line is arranged at intervals on the semiconductor substrate and is spaced laterally from the first bit line, A fourth bit line is placed at intervals on the third bit line, A third memory cell is arranged at intervals on the semiconductor substrate and is spaced laterally from the first memory cell, and is connected to the third bit line and the first word line, A fourth memory cell is arranged at intervals on the third memory cell and connected to the fourth bit line and the second word line, A third bit line transistor, which is spaced apart on the semiconductor substrate and spaced laterally apart from the third memory cell and the first bit line transistor, comprising a first source / drain electrode connected to the third bit line and a second source / drain electrode connected to the second conductive interconnect, A fourth bit-line transistor, spaced apart on the third bit-line transistor and spaced laterally apart from the fourth memory cell and the second bit-line transistor, comprising a first source / drain electrode connected to the fourth bit line and a second source / drain electrode connected to the second conductive interconnect, The integrated chip according to claim 9, further comprising:

11. A first switch line forming the gate electrode of the first bit line transistor and the gate electrode of the third bit line transistor, wherein the first switch line is arranged at intervals on the semiconductor substrate and is arranged at intervals laterally from the first word line, A second switch line forming the gate electrode of the second bit line transistor and the gate electrode of the fourth bit line transistor, wherein the first switch line is spaced apart on the first switch line and spaced apart laterally from the second word line, The integrated chip according to claim 10, further comprising:

12. The first word line and the second word line extend in a first direction, the first bit line and the second bit line extend in a second direction perpendicular to the first direction, and the first switch line and the second switch line extend in the first direction. The integrated chip according to claim 11.

13. A first word line drive circuit arranged along the semiconductor substrate, the first word line drive circuit being connected to the first word line by a plurality of first conductive interconnects on the semiconductor substrate and connected to the first switch line by a plurality of second conductive interconnects on the semiconductor substrate, A second word line drive circuit arranged along the semiconductor substrate, the second word line drive circuit being connected to the second word line by a plurality of third conductive interconnects on the semiconductor substrate and connected to the first switch line by a plurality of fourth conductive interconnects on the semiconductor substrate, The integrated chip according to claim 11, further comprising:

14. The first memory cell includes a first memory cell transistor and a first memory cell capacitor. The first memory cell capacitor includes a first electrode layer, a second electrode layer, and an insulating layer between the first electrode layer and the second electrode layer. The first memory cell transistor includes a first gate electrode connected to the first word line, a first channel layer spaced apart from the first gate electrode, a first source / drain electrode extending from the first channel layer to the first bit line, and a second source / drain electrode extending from the first channel layer to the first electrode layer of the first memory cell capacitor. The first bit-line transistor further includes a second gate electrode connected to a first switch line, and a second channel layer spaced apart from the second gate electrode, wherein the first source / drain electrodes of the first bit-line transistor extend from the second channel layer to the first bit line, and the second source / drain electrodes of the first bit-line transistor extend from the second channel layer to the first conductive interconnect. The integrated chip according to claim 9.

15. The first word line forms the first gate electrode, and the first switch line forms the second gate electrode. The integrated chip according to claim 14.

16. Multiple conductive interconnects extend from the first conductive interconnect to the first terminal of the first sense amplifier, and the first conductive interconnect is connected to the first terminal of the first sense amplifier. The integrated chip according to claim 9.

17. The first bit line is connected to the first bit line and the first word line, and the first memory cell is connected to the first bit line and the first word line, and the connection is made by providing a first switch line voltage to the control terminal of the first bit line transistor, and the first bit line is connected to the first bit line and the first word line, The second bit line is separated from the first terminal of the first sense amplifier by providing a second switch line voltage to the control terminal of the second bit line transistor, wherein the second memory cell is connected to the second bit line and the second word line, and the separation is performed as follows: In response to providing the first switch line voltage to the control terminal of the first bit line transistor and the second switch line voltage to the control terminal of the second bit line transistor, a precharge voltage is provided to the first bit line. In response to providing the precharge voltage to the first bit line, the first word line voltage is provided to the first word line to assert the first word line, In response to asserting the first word line, the change from the precharge voltage on the first bit line is determined, Based on the change from the precharge voltage on the first bit line, the value stored in the first memory cell is determined, Methods that include...

18. In response to determining the value stored in the first memory cell, a write voltage for writing to the first memory cell is provided to the first bit line, In response to writing to the first memory cell, a second word line voltage is provided to the first word line in order to deassert the first word line. In response to deasserting the first word line, the precharge voltage is provided to the bit line, In response to deasserting the first word line, in response to providing the precharge voltage to the first bit line, the second switch line voltage is provided to the control terminal of the first bit line transistor so as to cause the first bit line transistor to isolate the first bit line from the first terminal of the first sense amplifier, The method according to claim 17, further comprising:

19. The first switch line voltage is supplied to the control terminal of the third bit line transistor, causing the third bit line to connect to the first terminal of the second sense amplifier, wherein the third memory cell is connected to the third bit line and the first word line, and the connection is made as follows: The second switch line voltage is supplied to the control terminal of the fourth bit line transistor to isolate the fourth bit line from the first terminal of the second sense amplifier, wherein the fourth memory cell is connected to the fourth bit line and the second word line, and the isolation is performed as follows: In response to providing the first switch line voltage to the control terminal of the third bit line transistor and the second switch line voltage to the control terminal of the fourth bit line transistor, the precharge voltage is provided to the third bit line. The method according to claim 17, further comprising:

20. The first switch line voltage is provided to the control terminal of the first complementary bit line transistor, causing the first complementary bit line to connect to the second terminal of the first sense amplifier. The second switch line voltage is provided to the control terminal of the second complementary bit line transistor, thereby isolating the second complementary bit line from the second terminal of the first sense amplifier. In response to providing the first switch line voltage to the control terminal of the first complementary bit line transistor and the second switch line voltage to the control terminal of the second complementary bit line transistor, the precharge voltage is provided to the first complementary bit line. The change from the precharge voltage on the first bit line is determined by comparing the voltage on the first bit line with the precharge voltage on the first complementary bit line in response to asserting the first word line. The method according to claim 17, further comprising:

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