Semiconductor equipment

Abstract

The objective is to provide a semiconductor device in which the delay or distortion of the signal output to the gate signal line during the selection period is reduced. [Solution] The semiconductor device includes a gate signal line, a first gate driver circuit and a second gate driver circuit that output a selection signal and a deselection signal to the gate signal line, and a plurality of pixels electrically connected to the gate signal line and to which the selection signal and deselection signal are input. During the period when the gate signal line is selected, both the first gate driver circuit and the second gate driver circuit output a selection signal to the gate signal line, and during the period when the gate signal line is not selected... In this configuration, one of the first gate driver circuit and the second gate driver circuit outputs a non-selection signal to the gate signal line, while the other of the first gate driver circuit and the second gate driver circuit does not output a selection signal or a non-selection signal to the gate signal line.

Description

Technical Field

[0001] The technical field relates to a semiconductor device having a gate driver circuit.

Background Art

[0002] A display device driven by an active matrix method includes a pixel portion having a plurality of pixels provided with elements (such as transistors) that function as switches, and a driver circuit including a source driver circuit and a gate driver circuit. The source driver circuit outputs a video signal to the pixels provided with the elements when the elements that function as switches are on. The gate driver circuit controls the switching of the elements that function as switches. The gate driver circuit is provided close to the pixel portion. When the gate driver circuit is provided close to one side of the pixel portion, the area occupied by the pixel portion may be biased to one side of the display device. Therefore, a display device having a configuration in which the gate driver circuit is divided into left and right sides of the pixel portion has been proposed. As an example, the configuration of the display device disclosed in Patent Document 1 is shown in FIG. 58. In the display device shown in FIG. 58, a first gate driver circuit 5108 and a second gate driver circuit 5110 are arranged symmetrically on the left and right peripheral regions of the display area. The first gate driver circuit 5108 is arranged in the left peripheral region of the display area. The first gate driver circuit 5108 has a plurality of shift registers (SRC1, SRC3, etc.) each of whose output terminals is connected to odd-numbered gate lines (GL1, GL3, up to GL ).

[0003]

[0004]

[0005] n+1 The second gate driver circuit 5110 is arranged in the right peripheral region of the display area. The second gate driver circuit 5110 has a plurality of shift registers (SRC2, SRC4, etc.) each of whose output terminals is connected to even-numbered gate lines (GL2, GL4, up to GL

[0005] n+1 n+1 ). n+1 ) is composed of the second gate driver circuit 5110, which is the indicated area It is located in the peripheral region on the right side of the domain. The second gate driver circuit 5110 is even-numbered Gate line (GL2, GL4, ..., GL n Each output terminal is connected to the other terminal. Number shift register (SRC2, SRC4, ..., SRC n ) is composed of.

[0006] The first gate driver circuit 5108 controls the images arranged in odd-numbered rows of the pixel section 5102. The electrical connection between the element and the source driver circuit 5112 is controlled, and the second gate driver circuit 5110 controls the pixels arranged in even-numbered rows of the pixel section 5102 and the source driver circuit 51 Twelve electrical connections are controlled. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2003-076346 [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] As shown in the display device described with reference to Figure 58, the gate driver circuit is divided into left and right sides of the pixel section. In a display device with a divided configuration, the gate line (also called the "gate signal line") is selected. During the period (also called the "selection period"), the first gate driver circuit and the second gate A signal is output to the gate line from one side of the driver circuit. Also, the gate line is not selected. During the period (also called the "non-selection period"), the first gate driver circuit and the second gate driver No signal is output to the gate line from either side of the driver circuit.

[0009] In one aspect of the present invention, the delay or rawness of the signal output to the gate signal line during the selected period The objective is to provide a semiconductor device with reduced noise.

[0010] Alternatively, in one aspect of the present invention, a first gate driver circuit and a second gate driver circuit The objective is to provide a semiconductor device in which the degradation of transistors in the circuit is suppressed.

[0011] Alternatively, in one aspect of the present invention, the rise time or fall time of the potential of the gate signal line The objective is to provide a semiconductor device with a short gap between components. [Means for solving the problem]

[0012] One aspect of the present invention provides a gate signal line and outputs a selection signal and a deselection signal to the gate signal line. The first gate driver circuit and the second gate driver circuit, and the gate signal line and electrical A semiconductor device having multiple pixels connected to which a selection signal and a deselection signal are input. And during the period when the gate signal line is selected, the first gate driver circuit and the second Both gate driver circuits output a selection signal to the gate signal line, and the gate signal line is selected. During the period when it is not possible, one of the first gate driver circuit and the second gate driver circuit , outputs a non-selection signal to the gate signal line, and the first gate driver circuit and the second gate driver The other side of the IBA circuit does not output a selection signal or a deselection signal to the gate signal line.

[0013] Furthermore, the first gate driver circuit and the second gate driver circuit have multiple pixels. They may be arranged with the pixel portion in between.

[0014] Furthermore, the semiconductor device outputs a video signal to the pixel corresponding to the gate signal line on which the selection signal is output. It may have a source driver circuit for writing data. [Effects of the Invention]

[0015] One aspect of the present invention relates to the delay or distortion of the signal output to the gate signal line during the selected period. This allows us to provide a semiconductor device with reduced noise.

[0016] Alternatively, one aspect of the present invention comprises a first gate driver circuit and a second gate driver circuit. This makes it possible to provide a semiconductor device in which the degradation of transistors is suppressed.

[0017] Alternatively, in one aspect of the present invention, the rise time or fall time of the potential of the gate signal line. This can provide a short semiconductor device. [Brief explanation of the drawing]

[0018] [Figure 1] A diagram showing an example of the configuration of a semiconductor device, and a timing chart showing an example of the operation of a semiconductor device. [Figure 2] A diagram illustrating an example of semiconductor device operation. [Figure 3] A diagram illustrating an example of semiconductor device operation. [Figure 4] A diagram illustrating an example of the configuration and operation of a gate driver circuit. [Figure 5] A schematic diagram illustrating an example of each operation performed by a gate driver circuit. [Figure 6] A timing chart showing an example of gate driver circuit operation. [Figure 7] A timing chart showing an example of gate driver circuit operation. [Figure 8] A timing chart showing an example of gate driver circuit operation. [Figure 9]A diagram illustrating an example of the configuration and operation of a gate driver circuit. [Figure 10] A diagram illustrating an example of the configuration and operation of a gate driver circuit. [Figure 11] A diagram illustrating an example of a gate driver circuit configuration. [Figure 12] A diagram illustrating an example of gate driver circuit operation. [Figure 13] A diagram illustrating an example of gate driver circuit operation. [Figure 14] A diagram illustrating an example of the configuration and operation of a gate driver circuit. [Figure 15] A diagram illustrating an example of gate driver circuit operation. [Figure 16] A diagram showing an example of a circuit diagram for a semiconductor device. [Figure 17] A timing chart illustrating an example of the operation of a semiconductor device. [Figure 18] A diagram illustrating an example of semiconductor device operation. [Figure 19] A diagram illustrating an example of semiconductor device operation. [Figure 20] A diagram illustrating an example of semiconductor device operation. [Figure 21] A diagram illustrating an example of semiconductor device operation. [Figure 22] A timing chart illustrating an example of the operation of a semiconductor device. [Figure 23] A timing chart illustrating an example of the operation of a semiconductor device. [Figure 24] A diagram showing an example of a circuit diagram for a semiconductor device. [Figure 25] A diagram showing an example of a circuit diagram for a semiconductor device. [Figure 26] A diagram showing an example of a circuit diagram for a semiconductor device. [Figure 27] A timing chart illustrating an example of the operation of a semiconductor device. [Figure 28] A diagram illustrating an example of semiconductor device operation. [Figure 29]A diagram illustrating an example of semiconductor device operation. [Figure 30] A timing chart illustrating an example of the operation of a semiconductor device. [Figure 31] A diagram showing an example of a circuit diagram for a semiconductor device. [Figure 32] A diagram illustrating an example of semiconductor device operation. [Figure 33] A diagram illustrating an example of semiconductor device operation. [Figure 34] A diagram illustrating an example of semiconductor device operation. [Figure 35] A diagram illustrating an example of semiconductor device operation. [Figure 36] A diagram showing an example of a circuit diagram for a semiconductor device. [Figure 37] A diagram showing an example of a circuit diagram for a semiconductor device. [Figure 38] A diagram showing an example of a circuit diagram for a semiconductor device. [Figure 39] A diagram showing an example of a circuit diagram for a semiconductor device. [Figure 40] A diagram showing an example of a circuit diagram for a semiconductor device. [Figure 41] A diagram showing an example of a circuit diagram for a semiconductor device. [Figure 42] A diagram illustrating an example of semiconductor device operation. [Figure 43] A diagram illustrating an example of semiconductor device operation. [Figure 44] A diagram illustrating an example of semiconductor device operation. [Figure 45] A diagram illustrating an example of semiconductor device operation. [Figure 46] A diagram showing an example of the configuration of a display device and an example of the configuration of pixels. [Figure 47] A diagram showing an example of a shift register circuit diagram. [Figure 48] A diagram showing an example of a shift register circuit diagram. [Figure 49] A timing chart illustrating an example of shift register operation. [Figure 50]A diagram showing an example of the source driver circuit configuration, and a timing chart showing an example of the source driver circuit operation. [Figure 51] A diagram showing an example of a protection circuit diagram. [Figure 52] A diagram showing an example of the configuration of a semiconductor device equipped with a protection circuit. [Figure 53] A diagram showing an example of the structure of a display device and an example of the structure of a transistor. [Figure 54] A diagram showing an example of a display device configuration. [Figure 55] A diagram showing the layout of a semiconductor device. [Figure 56] A diagram illustrating an example of an electronic device. [Figure 57] A diagram illustrating an example of electrical equipment and an application example of semiconductor equipment. [Figure 58] A diagram showing the configuration of a display device. [Figure 59] This figure shows the circuit diagram of a comparative example semiconductor device. [Figure 60] A diagram showing the calculation results from circuit simulation. [Figure 61] A diagram showing the calculation results from circuit simulation. [Modes for carrying out the invention]

[0019] An example of an embodiment illustrating the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description and will not depart from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that its form and details can be changed in various ways. Therefore, the present invention shall not be construed as being limited to the embodiments described below. This shall apply. Furthermore, when referring to drawings, the symbols used to indicate the same thing across different drawings shall be used. There are cases where the same number is used in common. Also, when referring to the same thing across different drawings... The same hatch pattern may be used, and sometimes no sign is assigned.

[0020] Furthermore, the contents of each embodiment can be combined with each other as appropriate. The content of the states can be replaced with each other as appropriate.

[0021] Furthermore, the term "the kth" (where k is a natural number) used herein is used to avoid confusion of constituent elements. This was added to avoid the issue of a numerical limitation.

[0022] Generally speaking, the difference in electric potential between two points (also called potential difference) is called voltage. However, In electronic circuits, a circuit diagram or similar shows a reference potential (also called the reference potential) to the potential at a specific point. The potential difference between . and ) is sometimes used. Also, both voltage and potential are expressed in units of volts. V) may be used. Therefore, in this specification, unless otherwise specified, a single point In some cases, the potential difference between the potential and the reference potential is used as the voltage at that specific point.

[0023] In this specification, a transistor has at least three terminals (source, drain, The configuration includes a gate and a terminal, and the conductivity between the other two terminals is controlled by the potential of one terminal. It has. Also, depending on the structure and operating conditions of the transistor, the source and the drive of the transistor Rain and Rain may switch places.

[0024] Furthermore, "source" refers to part or all of the source electrode, or part or of the source wiring. It refers to everything. Also, it does not distinguish between the source electrode and the source wiring. A conductive layer that has both the function of a source and a drain is sometimes called a source. This refers to part or all of the drain electrode, or part or all of the drain wiring. Furthermore, without distinguishing between the drain electrode and the drain wiring, both the drain electrode and the drain wiring are treated as such. A conductive layer that has the function of a gate is sometimes called a drain. Also, a gate is the gate of a gate electrode. This refers to part or all of the gate wiring, or part or all of the gate wiring. A conductive layer that has the function of both a gate electrode and gate wiring, without distinguishing between poles and gate wiring. This is sometimes referred to as a gate.

[0025] In this specification, "A and B are connected" means that A and B are not directly connected. In addition to those that are already connected, this also includes those that are electrically connected. Specifically, A and B are connected via an element that functions as a switch, such as an inverter, and the switch and When an element that functions in this way is in a conductive state, A and B are at approximately the same potential, or resistive element A and B are connected via a child, and the potential difference generated across the resistor includes A and B. In cases where it does not affect the predetermined operation of the circuit, etc., when explaining the operation of the circuit, A When the part between A and B can be considered to be the same node, then A and B It is said that they are connected.

[0026] In this specification, "approximately" means that errors due to noise and process variations may occur. This includes various errors such as manufacturing errors, errors due to variations in the element manufacturing process, or measurement errors. Let's assume that.

[0027] In this specification, the potential of an L-level signal (also referred to as an "L signal") is defined as V1. Let V2 (V2 > V1) be the potential of a high-level signal (also called a "high signal"). When referring to "potential of L signal," "potential of L level," or "voltage V1," these are used. Assuming the potential is approximately V1, we refer to this as "the potential of the H signal," "the potential of the H level," or "voltage V When "2" is written, these potentials are assumed to be approximately V2.

[0028] (Embodiment 1) In this embodiment, a semiconductor having a gate driver circuit (also called "gate driver") The conductive device will be explained with reference to Figures 1(A) to 3(C).

[0029] Figure 1(A) shows an example of the configuration of a semiconductor device having a gate driver circuit. 1(B) is a timing chart showing an example of the operation of a semiconductor device. In addition to gate driver circuits, source driver circuits (also called "source drivers") are also used. .) It may also have a control circuit, etc.

[0030] In Figure 1(A), the semiconductor device comprises a pixel section 50 and a first gate driver circuit 51. , second gate driver circuit 52, first gate driver circuit 51 and second gate driver It has a gate line 54 (also called a "gate signal line") connected to the driver circuit 52. In 1(A), the semiconductor device has multiple gate lines G1 to gate line G m (where m is a natural number) Among them, gate line G i ~Gate Line G i+2 (i represents one of the values ​​from 1 to m-2) .

[0031] If gate line 54 is selected, gate driver circuit 51 and gate driver circuit 52 From there, an H signal is input to gate line 54. In this way, the gate driver circuit 51 and the gate When an H signal is input from both sides of the gate driver circuit 52, the potential of the gate line 54 is adjusted. The rise time or fall time can be shortened, and the output to the gate line 54 can be shortened. This can reduce the delay or distortion of the signal being transmitted.

[0032] On the other hand, if gate line 54 is not selected, the gate driver circuit 51 and gate driver An L signal is output to gate line 54 from one side of circuit 52, and a signal is output to gate line 54 from the other side. No output is produced. Therefore, a part of the transistor in the other gate driver circuit or It can turn everything off.

[0033] Furthermore, an example of the operation of the semiconductor device shown in Figure 1(A) will be explained below. Figure 2(A Figure 2(C) shows the half-frame at frame k, and Figures 3(A) to 3(C) show the half-frame at frame k+1. An example of the operation of a conductive device is shown.

[0034] In Figures 2(A) to 3(C), the arrows indicate the gate driver circuit (first gate). The driver circuit 51 or the second gate driver circuit 52 outputs a signal to the gate line 54. This means that the gate driver circuit does not output a signal to gate line 54. It tastes good.

[0035] Here, the direction of the arrow depends on the type of signal that the gate driver circuit outputs to the gate line 54. Use the appropriate method. The gate driver circuit sends a signal (for example, a non-selection signal) to the gate line 54. When outputting, the arrow should point from gate line 54 towards the gate driver circuit. On the other hand, the gate driver circuit sends a signal to the gate line 54 that is different from the above signal (for example, the non-selection signal). When outputting a signal (for example, a selection signal), the direction of the arrow should be from the gate driver circuit to the gate. This will direct you towards line 54.

[0036] As shown in Fig. 2(A), at the k-th frame, gate line G i is selected, and when gate line G i+1 and gate line G i+2 are not selected (corresponding to the period k_ i in Fig. 1(B)), an H signal is output from gate driver circuit 51 and gate driver circuit 52 to gate line G i . Also, signals are not output from gate driver circuit 51 to gate line G i+1 and gate line G i+2 , and signals are not output from gate driver circuit 52 to gate line G i+1 i+2 . Therefore, part or all of the transistors in gate driver circuit 52 can be turned off.

[0037] Next, as shown in Fig. 3(A), at the (k + 1)-th frame, when gate line G i is selected , and gate line G i+1 and gate line G i+2 are not selected (corresponding to the period k + 1 _ i in Fig. 1(B)), an H signal is output from gate driver circuit 51 and gate driver circuit 52 to gate line G i . Also, signals are not output from gate driver circuit 51 to gate line G

[0038] i+1 and gate line G i+2 , and an L signal is output from gate driver circuit 52 to gate line G i+1 and gate line G i+2 . Therefore, part or all of the transistors in gate driver circuit 51 can be turned off. <00​​​​​​Gate line G i and gate line G i+2 If this is not selected, the gate driver circuit 51 and From the gate driver circuit 52 to the gate line G i+1 An H signal is output. Also, gated From driver circuit 51 to gate wire G i and gate line G i+2 An L signal is output to the gate drive. From circuit 52 to gate wire G i and gate line G i+2 No signal is output to it. Therefore, Some or all of the transistors in the driver circuit 52 can be turned off.

[0039] Next, as shown in Figure 3(B), in the k+1 frame, gate line G i+1 is selected And, gate line G i and gate line G i+2 If not selected, gate driver circuit 51 and gate wire G from gate driver circuit 52 i+1 An H signal is output to the gate. From driver circuit 51 to gate wire G i and gate line G i+2 No signal is output to the gated From driver circuit 52 to gate wire G i and gate line G i+2 An L signal is output. Therefore, The gate driver circuit 51 can turn off some or all of its transistors. .

[0040] Similarly, as shown in Figure 2(C), in the k-th frame, gate line G i+2 Selected Gate line G i and gate line G i+1 If this is not selected, the gate driver circuit 51 and From the gate driver circuit 52 to the gate line G i+2 An H signal is output. Also, gated From driver circuit 51 to gate wire G i and gate line G i+1 An L signal is output to the gate drive. From circuit 52 to gate wire G i and gate line G i+1 No signal is output to it. Therefore, Some or all of the transistors in the driver circuit 52 can be turned off.

[0041] Next, as shown in Figure 3(C), in the k+1 frame, gate line G i+2 is selected And, gate line G i and gate line G i+1 If not selected, gate driver circuit 51 and gate wire G from gate driver circuit 52 i+2 An H signal is output to the gate. From driver circuit 51 to gate wire G i and gate line G i+1 No signal is output to the gated From driver circuit 52 to gate wire G i and gate line G i+1 An L signal is output. Therefore, The gate driver circuit 51 can turn off some or all of its transistors. .

[0042] In this way, the gate driver circuit 51 and the gate are connected to the gate line 54 that is not selected. Since no signal is output from one side of the driver circuit 52, the gate driver circuit on that side... Some or all of the transistors in the transistor can be turned off. It can suppress the deterioration of the studs.

[0043] (Embodiment 2) This embodiment describes the configuration and operation of the gate driver circuit.

[0044] <Gate driver circuit configuration> The configuration of the gate driver circuit will be explained with reference to Figure 4(A).

[0045] Figure 4(A) shows an example of the configuration of a gate driver circuit. The gate driver circuit is a circuit It has circuit 10A and circuit 10B. Note that in Figure 4(A), the gate driver circuit is circuit 1 The diagram shows the case where there are two circuits, 0A and circuit 10B, but the gate driver circuit is It may have three or more circuits, including path 10A and circuit 10B.

[0046] Circuit 10A is connected to wiring 11, and circuit 10B is connected to wiring 11.

[0047] A signal is input to wiring 11 from circuit 10A or circuit 10B, and wiring 11 is a signal line. It has the function of [this function]. Furthermore, a signal is sent to wiring 11 from a circuit separate from circuits 10A and 10B. It may be entered.

[0048] Furthermore, when the gate driver circuit shown in Figure 4(A) is used in a display device having a pixel section, Line 11 is arranged extending to the pixel area, and the transistors of the pixels constituting the pixel area (for example, S It is connected to the gate of a switching transistor (selection transistor, etc.). In this case, the wiring Line 11 has the function of a gate line (also called a "gate signal line"), a scan line, or a power line. do.

[0049] Alternatively, a constant voltage is supplied to wiring 11 from circuit 10A or circuit 10B, and wiring 11 It functions as a power line. Note that it is supplied from a circuit separate from circuits 10A and 10B. A voltage may be applied to line 11.

[0050] Next, we will explain the functions of circuits 10A and 10B.

[0051] Circuit 10A outputs a signal (for example, a selection signal or a deselection signal) to wiring 11 at the appropriate time. It has a function to control the signal. Alternatively, circuit 10A does not output a signal to wiring 11. It has a function to control the ming. Alternatively, circuit 10A has a signal to wiring 11 for a certain period of time. It outputs a signal (e.g., a non-selection signal), and at another time, it outputs a different signal (e.g., a selection signal) to wiring 11. It has the function of outputting a signal (number). Alternatively, circuit 10A has the function of outputting a signal to wiring 11 during a certain period of time. Outputs (for example, a selection signal or a deselection signal), and outputs a signal to wiring 11 at another time. It has a function that does not work.

[0052] Thus, circuit 10A has the function of a drive circuit or a control circuit. Circuit 10A may output another signal to wiring 11. In this case, circuit 10A is distributed Line 11 can output three or more types of signals.

[0053] Circuit 10B outputs a signal (for example, a selection signal or a deselection signal) to wiring 11 at the appropriate time. It has a function to control the timing. Alternatively, circuit 10B does not output a signal to wiring 11. It has a function to control the signal. Alternatively, circuit 10B transmits a signal to wiring 11 for a certain period of time. It outputs a signal (e.g., a non-selection signal), and at another time, it outputs a different signal (e.g., a selection signal) to wiring 11. It has the function of outputting a signal (number). Alternatively, circuit 10B outputs a signal to wiring 11 during a certain period of time. Outputs (for example, a selection signal or a deselection signal), and outputs a signal to wiring 11 at another time. It has a function that does not work.

[0054] Thus, circuit 10B has the function of a drive circuit or a control circuit. The path 10B may output another signal to the wiring 11. In this case, the circuit 10B will output a different signal to the wiring 11. Line 11 can output three or more types of signals.

[0055] <Operation of the gate driver circuit> Regarding the operation of the gate driver circuit in Figure 4(A), see Figures 4(B) and 5(A) to 5( See I) for further explanation.

[0056] Figure 4(B) shows an example of the operation of a gate driver circuit. In Figure 4(B), the gate driver... In each operation performed by the IBA circuit, the output signal OUTA of circuit 10A and the output signal of circuit 10B This indicates OUTB. Figures 5(A) to 5(I) show the gate driver circuit of Figure 4(A). This is a schematic diagram corresponding to an example of each action performed by [the system / function].

[0057] Note that in the gate driver circuit shown in Figure 4(A), circuits 10A and 10B are each distributed When a signal (for example, a non-selection signal) is output to line 11, and the same for circuits 10A and 10B. When that outputs a signal other than the signal in question (for example, a selection signal) to wiring 11, the circuit Circuits 10A and 10B each send signals (e.g., a non-selection signal and a selection signal) to wiring 11. By combining the cases where no output is produced with the appropriate combinations, the nine operations shown in Figure 4(B) can be performed. It is possible to do so.

[0058] In this embodiment, the nine operations described above will be explained. Note that the gate driver in Figure 4(A) The IBA circuit does not need to perform all nine operations; it can choose to perform some of the nine operations. This is possible. Furthermore, the gate driver circuit in Figure 4(A) performs operations other than these nine operations. That's fine.

[0059] In Figure 4(B), "○" indicates that the circuit (circuit 10A or circuit 10B) is connected to wiring 11 This means that a signal (for example, a non-selection signal) is output to wire 11. "◎" indicates that the circuit is connected to wire 11. This means that a signal other than the one in question (for example, a selection signal) is output. "×" indicates a circuit. This means that no signals (e.g., a non-selection signal and a selection signal) are output to wiring 11.

[0060] Note that in the schematic diagrams of Figures 5(A) to 5(I), the arrows indicate the circuit (circuit 10A or circuit 10B) means that a signal is output to wire 11, and the × mark means that the circuit does not output a signal to wire 11. This means that it does not exert force. Here, depending on the type of signal that the circuit outputs to wiring 11, the arrow Use the correct orientation. When the circuit outputs a signal (for example, a non-selection signal) to wiring 11 The direction of the arrow is defined as the direction from wiring 11 to the circuit. On the other hand, the circuit receives the above signal from wiring 11 ( For example, if you want to output a signal other than the non-selection signal (for example, a selection signal), the direction of the arrow... This is the direction from the circuit to the wiring 11.

[0061] In the schematic diagrams of Figures 5(A) to 5(I), the direction of the arrows indicates the direction and current of the current. This does not indicate that a signal will occur, but rather that a signal will be sent from the circuit (circuit 10A or circuit 10B) to the wiring 11. This means that a signal is output. The direction of the current is determined by the potential of wiring 11. Furthermore, if the potential of the signal output from the circuit is approximately equal to the potential of the wiring 11, a current is generated. The current may not flow or may become very weak.

[0062] An example of the operation of the gate driver circuit shown in Figure 4(A) is described below.

[0063] In operation 1 of Figure 5(A), circuit 10A outputs a signal (for example, a non-selection signal) to wiring 11. Circuit 10B outputs a signal (e.g., a non-selection signal) to wiring 11. Operation shown in Figure 5(B). In step 2, circuit 10A outputs a signal (for example, a non-selection signal) to wiring 11, and circuit 10B outputs No signal is output to wire 11. In operation 3 of Figure 5(C), circuit 10A outputs a signal to wire 11. Without any intervention, circuit 10B outputs a signal (for example, a non-selection signal) to wiring 11. Figure 5(D) In operation 4, circuit 10A does not output a signal to wire 11, and circuit 10B outputs a signal to wire 11. I don't have the strength.

[0064] In operation 5 of Figure 5(E), circuit 10A outputs another signal (for example, a selection signal) to wiring 11. Then, circuit 10B outputs another signal (for example, a selection signal) to wiring 11. Figure 5(F) In operation 6, circuit 10A outputs another signal (for example, a selection signal) to wiring 11, and circuit 10 B does not output a signal to wiring 11. In operation 7 of Figure 5(G), circuit 10A outputs a signal to wiring 11. Without outputting the signal, circuit 10B outputs another signal (for example, a selection signal) to wiring 11. Figure 5 In operation 8 of (H), circuit 10A outputs a signal (e.g., a non-selection signal) to wiring 11, and Path 10B outputs another signal (for example, a selection signal) to wiring 11. Operation 9 in Figure 5(I) Circuit 10A outputs another signal (for example, a selection signal) to wiring 11, and circuit 10B outputs a different signal to wiring 11. Output a signal (for example, a non-selection signal) to 11.

[0065] As described above, the gate driver circuit in Figure 4(A) can perform a variety of operations. Next, we will explain the advantages of each operation.

[0066] In operations 1 and 5, circuits 10A and 10B output the same signal to wiring 11. This allows the potential of wiring 11 to be set to a stable value with less noise. For example, Signals that should not be written to pixels connected to wiring 11 (for example, to pixels in another row) The input video signal can be prevented from being written. Alternatively, wiring 11 and This prevents the potential of the video signal held by the connected pixels from changing. As a result, the display quality of the display device can be improved.

[0067] Furthermore, in operations 1 and 5, circuits 10A and 10B output the same signal to wiring 11. By applying force, the change in potential of the wiring 11 is made steeper (for example, shortening the rise time). This allows for (or shortening the fall time). Therefore, the potential rolloff of the wiring 11 is This can be reduced. For example, data that should not be written to a pixel connected to wiring 11 This prevents unwanted signals (for example, video signals input to the pixels of the previous row) from being written. This can be achieved. As a result, crosstalk can be reduced, thus improving the display quality of the display device. Improvement can be achieved.

[0068] In operations 8 and 9, circuits 10A and 10B send separate signals to wiring 11 (for example) By outputting a selection signal and a deselection signal, the potential of the wiring 11 is controlled, and the circuit 10A outputs The potential can be set to a level between the potential of the signal being applied and the potential of the signal output by circuit 10B. Therefore, the potential of the wiring 11 can be controlled with high precision.

[0069] In operations 2, 3, 6, and 7, from one of circuits 10A and 10B By outputting a signal to wiring 11, the other side of circuit 10A and circuit 10B will not output a signal. Therefore, the transistors in the circuit that do not output the signal can be turned off. This can suppress the degradation of the transistor in question.

[0070] In operation 4, since no signals are output from circuits 10A and 10B to wiring 11, The transistors in path 10A and circuit 10B can be turned off. This can suppress the degradation of the transistor.

[0071] As described above, in operations 2, 3, 4, 6, and 7, the transistor's inferiority Because it can suppress deformation, amorphous semiconductors or Materials that are prone to degradation, such as non-single-crystal semiconductors like microcrystalline semiconductors, organic semiconductors, or oxide semiconductors. Materials can be used. Therefore, when manufacturing semiconductor devices, the number of processes can be reduced and the yield can be increased. It is possible to increase efficiency or reduce costs. Also, the method of manufacturing semiconductor devices is simplified. Therefore, the display device can be made larger.

[0072] Furthermore, in operations 2, 3, 4, 6, and 7, transistor degradation is suppressed. Therefore, to account for transistor degradation, the transistor channel width is increased. There is no need to reduce it. Therefore, the channel width of the transistor can be reduced. This allows for a reduction in layout area. In particular, the gate driver circuit of this embodiment When used in a display device, the layout area of ​​the gate driver circuit can be reduced. Therefore, the pixel resolution can be increased.

[0073] Furthermore, as described above, in operations 2, 3, 4, 6, and 7, the transition This allows for a reduction in the channel width, thereby reducing the load on the gate driver circuit. This is possible. Therefore, the circuit that supplies signals etc. to the gate driver circuit of this embodiment ( For example, the current supply capacity of the external circuit can be reduced. As a result, the signal etc. To reduce the scale of the supply circuit, or to use as a circuit that supplies such signals, etc. This reduces the number of IC chips required. It also reduces the load on the gate driver circuit. This allows for a reduction in the power consumption of the gate driver circuit.

[0074] Next, the operation of the gate driver circuit in Figure 4(A) is shown in Figures 5(A) to 5(I). Regarding the timing chart when some of actions 1 through 9 are combined: I will explain this below.

[0075] Here, the timing chart showing the operation of the gate driver circuit in Figure 4(A) is multiple It has a period. In each period, or in the period of transition from one period to another, Figure 4(A The gate driver circuit of ) performs one of operations 1 to 9 shown in Figures 5(A) to 5(I). This can be done. Furthermore, the gate driver circuit in Figure 4(A) is shown in Figures 5(A) to 5(I). You may perform actions other than those indicated by actions 1 through 9.

[0076] Figures 6(A) to 6(L) show a timing chart illustrating an example of gate driver circuit operation. In the timing charts of Figures 6(A) to 6(L), periods a, b and c It has and in order, and also has a period d. Note that in Figures 6(A) to 6(L), period a Although periods a, a, and d are arranged in this order, the order in which periods a, a, and d are arranged is not limited to this. Furthermore, the timing chart may include periods other than periods a to d.

[0077] Furthermore, in the timing charts of Figures 6(A) to 6(L), the solid line represents the circuit (Circuit 10 This means that A or circuit 10B) is outputting a signal to wiring 11, and the dotted line indicates that the circuit is connected to wiring 1 This means that no signal is being output to 1.

[0078] Refer to the timing chart shown in Figure 6(A), and transition from period a to period b. Figure 4 shows the period during which, period b, the transition period from period b to period c, period c, and period d. The operation of the gate driver circuit (A) will be explained.

[0079] In period a, the transition period from period b to period c, period c, and period d, see Figure 4(A) The gate driver circuit performs operation 2 in Figure 5(B). That is, from period a, period b to period c During the transition period, period c, and period d, circuit 10A sends a signal to wiring 11 (for example, Circuit 10B outputs a non-selected signal and does not output a signal to wiring 11.

[0080] During the transition period from period a to period b, and during period b, the gate driver shown in Figure 4(A) The circuit performs operation 6 in Figure 5(F). That is, the period of transition from period a to period b, and the period In b, circuit 10A outputs another signal (for example, a selection signal) to wiring 11, and circuit 10 B does not output a signal to wiring 11.

[0081] Thus, period a, the transition period from period a to period b, period b, and from period b to period c During the transition period, period c, and period d, circuit 10B does not output a signal to wiring 11. Therefore, the degradation of the transistors in circuit 10B can be suppressed. Also, In circuit 10B, a switch is provided to prevent the output of a signal, or a transistor is provided. By simply changing the circuit design, such as turning it off, the power consumption of circuit 10B can be reduced. .

[0082] In the timing chart shown in Figure 6(A), the transition from period a to period b occurs during period a. Of the period during which the action is performed, period b, the period transitioning from period b to period c, period c, and period d, a smaller number At the very least, circuit 10A does not need to output a signal to wiring 11.

[0083] Furthermore, as shown in Figure 6(B), circuit 10B is in the period when transitioning from period a to period b. Furthermore, another signal (for example, a selection signal) may be output to wiring 11. This allows wiring 1 The change in potential of 1 can be made steeper.

[0084] Furthermore, as shown in Figure 6(C), circuit 10B sends a signal to wiring 11 during period a (e.g., For example, it outputs a non-selection signal, and during the transition from period a to period b, separate wiring 11 It may also output a signal (for example, a selection signal). This will cause a rapid change in the potential of wiring 11. It can be made sharp.

[0085] Furthermore, as shown in Figure 6(D), circuit 10B is used during the transition period from period a to period b, and During period b, another signal (for example, a selection signal) may be output to wiring 11. This allows for a steeper change in the potential of the wiring 11.

[0086] Furthermore, as shown in Figure 6(E), circuit 10B sends a signal to wiring 11 during period a (e.g., For example, outputting a non-selection signal, during the transition period from period a to period b, and during period b, Another signal (for example, a selection signal) may be output to wiring 11. This will allow the power of wiring 11 to be controlled. It is possible to make the change in position steeper.

[0087] Furthermore, as shown in Figure 6(F), circuit 10B operates during the transition period from period b to period c. And a signal (for example, a non-selection signal) may be output to wiring 11. This allows for a steeper change in potential.

[0088] Furthermore, as shown in Figure 6(G), circuit 10B operates during the transition period from period b to period c. Then, a signal (for example, a non-selection signal) is output to wiring 11, and during period b, a separate signal is output to wiring 11. It may also output a signal (for example, a selection signal). This will cause a rapid change in the potential of wiring 11. It can be made sharp.

[0089] Furthermore, as shown in Figure 6(H), the circuit 10B is used during the transition period from period b to period c, and During period c, a signal (for example, a non-selection signal) may be output to wiring 11. This allows for a steeper change in the potential of the wiring 11.

[0090] Furthermore, as shown in Figure 6(I), the circuit 10B is used during the transition period from period b to period c, and During period c, a signal (e.g., a non-selection signal) is output to wiring 11, and during period b, Another signal (for example, a selection signal) may be output to wiring 11. This will allow the power of wiring 11 to be controlled. It is possible to make the change in position steeper.

[0091] Furthermore, as shown in Figure 6(J), circuit 10B is in the period when transitioning from period a to period b. Then, another signal (for example, a selection signal) is output to wiring 11, and the system transitions from period b to period c. During this period, a signal (for example, a non-selection signal) may be output to wiring 11. This will allow, The potential change in wiring 11 can be made steeper.

[0092] Furthermore, as shown in Figure 6(K), circuit 10B transitions from period a and period b to period c. During this period, a signal (for example, a non-selection signal) is output to wiring 11, from period a to period b During the transition period and during period b, output another signal (e.g., a selection signal) to wiring 11. This is also possible. This makes the change in potential of wiring 11 steeper.

[0093] Furthermore, as shown in Figure 6(L), circuit 10B transitions from period a and period b to period c. During period a and period c, a signal (e.g., a non-selection signal) is output to wiring 11, and during period a During the transition period from period b to period b, and during period b, another signal (for example, a selection signal) is sent to wiring 11. ) may be output. This makes the change in potential of wiring 11 steeper.

[0094] In the above explanation, the selection signal and the deselection signal are provided by circuits 10A and 10B. This is just one example of an output signal; it's fine as long as the signals are different from each other.

[0095] Next, the operation of the gate driver circuit in Figure 4(A) is shown in Figures 5(A) to 5(I). Figures 6(A) to 6(L) show the case where some of actions 1 to 9 are combined. The following describes different timing charts.

[0096] Figures 7(A) to 7(L) show a timing chart illustrating an example of gate driver circuit operation. It is.

[0097] Refer to the timing chart shown in Figure 7(A), and transition from period a to period b. Figure 4 shows the period during which, period b, the transition period from period b to period c, period c, and period d. The operation of the gate driver circuit (A) will be explained.

[0098] In period a, the transition period from period b to period c, period c, and period d, see Figure 4(A) The gate driver circuit performs operation 3 in Figure 5(C). That is, from period a, period b to period c During the transition period, period c, and period d, circuit 10A does not output a signal to wiring 11. Circuit 10B outputs a signal (for example, a non-selection signal) to wiring 11.

[0099] During the transition period from period a to period b, and during period b, the gate driver shown in Figure 4(A) The circuit performs operation 7 in Figure 5(G). That is, the period of transition from period a to period b, and the period In (b), circuit 10A does not output a signal to wiring 11, and circuit 10B outputs a different signal to wiring 11. It outputs (for example, a selection signal).

[0100] Thus, period a, the transition period from period a to period b, period b, and from period b to period c During the transition period, period c, and period d, circuit 10A does not output a signal to wiring 11. Therefore, the degradation of the transistor in circuit 10A can be suppressed. Also, In circuit 10A, a switch is provided to prevent the output of a signal, or a transistor is provided. By simply changing the circuit design, such as turning it off, the power consumption of the 10A circuit can be reduced. .

[0101] In the timing chart shown in Figure 7(A), the transition from period a to period b occurs during period a. Of the period during which the action is performed, period b, the period transitioning from period b to period c, period c, and period d, a smaller number At the very least, circuit 10B does not need to output a signal to wiring 11.

[0102] Furthermore, as shown in Figure 7(B), circuit 10A operates during the transition period from period a to period b. Furthermore, another signal (for example, a selection signal) may be output to wiring 11. This allows wiring 1 The change in potential of 1 can be made steeper.

[0103] Furthermore, as shown in Figure 7(C), circuit 10A sends a signal to wiring 11 during period a (e.g., For example, it outputs a non-selection signal, and during the transition from period a to period b, separate wiring 11 It may also output a signal (for example, a selection signal). This will cause a rapid change in the potential of wiring 11. It can be made sharp.

[0104] Furthermore, as shown in Figure 7(D), circuit 10A is used during the transition period from period a to period b, and During period b, another signal (for example, a selection signal) may be output to wiring 11. This allows for a steeper change in the potential of the wiring 11.

[0105] Furthermore, as shown in Figure 7(E), circuit 10A sends a signal to wiring 11 during period a (e.g., For example, outputting a non-selection signal, during the transition period from period a to period b, and during period b, Another signal (for example, a selection signal) may be output to wiring 11. This will allow the power of wiring 11 to be controlled. It is possible to make the change in position steeper.

[0106] Furthermore, as shown in Figure 7(F), circuit 10A is in the period when transitioning from period b to period c. And a signal (for example, a non-selection signal) may be output to wiring 11. This allows for a steeper change in potential.

[0107] Furthermore, as shown in Figure 7(G), circuit 10A is in the period when transitioning from period b to period c. Then, a signal (for example, a non-selection signal) is output to wiring 11, and during period b, a separate signal is output to wiring 11. It may output a signal (e.g., a selection signal). Thereby, the change in the potential of the wiring 11 can be made steep. Steep.

[0108] Also, as shown in FIG. 7(H), the circuit 10A may output a signal (e.g., a non-selection signal) to the wiring 11 during the period of transition from period b to period c and during period c. Thereby, the change in the potential of the wiring 11 can be made steep. Thereby, the change in the potential of the wiring 11 can be made steep. [[ID=, href="https: / / www.google.com / search?q=10]]Thereby, the change in the potential of the wiring 11 can be made steep.

[0109] Also, as shown in FIG. 7(I), the circuit 10A outputs a signal (e.g., a non-selection signal) to the wiring 11 during the period of transition from period b to period c and during period c, and may output another signal (e.g., a selection signal) to the wiring 11 during period b. Thereby, the change in the potential of the wiring 11 can be made steep. Also, as shown in FIG. 7(I), the circuit 10A outputs a signal (e.g., a non-selection signal) to the wiring 11 during the period of transition from period b to period c and during period c, and may output another signal (e.g., a selection signal) to the wiring 11 during period b. Thereby, the change in the potential of the wiring 11 can be made steep. Also, as shown in FIG. 7(I), the circuit 10A outputs a signal (e.g., a non-selection signal) to the wiring 11 during the period of transition from period b to period c and during period c, and may output another signal (e.g., a selection signal) to the wiring 11 during period b. Thereby, the change in the potential of the wiring 11 can be made steep. Thereby, the change in the potential of the wiring 11 can be made steep.

[0110] Also, as shown in FIG. 7(J), the circuit 10A outputs another signal (e.g., a selection signal) to the wiring during the period of transition from period a to period b, and may output a signal (e.g., a non-selection signal) to the wiring 11 during the period of transition from period b to period c. Thereby, the change in the potential of the wiring 11 can be made steep. Also, as shown in FIG. 7(J), the circuit 10A outputs another signal (e.g., a selection signal) to the wiring during the period of transition from period a to period b, and may output a signal (e.g., a non-selection signal) to the wiring 11 during the period of transition from period b to period c. Thereby, the change in the potential of the wiring 11 can be made steep. Also, as shown in FIG. 7(J), the circuit 10A outputs another signal (e.g., a selection signal) to the wiring during the period of transition from period a to period b, and may output a signal (e.g., a non-selection signal) to the wiring 11 during the period of transition from period b to period c. Thereby, the change in the potential of the wiring 11 can be made steep. Thereby, the change in the potential of the wiring can be made steep.

[0111] Also, as shown in FIG. 7(K), the circuit 10A outputs a signal (e.g., a non-selection signal) to the wiring 11 during period a and during the period of transition from period b to period c, and may output another signal (e.g., a selection signal) to the wiring 11 during the period of transition from period a to period b and during period b. Thereby, the change in the potential of the wiring 11 can be made steep. Also, as shown in FIG. 7(K), the circuit 10A outputs a signal (e.g., a non-selection signal) to the wiring 11 during period a and during the period of transition from period b to period c, and may output another signal (e.g., a selection signal) to the wiring 11 during the period of transition from period a to period b and during period b. Thereby, the change in the potential of the wiring 11 can be made steep. Also, as shown in FIG. 7(K), the circuit 10A outputs a signal (e.g., a non-selection signal) to the wiring 11 during period a and during the period of transition from period b to period c, and may output another signal (e.g., a selection signal) to the wiring 11 during the period of transition from period a to period b and during period b. Thereby, the change in the potential of the wiring 11 can be made steep. Thereby, the change in the potential of the wiring 11 can be made steep.

[0112] [[ID=, href="https: / / www.google.com / search?q=43]] Also, as shown in FIG. 7(L), the circuit 10A during period a and during the period of transition from period b to period c During period a and period c, a signal (e.g., a non-selection signal) is output to wiring 11, and during period a During the transition period from period b to period b, and during period b, another signal (for example, a selection signal) is sent to wiring 11. ) may be output. This makes the change in potential of wiring 11 steeper.

[0113] In the above explanation, the selection signal and the deselection signal are provided by circuits 10A and 10B. This is just one example of an output signal; it's fine as long as the signals are different from each other.

[0114] Next, the operation of the gate driver circuit in Figure 4(A) is shown in Figures 5(A) to 5(I). Figures 6(A) to 6(L) and when some of the actions from 1 to 9 are combined, The following describes timing charts that differ from those in Figures 7(A) to 7(L).

[0115] Figures 8(A) to 8(E) show a timing chart illustrating an example of gate driver circuit operation. It is.

[0116] The timing charts in Figures 8(A) to 8(C) have periods T1 and T2. Furthermore, in Figures 8(A) and 8(C), periods T1 and T2 are arranged alternately, As shown in Figure 8(B), even if multiple periods T1 and multiple periods T2 are arranged alternately, That's fine. It may also include periods other than periods T1 and T2.

[0117] Referring to the timing chart in Figure 8(A), in period T1 and period T2, Figure 4(A The operation of the gate driver circuit of ) will be explained.

[0118] In period T1, the timing chart shown in Figure 6(A) is used. Therefore, period T In case 1, the degradation of the transistor in circuit 10B can be suppressed. Also, during period T In section 2, the timing chart shown in Figure 7(A) is used. Therefore, in period T2, This can suppress the degradation of the transistor in circuit 10A.

[0119] Thus, in Figure 8(A), the degradation of the transistor in circuit 10B is suppressed. The period T1 during which this can be done, and the period during which the degradation of the transistors in circuit 10A can be suppressed. The spaces T2 and other elements are arranged alternately.

[0120] Here, if circuit 10A and circuit 10B have similar configurations, then period T1 and period T2 and By making the lengths approximately equal, the transistors in circuit 10A and circuit 10B are This makes the degree of degradation of the transistors roughly equal. By alternating between 1 and period T2, the operation of circuit 10A and circuit 10B is switched. However, this allows the change in potential across wiring 11 to be roughly equal.

[0121] Therefore, the gate driver circuit in Figure 4(A) has pixels that hold the video signal. When used in a display device, the video signal changes depending on the potential of the wiring 11 (for example, feed Even if the operation of circuit 10A and circuit 10B switches (through, capacitive coupling, etc.), the wiring 11 remains connected. The changes in the video signal held by successive pixels can be made approximately equal. Therefore, pixels Since the brightness or transmittance can be made approximately equal, the display quality can be improved. Cut.

[0122] Furthermore, during period T1, one of the timing charts shown in Figures 6(A) to 6(L) will be used. Alternatively, in period T2, any of the timing charts shown in FIGS. 7(A) to 7(L) may be used. For example, as shown in FIG. 8(C), in period T1, the timing chart of FIG. 6(K) may be used, and in period T2, the timing chart of FIG. 7(K) may be used.

[0123] Next, an example of the operation of the gate driver circuit of FIG. 4(A) in the period d shown in FIGS. 6(A) to 6(L), FIGS. 7(A) to 7(L), FIG. 8(A), and FIG. 8(C ) will be described with reference to FIG. 8(D). FIG. 8(D) is a timing chart showing an example of the operation of the gate driver circuit in period d.

[0124] In the timing charts shown in FIGS. 6(A) to 6(L), FIGS. 7(A) to 7(L), FIG. 8(A), and FIG. 8(C), period d is divided into a plurality of periods. For example, as shown in FIG. 8(D), period d is divided into two periods, period d1 and period d2. However, the number of divisions of period d

[0125] is not limited to this, and period d may be divided into three or more periods. Also, in FIG. 8 (D), period d1 and period d2 are arranged alternately, but a plurality of periods d1 and a plurality of periods d2 may be arranged alternately.

[0126] Referring to the timing chart of FIG. 8(D), the operation of the gate driver circuit of FIG. 4(A

[0126] ) in periods d1 and d2 will be described. In period d1, the gate driver circuit performs operation 2 of FIG. 5(B). That is, in period d

[0127] 1, circuit 10A outputs a signal to wiring 11, and circuit 10B outputs a signal to wiring 11. ​No. Also, during period d2, the gate driver circuit performs operation 3 in Figure 5(C). Furthermore, during period d2, circuit 10A does not output a signal to wiring 11, and circuit 10B does not output a signal to wiring 1 Output a signal to 1.

[0128] In this way, signals are sent to the gates of the transistors in both circuit 10A and circuit 10B. Since input can be applied, the degradation of each transistor can be suppressed. Therefore, even if the operation of circuit 10A and circuit 10B switches, the change in potential of wiring 11 is minimized. It can be made equal.

[0129] Therefore, the gate driver circuit in Figure 4(A) has pixels that hold the video signal. When used in a display device, the video signal changes depending on the potential of the wiring 11 (for example, feed Even if the operation of circuit 10A and circuit 10B switches (through, capacitive coupling, etc.), the wiring 11 remains connected. The changes in the video signal held by successive pixels can be made approximately equal. Therefore, pixels Since the brightness or transmittance can be made approximately equal, the display quality can be improved. Cut.

[0130] Next, the timing chart in Figure 4(A) shows another example of the operation of the gate driver circuit. I will explain about this.

[0131] Figures 6(A) to 6(L), Figures 7(A) to 7(L), Figure 8(A), Figure 8(C), and Figure In 8(D), the potential of the output signal OUTA of circuit 10A and the output signal OU of circuit 10B are measured. The potential of TB is constant during each period. Or, during a certain period, the output signal The potential of the voltage may have multiple values. For example, as shown in Figure 8(E), during period d Furthermore, the potential of the output signal OUTA of circuit 10A and the potential of the output signal OUTB of circuit 10B Each may have two values ​​that alternate.

[0132] Furthermore, the potentials of output signal OUTA and output signal OUTB during period d You can also change it in an analog way.

[0133] As described above, the gate driver circuit in Figure 4(A) can perform a variety of operations.

[0134] <Other configurations of gate driver circuits> Next, refer to Figure 9(A) for a gate driver circuit configuration different from that shown in Figure 4(A). I will explain.

[0135] Figure 9(A) shows an example of the configuration of a gate driver circuit. The gate driver circuit is a circuit It has circuit 10A, circuit 10B, circuit 10C, and circuit 10D. Circuit 10C and circuit 1 Each of the 0D circuits may have the same function as circuit 10A or circuit 10B.

[0136] Note that in the gate driver circuit shown in Figure 9(A), circuits 10A to 10D are wired as follows: When a signal (for example, a non-selection signal) is output to 11, and circuits 10A to 10D are each In the case where a signal other than the said signal (for example, a selection signal) is output to wiring 11, and circuit 10 Circuits A through 10D each output signals (for example, a non-selection signal and a selection signal) to wiring 11. By appropriately combining the option of not doing so with the option of not doing so, various actions can be performed.

[0137] Note that in Figure 9(A), the gate driver circuit is connected to the wiring 11, and there are four circuits (circuits) We have described the case where there is a circuit 10A (10D), but the gate driver of this embodiment The circuit configuration is not limited to this. The gate driver circuit of this embodiment is N (where N is natural). It may have a number of circuits. Note that each of the N circuits is either circuit 10A or circuit It may have the same functionality as 10B.

[0138] <Operation of the gate driver circuit> The operation of the gate driver circuit in Figure 9(A) will be explained with reference to Figure 9(B). Figure 9(B) shows an example of the operation of a gate driver circuit.

[0139] In operation 1, circuit 10A outputs a signal (e.g., a non-selection signal) to wiring 11, and circuit 1 Circuits 0B, 10C, and 10D do not output a signal to wiring 11. In operation 2, the circuit 10B outputs a signal (e.g., a non-selection signal) to wiring 11, and circuits 10A and 10C, And circuit 10D does not output a signal to wiring 11. In operation 3, circuit 10C outputs a signal to wiring 11 A signal (for example, a non-selection signal) is output to the circuit, and circuits 10A, 10B, and 10D are: No signal is output to wiring 11. In operation 4, circuit 10D outputs a signal to wiring 11 (e.g., non Circuits 10A, 10B, and 10C output a selection signal and send a signal to wiring 11. I don't have the strength.

[0140] In operation 5, circuits 10A and 10C send a signal (e.g., a non-selection signal) to wiring 11. Circuits 10B and 10D do not output a signal to wiring 11. In operation 6, the circuit Circuits 10B and 10D output a signal (e.g., a non-selection signal) to wiring 11, and circuit 10A Circuit 10C does not output a signal to wiring 11. In operation 7, circuits 10A and 10B Circuits 10C and 10D output signals (e.g., non-selection signals) to wiring 11. In operation 8, circuits 10A, 10B, 10C, and 10D send signals to wiring 11. It does not output.

[0141] In operation 9, circuit 10A outputs another signal (for example, a selection signal) to wiring 11, and the circuit Circuits 10B, 10C, and 10D do not output signals to wiring 11. In operation 10, Circuit 10B outputs another signal (for example, a selection signal) to wiring 11, and circuits 10A and 1 Circuit 0C and circuit 10D do not output a signal to wiring 11. In operation 11, circuit 10C is Another signal (for example, a selection signal) is output to wiring 11, and circuits 10A, 10B, and circuit Circuit 10D does not output a signal to wiring 11. In operation 12, circuit 10D outputs another signal to wiring 11. Circuits 10A, 10B, and 10C output a signal (for example, a selection signal) and are wired together. No signal is output to 11.

[0142] In operation 13, circuits 10A and 10C receive another signal (for example, a selection signal) from wiring 11. Circuits 10B and 10D output a signal, and do not output a signal to wiring 11. In operation 14, Circuits 10B and 10D output another signal (for example, a selection signal) to wiring 11, and Path 10A and circuit 10C do not output signals to wiring 11. In operation 15, circuit 10A, Circuits 10B, 10C, and 10D receive another signal (e.g., a selection signal) from wiring 11. Outputs.

[0143] As described above, the gate driver circuit in Figure 9(A) can perform a variety of operations.

[0144] Note that the gate driver circuit of this embodiment includes circuits (circuit 10A, circuit 10B, etc.) The more (N) there are, that is, the larger N is, the more each circuit outputs a signal. This reduces the number of times it is performed. Therefore, it suppresses the degradation of the transistors in each circuit. This is possible. However, if N is too large, the circuit size will become large, so N should be less than 6. It is preferable to make N smaller, preferably less than 4, and even more preferably N=2. .

[0145] Furthermore, when the gate driver circuit of this embodiment is used in a display device, the frame of the display device is In order to make the left and right sides roughly equal, it is preferable that N be an even number. Also, both sides of the pixel area To ensure that the number of circuits placed on each side is equal, it is preferable that N is an even number.

[0146] (Embodiment 3) This embodiment describes the configuration and operation of the gate driver circuit.

[0147] <Gate driver circuit configuration> The configuration of the gate driver circuit is described below.

[0148] Figures 10(A), 10(B), 11(A), and 11(B) show the gate driver rotation. An example of a circuit configuration is shown. The gate driver circuit has circuit 100A and circuit 100B. .

[0149] Circuit 100A has switches 101A and 102A. Switch 101A It is connected between wire 112A and wire 111. Switch 102A is connected to wire 113A It is connected between and wiring 111.

[0150] Circuit 100B includes switches 101B and 102B. Switch 101B It is connected between wiring 112B and wiring 111. Switch 102B is connected to wiring 113B It is connected between and wiring 111.

[0151] Here, as shown in Figures 10(B) and 11(B), the wiring 112A and wiring 111 The path between them is path 121A, the path between wiring 113A and wiring 111 is path 122A, wiring The path between 112B and wiring 111 is path 121B, and the path between wiring 113B and wiring 111 Let the route be designated as route 122B.

[0152] Note that when referring to the path between A and B, a switch is connected between A and B. That's also fine. Furthermore, between A and B, in addition to a switch, there could be other elements (for example, a transistor, a dash). (Iodes, resistive elements, or capacitive elements, etc.), or circuits (e.g., buffer circuits, inverters) A circuit or shift register circuit may be connected. Alternatively, between A and B, An element (for example, a resistor or a transistor) is connected in series with the switch, or in parallel with the switch. ) may be connected.

[0153] Note that circuits 100A, 100B, and wiring 111 are the circuits of Embodiment 2, respectively. It corresponds to 10A, circuit 10B, and wiring 11, and has the same function.

[0154] Next, we will explain wiring 112A, wiring 113A, wiring 112B, and wiring 113B. ru.

[0155] When the clock signal CK1 is input to wiring 112A and wiring 112B, wiring 112A And wiring 112B is a signal line or a clock signal line ("clock line", "clock supply line") Also known as, it has the function of, or a certain amount of electricity to wiring 112A and wiring 112B. When voltage is supplied, wiring 112A and wiring 112B function as power lines.

[0156] Note that if the same signal or voltage is input to both wiring 112A and wiring 112B, wiring 1 12A and wiring 112B may be connected. In this case, as shown in Figure 11(A), The same wiring 112 may be used for both wiring 112A and wiring 112B. Alternatively, wiring 112A Separate signals or separate voltages may be supplied to wiring 112B.

[0157] Wiring 113A and Wiring 113B are connected to the power supply voltage, reference voltage, ground voltage, earth, or negative voltage. When a voltage V1 having a function such as power supply potential is supplied, wiring 113A and wiring 113B , it functions as a power line or ground. Or, wiring 113A and wiring 113B When a signal is input, wiring 113A and wiring 113B function as signal lines. .

[0158] Note that if the same signal or voltage is supplied to wiring 113A and wiring 113B, wiring 1 13A and wiring 113B may be connected. Also, in this case, as shown in Figure 11(A), The same wiring 113 may be used for both wiring 113A and wiring 113B. Alternatively, wiring 113A Separate signals or separate voltages may be supplied to wiring 113B.

[0159] Next, switch 101A, switch 102A, switch 101B, and switch 102 Let me explain B.

[0160] Switch 101A controls the timing of electrical conductivity between wire 112A and wire 111. It has the ability to supply the potential of wiring 112A to wiring 111. It has a function to control the timing. Alternatively, switch 101A supplies power to wiring 112A. The signal or voltage (for example, clock signal CK1, clock signal CK2, or voltage V) 2) It has a function to control the timing of supplying to the wiring 111. Or, switch 10 1A has the function of controlling the timing at which signals or voltages are not supplied to wiring 111. Alternatively, switch 101A can supply an H signal (e.g., clock signal CK1) to wiring 111. It has a function to control the timing of supply. Alternatively, switch 101A has an L signal (for example Furthermore, it has a function to control the timing of supplying the clock signal CK1) to the wiring 111. Alternatively, switch 101A has a function to control the timing of raising the potential of wiring 111. It has. Alternatively, switch 101A controls the timing of reducing the potential of wiring 111. It has a function to control. Alternatively, switch 101A maintains the potential of wiring 111 at the timing It has a function to control the pacing.

[0161] Note that if the clock signal CK2 corresponds to the inverted signal of the clock signal CK1, Signal CK1 and clock signal CK2 are inverted signals of each other, or their phases are shifted by approximately 180°. It would be good to use that as the signal.

[0162] Furthermore, clock signal CK1 or clock signal CK2 may be balanced or unbalanced. It is also called "equilibrium." ) It may also be called equilibrium. Equilibrium is the period in one cycle during which the H level and the L level This refers to a situation where the period of time at the H level is approximately equal to the period of time at the L level. Non-equilibrium refers to a situation where the period of time at the H level is approximately equal to the period of time at the L level. This refers to a situation where the period of time is different from the period of time when it becomes [something].

[0163] Furthermore, if the clock signals CK1 and CK2 are unbalanced, If CK2 is not the inverted signal of clock signal CK1, then the clock signal CK1 will be at a high level. The length of the period during which this occurs and the length of the period during which the clock signal CK2 is at a high level can be made approximately equal. stomach.

[0164] Switch 102A controls the timing of electrical conductivity between wire 113A and wire 111. It has the ability to supply the potential of wiring 113A to wiring 111. It has a function to control the timing. Alternatively, switch 102A supplies power to wiring 113A. The signal or voltage (for example, clock signal CK2 or voltage V1) is supplied to the wiring 111. It has a function to control the timing of supply. Alternatively, switch 102A has a function to control the timing of the supply of signals or voltage. It has a function to control the timing at which it does not supply the wiring 111. Alternatively, switch 10 2A has the function of controlling the timing of supplying voltage V1 to wiring 111. Or, Switch 102A has the function of controlling the timing of reducing the potential of wiring 111. Alternatively, switch 102A has a function to control the timing of maintaining the potential of wiring 111. It holds.

[0165] Switch 101B controls the timing of electrical conductivity between wiring 112B and wiring 111. It has the ability to supply the potential of wiring 112B to wiring 111. It has a function to control the timing. Alternatively, switch 101B supplies to wiring 112B. The signal or voltage (for example, clock signal CK1, clock signal CK2, or voltage V) 2) It has a function to control the timing of supplying to the wiring 111. Or, switch 10 1B has the function of controlling the timing at which signals or voltages are not supplied to wiring 111. Alternatively, switch 101B may supply an H signal (e.g., clock signal CK1) to wiring 111. It has a function to control the timing of supply. Alternatively, switch 101B receives an L signal (for example) Furthermore, it has a function to control the timing of supplying the clock signal CK1) to the wiring 111. Alternatively, switch 101B has a function to control the timing of raising the potential of wiring 111. It has. Alternatively, switch 101B controls the timing of reducing the potential of wiring 111. It has a function to control. Alternatively, switch 101B maintains the potential of wiring 111. It has a function to control the pacing.

[0166] Switch 102B controls the timing of electrical conductivity between wire 113B and wire 111. It has the ability to supply the potential of wiring 113B to wiring 111. It has a function to control the timing. Alternatively, switch 102B supplies to wiring 113B. The signal or voltage (for example, clock signal CK2 or voltage V1) is supplied to the wiring 111. It has a function to control the timing of supply. Alternatively, switch 102B controls the signal or voltage. It has a function to control the timing at which it does not supply the wiring 111. Alternatively, switch 10 2B has the function of controlling the timing of supplying voltage V1 to wiring 111. Or, Switch 102B has the function of controlling the timing of reducing the potential of wiring 111. Alternatively, switch 102B has the function of controlling the timing of maintaining the potential of wiring 111. It holds.

[0167] <Operation of the gate driver circuit> Next, the operation of the gate driver circuit in Figure 10(A) will be explained below.

[0168] Figure 10(C) shows an example of the operation performed by the gate driver circuit in Figure 10(A). Figure 10 (C) shows the operation performed by the gate driver circuit, switch 101A, switch 1 This indicates the status (on or off) of switch 02A, switch 101B, and switch 102B. By combining the on and off states of these switches, the gate dry in Figure 10(A) A circuit can perform a variety of operations.

[0169] For the operation of each gate driver circuit in Figure 10(A), see Figures 10(C) and 12(A). )~This will be explained with reference to Figure 13(E).Here, we will refer to Figure 5(A)~ which was explained in Embodiment 2. The gate driver circuit shown in Figure 10(A) is used to realize operations 1 to 7 shown in Figure 5(G). This explains how it works.

[0170] First, to realize operation 1 in Figure 5(A), the gate driver circuit in Figure 10(A) Let me explain the creation process.

[0171] As shown in operation 1a of Figure 12(A), switch 101A is turned on, so wiring 11 2A and wiring 111 become conductive. Therefore, the potential of wiring 112A (for example, clock Signal CK1) is supplied to wiring 111. Switch 102A is turned on, so wiring 1 13A and wiring 111 become conductive. Therefore, the potential of wiring 113A (for example, voltage V) 1) is supplied to wiring 111. Switch 101B is turned on, so wiring 112B and Wiring 111 becomes conductive. Therefore, the potential of wiring 112B (for example, the clock signal C) K1) is supplied to wiring 111. Also, since switch 102B is turned on, wiring 1 Wiring 13B and wiring 111 become conductive. Therefore, the potential of wiring 113B (for example, voltage V) 1) is supplied to wiring 111.

[0172] Therefore, when potential is supplied from circuits 100A and 100B to wiring 111, This makes it possible to realize operation 1 in Figure 5(A).

[0173] Furthermore, in operation 1a of Figure 12(A), as shown in operation 1b of Figure 12(B), Switch 101A and switch 101B may be turned off. Alternatively, operation 1 in Figure 12(A) may be performed. In a, as shown in operation 1c of Figure 12(C), switch 102A and switch 10 2B may be turned off. Alternatively, in operation 1a of Figure 12(A), switch 101A Turn off any one of the following: switch 102A, switch 101B, or switch 102B. Alternatively, in operation 1a of Figure 12(A), switch 101A and switch 102B may be turned off. Alternatively, in operation 1a of Figure 12(A), switch 10 1B and switch 102A may be turned off.

[0174] Next, to realize operation 2 in Figure 5(B), the gate driver circuit in Figure 10(A) Let me explain the creation process.

[0175] As shown in operation 2a of Figure 12(D), switch 101A is turned on, so wiring 11 2A and wiring 111 become conductive. Therefore, the potential of wiring 112A (for example, clock Signal CK1) is supplied to wiring 111. Switch 102A is turned on, so wiring 1 13A and wiring 111 become conductive. Therefore, the potential of wiring 113A (for example, voltage V) 1) is supplied to wiring 111. Switch 101B is turned off, so wiring 112B and Wiring 111 becomes non-conductive. Also, switch 102B is turned off, so wiring 11 3B and wiring 111 will be in a non-conductive state.

[0176] Therefore, potential is supplied from circuit 100A to wiring 111, and from circuit 100B to wiring 111 By not supplying potential to the device, operation 2 shown in Figure 5(B) can be achieved.

[0177] Furthermore, in operation 2a in Figure 12(D), as shown in operation 2b in Figure 12(E), You may turn off switch 102A. Alternatively, in operation 2a of Figure 12(D), Figure 12( As shown in operation 2c of F), switch 101A may be turned off.

[0178] Next, to realize operation 3 in Figure 5(C), the gate driver circuit in Figure 10(A) Let me explain the creation process.

[0179] As shown in operation 3a of Figure 12(G), switch 101A is turned off, so wiring 11 2A and wire 111 become non-conductive. Switch 102A is turned off, so wire 11 3A and wiring 111 become non-conductive. Switch 101B turns on, so wiring 11 2B and wiring 111 become conductive. Therefore, the potential of wiring 112B (for example, clock) The signal CK1) is supplied to wiring 111. Also, switch 102B is turned on, Wiring 113B and wiring 111 become conductive. Therefore, the potential of wiring 113B (for example, Voltage V1) is supplied to wiring 111.

[0180] Therefore, no potential is supplied from circuit 100A to wiring 111, and no potential is supplied from circuit 100B to wiring 11 By supplying potential to point 1, operation 3 in Figure 5(C) can be realized.

[0181] Furthermore, in operation 3a of Figure 12(G), as shown in operation 3b of Figure 12(H), You may turn off switch 102B. Alternatively, in operation 3a of Figure 12(G), Figure 13( As shown in operation 3c of A), switch 101B may be turned off.

[0182] Next, to realize operation 4 in Figure 5(D), the gate driver circuit in Figure 10(A) Let me explain the creation process.

[0183] As shown in operation 4a of Figure 13(B), switch 101A is turned off, so wiring 11 2A and wire 111 become non-conductive. Switch 102A is turned off, so wire 11 3A and wiring 111 become non-conductive. Switch 101B is turned off, so wiring 11 2B and wiring 111 become non-conductive. Also, switch 102B is turned off, so Line 113B and wiring 111 become non-conductive.

[0184] Therefore, because no potential is supplied from circuits 100A and 100B to wiring 111, This allows us to achieve operation 4 in Figure 5(D).

[0185] Next, to realize operation 5 in Figure 5(E), the gate driver circuit in Figure 10(A) Let me explain the creation process.

[0186] As shown in operation 5a of Figure 13(C), switch 101A is turned on, so wiring 11 2A and wiring 111 become conductive. Therefore, wiring 112A has a different potential (for example, chrome The CK signal (CK2) is supplied to wiring 111. Switch 102A is turned off, so wiring Line 113A and wiring 111 become non-conductive. Switch 101B turns on, so Line 112B and wiring 111 become conductive. Therefore, another potential of wiring 112B (for example) The clock signal CK2 is supplied to wiring 111. Also, switch 102B is turned off. Therefore, wiring 113B and wiring 111 become non-conductive.

[0187] Therefore, a different potential is supplied to the wiring 111 from circuits 100A and 100B. Therefore, operation 5 in Figure 5(E) can be realized.

[0188] Next, to realize operation 6 in Figure 5(F), the gate driver circuit in Figure 10(A) Let me explain the creation process.

[0189] As shown in operation 6a of Figure 13(D), switch 101A is turned on, so wiring 11 2A and wiring 111 become conductive. Therefore, wiring 112A has a different potential (for example, chrome The CK signal (CK2) is supplied to wiring 111. Switch 102A is turned off, so wiring Line 113A and wiring 111 become non-conductive. Switch 101B is turned off, so Wire 112B and wiring 111 become non-conductive. Also, switch 102B is turned off. As a result, wiring 113B and wiring 111 become non-conductive.

[0190] Therefore, a different potential is supplied from circuit 100A to wiring 111, and from circuit 100B to wiring 1 By preventing the output of a potential at 11, operation 6 in Figure 5(F) can be achieved.

[0191] Next, to realize operation 7 in Figure 5(G), the gate driver circuit in Figure 10(A) Let me explain the creation process.

[0192] As shown in operation 7a of Figure 13(E), switch 101A is turned off, so wiring 11 2A and wire 111 become non-conductive. Switch 102A is turned off, so wire 11 3A and wiring 111 become non-conductive. Switch 101B turns on, so wiring 11 2B and wiring 111 become conductive. Therefore, wiring 112B is at a different potential (for example, chrome). The CK signal (CK2) is supplied to wiring 111. Also, switch 102B is turned off. As a result, wiring 113B and wiring 111 become non-conductive.

[0193] Therefore, no potential is supplied from circuit 100A to wiring 111, and no potential is supplied from circuit 100B to wiring 11 By supplying a different potential to point 1, operation 7 shown in Figure 5(G) can be realized.

[0194] As described above, switch 101A, switch 102A, switch 101B, and switch By controlling the on and off states of Chi 102B, the second embodiment can be represented in Figures 5(A) to 5( The operation of the gate driver circuit described in reference to G) can be realized.

[0195] Note that operation 1a in Figure 12(A), operation 2a in Figure 12(D), and operation 3 in Figure 12(G) In (a), it is preferable that the potentials of wiring 112A and wiring 112B are approximately equal. It is preferable that the potentials of wiring 113A and wiring 113B are approximately equal. For example, wiring 11 When voltage V1 is supplied to 3A and wiring 113B, the clock signal CK1 is at a low level. It is preferable to do so.

[0196] Also, see operation 5a in Figure 13(C), operation 6a in Figure 13(D), and operation 7 in Figure 13(E). In a, if the potential of wiring 113A and wiring 113B is V1, then wiring 112A and The potential of wiring 112B is preferably approximately V2. For example, wiring 112A and wiring The clock signal CK2 input to 112B is preferably at a high level.

[0197] Next, Figures 6(A) to 6(L) and Figures 7(A) to 7(L) described in Embodiment 2. The operation of the gate driver circuit in Figure 10(A) to realize the timing chart shown. I will explain this.

[0198] In Embodiment 2, the operation of the gate driver circuit in Figure 4(A) over an arbitrary period of time is as follows: As explained with reference to Figures 5(A) to (I), in order to achieve this operation, Figure 10 The gate driver circuit in (A) performs the operation shown in Figure 10(C) during any given period. Any of the following can be done. For example, in order to achieve operation 1 shown in Figure 5(A), Figure 10( The gate driver circuit of A) is shown in Figure 10(C) for operation 1a, operation 1b, and operation 1c. One of the following can be done (corresponding to Figures 12(A), 12(B), and 12(C)): .

[0199] First, to realize the timing chart shown in Figure 6(A), the gate shown in Figure 10(A) The operation of the driver circuit will be explained.

[0200] As described in Embodiment 2, period a, period transitioning from period b to period c, period c, During period d, the gate driver circuit in Figure 10(A) performs operation 2 shown in Figure 5(B). Therefore, in order to realize the operation 2, period a, period b to transition to period c, During periods c and d, the gate driver circuit in Figure 10(A) is, for example, in Figure 10( Operation 2a, operation 2b, and operation 2c shown in C) (Figures 12(D), 12(E), and 1 One of the following actions (corresponding to 2(F)) can be performed.

[0201] Furthermore, during the transition period from period a to period b, and during period b, the gate shown in Figure 10(A) The driver circuit performs operation 6 in Figure 5(F). Therefore, in order to realize operation 6, During the transition period from period a to period b, and during period b, the gate driver circuit shown in Figure 10(A) For example, it can perform operation 6a shown in Figure 10(C) (corresponding to Figure 13(D)).

[0202] In this way, the gate driver circuit in Figure 10(A) corresponds to the timing shown in Figure 6(A). It can perform actions corresponding to the chart.

[0203] In the timing chart in Figure 6(A), the transition from period a and from period b to period c is shown. During the execution period, circuit 100B outputs a signal (e.g., a non-selection signal) to wiring 111. In that case, the gate driver circuit in Figure 10(A) performs, for example, operation 1a shown in Figure 10(C). , operation 1b, and operation 1c (corresponding to Figures 12(A), 12(B), and 12(C)) You can do either of these.

[0204] Furthermore, in the timing chart in Figure 6(A), the period of transition from period a to period b, And during period b, circuit 100B outputs another signal (for example, a selection signal) to wiring 111. When applying force, the gate driver circuit in Figure 10(A) performs operation 5, for example, as shown in Figure 10(C). (This corresponds to Figure 13(C)) can be performed.

[0205] In this way, the gate driver circuit in Figure 10(A) is configured to produce the timing shown in Figure 6(K). It can perform actions corresponding to the chart.

[0206] Similarly, the gate driver circuit in Figure 10(A) operates as described in Figure 10(C). By performing this shift, the timing shown in Figures 6(B) to 6(J) and 6(L) is achieved. It is possible to realize the chart.

[0207] Next, the gate shown in Figure 10(A) is used to realize the timing chart shown in Figure 7(A). The operation of the driver circuit will be explained.

[0208] As described in Embodiment 2, period a, period transitioning from period b to period c, period c, During period d, the gate driver circuit in Figure 10(A) performs operation 3 shown in Figure 5(C). Therefore, in order to realize the operation 3, period a, period b to transition to period c, During periods c and d, the gate driver circuit in Figure 10(A) is, for example, in Figure 10( Operation 3a, operation 3b, and operation 3c shown in C) (Figures 12(G), 12(H), and 1 One of the following can be performed (corresponding to 3(A)).

[0209] Furthermore, during the transition period from period a to period b, and during period b, the gate shown in Figure 10(A) The driver circuit performs operation 7 in Figure 5(G). Therefore, in order to realize operation 7, During the transition period from period a to period b, and during period b, the gate driver circuit shown in Figure 10(A) For example, it can perform operation 7a shown in Figure 10(C) (corresponding to Figure 13(E)).

[0210] In this way, the gate driver circuit in Figure 10(A) is configured to produce the timing shown in Figure 7(A). It can perform actions corresponding to the chart.

[0211] In the timing chart in Figure 7(A), the transition from period a and from period b to period c is shown. During the period in which the operation is performed, circuit 100A outputs a signal (for example, a non-selection signal) to wiring 111. In that case, the gate driver circuit in Figure 10(A) performs, for example, operation 1a shown in Figure 10(C). , operation 1b, and operation 1c (corresponding to Figures 12(A), 12(B), and 12(C)) You can do either of these.

[0212] Furthermore, in the timing chart of Figure 7(A), the period of transition from period a to period b, And during period b, circuit 100A outputs another signal (for example, a selection signal) to wiring 111. When applying force, the gate driver circuit in Figure 10(A) performs operation 5, for example, as shown in Figure 10(C). (This corresponds to Figure 13(C)) can be performed.

[0213] In this way, the gate driver circuit in Figure 10(A) is configured to produce the timing shown in Figure 7(K). It can perform actions corresponding to the chart.

[0214] Similarly, the gate driver circuit in Figure 10(A) operates as described in Figure 10(C). By performing a shift, the timing shown in Figures 7(B) to 7(J) and 7(L) is achieved. It is possible to realize the chart.

[0215] As described above, the gate driver circuit in Figure 10(A) incorporates the operation shown in Figure 10(C). By combining them, the following can be seen in Figures 6(A) to 6(L) and Figures 7(A) to 7(L). This allows for the creation of timing charts.

[0216] <Gate driver circuit configuration> Next, a gate driver circuit configuration different from that shown in Figure 10(A) will be described below. Here, the gate driver circuit has the same function as circuit 100A or circuit 100B. We will now explain the case where there are N (where N is a natural number) circuits.

[0217] Figure 11(C) shows an example of the configuration of a gate driver circuit. The gate driver circuit is a gate driver circuit. It has a path 100A, a circuit 100B, a circuit 100C, and a circuit 100D. Circuit 100D has the same function as circuit 100A or circuit 100B.

[0218] Circuit 100C has switches 101C and 102C. 101C is connected between wire 112C and wire 111, and switch 102C is connected to wire 1 It is connected between 13C and wiring 111. Switch 101C is connected to switch 101A or S It has the same function as switch 101B. Switch 102C is the same as switch 102A or switch It has the same function as switch 102B. Wiring 112C is connected to wiring 112A or wiring 112B. They have similar functions and are input to the same signals or voltages. Wiring 113C is connected to wiring 113A or This has the same function as wiring 113B and receives the same signal or voltage input.

[0219] Circuit 100D has switches 101D and 102D. 101D is connected between wiring 112D and wiring 111, and switch 102D is connected to wiring 1 It is connected between 13D and wiring 111. Switch 101D is connected to switch 101A or S It has the same function as switch 101B. Switch 102D is the same as switch 102A or switch It has the same function as switch 102B. Wiring 112D is connected to wiring 112A or wiring 112B. They have similar functions and are input to the same signals or voltages. Wiring 113D is connected to wiring 113A or This has the same function as wiring 113B and receives the same signal or voltage input.

[0220] Figure 14(A) shows an example of another configuration of the gate driver circuit. The gate driver circuit is It has circuits 100A and 100B.

[0221] Circuit 100A includes switches 101A and 102A, as well as switch 103A. It has. Switch 103A is connected between wiring 113A and wiring 111. Switch Switch 103A can perform the same operation as switch 102A.

[0222] Circuit 100B includes switches 101B and 102B, as well as switch 103B. It has. Switch 103B is connected between wiring 113B and wiring 111. Switch Switch 103B can perform the same operation as switch 102B.

[0223] <Operation of the gate driver circuit> Regarding the operation of the gate driver circuit in Figure 14(A), see Figures 14(B) and 15(A). This will be explained with reference to Figure 15(E). Here, we will refer to Figure 5(A) to Figure 15(E) which was explained in Embodiment 2. To realize operations 1 to 7 shown in 5(G), the gate driver circuit in Figure 14(A) Let me explain how it works.

[0224] First, to realize operation 1 in Figure 5(A), the gate driver circuit in Figure 14(A) Let me explain the creation process.

[0225] As shown in operation 1d of Figure 14(B), switch 101A is turned off, so wiring 11 2A and wiring 111 become non-conductive. Switches 102A and 103A are ON. Therefore, wiring 113A and wiring 111 become electrically connected. Thus, the electrical current of wiring 113A A voltage (for example, V1) is supplied to wiring 111. Switch 101B is turned off. Then, wiring 112B and wiring 111 become non-conductive. Switch 102B and switch 1 Since 03B is turned on, wiring 113B and wiring 111 become conductive. Therefore, wiring The potential of 113B (for example, voltage V1) is supplied to wiring 111.

[0226] Furthermore, in operation 1d in Figure 14(B), as shown in operation 1e in Figure 14(B), Switch 103A and switch 103B may be turned off. Alternatively, operation 1 in Figure 14(B) may be performed. In d, as shown in operation 1f of Figure 14(B), switch 102A and switch 10 2B may be turned off. Alternatively, operations 1d, 1e, and 1f in Figure 14(B) may be changed. You may then turn on switch 101A or switch 101B.

[0227] Next, to realize operation 2 in Figure 5(B), the gate driver circuit in Figure 14(A) Let me explain the creation process.

[0228] As shown in operation 2d of Figure 14(B), switch 101A is turned off, so wiring 11 2A and wiring 111 become non-conductive. Switches 102A and 103A are ON. Therefore, wiring 113A and wiring 111 become electrically connected. Thus, the electrical current of wiring 113A A voltage (for example, V1) is supplied to wiring 111. Switch 101B is turned off. Then, wiring 112B and wiring 111 become non-conductive. Switch 102B and switch 1 Since 03B is turned off, wiring 113B and wiring 111 become non-conductive.

[0229] Furthermore, in operation 2d of Figure 14(B), operation 2e of Figure 14(B) is compared to operation 2e of Figure 15(A). As shown in ( ), switch 103A may be turned off. Alternatively, the operation shown in Figure 14(B) In 2d, as shown in operation 2f of Figure 14(B) (corresponding to Figure 15(B)), the switch 102A may be turned off. Alternatively, operations 2d, 2e, and 2 in Figure 14(B) may be used. In case f, switch 101A may be turned on.

[0230] Next, to realize operation 3 in Figure 5(C), the gate driver circuit in Figure 14(A) Let me explain the creation process.

[0231] As shown in operation 3d of Figure 14(B), switch 101A is turned off, so wiring 11 2A and wiring 111 become non-conductive. Switches 102A and 103A are off. Therefore, wire 113A and wire 111 become non-conductive. Switch 101B is off. Therefore, wiring 112B and wiring 111 become non-conductive. Switch 102B and Switch 103B turns on, so wires 113B and 111 become conductive. The potential of wiring 113B (for example, voltage V1) is then supplied to wiring 111.

[0232] Furthermore, in operation 3d of Figure 14(B), operation 3e of Figure 14(B) is compared to operation 3e of Figure 15(C). As shown in ( ), switch 103B may be turned off. Alternatively, the operation shown in Figure 14(B) In 3d, as shown in operation 3f of Figure 14(B) (corresponding to Figure 15(D)), the switch 102B may be turned off. Alternatively, operations 3d, 3e, and 3 in Figure 14(B) may be used. In case f, switch 101B may be turned on.

[0233] Next, to realize operation 4 in Figure 5(D), the gate driver circuit in Figure 14(A) Let me explain the creation process.

[0234] As shown in operation 4b of Figure 14(B), switch 101A is turned off, so wiring 11 2A and wiring 111 become non-conductive. Switches 102A and 103A are off. Therefore, wire 113A and wire 111 become non-conductive. Switch 101B is off. Therefore, wiring 112B and wiring 111 become non-conductive. Switch 102B and Switch 103B is turned off, so wires 113B and 111 become non-conductive.

[0235] Next, to realize operation 5 in Figure 5(E), the gate driver circuit in Figure 14(A) Let me explain the creation process.

[0236] As shown in operation 5b of Figure 14(B) (corresponding to Figure 15(E)), switch 101A is O Therefore, wiring 112A and wiring 111 become electrically connected. Thus, wiring 112A The electric potential (for example, the clock signal CK1) is supplied to the wiring 111. Switch 102A and Since switch 103A is turned off, wiring 113A and wiring 111 become non-conductive. Switch 101B is turned on, so wire 112B and wire 111 become electrically connected. Therefore, the potential of wiring 112B (for example, the clock signal CK1) is supplied to wiring 111. Switches 102B and 103B will be turned off, so wires 113B and 11 1 results in a non-conductive state.

[0237] Next, to realize operation 6 in Figure 5(F), the gate driver circuit in Figure 14(A) Let me explain the creation process.

[0238] As shown in operation 6b of Figure 14(B), switch 101A is turned on, so wiring 11 2A and wiring 111 become conductive. Therefore, the potential of wiring 112A (for example, clock Signal CK1) is supplied to wiring 111. Switches 102A and 103A are O As a result, wiring 113A and wiring 111 become non-conductive. Switch 101B is O As a result, wiring 112B and wiring 111 become non-conductive. Switch 102B and Since switch 103B is turned off, wiring 113B and wiring 111 become non-conductive.

[0239] Next, to realize operation 7 in Figure 5(G), the gate driver circuit in Figure 14(A) Let me explain the creation process.

[0240] As shown in operation 7b of Figure 14(B), switch 101A is turned off, so wiring 11 2A and wiring 111 become non-conductive. Switches 102A and 103A are off. Therefore, wire 113A and wire 111 become non-conductive. Switch 101B is ON. Therefore, wiring 112B and wiring 111 become electrically connected. Thus, the electrical current of wiring 112B The position (for example, the clock signal CK1) is supplied to wiring 111. Switch 102B and Since switch 103B is turned off, wiring 113B and wiring 111 become non-conductive.

[0241] As described above, switch 101A, switch 102A, switch 103A, switch 1 By controlling the on and off states of 01B, switch 102B, and switch 103B The gate driver circuit described with reference to Figures 5(A) to 5(G) of Embodiment 2 is described below. It is possible to realize the project.

[0242] (Embodiment 4) In this embodiment, a semiconductor device having the gate driver circuit described in the above embodiment is provided. I will explain this.

[0243] <Configuration of semiconductor device> An example of the configuration of the semiconductor device of this embodiment will be described with reference to Figure 16(A). Figure 16(A) shows an example of a semiconductor device circuit diagram. The semiconductor device in Figure 16(A) is a G It has circuits 200A and 200B that constitute the driver.

[0244] Circuit 200A consists of transistors 201A, 202A, and circuit 300A. Circuit 200B includes transistor 201B, transistor 202B, and circuit 30 It has 0B.

[0245] Note that in Figure 16(A), transistors 201A, 202A, and Transistor 201B and transistor 202B are described as N-channel transistors. An N-channel transistor has a threshold for the potential difference (Vgs) between the gate and source. It turns on when the voltage value (Vth) is exceeded.

[0246] These transistors may also be P-channel transistors. In a type 1 transistor, the potential difference (Vgs) between the gate and source is equal to the threshold voltage (Vth It turns on when the value falls below ).

[0247] Transistor 201A has its first terminal connected to wire 112A, and its second terminal connected to wire 1 It is connected to 11. Transistor 202A has its first terminal connected to wiring 113A, and the Terminal 2 is connected to wiring 111. Circuit 300A is connected to wiring 113A, wiring 114A, wiring Wire 115A, Wiring 116A, Gate of Transistor 201A, and Transistor 202A It is connected to the gate. Note that circuit 300A is connected to all of wiring 113A to 116A. It does not need to be connected, and is configured not to be connected to any of the wirings 113A to 116A. That's good too.

[0248] Note that the connection point between the gate of transistor 201A and circuit 300A is node A1, and the transistor The connection point between the gate of transistor 202A and circuit 300A is indicated as node A2. Also, The potential at node A1 is also referred to as potential Va1, and the potential at node A2 is also referred to as potential Va2.

[0249] Transistor 201B has its first terminal connected to wire 112B and its second terminal connected to wire 1 It is connected to 11. Transistor 202B has its first terminal connected to wiring 113B, and the Terminal 2 is connected to wiring 111. Circuit 300B is connected to wiring 113B, wiring 114B, wiring Wire 115B, wiring 116B, gate of transistor 201B, and transistor 202B It is connected to the gate. Note that circuit 300B is connected to all of wiring 113B to 116B. It does not need to be connected, and is configured not to be connected to any of the wirings 113B to 116B. That's good too.

[0250] Note that the connection point between the gate of transistor 201B and circuit 300B is node B1, and the transistor The connection point between the gate of transistor 202B and circuit 300B is indicated as node B2. The potential at node B1 is also referred to as potential Vb1, and the potential at node B2 is also referred to as potential Vb2.

[0251] Next, wiring 111, wiring 114A, wiring 115A, wiring 116A, wiring 114B, wiring This section will explain 115B and wiring 116B.

[0252] Wiring 111 receives signal OUTA from circuit 200A and signal O from circuit 200B. The UTB (Unified Track Boundary) is output.

[0253] Wiring 111 extends to the pixel area and is arranged as a gate signal line (also called a "gate line"), It functions as a scan line or a signal line. Therefore, signal OUTA and signal OUTB are This corresponds to a gate signal, scan signal, or selection signal.

[0254] Furthermore, if the semiconductor device has multiple circuits 200A, the wiring 111 is connected to another stage (for example, It may be connected to the wiring 114A of the next stage circuit 200A. In this case, the signal OUTA is This corresponds to a transfer signal or start signal. Furthermore, the semiconductor device has multiple circuits 200A. In this case, wiring 111 is connected to wiring 116A of circuit 200A in another stage (for example, the previous stage). This is also acceptable. In this case, signal OUTA corresponds to the reset signal.

[0255] Furthermore, if the semiconductor device has multiple circuits 200B, the wiring 111 is connected to another stage (for example, It may also be connected to the wiring 114B of circuit 200B in the next stage. In this case, signal OUTB is This corresponds to a transfer signal or start signal. Also, the semiconductor device has multiple circuits 200B. In this case, wiring 111 is connected to wiring 116B of circuit 200B of another stage (for example, the previous stage). This is also acceptable. In this case, signal OUTB corresponds to the reset signal.

[0256] The start signal SP is input to wiring 114A and wiring 114B. Therefore, wiring 1 Wiring 14A and 114B function as signal lines.

[0257] Furthermore, if the semiconductor device has multiple circuits 200A, the wiring 114A is connected to another stage (for example). It may also be connected to the wiring 111 of the preceding circuit 200A. In this case, wiring 114A is It functions as a gate signal line (also called a "gate line"), a scan line, or a signal line. Therefore, the start signal SP corresponds to a gate signal, a scan signal, or a selection signal.

[0258] Furthermore, if the semiconductor device has multiple circuits 200B, the wiring 114B is connected to another stage (for example). It may also be connected to the wiring 111 of the preceding circuit 200B. In this case, wiring 114B is It functions as a gate signal line (also called a "gate line"), a signal line, or a scan line. Therefore, the start signal SP corresponds to a gate signal, selection signal, or scan signal.

[0259] Note that if the same signal is input to both wiring 114A and wiring 114B, wiring 114A and wiring 114B may be connected. Also, in this case, the same applies to wiring 114A and wiring 114B. Wiring may be used. Alternatively, separate signals may be input to wire 114A and wire 114B. That's good too.

[0260] Signal SELA is input to wiring 115A, and signal SELB is input to wiring 115B. It will be done.

[0261] Signals SELA and SELB are inverted signals of each other, or signals with a phase difference of approximately 180°. It would be good to use signals. And signals SELA and SELB are set at certain intervals (for example, If the signal SELA and SELB alternate between high and low levels (for each frame period), This corresponds to a control signal, clock signal, or clock control signal. Therefore, wiring 115A And wiring 115B is a signal line, control line, or clock signal line ("clock line", "clock signal line"). Also called a "supply line". It has the function of a signal. In addition, signals SELA and SELB are The signal alternates between high and low levels every few frames, each time the power is turned on, or randomly. It is also permissible to set both signal SELA and signal SELB to H level or during the same period. It may also be designated as L level.

[0262] The reset signal RE is input to wiring 116A and wiring 116B. Therefore, wiring 1 Wiring 16A and 116B function as signal lines.

[0263] Furthermore, if the semiconductor device has multiple circuits 200A, the wiring 116A is connected to another stage (for example). It may also be connected to the wiring 111 of the next stage circuit 200A. In this case, wiring 116A is It functions as a gate signal line (also called a "gate line"), a signal line, or a scan line. Therefore, the reset signal RE corresponds to a gate signal, selection signal, or scan signal.

[0264] Furthermore, if the semiconductor device has multiple circuits 200B, the wiring 116B is connected to another stage (for example). It may also be connected to the wiring 111 of the next stage circuit 200B. In this case, wiring 116B is It functions as a gate signal line (also called a "gate line"), a signal line, or a scan line. Therefore, the reset signal RE corresponds to a gate signal, selection signal, or scan signal.

[0265] Note that if the same signal is input to both wiring 116A and wiring 116B, wiring 116A and wiring 116B may be connected. Also, in this case, the same applies to wiring 116A and wiring 116B. Wiring may be used. Alternatively, separate signals may be input to wire 116A and wire 116B. That's good too.

[0266] Next, transistor 201A, transistor 202A, circuit 300A, transistor 2 This section describes transistor 01B, transistor 202B, and circuit 300B.

[0267] Transistor 201A has the same function as switch 101A described in Embodiment 3. Alternatively, transistor 201A has the function of performing bootstrap operation. Alternatively, transistor 201A can be used to set the potential of node A1 to bootstrap operation. Therefore, it may have a function to increase the level.

[0268] Thus, transistor 201A functions as a switch or as a buffer. It has functions such as [specific functions]. Furthermore, transistor 201A is controlled according to the potential of node A1. That's good too.

[0269] Transistor 202A has the same function as switch 102A described in Embodiment 3. In addition, transistor 202A may be controlled according to the potential of node A2.

[0270] Circuit 300A has the function of controlling the potential of node A1 or node A2. Alternatively, circuit 300A supplies signals or voltages to node A1 or node A2 at the appropriate times. It has a function to control the ng. Alternatively, circuit 300A is connected to node A1 or node A2. It has a function to control the timing of when it does not supply signals or voltage, etc. Alternatively, circuit 300A This controls the timing of supplying an H signal or voltage V2 to node A1 or node A2. It has the function of sending an L signal or voltage to node A1 or node A2. It has a function to control the timing of supplying V1. Alternatively, circuit 300A is node A It has a function to control the timing of raising the potential of node 1 or the potential of node A2. Circuit 300A controls the timing of reducing the potential of node A1 or node A2. It has the function of controlling. Alternatively, circuit 300A is the potential of node A1 or the potential of node A2. It has a function to control the timing of maintaining it. Alternatively, circuit 300A is node A1 or It has a function to control the timing of putting node A2 into a floating state.

[0271] Circuit 300A responds to the start signal SP, signal SELA, or reset signal RE. It may be controlled by the aforementioned signals (start signal SP, signal). Alternatively, circuit 300A may control the aforementioned signals (start signal SP, signal). SELA and the reset signal RE) are separate signals (for example, signal OUTA, clock signal) It may be controlled according to CK1, or a clock signal such as CK2.

[0272] Transistor 201B has the same function as switch 101B described in Embodiment 3. Alternatively, transistor 201B has the function of performing bootstrap operation. Alternatively, transistor 201B can be used to set the potential of node B1 to bootstrap operation. Therefore, it may have a function to increase the level.

[0273] Thus, transistor 201B functions as a switch or as a buffer. It has functions such as [specific functions]. Furthermore, transistor 201B is controlled according to the potential of node B1. That's good too.

[0274] Transistor 202B has the same function as switch 102B described in Embodiment 3. In addition, transistor 202B may be controlled according to the potential of node B2.

[0275] Circuit 300B has the function of controlling the potential of node B1 or node B2. Alternatively, circuit 300B supplies signals or voltages to node B1 or node B2 at the appropriate time. It has a function to control the ng. Alternatively, circuit 300B is connected to node B1 or node B2. It has a function to control the timing of when signals or voltages are not supplied. Or, circuit 300B This controls the timing of supplying an H signal or voltage V2 to node B1 or node B2. It has the function of sending an L signal or voltage to node B1 or node B2. It has a function to control the timing of supplying V1. Alternatively, circuit 300B is node B It has a function to control the timing of raising the potential of node 1 or the potential of node B2. Circuit 300B controls the timing of reducing the potential of node B1 or node B2. It has the function of controlling. Alternatively, circuit 300B is the potential of node B1 or the potential of node B2. It has a function to control the timing of maintaining it. Alternatively, circuit 300B is node B1 or It has a function to control the timing of putting node B2 into a floating state.

[0276] Circuit 300B responds to the start signal SP, signal SELB, or reset signal RE. It may be controlled by the aforementioned signals (start signal SP, signal). Alternatively, circuit 300B may control the aforementioned signals (start signal SP, signal). SELB and the reset signal RE) are separate signals (e.g., signal OUTB, clock signal) It may be controlled according to CK1, or a clock signal such as CK2.

[0277] <Semiconductor device operation> For an example of the operation of a semiconductor device shown in Figure 16(A), see the timing chart shown in Figure 17. Refer to the following for explanation. Also, Figures 18(A) to 23 are the semiconductor device shown in Figure 16(A), respectively. This is a diagram illustrating an example of its operation, along with a timing chart showing an example of its operation. We will omit explanations of aspects that are common to those described in the above embodiments.

[0278] First, during period a1, as shown in Figure 18(A), the start signal SP reaches the H level. Yes. At the timing when this start signal SP becomes high level, circuit 300A receives the high signal or It begins supplying voltage V2 to node A1. Therefore, the potential of node A1 rises. As the potential at node A1 rises, circuit 300A sends an L signal or voltage V1 to node A It supplies power to node 2. Therefore, the potential at node A2 decreases to L level. Then, the transistor Since the ZISTA 202A is turned off, wiring 113A and wiring 111 become non-conductive.

[0279] Subsequently, the potential of node A1 continues to rise. Eventually, the potential of node A1 reaches V1+Vth 201A (Vth 201A When it rises to the threshold voltage of transistor 201A, Since transistor 201A is turned on, wiring 112A and wiring 111 become conductive. Then, the low-level clock signal CK1 is transmitted to wiring 111 via transistor 201A. It is supplied. As a result, signal OUTA becomes low.

[0280] Subsequently, the potential at node A1 rises further. Eventually, circuit 300A reaches node A1. Since the supply of the signal or voltage is stopped, circuit 300A and node A1 become non-conductive. As a result, node A1 becomes floating, and the potential of node A1 is V1 + Vth 201A It is maintained at +Vx (where Vx is a positive number).

[0281] During period a1, circuit 300A will stop supplying signals or voltage to node A1. Instead, V1+Vth 201A You may continue supplying the +Vx voltage to node A1.

[0282] On the other hand, during period a1, at the timing when the start signal SP becomes high level, circuit 30 0B begins supplying an H signal or voltage V2 to node B1. Therefore, the potential of node B1 is It rises. At this time, since the signal SELB is at a low level, the potential of node B1 rises. Therefore, circuit 300B supplies an L signal or voltage V1 to node B2. Thus, node B The potential of 2 decreases and becomes L level. Then transistor 202B turns off. Wiring 113B and wiring 111 become non-conductive.

[0283] Subsequently, the potential of node B1 continues to rise. Eventually, the potential of node B1 reaches V1+Vth 201B (Vth 201B When it rises to the threshold voltage of transistor 201B, Since transistor 201B is turned on, wiring 112B and wiring 111 become conductive. Then, the low-level clock signal CK1 is transmitted to wiring 111 via transistor 201B. It is supplied. As a result, signal OUTB becomes low.

[0284] Subsequently, the potential at node B1 rises further. Eventually, circuit 300B reaches node B1. Since the supply of the signal or voltage is stopped, circuit 300B and node B1 become non-conductive. As a result, node B1 becomes floating, and the potential of node B1 is V1 + Vth 201B It is maintained at +Vx.

[0285] During period a1, circuit 300B stops supplying signals or voltage to node B1. Instead, V1+Vth 201B You may continue supplying the +Vx voltage to node B1.

[0286] Next, during period b1, as shown in Figure 18(B), the start signal SP is at the L level. Therefore, circuit 300A is kept in a state where it does not supply any signal or voltage to node A1. Therefore, since node A1 remains in a floating state, the potential of node A1 is V1 + Vt h 201A It remains at +Vx. In other words, transistor 201A remains in the ON state. Therefore, wiring 112A and wiring 111 maintain continuity.

[0287] Furthermore, since the potential of node A1 is maintained at the value that rose during period a1, the circuit 300A This is maintained in a state where an L signal or voltage V1 is supplied to node A2. Therefore, the transistor Since 202A remains in the off state, wiring 113A and wiring 111 remain in a non-conductive state. do.

[0288] At this time, the clock signal CK1 rises from L level to H level. Then, H level The clock signal CK1 is supplied to wiring 111 via transistor 201A, The potential of wiring 111 rises. Then, since node A1 remains in a floating state, The potential of A1 is determined by the parasitic capacitance between the gate and the second terminal of transistor 201A. , V2+Vth 202A +Vx(Vth 202AThreshold voltage of transistor 202A It rises to ). This is what is known as bootstrap operation. Thus, the potential of wiring 111 As it rises to V2, the signal OUTA becomes high level.

[0289] On the other hand, during period b1, the start signal SP becomes L level, so circuit 300B, The state in which no signal or voltage is supplied to node B1 is maintained. Therefore, node B1 is in a floating state. Since it is held, the potential of node B1 is V1+Vth 201B It is maintained at +Vx. In other words, transistor 201B remains in the ON state, so wiring 112B and wiring 111 This means maintaining a conductive state.

[0290] Also, since the signal SELB is at a low level, or the potential of node B1 rises during period a1. Since it is maintained at that value, circuit 300B supplies an L signal or voltage V1 to node B2. It remains in the off state. Therefore, transistor 202B remains in the off state, so wiring 113 B and wiring 111 remain in a non-conductive state.

[0291] At this time, the clock signal CK1 rises from L level to H level. Then, H level The clock signal CK1 is supplied to wiring 111 via transistor 201B, The potential of wiring 111 rises. Then, since node B1 remains in a floating state, The potential of B1 is determined by the parasitic capacitance between the gate and the second terminal of transistor 201B. , V2+Vth 202B +Vx(Vth 202B :Threshold voltage of transistor 202B It rises to ). This is what is known as bootstrap operation. Thus, the potential of wiring 111 As the voltage rises to V2, the signal OUTB becomes high.

[0292] Next, during period c1, as shown in Figure 19(A), the reset signal RE reaches the H level. Yes. At the moment when this reset signal RE becomes high level, circuit 300A receives a low signal or This supplies voltage V1 to node A1. Therefore, the potential of node A1 becomes voltage V1. It decreases to this. Then, transistor 201A turns off, so wiring 112A and wiring 11 1 becomes non-conductive. On the other hand, the potential of node A1 decreases, so circuit 300A becomes H A signal or voltage V2 is supplied to node A2. Therefore, the potential of node A2 rises. As a result, transistor 202A turns on, and wires 113A and 111 become conductive. As a result, voltage V1 is supplied to wiring 111 via transistor 202A. As a result, the potential of wiring 111 decreases, and signal OUTA becomes low.

[0293] Furthermore, during period c1, the timing at which the clock signal CK1 becomes low is as follows: The timing of the ZISTA201A turning off may be earlier. Until 201A is turned off, the low-level clock signal CK1 controls transistor 201A. It is preferable that the power is supplied to wiring 111 via this. Also, the channel width of transistor 201A is increased. This allows you to shorten the falling edge time of signal OUTA.

[0294] During period c1, with respect to wiring 111, voltage V1 is transmitted through transistor 202A. When supplied to wiring 111, and when the low-level clock signal CK1 is supplied to transistor 201A When the voltage V1 is supplied to wiring 111 via transistor 202A, and when the voltage V1 is supplied to wiring 111 via transistor 202A A clock signal CK1, which is supplied to 111 and is at an L level, is transmitted via transistor 201A. There are three patterns: when it is supplied to wiring 111, and

[0295] On the other hand, during period c1, at the timing when the reset signal RE becomes high, circuit 30 0B supplies an L signal or voltage V1 to node B1. Therefore, the potential of node B1 is The voltage decreases to V1. Then, transistor 201B turns off, so wiring 1 12B and wiring 111 become non-conductive. Meanwhile, the SELB signal is maintained at a low level. Therefore, circuit 300B is kept in a state that supplies an L signal or voltage V1 to node B2. Therefore, the potential of node B2 is maintained at the L level. Then, transistor 202B Since the OFF state is maintained, wiring 113B and wiring 111 remain in a non-conductive state.

[0296] Furthermore, during period c1, the timing at which the clock signal CK1 becomes low is as follows: The timing may be earlier than when the ZISTA201B turns off. Until 201B is turned off, the low-level clock signal CK1 is applied to transistor 201B It is preferable that the power is supplied to wiring 111 via this. Also, the channel width of transistor 201B is increased. This allows you to shorten the falling edge time of signal OUTB.

[0297] Next, during period d1, as shown in Figure 19(B), circuit 300A receives an L signal or an electric signal. The voltage V1 is maintained in a state where it is supplied to node A1. Therefore, the potential of node A1 is at the L level. It is maintained. Then, transistor 201A is kept in the off state, so wiring 112A The wiring 111 remains in a non-conductive state.

[0298] Furthermore, circuit 300A is kept in a state that supplies an H signal or voltage V2 to node A2. Therefore, the potential at node A2 is maintained at the H level. Then, transistor 202A is O Because it is kept in this state, wiring 113A and wiring 111 maintain a conductive state. The voltage V1 is maintained in a state where it is supplied to the wiring 111 via transistor 202A.

[0299] Meanwhile, during period d1, circuit 300B supplies an L signal or voltage V1 to node B1. This state is maintained. Therefore, the potential of node B1 is maintained at the L level. Then, Since the ZISTA 201B remains in the OFF state, wiring 112B and wiring 111 are not conductive. It holds.

[0300] Furthermore, circuit 300B is kept in a state that supplies an L signal or voltage V1 to node B2. Therefore, the potential of node B2 is maintained at the L level. Then, transistor 202B is O Since it remains in the "F" state, wiring 113B and wiring 111 remain in a non-conductive state.

[0301] Next, the operation of the semiconductor device during period a2 is as shown in Figure 20(A), in period a1. The operation is similar to that of a semiconductor device. However, when the signal SELA becomes L level, the signal S The difference is that the ELB becomes H level.

[0302] Next, the operation of the semiconductor device during period b2 is as shown in Figure 20(B), in period b1. The operation is similar to that of a semiconductor device. However, when the signal SELA becomes L level, the signal S The difference is that the ELB becomes H level.

[0303] Next, the operation of the semiconductor device during period c2 will be explained with reference to Figure 21(A). The operation of the semiconductor device during period c1 is that the signal SELA becomes L level, and the signal SEL The difference lies in the fact that B becomes an H level.

[0304] Since the signal SELA becomes L level, circuit 300A receives the L signal or voltage V1 at node A. It supplies power to 2. Therefore, transistor 202A is turned off, and wires 113A and 1 11 becomes a non-conductive state.

[0305] On the other hand, since the signal SELB becomes high, circuit 300B receives the high signal or voltage V2. It supplies power to B2. Therefore, transistor 202B turns on, and wiring 113B and The wiring 111 becomes conductive. Then, voltage V1 is distributed via transistor 202B. It is supplied to line 111.

[0306] Furthermore, during period c2, the timing at which the clock signal CK1 becomes low is as follows: The timing of the ZISTA201A turning off may be earlier. Until 201A is turned off, the low-level clock signal CK1 controls transistor 201A. It is preferable that the power is supplied to wiring 111 via this. Also, the channel width of transistor 201A is increased. This allows you to shorten the falling edge time of signal OUTA.

[0307] Furthermore, during period c2, the timing at which the clock signal CK1 becomes low is as follows: The timing may be earlier than when the ZISTA201B turns off. Until 201B is turned off, the low-level clock signal CK1 is applied to transistor 201B It is preferable that the power is supplied to wiring 111 via this. Also, the channel width of transistor 201B is increased. This allows you to shorten the falling edge time of signal OUTB.

[0308] During period c2, with respect to wiring 111, voltage V1 is transmitted through transistor 202B. When supplied to wiring 111, and when an L-level clock signal CK1 is supplied to transistor 201B When the voltage V1 is supplied to wiring 111 via transistor 202B, and when the voltage V1 is supplied to wiring 111 via transistor 202B A clock signal CK1, which is supplied to 111 and is at an L level, is transmitted via transistor 201B. There are three patterns: when it is supplied to wiring 111, and

[0309] Next, the operation of the semiconductor device during period d2 will be explained with reference to Figure 21(B). The operation of the semiconductor device during period d1 is such that the signal SELA becomes L level, and the signal SEL The difference lies in the fact that B becomes an H level.

[0310] Since the signal SELA becomes L level, circuit 300A receives the L signal or voltage V1 at node A. It supplies power to 2. Therefore, transistor 202A is turned off, and wires 113A and 1 11 becomes a non-conductive state.

[0311] On the other hand, since the signal SELB becomes high, circuit 300B receives the high signal or voltage V2. It supplies power to B2. Therefore, transistor 202B turns on, and wiring 113B and The wiring 111 becomes conductive. Then, voltage V1 is distributed via transistor 202B. It is supplied to line 111.

[0312] As described above, between transistors 202A and 202B, turn them on alternately. This suppresses the degradation of the characteristics of each transistor. As the semiconductor layer of the transistor, non-single-crystal semiconductors such as amorphous semiconductors or microcrystalline semiconductors are used. Materials that are prone to degradation, such as bodies, organic semiconductors, or oxide semiconductors, can be used. Therefore, when manufacturing semiconductor devices, the number of processes is reduced, the yield is increased, or costs are reduced. It is possible. Furthermore, when the semiconductor device of this embodiment is used as a display device, the semiconductor device Because the manufacturing method for the device becomes easier, the display device can be made larger.

[0313] Furthermore, it can suppress the degradation of transistor characteristics, thus reducing the risk of transistor degradation. There is no need to increase the channel width of the transistor out of consideration. Because the channel width can be reduced, the layout area can be reduced. Furthermore, when the semiconductor device of this embodiment is used as a display device, the layout of the gate driver circuit Because the area can be reduced, the pixel resolution can be increased. The channel width of the transistor can be reduced, thus reducing the load on the gate driver circuit. It can be cut. Therefore, the power consumption of the driver circuit having a gate driver circuit This can be reduced.

[0314] Furthermore, during periods b1 and b2, a high-level clock signal CK1 is transmitted to the transistor Since it is supplied to wiring 111 via 201A and transistor 201B, wiring 111 The rise or fall time of the supplied signal can be shortened. Therefore, This prevents video signals intended for pixels in another row from being written to pixels in a selected row. It can be stopped. As a result, crosstalk can be reduced, so the display device This can improve the quality of the displays.

[0315] Furthermore, the rise time or fall time of the signal supplied to wiring 111 is shortened. Therefore, when the scan signal corresponds to a start signal, etc., the gate driver circuit is driven. The frequency can be increased. Therefore, the semiconductor device of this embodiment can be used as a display device. In some cases, the display device can be made larger, or the pixel resolution can be increased.

[0316] Note that the waveforms of signals OUTA and OUTB during period T1 are shown in Figure 6(K) Corresponds to the rang chart. Note that the waveforms of signals OUTA and OUTB during period T1. Figures 6(A) to 6(L) can be used for this purpose.

[0317] Note that the waveforms of signals OUTA and OUTB during period T2 are shown in Figure 7(K) Corresponds to the rang chart. Note that the waveforms of signals OUTA and OUTB during period T2. Figures 7(A) to 7(L) can be used for this purpose.

[0318] Furthermore, the clock signal CK1 can be unbalanced. Figure 22 shows that, within one period, An example of semiconductor device operation when the period of being at H level is shorter than the period of being at L level. This is the timing chart shown. In the timing chart of Figure 22, period c1 or period c In step 2, a low-level clock signal CK1 can be supplied to the wiring 111, The falling time of signals OUTA and OUTB can be shortened. In particular, wiring 1 If 11 is formed by extending to the pixel area, video signals that should not be written to the pixel may be lost. This prevents the writing of numbers. Also, the period within one cycle that is at the H level is set to L level. It can be made for a longer period than the time it takes to become a bell.

[0319] Furthermore, a multiphase clock signal can be used in semiconductor devices. An n-phase (where n is a natural number) clock signal can be used. This refers to n clock signals, each with a period shifted by 1 / n periods. Figure 23 shows semiconductor Timing example showing the operation of a semiconductor device when a three-phase clock signal is used in the device. This is a chart.

[0320] Furthermore, the larger n is, the lower the clock frequency, thus reducing power consumption. Yes, it's possible. However, if n is too large, the number of signals increases, so the layout area will be larger. Alternatively, the scale of the external circuit becomes larger. Therefore, n should be smaller than 8, preferably n Let n be less than 6, and more preferably n=4 or n=3.

[0321] Furthermore, in periods c1, d1, c2, or d2, transistor 202A The transistor 202B can be turned on simultaneously. Therefore, the voltage V1 is When power is supplied to wiring 111 via transistors 202A and 202B, the wiring Since noise can be reduced, a semiconductor device that is less susceptible to noise can be obtained. It is possible.

[0322] Furthermore, in periods a1, b1, a2, or b2, transistor 201A And one of transistors 201B can be turned on. For example, period a1 and period In b1, transistor 201A is turned on and transistor 201B is turned off. This can be done. Alternatively, during periods a2 and b2, transistor 201A can be turned off. This allows transistor 201B to be turned on. Therefore, transistor 201A and Since the number of times each transistor (Rangista 201B) turns on will decrease, each transistor This can suppress the degradation of the ZISTA.

[0323] To realize such a drive method, for example, during period T1, the wiring 114B is connected The signal being powered is kept at an L level, and during period T2, the signal input to wiring 114A is maintained at an L level. It is best to maintain it at an L level. As another example, in circuit 200A, during period T1, the signal A circuit is provided that has the function of maintaining the potential of node A1 at an L level in response to SELA, and the circuit In 200B, during period T2, the potential of node B1 is set to L level in response to the signal SELB. It is advisable to provide a circuit that has a maintenance function.

[0324] <Transistor size> Next, we will discuss transistor size, including channel width and channel length. To clarify, when referring to the channel width of a transistor, the W / L (W is) of the transistor is... This can sometimes be rephrased as the channel width ratio (where L is the channel length).

[0325] The channel width of transistor 201A and the channel width of transistor 201B are approximately It is preferable that they be equal. Alternatively, the channel width of transistor 202A and transistor 2 It is preferable that the channel width of 02B be approximately equal to that of 02B.

[0326] In this way, by making the channel widths of the transistors roughly equal, the current supply capability is improved. This can be made roughly equal, or the degree of transistor degradation can be made roughly equal. Therefore, even if the selected transistor is switched, the waveform of the output signal OUT will remain roughly the same. It can be done.

[0327] For the same reason, the channel length of transistor 201A and transistor 201B The channel length is preferably approximately equal to that of transistor 202A. It is preferable that the length and the channel length of transistor 202B are approximately equal.

[0328] Note that the negative gate signal line connected to transistor 201A or transistor 201B When the load is large, in circuit 200A, more than the other transistors in circuit 200A Increase the channel width of transistor 201A, or in circuit 200B, circuit 20 By making the channel width of transistor 201B larger than that of other transistors in 0B This is preferable.

[0329] Note that the load of the gate signal line driven by transistor 201A or transistor 201B If the value is large, increase the channel width of transistor 201A or transistor 201B. It is preferable that the channel width of transistor 201A and transistor 2 The channel width of O1B is preferably 1000 μm to 30000 μm, more preferably 20 00 μm to 20000 μm, more preferably 3000 μm to 8000 μm or 1000 A range of 0 μm to 18,000 μm is recommended.

[0330] <Configuration of semiconductor device> Next, regarding an example of the configuration of the semiconductor device of this embodiment, a different semiconductor device from the one shown in Figure 16(A) will be used. An example of a circuit diagram for the device is explained with reference to Figure 16(B) and Figures 24(A) to 25(B). I will reveal it.

[0331] Figures 16(B) and 24(A) to 25(B) show examples of circuit diagrams for semiconductor devices. .

[0332] The semiconductor device shown in Figure 16(B) has the same transistors as the semiconductor device shown in Figure 16(A) This configuration corresponds to a configuration in which a capacitive element 203A is connected between the gate of TA201A and the second terminal. Alternatively, connect the capacitive element 203B between the gate and the second terminal of transistor 201B. It supports the configuration.

[0333] By using this configuration, during the bootstrap operation, the potential of node A1 or This makes it easier for the potential of node B1 to rise. Therefore, the gate and saw of transistor 201A The potential difference (Vgs) between the gate and source of transistor 201B, or the potential difference between the gate and source of transistor 201B. (Vgs) can be increased. As a result, transistor 201A or transistor The channel width of the TA201B can be reduced. Alternatively, the signal OUTA or signal OU The fall time or rise time of the TB can be shortened.

[0334] For capacitive elements 203A and 203B, for example, MOS capacitors can be used. It can be done. Furthermore, the material of one electrode of capacitive element 203A and capacitive element 203B is a transistor. It is preferable that the gates of transistors 201A and 201B be made of the same material. i. Alternatively, the material of the other electrode of capacitive element 203A and capacitive element 203B is a transistor The source and drain of transistors 201A and 201B are made of the same material, respectively. It is preferable to use such materials to reduce the layout area. This can be done, or the capacity value can be increased.

[0335] It is preferable that the capacitance values ​​of capacitive element 203A and capacitive element 203B are approximately equal. It seems. Or, in capacitive elements 203A and 203B, one electrode and the other electrode It is preferable that the area where the poles overlap is approximately equal. By adopting such a configuration, When a signal is input from circuit 200A to wiring 111, and when a signal is input from circuit 200B to wiring 111 When a signal is input, the wavelength of the signal input to wiring 111 is made approximately equal. can.

[0336] Furthermore, in the semiconductor device shown in Figures 16(A) and 16(B), as shown in Figure 24(A) As shown, transistor 201A is connected such that one electrode (for example, the positive electrode) is connected to node A1. The other electrode (for example, the negative electrode) is replaced with a diode 211A connected to the wiring 111. Alternatively, one electrode (e.g., the positive electrode) of transistor 202A may be connected to wiring 111. Diode 212A is connected to node A2, with the other electrode (for example, the negative electrode) connected to node A2. It can also be replaced with this.

[0337] Furthermore, transistor 201B is connected such that one electrode (for example, the positive electrode) is connected to node B1. The other electrode (for example, the negative electrode) is replaced by a diode 211B connected to the wiring 111. Alternatively, the transistor 202B may be connected to wiring 111, where one electrode (e.g., the positive electrode) is connected to the other electrode. Diode 212B is connected to node B2, with the other electrode (for example, the negative electrode) connected to node B2. It can also be replaced with this.

[0338] Furthermore, in the semiconductor device shown in Figures 16(A) and 16(B), as shown in Figure 24(B) As shown, the first terminal of transistor 201A may be connected to node A1. Also, The first terminal of transistor 202A is connected to node A2, and the transistor 202A The gate may be connected to wiring 111.

[0339] Alternatively, the first terminal of transistor 201B may be connected to node B1. The first terminal of transistor 202B is connected to node B2, and the transistor 202B The gate may be connected to wiring 111.

[0340] Next, there is a configuration that generates a transmission signal separately from signal OUTA, or signal OUTB An example of a semiconductor device having a configuration that generates a separate signal for transfer is shown in Figures 25(A) and 25(A) and 25(A). Refer to 25(B) for further explanation.

[0341] When a semiconductor device has multiple circuits (including circuits 200A and 200B), The transmission signal is not input to wiring 111, but is instead input to the next stage circuit as a start signal. This reduces the delay or distortion of the transmission signal to be smaller than that of signal OUTA or signal OUTB. Therefore, semiconductor devices can use signals with reduced delay or saturation. Because it can be driven, it can reduce the delay of the output signal of the semiconductor device. This allows the timing of charging node A1 or node B1 to be accelerated, so operation The range can be widened. Alternatively, the transmission signal may be output to wiring 111.

[0342] Therefore, the semiconductor shown in Figures 16(A), 16(B), 24(A), and 24(B) In the device, as shown in Figure 25(A), the first terminal is connected to the circuit 200A via wiring 112 It is connected to A, the second terminal is connected to wiring 117A, and the gate is connected to node A1. Transistor 204A may also be provided. Furthermore, the first terminal of circuit 200B is connected to wiring 11 It is connected to 2B, the second terminal is connected to wiring 117B, and the gate is connected to node B1. Alternatively, transistor 204B may be provided.

[0343] Alternatively, the semiconductor equipment shown in Figures 16(A), 16(B), 24(A), and 24(B) In this configuration, as shown in Figure 25(B), the first terminal of circuit 200A is connected to wiring 113A. The second terminal is connected to wiring 117A, and the gate is connected to node A2. A transistor 205A may be provided. Also, the first terminal of circuit 200B is connected to wiring 113B. The second terminal is connected to wiring 117B, and the gate is connected to node B2. Transistor 205B may be provided.

[0344] Note that transistor 204A has the same function as transistor 201A and has the same polarity. It is preferable that it has the same function as transistor 202A. It is preferable that it has the same polarity and is capable of doing so. Also, transistor 204B is a transistor It is preferable that it has the same function as the TA201B and has the same polarity. It is preferable that transistor 205B has the same function as transistor 202B and has the same polarity. Note that transistors 204A, 204B, 205A, and The Rangista 205B is an N-channel transistor and a P-channel transistor. You may also use this.

[0345] Furthermore, when multiple circuits of a semiconductor device are connected, wiring 117A is connected to another stage (e.g., For example, it may be connected to wiring 114A of the next stage semiconductor device. Also, wiring 117B is It may be connected to the wiring 114B of another semiconductor device (for example, the next stage). By having this configuration, wiring 117A and wiring 117B have the function of signal lines. .

[0346] Furthermore, when multiple circuits of a semiconductor device are connected, wiring 117A is connected to another stage (e.g., For example, it may be connected to the wiring 116A of the semiconductor device mentioned above. Also, wiring 117B is It may also be connected to wiring 116B of a semiconductor device in another stage (for example, the preceding stage). 17A may be extended and arranged in the pixel area. Also, wiring 117B may be extended in the pixel area. They may be arranged in this manner. With this configuration, wiring 117A and wiring 117 B functions as a gate signal line or a scan line.

[0347] <Configuration of semiconductor device> Next, an example of the configuration of the semiconductor device of this embodiment is shown in Figures 16(A) and 16(B). And, for an example of a circuit diagram of a semiconductor device different from Figures 24(A) to 25(B), see Figure 2 Refer to section 6 for further explanation.

[0348] The semiconductor device shown in Figure 26 is the same as the semiconductor device shown in Figure 16(A), but with transistor 2 This configuration supports the use of transistors 07A and 207B.

[0349] Transistor 207A has its first terminal connected to wire 113A, and its second terminal connected to wire 1 It is connected to 11, and its gate is connected to circuit 300A. Also, transistor 207B The first terminal is connected to wiring 113B, and the second terminal is connected to wiring 111, and the gate It is connected to circuit 300B.

[0350] Note that the connection point between the gate of transistor 207A and circuit 300A is node A3, and the transistor The connection point between the gate of inverter 207B and circuit 300B is indicated as node B3.

[0351] Furthermore, it is preferable that transistor 207A has the same function as transistor 202A. Furthermore, transistor 207B has the same function as transistor 202B. preferable.

[0352] <Semiconductor device operation> For an example of the operation of the semiconductor device shown in Figure 26, please refer to the timing chart shown in Figure 27. This will be explained. Figures 28(A) to 29(B) show an example of the operation of the semiconductor device in Figure 26. This is a diagram for explanation.

[0353] Transistors 202A and 207A have a gate selection period of 1 during period T1. It turns on alternately every interval, or every half-cycle of the clock signal CK1. For example, during period d1 During the period when the clock signal CK1 is at a high level, as shown in Figure 28(A), the transient Transistor 202A turns on, and transistor 207A turns off. Meanwhile, during period d1 During the period when the clock signal CK1 is at a low level, the transients are as shown in Figure 28(B). Transistor 202A turns off, and transistor 207A turns on.

[0354] Furthermore, transistors 202B and 207B have 1 gate during period T2. It turns on alternately during each selected period or every half-cycle of the clock signal CK1. For example, during period d During the period in which the clock signal CK1 is at a high level, as shown in Figure 29(A), Transistor 202B turns on, and transistor 207B turns off. Meanwhile, during period d2 During the period when the clock signal CK1 is at a low level, as shown in Figure 29(B), Transistor 202B turns off, and transistor 207B turns on.

[0355] Thus, during period T1, transistors 202A and 207A intersect. They turn on to each other, and during period T2, transistor 202B and transistor 207B They turn on alternately. This allows us to shorten the time each transistor is on. Therefore, the degradation of each transistor can be suppressed.

[0356] Alternatively, one of node A2 and node A3 may receive a clock signal CK2 (for example, a clock signal A wire may be connected to which the inverted signal of CK1 is input. Also, node B2 and A wire receiving the clock signal CK2 may be connected to one side of node B3.

[0357] Alternatively, during the same period (for example, period b1 or period b2), transistor 202A, Transistors 207A, 202B, and 207B are off. Alternatively, during the same period (for example, period a1 or period a2), the transition Transistor 202A, Transistor 207A, Transistor 202B, and Transistor 207B Two or more transistors may be turned on.

[0358] Alternatively, the order in which transistors 202A and 207A are turned on can be set arbitrarily. It is also acceptable for transistors 202B and 207B to be turned on in any order. You may set it to that.

[0359] Next, regarding an example of the operation of the semiconductor device in Figure 26, a different timing chart from Figure 27 will be used. Regarding point T, please refer to Figure 30 for further explanation.

[0360] Transistor 202A, Transistor 207A, Transistor 202B, and Transistor Sta207B may be turned on every frame period. In Figure 30, during period T1 Of these, the period during which transistor 202A is ON is period T1a, and the period during which transistor 207A is ON is... The period during which the transistor is ON is denoted as period T1b. Furthermore, during period T2, transistor 202B is ON. The period during which this occurs is denoted as period T2a, and the period during which transistor 207B is turned on is denoted as period T2b.

[0361] In addition, in the timing chart of Figure 30, periods T1a, T2a, T1b, and This shows the case where periods T2b are arranged sequentially, but the order of these periods is arbitrary. You can also set it up as follows: for example, arrange it in the order of period T1a, period T1b, period T2a, and period T2b. They may be arranged in multiple time periods or randomly.

[0362] During period d1 of period T1a, the potential at node A2 becomes H level, and the potential at node A3 ( The potential of node A3 (also referred to as potential Va3), the potential of node B2, and the potential of node B3 The potential (the potential at node B3 is also referred to as potential Vb3) becomes L level. Therefore, As shown in Figure 28(A), transistor 202A turns on, and transistor 207A Transistors 202B and 207B are turned off.

[0363] During period d1 of period T1b, the potential at node A3 becomes H level, and the potential at node A2, The potentials at node B2 and node B3 become L level. Therefore, Figure 28(B) As shown, transistor 207A turns on, and transistor 202A, transistor Transistors 202B and 207B are turned off.

[0364] During period d2 of period T2a, the potential at node B2 becomes H level, and the potential at node A2, The potentials at node A3 and node B3 become L level. Therefore, Figure 29(A) As shown, transistor 202B turns on, and transistor 202A, transistor Transistors 207A and 207B are turned off.

[0365] During period d2 of period T2b, the potential at node B3 becomes H level, and the potential at node A2, The potentials at node A3 and node B2 become L level. Therefore, Figure 29(B) As shown, transistor 207B turns on, transistor 202A, transistor Transistors 207A and 202B are turned off.

[0366] The semiconductor device shown in Figure 26 turns on the transistor when it performs the above operation. The time can be shortened. Or, a signal to control the conduction state of a transistor. Because the frequency can be lowered, power consumption can be reduced.

[0367] Alternatively, the first terminal may be connected to wiring 113A and the second terminal may be connected to wiring 111. Multiple transistors may be provided. These multiple transistors are transistor 202A or It has the same function as transistor 207A. And these multiple transistors are 1 You can turn them on sequentially, either during each gate selection period or every frame.

[0368] Furthermore, the first terminal is connected to wiring 113B, and the second terminal is connected to wiring 111. Multiple transistors may be provided. These multiple transistors are transistor 202B or It has the same function as transistor 207B. And these multiple transistors are 1 You can turn them on sequentially, either during each gate selection period or every frame.

[0369] By providing multiple transistors in this way, each transistor turns on. This shortens the time required, thus suppressing the degradation of each transistor. can.

[0370] (Embodiment 5) In this embodiment, a semiconductor device having the gate driver circuit described in the above embodiment is provided. I will explain this.

[0371] <Configuration of semiconductor device> The configuration of the semiconductor device in this embodiment is shown with reference to Figures 31(A) and 31(B). Let me explain. Figures 31(A) and 31(B) show examples of circuit diagrams for semiconductor devices.

[0372] In Figure 31(A), circuit 300A consists of transistor 301A and transistor 302 Circuit 300B has transistor 301B and transistor 400A. It has circuit 302B and circuit 400B.

[0373] Transistor 301A, Transistor 302A, Circuit 400A, Transistor 301B For an example of the configuration of transistor 302B and circuit 400B, see Figure 31(A). Let's explain. Here, transistor 301A, transistor 302A, transistor 3 01B and transistor 302B will be described as N-channel transistors. These transistors may also be P-channel transistors.

[0374] Transistor 301A has its first terminal connected to wire 114A and its second terminal connected to a node It is connected to A1 and its gate is connected to wiring 114A. Transistor 302A is the first The terminal is connected to wiring 113A, the second terminal is connected to node A1, and the gate is connected to wiring 11 It is connected to 6A. Circuit 400A is connected to wiring 115A, node A1, wiring 113A, and node A1. It connects to code A2.

[0375] Transistor 301B has its first terminal connected to wiring 114B and its second terminal connected to a node It is connected to B1 and its gate is connected to wiring 114B. Transistor 302B is the first The terminal is connected to wiring 113B, the second terminal is connected to node B1, and the gate is connected to wiring 11 It is connected to 6B. Circuit 400B is connected to wiring 115B, node B1, wiring 113B, and It connects to B2.

[0376] Next, transistor 301A, transistor 302A, circuit 400A, transistor 3 An example of the functions of 01B, transistor 302B, and circuit 400B will be described.

[0377] Transistor 301A controls the timing of the conductivity between wiring 114A and node A1. It has the function of raising the potential of wiring 114A to node A1. It has a function to control the timing of supply. Alternatively, transistor 301A is connected to wiring 1 Signals or voltages supplied to 14A (for example, start signal SP, clock signal CK1, The clock signal CK2, signal SELA, signal SELB, or voltage V2) is supplied to node A1. It has a function to control the timing of the signal or electricity. Alternatively, transistor 301A has a function to control the timing of the signal or electricity. It has a function to control the timing at which pressure, etc., is not supplied to node A1. Or, the transistor The TA301A has a function to control the timing of supplying the H signal or voltage V2 to node A1. It has. Or, transistor 301A has the timing to raise the potential of node A1. It has a control function. Alternatively, transistor 301A puts node A1 into a floating state. It has a function to control the timing.

[0378] Thus, transistor 301A is a switch, rectifier, diode, or dio It functions as a transistor with a standard connection. Note that transistor 301A is a standard It may be controlled according to the signal SP.

[0379] Transistor 302A controls the timing of the conductivity between wiring 113A and node A1. It has the function of raising the potential of wiring 113A to node A1. Alternatively, transistor 302A raises the potential of wiring 113A to node A1. It has a function to control the timing of supply. Alternatively, transistor 302A is connected to wiring 1 The signal or voltage supplied to 13A (for example, the clock signal CK2 or voltage V1) It has a function to control the timing of supply to code A1. Alternatively, transistor 302A It has the function of controlling the timing of supplying voltage V1 to node A1. Or, The generator 302A has the function of controlling the timing of reducing the potential of node A1. Alternatively, transistor 302A controls the timing of maintaining the potential of node A1. It has a function.

[0380] Thus, transistor 302A functions as a switch. The ZISTA 302A may be controlled in accordance with the reset signal RE.

[0381] Circuit 400A has the function of controlling the potential of node A2. Alternatively, circuit 400A is It has a function to control the timing of supplying signals or voltages, etc., to node A2. Or, Circuit 400A has a function to control the timing at which signals or voltages are not supplied to node A2. It has. Or, circuit 400A supplies an H signal or voltage V2 to node A2 at the timing It has the function of controlling the signal. Alternatively, circuit 400A receives the L signal or voltage V1 from node A2 It has a function to control the timing of supply to Node A2. Alternatively, Circuit 400A is It has a function to control the timing of raising the potential. Alternatively, circuit 400A is node It has a function to control the timing of decreasing the potential of A2. Alternatively, circuit 400A is It has a function to control the timing of maintaining the potential of node A2.

[0382] Thus, circuit 400A functions as a control circuit. It may be controlled according to the signal SELA or the potential of node A1.

[0383] Transistor 301B controls the timing of the conduction between wiring 114B and node B1. It has the function of raising the potential of wiring 114B to node B1. Alternatively, transistor 301B raises the potential of wiring 114B to node B1. It has a function to control the timing of supply. Alternatively, transistor 301B is connected to wiring 1 Signals or voltages supplied to 14B (for example, start signal SP, clock signal CK1, The clock signal CK2, signal SELA, signal SELB, or voltage V2 are supplied to node B1. It has a function to control the timing of the signal or electricity. Alternatively, transistor 301B has a function to control the timing of the signal or electricity. It has a function to control the timing at which pressure, etc., is not supplied to node B1. Or, the transistor The 301B has a function to control the timing of supplying the H signal or voltage V2 to node B1. It has. Or, transistor 301B has the timing to raise the potential of node B1. It has a control function. Alternatively, transistor 301B puts node B1 into a floating state. It has a function to control the timing.

[0384] Thus, transistor 301B is a switch, rectifier, diode, or dio It functions as a transistor with a standard connection. Note that transistor 301B is a standard It may be controlled according to the signal SP.

[0385] Transistor 302B controls the timing of the conduction between wiring 113B and node B1. It has the function of raising the potential of wiring 113B to node B1. Alternatively, transistor 302B raises the potential of wiring 113B to node B1. It has a function to control the timing of supply. Alternatively, transistor 302B is connected to wiring 1. The signal or voltage supplied to 13B (for example, the clock signal CK2 or voltage V1) It has a function to control the timing of supply to the B1. Alternatively, transistor 302B It has the function of controlling the timing of supplying voltage V1 to node B1. Or, The converter 302B has the function of controlling the timing of the reduction in the potential of node B1. Alternatively, transistor 302B controls the timing of maintaining the potential of node B1. It has a function.

[0386] Thus, transistor 302B functions as a switch. The ZISTA 302B may be controlled in accordance with the reset signal RE.

[0387] Circuit 400B has the function of controlling the potential of node B2. Alternatively, circuit 400B is It has a function to control the timing of supplying signals or voltages, etc., to node B2. Or, Circuit 400B has a function to control the timing at which signals or voltages are not supplied to node B2. It has. Or, circuit 400B supplies an H signal or voltage V2 to node B2 at the timing It has a function to control the signal. Alternatively, circuit 400B receives the L signal or voltage V1 from node B2 It has a function to control the timing of supply to node B2. Alternatively, circuit 400B is node B2 It has a function to control the timing of raising the potential. Alternatively, circuit 400B is node It has a function to control the timing of decreasing the potential of B2. Alternatively, circuit 400B is It has a function to control the timing of maintaining the potential of node B2.

[0388] Thus, circuit 400B has the function of a control circuit. It may be controlled according to the signal SELB or the potential of node B1.

[0389] Next, an example of the configuration of circuits 400A and 400B is shown with reference to Figure 31(B). explain.

[0390] Circuit 400A has transistors 401A and 402A. Circuit 40 0B has transistors 401B and 402B.

[0391] Transistor 401A, Transistor 402A, Transistor 401B, and Trans An example of the configuration of ST402B will be explained with reference to Figure 31(B). Here, Transistor 401A, Transistor 402A, Transistor 401B, and Transistor 40 2B will be described as an N-channel transistor. Note that these transistors are P A channel transistor may also be used.

[0392] Transistor 401A has its first terminal connected to wire 115A and its second terminal connected to a node It is connected to A2 and its gate is connected to wiring 115A. Transistor 402A is the first The terminal is connected to wiring 113A, the second terminal is connected to node A2, and the gate is node A It is connected to 1.

[0393] Transistor 401B has its first terminal connected to wiring 115B and its second terminal connected to a node It is connected to B2 and its gate is connected to wiring 115B. Transistor 402B is the first The terminal is connected to wiring 113B, the second terminal is connected to node B2, and the gate is node B It is connected to 1.

[0394] Next, transistors 401A, 402A, 401B, and This section describes an example of the functions of the Rangista 402B.

[0395] Transistor 401A controls the timing of the conductivity between wiring 115A and node A2. It has the function of raising the potential of wiring 115A to node A2. Alternatively, transistor 401A raises the potential of wiring 115A to node A2. It has a function to control the timing of supply. Alternatively, transistor 401A is connected to wiring 1 The signal or voltage supplied to 15A (for example, signal SELA or voltage V2) is connected to node A It has a function to control the timing of supplying to 2. Alternatively, transistor 401A is signal It has a function to control the timing of when it does not supply a signal or voltage to node A2. Or, The 401A inverter controls the timing of supplying the H signal or voltage V2, etc., to node A2. It has the function of raising the potential of node A2. Alternatively, transistor 401A raises the potential of node A2. It has a function to control the ming.

[0396] Thus, transistor 401A is a switch, rectifier, diode, or dio It functions as a transistor with a code connection. Note that transistor 401A is a signal It may be controlled according to SELA.

[0397] Transistor 402A controls the timing of the conductivity between wiring 113A and node A2. It has the function of raising the potential of wiring 113A to node A2. Alternatively, transistor 402A raises the potential of wiring 113A to node A2. It has a function to control the timing of supply. Alternatively, transistor 402A is connected to wiring 1 The signal or voltage supplied to 13A (for example, the clock signal CK2 or voltage V1) It has a function to control the timing of supply to the A2. Alternatively, transistor 402A It has the function of controlling the timing of supplying voltage V1 to node A2. Or, The 402A converter has the function of controlling the timing of the reduction in the potential of node A2. Alternatively, transistor 402A controls the timing of maintaining the potential of node A2. It has a function.

[0398] Thus, transistor 402A functions as a switch. The zista 402A may be controlled according to the potential of node A1 or the potential of wiring 111.

[0399] Transistor 401B controls the timing of the conduction between wiring 115B and node B2. It has the function of raising the potential of wiring 115B to node B2. Alternatively, transistor 401B raises the potential of wiring 115B to node B2. It has a function to control the timing of supply. Alternatively, transistor 401B is connected to wiring 1 The signal or voltage (e.g., signal SELB or voltage V2) supplied to 15B is sent to node B It has a function to control the timing of supplying to 2. Alternatively, transistor 401B is signal It has a function to control the timing of when it does not supply a signal or voltage to node B2. Or, The 401B inverter controls the timing of supplying the H signal or voltage V2, etc., to node B2. It has the function of raising the potential of node B2. Alternatively, transistor 401B raises the potential of node B2. It has a function to control the ming.

[0400] Thus, transistor 401B is a switch, rectifier, diode, or dio It functions as a transistor with a code connection. Note that transistor 401B is a signal It may be controlled according to SELB.

[0401] Transistor 402B controls the timing of the conduction between wiring 113B and node B2. It has the function of raising the potential of wiring 113B to node B2. Alternatively, transistor 402B raises the potential of wiring 113B to node B2. It has a function to control the timing of supply. Alternatively, transistor 402B is connected to wiring 1 The signal or voltage supplied to 13B (for example, the clock signal CK2 or voltage V1) It has a function to control the timing of supply to the B2. Alternatively, transistor 402B It has the function of controlling the timing of supplying voltage V1 to node B2. Or, The 402B generator has the function of controlling the timing of the reduction in the potential of node B2. Alternatively, transistor 402B controls the timing of maintaining the potential of node B2. It has a function.

[0402] Thus, transistor 402B functions as a switch. The zista 402B may be controlled according to the potential of node B1 or the potential of wiring 111.

[0403] <Semiconductor device operation> Next, regarding an example of the operation of the semiconductor device shown in Figure 31(B), see Figures 32(A) to 35(B). This will be explained by referring to Figures 32(A) to 35(B), respectively, which describe the period described in Embodiment 4. Period a1, Period b1, Period c1, Period d1, Period a2, Period b2, Period c2, Period d2 This corresponds to a schematic diagram of a semiconductor device.

[0404] Note that the semiconductor device in Figure 31(B) has a portion that is common with the semiconductor device in Figure 16(A). The operation in this case will be explained by referring to the timing chart in Figure 17.

[0405] First, as shown in Figure 32(A), during period a1, the start signal SP reaches the H level. Therefore, transistor 301A turns on, and the connection between wiring 114A and node A1 is It becomes conductive. Then the H-level start signal SP is transmitted through transistor 301A. Since it is supplied to node A1, the potential of node A1 rises.

[0406] Eventually, the potential of node A1 will be equal to the potential of the gate of transistor 301A (for example, voltage V). 2) From this, the threshold voltage (Vth) of transistor 301A 301A The value obtained by subtracting (V2-Vt) h 301AAt this point, transistor 301A turns off. Therefore, wiring 11 Since 4A and node A1 become non-conductive, the potential of node A1 rises. Node A1 When the potential rises, transistor 402A turns on, so wiring 113A and node A 2 becomes conductive. Then, voltage V1 is transmitted to node A2 via transistor 402A. It is supplied to.

[0407] Furthermore, during period a1, the signal SELA becomes high. Therefore, transistor 40 Since 1A is turned on, wiring 115A and node A2 become conductive. As a result, H The bell signal SELA is supplied to node A2 via transistor 401A. The current supply capacity of transistor 402A is greater than that of transistor 401A. (For example, the channel width of transistor 402A is the channel width of transistor 401A) By making it larger than the width, the potential of node A2 becomes L level.

[0408] Furthermore, during period a1, the reset signal RE becomes low. Therefore, the transistor Since 302A is turned off, wiring 113A and node A1 become non-conductive.

[0409] On the other hand, during period a1, the start signal SP becomes high level. Therefore, the transistor 301B turns on, so wiring 114B and node B1 become conductive. Then H The level start signal SP is supplied to node B1 via transistor 301B. Then, the potential of node B1 rises.

[0410] Eventually, the potential of node B1 will be equal to the potential of the gate of transistor 301B (for example, voltage V). 2) From this, the threshold voltage (Vth) of transistor 301B 301B The value obtained by subtracting (V2-Vt) h 301B At this point, transistor 301B turns off. Therefore, wiring 11 Since 4B and node B1 become non-conductive, the potential of node B1 rises. Node B1 When the potential rises, transistor 402B turns on, so wiring 113B and node B 2 becomes conductive. Then, voltage V1 is transmitted to node B2 via transistor 402B. It is supplied to.

[0411] Furthermore, during period a1, the signal SELB becomes L level. Therefore, transistor 40 Since 1B is turned off, wiring 115B and node B2 become non-conductive. As a result, The potential of line B2 will be at the L level.

[0412] Furthermore, during period a1, the reset signal RE becomes low. Therefore, the transistor Since 302B is turned off, wiring 113B and node B1 become non-conductive.

[0413] Next, as shown in Figure 32(B), during period b1, the start signal SP is at the L level. Therefore, transistor 301A remains in the off state, and is no longer connected to wiring 114A. A1 maintains a non-conductive state.

[0414] Furthermore, during period b1, the reset signal RE is maintained at the L level. Therefore, Since transistor 302A remains in the off state, there is no conductivity between wiring 113A and node A1. The state is maintained. The potential of node A1 rises due to the bootstrap operation. Therefore Since transistor 402A remains in the ON state, the wire 113A and node A2 are connected. Maintain the normal state.

[0415] Furthermore, during period b1, the signal SELA is maintained at the H level. Therefore, Since the ZISTA 401A remains in the ON state, there is continuity between wiring 115A and node A2. Maintain this state. As a result, the potential at node A2 is maintained at the L level.

[0416] On the other hand, during period b1, when the start signal SP becomes L level, transistor 301 Since B remains in the off state, wiring 114B and node B1 remain in a non-conductive state.

[0417] Furthermore, during period b1, the reset signal RE is maintained at the L level. Therefore, Since transistor 302B remains in the off state, there is no conductivity between wiring 113B and node B1. The state is maintained. The potential of node B1 increases due to the bootstrap operation. Therefore Since transistor 402B remains in the ON state, the wiring 113B and node B2 are connected. Maintain the normal state.

[0418] Furthermore, during period b1, the signal SELB is maintained at the L level. Therefore, Since the zista 401B remains in the off state, there is no conductivity between wiring 115B and node B2. This maintains the L level. As a result, the potential at node B2 is maintained at the L level.

[0419] Next, as shown in Figure 33(A), during period c1, the start signal SP is at the L level. It is maintained. Therefore, transistor 301A remains in the off state, so wiring 11 4A and node A1 remain in a non-conductive state.

[0420] Furthermore, during period c1, the reset signal RE becomes high. Therefore, the transistor Since 302A turns on, wiring 113A and node A1 become conductive. Then, Voltage V1 is supplied to node A1 via transistor 302A, so the power of node A1 The voltage decreases and becomes L level. When the potential of node A1 becomes L level, transistor 40 Since 2A is turned off, wiring 113A and node A2 become non-conductive.

[0421] Furthermore, during period c1, the signal SELA is maintained at a high level. Therefore, Since the ZISTA 401A remains in the ON state, there is continuity between wiring 115A and node A2. Hold. Then, the H-level signal SELA is sent to node A via transistor 401A. Since it is supplied to node 2, the potential at node A2 rises and reaches the H level.

[0422] On the other hand, during period c1, the start signal SP is maintained at the L level. Therefore, Since transistor 301B remains in the off state, there is no conductivity between wiring 114B and node B1. Maintain the state.

[0423] Furthermore, during period c1, the reset signal RE becomes high. Therefore, the transistor 302B turns on, so wiring 113B and node B1 become conductive. Then the power Voltage V1 is supplied to node B1 via transistor 302B, so the power of node B1 The voltage decreases and becomes L level. When the potential of node B1 becomes L level, transistor 40 Since 2B is turned off, wiring 113B and node B2 become non-conductive.

[0424] Furthermore, during period c1, the signal SELB is maintained at the L level. Therefore, Since the zista 401B remains in the off state, there is no conductivity between wiring 115B and node B2. This maintains the state. As a result, node B2 becomes floating, and the potential of node B2 is at the L level. It is maintained.

[0425] Next, as shown in Figure 33(B), during period d1, the start signal SP is at the L level. It is maintained. Therefore, transistor 301A remains in the off state, so wiring 11 4A and node A1 remain in a non-conductive state.

[0426] Furthermore, during period d1, the reset signal RE becomes low. Therefore, the transistor Since 302A is turned off, wiring 113A and node A1 become non-conductive. Then, Node A1 becomes floating, and the potential of node A1 is maintained at the L level. Therefore, Since inverter 402A remains in the off state, there is no conductivity between wiring 113A and node A2. Maintain the state.

[0427] Furthermore, during period d1, the signal SELA is maintained at the H level. Therefore, Since the ZISTA 401A remains in the ON state, there is continuity between wiring 115A and node A2. Hold. Then, the H-level signal SELA is sent to node A via transistor 401A. Since it is supplied to node 2, the potential at node A2 rises and reaches the H level.

[0428] On the other hand, during period d1, the start signal SP is maintained at the L level. Therefore, Since transistor 301B remains in the off state, there is no conductivity between wiring 114B and node B1. Maintain the state.

[0429] Furthermore, during period d1, the reset signal RE becomes low. Therefore, the transistor Since 302B is turned off, wiring 113B and node B1 become non-conductive. Then, Node B1 becomes floating, and the potential of node B1 is maintained at the L level. Therefore, Since inverter 402B remains in the off state, there is no conductivity between wiring 113B and node B2. Maintain the state.

[0430] Furthermore, during period d1, the signal SELB is maintained at the L level. Therefore, Since the zista 401B remains in the off state, there is no conductivity between wiring 115B and node B2. This maintains the floating state. As a result, node A2 remains floating, and the potential of node B2 is L. It is maintained by the bell.

[0431] Next, the operation of the semiconductor device during period a2 will be explained with reference to Figure 34(A). The difference between the semiconductor device and its operation during period a1 shown in Figure 32(A) is the signal SEL. This is the point where A becomes low and signal SELB becomes high.

[0432] Therefore, transistor 401A is turned off, and wiring 115A and node A2 are decoupled. It enters a normal state.

[0433] On the other hand, transistor 401B turns on, so there is conductivity between wiring 115B and node B2. This is the state. Therefore, the H-level signal SELB is transmitted through transistor 401B to node B. It is supplied to 2. Here, the current supply capability of transistor 402B is compared to that of transistor 401B. Make it larger than the current supply capacity (for example, the channel width of transistor 402B is greater than the current supply capacity of transistor 402B). By making it larger than the channel width of the ZISTA 401B, the potential of node B2 becomes L It becomes a bell.

[0434] Next, the operation of the semiconductor device during period b2 will be explained with reference to Figure 34(B). The difference between the semiconductor device and its operation during period b1 shown in Figure 32(B) is the signal SEL. This is the point where A becomes low and signal SELB becomes high.

[0435] Therefore, transistor 401A remains in the off state, and wiring 115A and node A 2 becomes a non-conductive state.

[0436] On the other hand, transistor 401B remains in the ON state, so wiring 115B and node B2 This means maintaining a conductive state.

[0437] Next, the operation of the semiconductor device during period c2 will be explained with reference to Figure 35(A). The difference between the semiconductor device and its operation during period c1 shown in Figure 33(A) is the signal SEL. This is the point where A becomes low and signal SELB becomes high.

[0438] Therefore, transistor 401A remains in the off state, and wiring 115A and node A Node 2 becomes non-conductive. As a result, node A2 becomes floating, and its potential is at level L. It will be maintained.

[0439] On the other hand, transistor 401B remains in the ON state, so wiring 115B and node B2 This maintains a conductive state. Therefore, the H-level signal SELB is transmitted to transistor 401B. Since it is supplied to node B2 via this route, the potential of node B2 increases.

[0440] Next, the operation of the semiconductor device during period d2 will be explained with reference to Figure 35(B). The difference between the semiconductor device and its operation during period d1 shown in Figure 33(B) is the signal SEL. This is the point where A becomes low and signal SELB becomes high.

[0441] Therefore, transistor 401A remains in the off state, and wiring 115A and node A Node 2 becomes non-conductive. As a result, node A2 becomes floating, and its potential is at level L. It will be maintained.

[0442] On the other hand, transistor 401B remains ON, so wiring 115B and node B2 This maintains a conductive state. Therefore, the H-level signal SELB is transmitted through transistor 401B. Since it is supplied to node B2 via this, the potential of node B2 is maintained at the H level.

[0443] <Transistor size> Next, let's discuss the size of the transistor, such as its channel width and channel length. explain.

[0444] The channel width of transistor 301A and the channel width of transistor 301B are approximately It is preferable that they be equal. Alternatively, the channel width of transistor 302A and transistor 3 The channel width of 02B is preferably approximately equal to that of transistor 401A. It is preferable that the channel width and the channel width of transistor 401B are approximately equal. For example, the channel width of transistor 402A and the channel width of transistor 402B are, It is preferable that they are approximately equal.

[0445] In this way, by making the channel widths of the transistors roughly equal, the current supply capability is improved. This can be made roughly equal, or the degree of transistor degradation can be made roughly equal. Therefore, even if the selected transistor is switched, the waveform of the output signal OUT will remain roughly the same. It can be done.

[0446] For the same reason, the channel length of transistor 301A and transistor 301B The channel length is preferably approximately equal to that of transistor 302A. It is preferable that the length and the channel length of transistor 302B are approximately equal. The channel length of transistor 401A and the channel length of transistor 401B are approximately equal. It is preferable that the channel length of transistor 402A and transistor 402 It is preferable that the channel length of B is approximately equal to that of B.

[0447] Specifically, the channel width of transistor 301A and the channel of transistor 301B The width is preferably 500 μm to 3000 μm, more preferably 800 μm to 2500 μm. More preferably, the particle size should be between 1000 μm and 2000 μm.

[0448] Furthermore, the channel width of transistor 302A and the channel width of transistor 302B are set as follows: Preferably 100 μm to 3000 μm, more preferably 300 μm to 2000 μm, further Preferably, the particle size should be between 300 μm and 1000 μm.

[0449] Furthermore, the channel width of transistor 401A and the channel width of transistor 401B are as follows: Preferably 100 μm to 2000 μm, more preferably 200 μm to 1500 μm, further Preferably, the thickness should be between 300 μm and 700 μm.

[0450] Furthermore, the channel width of transistor 402A and the channel width of transistor 402B are: Preferably 300 μm to 3000 μm, more preferably 500 μm to 2000 μm, further Preferably, the thickness should be between 700 μm and 1500 μm.

[0451] <Configuration of semiconductor device> Next, regarding an example of the semiconductor device circuit of this embodiment, a different semiconductor device from the one shown in Figure 31(B) is shown. An example of a circuit diagram for the main unit will be explained with reference to Figures 36(A) to 41(B).

[0452] Figures 36(A) to 41(B) show examples of circuit diagrams for semiconductor devices.

[0453] The semiconductor device shown in Figure 36(A) has the same transistors as the semiconductor device shown in Figure 31(B) The first terminal of transistor 202A, the first terminal of transistor 302A, and transistor 402A The first terminal corresponds to a configuration in which it is connected to separate wiring. Alternatively, as shown in Figure 31(B). The first terminal of transistor 202B and the first terminal of transistor 302B of the semiconductor device This corresponds to a configuration where the terminal and the first terminal of transistor 402B are connected by separate wiring. .

[0454] In Figure 36(A), wiring 113A is divided into multiple parts, from wiring 113A_1 to wiring 113A_3. It is divided into the following wirings. Wiring 113B is divided into multiple wirings, from wiring 113B_1 to wiring 113B_3. The wiring is divided into the following. The first terminal of transistor 202A is connected to wiring 113A_1. The first terminal of transistor 302A is connected to wiring 113A_2, and transistor 40 The first terminal of 2A is connected to wiring 113A_3. The first terminal of transistor 202B It is connected to wiring 113B_1, and the first terminal of transistor 302B is connected to wiring 113B_2 The first terminal of transistor 402B is connected to wire 113B_3.

[0455] Note that wiring 113A_1 to wiring 113A_3 have the same function as wiring 113A, and Lines 113B_1 to 113B_3 have the same function as wiring 113B. Wiring 113A_1 to 113A_3 and wiring 113B_1 to 113B_3 are, It can supply voltages such as voltage V1. Alternatively, wiring 113A_1~wiring 113A_ 3 may be supplied with separate voltages or separate signals. Alternatively, wiring 113B_1~ wiring 113B_3 may be supplied with different voltages or different signals.

[0456] Furthermore, in the configuration shown in Figures 31(B) and 36(A), as shown in Figure 37(A) Transistor 302A has one electrode (for example, the positive electrode) connected to node A1, and the other electrode connected to node A1. Even if the electrode (for example, the negative electrode) is replaced with diode 312A connected to wiring 116A Good. Alternatively, connect transistor 402A so that one electrode (e.g., the positive electrode) is in contact with node A2. The other electrode (for example, the negative electrode) is connected to diode 412A, which is connected to node A1. You may replace it.

[0457] Furthermore, transistor 302B is connected such that one electrode (for example, the positive electrode) is connected to node B1. The other electrode (for example, the negative electrode) is replaced by a diode 312B connected to wiring 116B. Alternatively, one electrode (e.g., the positive electrode) of transistor 402B may be connected to node B. Diode 412 is connected to node 2, with the other electrode (e.g., the negative electrode) connected to node B1. You may substitute B.

[0458] Furthermore, in the configuration shown in Figures 31(B) and 36(A), as shown in Figure 37(B) The first terminal of transistor 302A is connected to wiring 116A, and transistor 302A The gate of the transistor may be connected to node A1, or to the first terminal of transistor 402A. Even if it is connected to node A1 and the gate of transistor 402A is connected to node A2, stomach.

[0459] Furthermore, the first terminal of transistor 302B is connected to wiring 116B, and transistor 3 The gate of 02B may be connected to node B1. Alternatively, the first of transistor 402B The terminal of is connected to node B1, and the gate of transistor 402B is connected to node B2. That's fine.

[0460] Furthermore, the configuration shown in Figures 31(B), 36(A), 37(A), and 37(B) As shown in Figure 38(A), the gate of transistor 402A is connected to wiring 111. It is also possible that the gate of transistor 402B is connected to wiring 111.

[0461] Furthermore, the configuration shown in Figures 31(B), 36(A), and 37(A) to 38(A) As shown in Figure 38(B), the first terminal of transistor 301A is connected to wiring 118A. The gate of transistor 301A may be connected to wiring 114A. The first terminal of transistor 301B is connected to wiring 118B, and the gate of transistor 301B The wire may be connected to wiring 114B.

[0462] Alternatively, the first terminal of transistor 301A is connected to wiring 114A, and the transistor The gate of 301A may be connected to wiring 118A. Also, the gate of transistor 301B The first terminal is connected to wire 114B, and the gate of transistor 301B is connected to wire 118 It may be connected to B.

[0463] Furthermore, if voltage V2 is supplied to wiring 118A and wiring 118B, wiring 118A and Wiring 118B functions as a power line. Alternatively, wiring 118A and wiring 118B A clock signal CK2 may be input to this. Alternatively, the wiring 118A and wiring 118B may be connected to this. Separate voltages or separate signals may be supplied.

[0464] Note that if the same voltage is input to wiring 118A and wiring 118B, wiring 118A and wiring 118B may be connected. Also, in this case, the same applies to wiring 118A and wiring 118B. Wiring may be used.

[0465] Furthermore, the configuration shown in Figures 31(B), 36(A), and 37(A) to 38(B) Then, as shown in Figure 39(A), replace transistor 401A with resistor element 403A. It is also acceptable. Resistor element 403A is connected between wiring 115A and node A2. As shown in Figure 39(B), transistor 401B may be replaced with resistor element 403B. The resistor element 403B is connected between wiring 115B and node B2.

[0466] By using the configuration shown in Figures 39(A) and 39(B), period c1 and period d1 In this configuration, a low-level signal SELB can be supplied to node B2. Alternatively, During interval c2 and period d2, a low-level signal SELA is supplied to node A2. Yes, it is possible. Therefore, the potentials of node A2 and node B2 can be fixed, This makes it possible to obtain semiconductor devices that are less susceptible to noise.

[0467] Furthermore, the configuration shown in Figures 31(B), 36(A), and 37(A) to 38(B) Then, as shown in Figure 39(C), the first terminal is connected to wiring 115A, and the second terminal is A transistor 404A is provided, which is connected to node A2 and whose gate is also connected to node A2. This is also acceptable. Furthermore, as shown in Figure 39(D), the first terminal is connected to wiring 115B, and the second terminal is connected to wiring 115B. The terminals of transistor 404B are connected to node B2, and the gate is also connected to node B2. You may provide one.

[0468] By adopting the configuration shown in Figures 39(C) and 39(D), Figures 39(A) and 3 Similar to case 9(B), the potentials of node A2 and node B2 can be fixed. Therefore, it is possible to obtain semiconductor devices that are less susceptible to noise.

[0469] Furthermore, the configuration shown in Figures 31(B), 36(A), and 37(A) to 39(D) As shown in Figure 39(E), the first terminal of circuit 400A is connected to wiring 115A. The second terminal is connected to node A2, and the gate is connected to the second terminal of transistor 401A. The connection point between the second terminal of transistor 402A and transistor 405A, The first terminal is connected to wiring 113A, the second terminal is connected to node A2, and the gate is It may also have a transistor 406A connected to code A1.

[0470] Furthermore, as shown in Figure 39(F), the first terminal of circuit 400B is connected to wiring 115B. The second terminal is connected to node B2, and the gate is the second terminal of transistor 401B. The connection point between the second terminal of transistor 402B and the connected transistor 405B The first terminal is connected to wiring 113B, the second terminal is connected to node B2, and the gate is It may also have a transistor 406B connected to node B1.

[0471] By using the configuration shown in Figures 39(E) and 39(F), the potential of node A2 or Since the potential of node B2 can be set to V2, the amplitude of the signal can be increased. .

[0472] Alternatively, the first terminal of transistor 401A and the first terminal of transistor 405A are They may be connected to separate wiring. For example, in Figure 40(A), wiring 115A is The wiring is divided into multiple wires, namely 115A_1 and 115A_2, and transistor 401A The first terminal of is connected to wiring 115A_1, and the first terminal of transistor 405A is connected to wiring It is connected to 115A_2. In this case, a signal is sent to either wiring 115A_1 or 115A_2. Simply input SELA and supply voltage V2 to the other end.

[0473] Alternatively, the first terminal of transistor 401B and the first terminal of transistor 405B are They may be connected to separate wiring. For example, in Figure 40(B), wiring 115B is The wiring is divided into multiple wires, namely 115B_1 and 115B_2, and transistor 401B The first terminal of is connected to wiring 115B_1, and the first terminal of transistor 405B is connected to wiring It is connected to 115B_2. In this case, a signal is sent to either wiring 115B_1 or 115B_2. Simply input SELB and supply voltage V2 to the other end.

[0474] By using the configuration shown in Figures 40(A) and 40(B), period c1 and period d1 In this configuration, a low-level signal SELB can be supplied to node B2. Alternatively, During interval c2 and period d2, a low-level signal SELA is supplied to node A2. Yes, it is possible. Therefore, the potentials of node A2 and node B2 can be fixed, This makes it possible to obtain semiconductor devices that are less susceptible to noise.

[0475] Furthermore, the configuration shown in Figures 31(B), 36(A), and 37(A) to 39(D) As shown in Figure 40(C), the circuit 400A has a first terminal connected to wiring 118A. The second terminal is connected to node A2 and the gate is connected to wiring 118A. Terminal 407A has its first terminal connected to wiring 113A, and its second terminal connected to node A2. The gate of transistor 408A is connected to node A1, and the first terminal is connected to wiring 113 It is connected to A, the second terminal is connected to node A2, and the gate is connected to wiring 115A. It may have a transistor 409A.

[0476] Furthermore, as shown in Figure 40(D), the first terminal of circuit 400B is connected to wiring 118B. The second terminal is connected to node B2 and the gate is connected to wiring 118B. Station 407B has its first terminal connected to wiring 113B, and its second terminal connected to node B2. The gate of transistor 408B is connected to node B1, and the first terminal is connected to wiring 11 It is connected to 3B, the second terminal is connected to node B2, and the gate is connected to wiring 115B. It may also have a transistor 409B.

[0477] By using the configuration shown in Figures 40(C) and 40(D), period c1 and period d1 In this configuration, a low-level signal SELB can be supplied to node B2. Alternatively, During interval c2 and period d2, a low-level signal SELA is supplied to node A2. Yes, it is possible. Therefore, the potentials of node A2 and node B2 can be fixed, This makes it possible to obtain semiconductor devices that are less susceptible to noise.

[0478] Furthermore, the configuration shown in Figures 31(B), 36(A), and 37(A) to 40(D) Furthermore, as shown in Figure 41(A), transistor 206A and circuit 500A may be provided. Circuit 500A has transistors 501A and 502A.

[0479] Transistor 206A has its first terminal connected to wiring 113A and its second terminal connected to a node It is connected to A1. Transistor 501A has its first terminal connected to wiring 118A, and the Terminal 2 is connected to the gate of transistor 206A, and the gate is connected to wiring 118A. Transistor 502A has its first terminal connected to wiring 113A, and its second terminal is connected to the transistor. It is connected to the gate of inverter 206A, and the gate is connected to node A1.

[0480] Furthermore, as shown in Figure 41(A), even if transistor 206B and circuit 500B are provided... Good. Circuit 500B has transistors 501B and 502B.

[0481] Transistor 206B has its first terminal connected to wiring 113B and its second terminal connected to a node It is connected to B1. Transistor 501B has its first terminal connected to wiring 118B, and the Terminal 2 is connected to the gate of transistor 206B, and the gate is connected to wiring 118B. Transistor 502B has its first terminal connected to wiring 113B, and its second terminal is connected to the transistor. It is connected to the gate of Node 206B, and the gate is connected to Node B1.

[0482] Note that in Figure 41(A), the gate of transistor 206A and transistor 501 The connection point between the second terminal of A and the second terminal of transistor 502A is indicated as node A3. Also, the gate of transistor 206B and the second terminal of transistor 501B, The connection point to the second terminal of the converter 502B is indicated as node B3.

[0483] Furthermore, the gate of transistor 502A may be connected to wiring 111. The gate of inverter 502B may be connected to wiring 111.

[0484] As another example, as shown in Figure 41(B), circuit 500A is omitted, and transistor 20 The gate of 6A may be connected to node A2. Also, circuit 500B may be omitted, and the transistor The gate of st206B may be connected to node B2. The configuration is as shown in Figure 41(B). This allows for a reduction in circuit size, thus reducing the layout area. Alternatively, it can reduce power consumption.

[0485] Next, transistor 206A, circuit 500A, transistor 501A, transistor 5 02A, transistor 206B, circuit 500B, transistor 501B, transistor 5 An example of the function of 02B will be explained with reference to Figures 41(A) and 41(B).

[0486] Transistor 206A controls the timing of the conductivity between wiring 113A and node A1. It has the function of raising the potential of wiring 113A to node A1. Alternatively, transistor 206A raises the potential of wiring 113A to node A1. It has a function to control the timing of supply. Alternatively, transistor 206A is connected to wiring 1 The signal or voltage supplied to 13A (for example, the clock signal CK2 or voltage V1) It has a function to control the timing of supply to the A1. Alternatively, transistor 206A It has the function of controlling the timing of supplying voltage V1 to node A1. Or, The 206A converter has the function of controlling the timing of the decrease in the potential of node A1. Alternatively, transistor 206A controls the timing of maintaining the potential of node A1. It has a function.

[0487] Thus, transistor 206A functions as a switch. ZISTA 206A may be controlled according to the potential of node A3.

[0488] Circuit 500A has the function of controlling the potential of node A3. Alternatively, circuit 500A is It has a function to control the timing of supplying signals or voltages, etc., to node A3. Or, Circuit 500A has a function to control the timing at which signals or voltages are not supplied to node A3. It has. Or, circuit 500A supplies an H signal or voltage V2 to node A3 at the timing It has the function of controlling the signal. Alternatively, circuit 500A receives the L signal or voltage V1 at node A3 It has a function to control the timing of supply to Node A3. Alternatively, Circuit 500A is It has a function to control the timing of raising the potential. Alternatively, circuit 500A is node It has a function to control the timing of decreasing the potential of A3. Alternatively, circuit 500A is It has a function to control the timing of maintaining the potential of node A3. Alternatively, circuit 500A It has a function to control the timing of inverting the potential of node A1 and outputting it to node A3. ru.

[0489] Thus, circuit 500A functions as a control circuit or an inverter circuit. Circuit 500A may also be controlled according to the potential of node A1.

[0490] Transistor 501A controls the timing of the conductivity between wiring 118A and node A3. It has the function of raising the potential of wiring 118A to node A3. Alternatively, transistor 501A raises the potential of wiring 118A to node A3. It has a function to control the timing of supply. Alternatively, transistor 501A is wired 1 The timing of supplying the signal or voltage (e.g., voltage V2) supplied to 18A to node A3 It has a function to control the signal. Alternatively, transistor 501A receives signals or voltages, etc. It has a function to control the timing of when it does not supply power to A3. Alternatively, transistor 501A It has the function of controlling the timing of supplying the H signal or voltage V2 to node A3. Alternatively, transistor 501A controls the timing of raising the potential of node A3. To have the ability.

[0491] Thus, transistor 501A is a switch, rectifier, diode, or dio It functions as a transistor or similar device with a code connection.

[0492] Transistor 502A controls the timing of the conductivity between wiring 113A and node A3. It has the function of raising the potential of wiring 113A to node A3. Alternatively, transistor 502A raises the potential of wiring 113A to node A3. It has a function to control the timing of supply. Alternatively, transistor 502A is connected to wiring 1 The signal or voltage supplied to 13A (for example, the clock signal CK2 or voltage V1) It has a function to control the timing of supply to the A3. Alternatively, transistor 502A It has the function of controlling the timing of supplying voltage V1 to node A3. Or, The 502A generator has the function of controlling the timing of the reduction in the potential of node A3. Alternatively, transistor 502A controls the timing of maintaining the potential of node A3. It has a function.

[0493] Thus, transistor 502A functions as a switch.

[0494] Transistor 206B controls the timing of the conduction between wiring 113B and node B1. It has the function of raising the potential of wiring 113B to node B1. Alternatively, transistor 206B raises the potential of wiring 113B to node B1. It has a function to control the timing of supply. Alternatively, transistor 206B is connected to wiring 1 The signal or voltage supplied to 13B (for example, the clock signal CK2 or voltage V1) It has a function to control the timing of supply to the B1. Alternatively, transistor 206B It has the function of controlling the timing of supplying voltage V1 to node B1. Or, The 206B converter has the function of controlling the timing of the reduction in the potential of node B1. Alternatively, transistor 206B controls the timing of maintaining the potential of node B1. It has a function.

[0495] Thus, transistor 206B functions as a switch. Zistor 206B may be controlled according to the potential of node B3.

[0496] Circuit 500B has the function of controlling the potential of node B3. Alternatively, circuit 500B is It has a function to control the timing of supplying signals or voltages, etc., to node B3. Or, Circuit 500B has a function to control the timing at which signals or voltages are not supplied to node B3. It has. Or, circuit 500B supplies an H signal or voltage V2 to node B3 at the timing It has a function to control the signal. Alternatively, circuit 500B receives the L signal or voltage V1 from node B3. It has a function to control the timing of supply to node B3. Alternatively, circuit 500B is node B3 It has a function to control the timing of raising the potential. Alternatively, circuit 500B is node It has a function to control the timing of decreasing the potential of B3. Alternatively, circuit 500B is It has a function to control the timing of maintaining the potential of node B3. Alternatively, circuit 500B It has a function to control the timing of inverting the potential of node B1 and outputting it to node B3. ru.

[0497] Thus, circuit 500B functions as a control circuit or an inverter circuit. Circuit 500B may also be controlled according to the potential of node B1.

[0498] Transistor 501B controls the timing of the conduction between wiring 118B and node B3. It has the function of raising the potential of wiring 118B to node B3. Alternatively, transistor 501B raises the potential of wiring 118B to node B3. It has a function to control the timing of supply. Alternatively, transistor 501B is connected to wiring 1. The timing of supplying the signal or voltage (e.g., voltage V2) supplied to 18B to node B3 It has a function to control the signal. Alternatively, transistor 501B receives signals or voltages, etc. It has a function to control the timing of when it does not supply power to B3. Alternatively, transistor 501B It has the function of controlling the timing of supplying the H signal or voltage V2 to node B3. Alternatively, transistor 501B controls the timing of raising the potential of node B3. To have the ability.

[0499] Thus, transistor 501B can function as a switch, rectifier, diode, or dio It functions as a transistor or similar device with a code connection.

[0500] Transistor 502B controls the timing of the conduction between wiring 113B and node B3. It has the function of raising the potential of wiring 113B to node B3. Alternatively, transistor 502B raises the potential of wiring 113B to node B3. It has a function to control the timing of supply. Alternatively, transistor 502B is connected to wiring 1. The signal or voltage supplied to 13B (for example, the clock signal CK2 or voltage V1) It has a function to control the timing of supply to the B3. Alternatively, transistor 502B It has the function of controlling the timing of supplying voltage V1 to node B3. Or, The 502B generator has the function of controlling the timing of the reduction in the potential of node B3. Alternatively, transistor 502B controls the timing of maintaining the potential of node B3. It has a function.

[0501] Thus, transistor 502B functions as a switch.

[0502] <Semiconductor device operation> Next, for the operation of the semiconductor device shown in Figure 41(A), please refer to Figures 42(A) to 45(B). Let me explain. Figures 42(A) to 45(B) are, in order, period a1, period b1, period c1, This corresponds to a schematic diagram of the semiconductor device during periods d1, a2, b2, c2, and d2. do.

[0503] During periods a1, b1, a2, and b2, node A1 is at a potential of H level. Therefore, circuit 500A outputs an L signal to node A3, just like circuit 400A. Then, transistor 206A turns off, and the wiring 113A and node A1 become decoupled. It enters a normal state.

[0504] Specifically, in periods a1, b1, a2, and b2, transistor 5 Since 02A is turned on, wiring 113A and node A3 become conductive. Therefore, voltage V1 is supplied to node A3 via transistor 502A. At this time, the transistor Since TA501A is turned on, wiring 118A and node A3 become conductive. Therefore, Voltage V2 is supplied to node A3 via transistor 501A.

[0505] Here, the current supply capability of transistor 502A is compared to the current supply capability of transistor 501A. To make it larger than (for example, the channel width of transistor 502A is greater than that of transistor 501A) By making it larger than the channel width, the potential of node A3 becomes L level.

[0506] Furthermore, during periods a1, b1, a2, and b2, node B1 is at the H level. It becomes electric potential. Therefore, circuit 500B outputs an L signal to node B3, just like circuit 400B. This will turn off transistor 206B, so the wiring 113B and node B1 It becomes non-conductive.

[0507] Specifically, in periods a1, b1, a2, and b2, transistor 5 Since 02B is turned on, wiring 113B and node B3 become conductive. Therefore, voltage V1 is supplied to node B3 via transistor 502B. At this time, the transistor Since TA501B is turned on, wiring 118B and node B3 become conductive. Therefore, Voltage V2 is supplied to node B3 via transistor 501B.

[0508] Here, the current supply capability of transistor 502B is compared to the current supply capability of transistor 501B. To make it larger than (for example, the channel width of transistor 502B is greater than that of transistor 501B) By making it larger than the channel width, the potential at node B3 becomes L level.

[0509] During periods c1, d1, c2, and d2, node A1 is at an L level potential. Therefore, circuit 500A outputs an H signal to node A3, just like circuit 400A. Then, transistor 206A turns on, and there is continuity between wire 113A and node A1. This state is reached. Then, voltage V1 is supplied to node A1 via transistor 206A. ru.

[0510] Specifically, in periods c1, d1, c2, and d2, transistor 5 Since 02A is turned off, wiring 113A and node A3 become non-conductive. At this time, Transistor 501A turns on, so wiring 118A and node A3 become conductive. Therefore, voltage V2 is supplied to node A3 via transistor 501A.

[0511] Furthermore, during periods c1, d1, c2, and d2, node B1 is L level. It becomes electric potential. Therefore, circuit 500B outputs an H signal to node B3, just like circuit 400B. This will turn on transistor 206B, so connect wire 113B and node B1. The circuit becomes conductive. Then, voltage V1 is supplied to node B1 via transistor 206B. To be given.

[0512] Specifically, in periods c1, d1, c2, and d2, transistor 5 Since 02B is turned off, wiring 113B and node B3 become non-conductive. At this time, Transistor 501B turns on, so wiring 118B and node B3 become conductive. Therefore, voltage V2 is supplied to node B3 via transistor 501B.

[0513] Thus, during periods c1 and d1, transistor 206A is turned on. Wiring 113A and node A1 become conductive. Then, voltage V1 is transmitted through transistor 2 It is supplied to node A1 via 06A. Therefore, the potential of node A1 can be fixed. Therefore, it is possible to obtain semiconductor devices that are less susceptible to noise.

[0514] Also, during periods c2 and d2, transistor 206B is turned on, so wiring 113B and node B1 become conductive. Then, voltage V1 is transmitted through transistor 206B. It is supplied to node B1 via this. Therefore, the potential of node B1 can be fixed. This allows us to obtain semiconductor devices that are less susceptible to noise.

[0515] <Transistor size> Next, let's discuss the size of the transistor, such as its channel width and channel length. explain.

[0516] The channel width of transistor 501A and the channel width of transistor 501B are approximately It is preferable that they be equal. Alternatively, the channel width of transistor 502A and transistor 5 It is preferable that the channel width of 02B be approximately equal to that of 02B.

[0517] In this way, by making the channel widths of the transistors roughly equal, the current supply capability is improved. This can be made roughly equal, or the degree of transistor degradation can be made roughly equal. Therefore, even if the selected transistor is switched, the waveform of the output signal OUT will remain roughly the same. It can be done.

[0518] For the same reason, the channel length of transistor 501A and transistor 501B The channel length is preferably approximately equal to that of transistor 502A. It is preferable that the length and the channel length of transistor 502B are approximately equal.

[0519] Specifically, the channel width of transistor 501A and the channel of transistor 501B The width is preferably 100 μm to 2000 μm, more preferably 200 μm to 1500 μm. More preferably, the particle size should be between 300 μm and 700 μm.

[0520] Furthermore, the channel width of transistor 502A and the channel width of transistor 502B are: Preferably 300 μm to 3000 μm, more preferably 500 μm to 2000 μm, further Preferably, the thickness should be between 700 μm and 1500 μm.

[0521] Furthermore, the configuration shown in Figures 31(B), 36(A), and 37(A) to 41(B) The second terminal of transistor 302A may be connected to wiring 111, and the transistor The second terminal of sta 302B may be connected to wiring 111. Or, such a connection A transistor may be provided to realize the relationship. By shortening the falling time of signal OUTA and signal OUTB can.

[0522] Alternatively, the configuration shown in Figures 31(B), 36(A), and 37(A) to 41(B) The first terminal of transistor 302A is connected to wiring 118A, and transistor 3 The second terminal of 02A is connected to node A2, and the gate of transistor 302A is wired It may also be connected to 116A. Also, the first terminal of transistor 302B is connected to wiring 1 Connected to 18B, the second terminal of transistor 302B is connected to node B2, The gate of inverter 302B may be connected to wiring 116B. Or, A transistor may be provided to achieve such a connection relationship. Therefore, applying a reverse bias to transistors 302A and 302B is possible. This allows us to suppress the degradation of each transistor.

[0523] Furthermore, the configuration shown in Figures 31(B), 36(A), and 37(A) to 41(B) Furthermore, as shown in Figure 36(B), a P-channel transistor is used as the transistor. It's okay to be there.

[0524] In Figure 36(B), transistor 201pA, transistor 202pA, and transistor 301pA transistor, 302pA transistor, 401pA transistor, and transistor 402pA is a P-channel transistor, and each of the transistors in Figure 36(A) Transistor 201A, Transistor 202A, Transistor 301A, Transistor 302 A has the same function as transistors 401A and 402A.

[0525] Also, in Figure 36(B), transistor 201pB, transistor 202pB, Transistor 301pB, transistor 302pB, transistor 401pB, and The ZISTA 402pB is a P-channel transistor, and as shown in Figure 36(A)... transistors 201B, 202B, 301B, and transistors It has the same function as transistors 302B, 401B, and 402B.

[0526] Note that if the transistor is a P-channel type transistor, wiring 113A and wiring 113 Voltage V1 is supplied to B. Also, in this case, signal OUTA, signal OUTB, Lock signal CK1, Start signal SP, Reset signal RE, Signal SELA, Signal SELB The potentials of node A1, node A2, node B1, and node B2 are shown. The timing chart corresponds to the inverted version of the timing chart in Figure 17.

[0527] (Embodiment 6) In this embodiment, a gate driver circuit (also called "gate driver") and a gate A display device having a driver circuit will be described with reference to Figures 46(A) to 49.

[0528] <Display device configuration> An example of the configuration of a display device will be explained with reference to Figures 46(A) to 46(D). The display devices in Figures 46(A) to 46(D) are circuits 1001, 1002, and 1003. 1. It has a circuit 1003_2, a pixel section 1004, and a terminal 1005.

[0529] The pixel section 1004 has multiple wirings extending from circuits 1003_1 and 1003_2. These are arranged. These multiple wires include gate lines (also called "gate signal lines"), scan lines, Alternatively, it functions as a signal line. In addition, the pixel section 1004 has an extension from the circuit 1002. Multiple wires are arranged. These multiple wires include video signal lines, data lines, signal lines, or It functions as a source line (also called a "source signal line"). And the pixel section 100 4 contains multiple wires extending from circuits 1003_1 and 1003_2, and circuit 100 Multiple pixels are arranged corresponding to multiple wirings extending from 2.

[0530] Furthermore, the pixel section 1004 also has functions such as power lines or capacitance lines in addition to the above-mentioned wiring. Wiring may be arranged in this manner.

[0531] Circuit 1001 sends signals to circuits 1002, 1003_1, and 1003_2. It has a function to control the timing of supplying voltage or current, etc. Alternatively, circuit 1001 It has the function of controlling circuits 1002, 1003_1, and 1003_2. Thus, circuit 1001 consists of a controller, control circuit, timing generator, and power supply. It functions as a circuit or a regulator.

[0532] Circuit 1002 has a function to control the timing of supplying the video signal to the pixel unit 1004. It has. Alternatively, circuit 1002 controls the brightness or transmittance of the pixels of the pixel unit 1004. It has the function of controlling. Thus, circuit 1002 is a source driver circuit, or a signal line driver. It functions as a dynamic circuit.

[0533] Circuit 1003_1 is the same as circuit 10A, circuit 100A, or circuit described in the above embodiment. It has the same function as 200A. Furthermore, circuit 1003_2 is described in the above embodiment. Circuit 10B, Circuit 100B, or Circuit 200B have the same function. Circuits 1003_1 and 1003_2 each function as gate driver circuits. ru.

[0534] Furthermore, as shown in Figures 46(A) and 46(B), circuits 1001 and 1002 are , a substrate other than the substrate 1006 on which the pixel portion 1004 is formed (for example, a semiconductor substrate, or S It may also be formed on an OI substrate. In addition, circuits 1003_1 and 1003_2 may be formed on the pixel part It may be formed on the same substrate as 1004.

[0535] The drive frequencies of circuits 1003_1 and 1003_2 are the same as those of circuits 1001 and 100 If it is lower than 2, the transients constituting circuits 1003_1 and 1003_2 A transistor with low mobility may be used as the station. Therefore, circuit 1003_1 and The semiconductor layer of the transistor constituting circuit 1003_2 is an amorphous semiconductor or a microcrystalline semiconductor. Non-single-crystal semiconductors such as crystalline semiconductors, organic semiconductors, or oxide semiconductors can be used. Therefore, when manufacturing semiconductor devices, the number of processes is reduced, the yield is increased, or costs are reduced. This can be reduced. Also, the manufacturing method for semiconductor devices becomes easier, allowing for larger display devices. It can be done.

[0536] Furthermore, as shown in Figures 46(A), 46(C), and 46(D), circuit 1003_ 1 and circuit 1003_2 may be arranged facing each other with the pixel section 1004 in between. For example, As shown in Figure 46(A), circuit 1003_1 is located to the left of pixel section 1004, and Path 1003_2 is located to the right of pixel section 1004. Alternatively, as shown in Figure 46(B) For example, circuits 1003_1 and 1003_2 are on the same side with respect to the pixel section 1004 (for example) It may be placed on the left or right side.

[0537] Furthermore, in the configuration shown in Figures 46(A) and 46(B), as shown in Figure 46(C) Alternatively, the circuit 1002 may be formed on the same substrate 1006 as the pixel section 1004.

[0538] Furthermore, in the configuration shown in Figures 46(A) to 46(C), as shown in Figure 46(D), A portion of circuit 1002 (for example, circuit 1002a) is provided on substrate 10 on which pixel section 1004 is located. Formed on 06, another part of circuit 1002 (for example, circuit 1002b) is separated from substrate 1006. It may be formed on a separate substrate. In this case, circuit 1002a may include a switch, a shift resistor, It is preferable to use a circuit with a relatively low drive frequency, such as a turntable or selector.

[0539] Next, the pixels of the display device's pixel section will be explained with reference to Figure 46(E). An example of the pixel configuration is shown in 46(E).

[0540] Pixel 3020 comprises transistor 3021, liquid crystal element 3022, and capacitive element 3023 It has. Transistor 3021 has a first terminal connected to wiring 3031 and a second terminal One electrode of the liquid crystal element 3022 and one electrode of the capacitive element 3023 are connected, and the gate is It is connected to wiring 3032. The other electrode of liquid crystal element 3022 is connected to electrode 3034. The other electrode of the capacitive element 3023 is connected to the wiring 3033.

[0541] The video signal is received from circuit 1002 shown in Figures 46(A) to 46(D) via wiring 3031. It is input. Therefore, wiring 3031 is a signal line, a video signal line, or a source line ("source" line). It also functions as a "signal line."

[0542] Wiring 3032 has circuits 1003_1 and 10 shown in Figures 46(A) to 46(D) A gate signal, scan signal, or selection signal is input from 03_2. Therefore, wiring 303 2 has the function of a gate line (also called a "gate signal line"), scan line, or signal line. do.

[0543] Wiring 3033 and electrode 3034 are connected to circuit 1001 shown in Figures 46(A) to 46(D). A constant voltage is supplied from there. Therefore, wiring 3033 is a power line or a capacitance line. It has the ability to function as a common electrode or a counter electrode.

[0544] Furthermore, a precharge voltage may be supplied to wiring 3031. The precharge voltage is It is preferable to set it to a value approximately equal to the voltage supplied to electrode 3034. Alternatively, wiring 303 A signal may be input to 3. In this way, the voltage applied to the liquid crystal element 3022 is controlled. By controlling this, the amplitude of the video signal can be reduced, and inverted drive can be achieved. This can be done. Alternatively, when a signal is input to electrode 3034, frame inversion can occur. It can be driven.

[0545] Transistor 3021 is electrically connected to wiring 3031 and one electrode of liquid crystal element 3022. It has a function to control the timing of writing the video signal to the pixels. It has the function of controlling. Thus, transistor 3021 functions as a switch. It holds.

[0546] The capacitive element 3023 is connected to the potential of one electrode of the liquid crystal element 3022 and the potential of the wiring 3033. It has the function of maintaining the potential difference. Alternatively, the voltage applied to the liquid crystal element 3022 is constant. It has the function of holding in that state. Thus, the capacitive element 3023 has the function of holding capacitance. It has a function.

[0547] <Shift register configuration> Next, the configuration of the gate driver circuit of the display device will be described below. Figures 47 and 48 show the configuration of the shift register in the gate driver circuit. Refer to the following for explanation. Figures 47 and 48 are examples of circuit diagrams for a shift register.

[0548] In Figure 47, the shift register 1100A is connected to the flip-flop 1101A_1~ It has multiple flip-flops called 1101A_N (where N is a natural number). As shown in Figure 47, flip-flops 1101A_1 to 1101A_N In each case, the circuit 200A of the semiconductor device shown in Figure 16(A) can be used. .

[0549] Furthermore, the shift register 1100B is connected to the flip-flop 1101B_1~ It has multiple flip-flops named 1101B_N (where N is a natural number). (See Figure 47) Let flip-flops 1101B_1 to 1101B_N be used, respectively Alternatively, the circuit 200B of the semiconductor device shown in Figure 16(A) can be used.

[0550] Shift register 1100A is connected to wiring 1111_1 to 1111_N and wiring 1112A. , wiring 1113A, wiring 1114A, wiring 1115A, wiring 1116A, and wiring 111 It is connected to 9A. Then, the flip-flop 1101A_i (where i is one of 1 to N) is connected. In one of them, wiring 111, wiring 112A, wiring 113A, wiring 114A, wiring 115 A and wiring 116A are, respectively, wiring 1111_i, wiring 1112A, and wiring 1113 A is connected to wiring 1111_i-1, wiring 1115A, and wiring 1111_i+1.

[0551] Furthermore, when connecting wiring 112A to either wiring 1112A or wiring 1119A, odd number The flip-flops in the first stage and the flip-flops in the even-numbered stages are connected to the same destination as wiring 112A. It's okay to make them different.

[0552] Additionally, the shift register 1100B has wiring 1111_1 to 1111_N, and wiring 11 12B, wiring 1113B, wiring 1114B, wiring 1115B, wiring 1116B, and wiring It is connected to 1119B. Then, the flip-flop 1101B_i (where i is a number from 1 to N) In either one of them, wiring 111, wiring 112B, wiring 113B, wiring 114B, wiring Wiring 115B and wiring 116B are, respectively, wiring 1111_i, wiring 1112B, and wiring 1 113B is connected to wiring 1111_i-1, wiring 1115B, and wiring 1111_i+1. .

[0553] Furthermore, when connecting wiring 112B to either wiring 1112B or wiring 1119B, odd number The flip-flops in the first stage and the flip-flops in the even-numbered stages are connected to the same destination as wiring 112B. It's okay to make them different.

[0554] The shift register 1100A has signals GOUTA_1 to GOUTA_N connected to wire 111 1_1 outputs to wiring 1111_N. Signals GOUTA_1 to GOUTA_N are... The output signals of flip-flops 1101A_1 to 1101A_N, respectively. This corresponds to the signal OUTA. Also, the shift register 1100B corresponds to the signal GOUTB. _1~Outputs signal GOUTB_N to wiring 1111_1~wire 1111_N. Signal GO UTB_1~ Signal GOUTB_N corresponds to the flip-flop 1101B_1~ flip-flop. This is the output signal of the 1101B_N op-flop, and corresponds to signal OUTB. Therefore, wiring Wiring 1111_1 to 1111_N has the same function as wiring 111.

[0555] The signal GCK1 is input to wiring 1112A and wiring 1112B, and wiring 1119A and Signal GCK2 is input to wiring 1119B. Signals GCK1 and GCK2 are... These correspond to clock signals CK1 and CK2, respectively. Therefore, wiring 1112A And wiring 1119A has the same function as wiring 112A, and wiring 1112B and wiring 11 19B has the same function as wiring 112B.

[0556] Voltage V1 is supplied to wiring 1113A and wiring 1113B. Therefore, wiring 111 3A has the same function as wiring 113A, and wiring 1113B has the same function as wiring 113B. To possess.

[0557] Signal GSP is input to wiring 1114A and wiring 1114B. Signal GSP is... It corresponds to the start signal SP. Therefore, wiring 1114A has the same function as wiring 114A. Wiring 1114B has the same function as wiring 114B.

[0558] Signal SELA is input to wiring 1115A, and signal SELB is input to wiring 1115B. It is input. Therefore, wiring 1115A has the same function as wiring 115A, and wiring 1115 B has the same function as wiring 115B.

[0559] The signal GRE is input to wiring 1116A and wiring 1116B. The signal GRE is, It corresponds to the set signal RE. Therefore, wiring 1116A has the same function as wiring 116A. Wiring 1116B has the same function as wiring 116B.

[0560] Note that if the same signal is input to both wiring 1112A and wiring 1112B, wiring 1112A The wiring 1112B may be connected to the other wiring. Alternatively, in this case, the wiring may be connected as shown in Figure 48. The same wiring (wiring 1112) may be used for both wiring 1112A and wiring 1112B. Alternatively, wiring Separate signals or separate voltages may be input to wiring 1112A and wiring 1112B.

[0561] Also, if the same signal is input to both wiring 1113A and wiring 1113B, wiring 1113A The wiring 1113B may be connected to the other. Alternatively, in this case, the wiring may be connected as shown in Figure 48. The same wiring (wiring 1113) may be used for both wiring 1113A and wiring 1113B. Alternatively, wiring Separate signals or voltages may be input to wiring 1113A and wiring 1113B.

[0562] Also, if the same signal is input to both wiring 1114A and wiring 1114B, wiring 1114A The wiring 1114B may be connected to the other. Alternatively, in this case, the wiring may be connected as shown in Figure 48. The same wiring (wiring 1114) may be used for both wiring 1114A and wiring 1114B. Alternatively, wiring Separate signals or separate voltages may be input to wiring 1114A and wiring 1114B.

[0563] Also, if the same signal is input to both wiring 1116A and wiring 1116B, wiring 1116A The wiring 1116B may be connected to the other. Alternatively, in this case, the wiring may be connected as shown in Figure 48. The same wiring (wiring 1116) may be used for both wiring 1116A and wiring 1116B. Alternatively, wiring Separate signals or separate voltages may be input to 1116A and wiring 1116B.

[0564] Also, if the same signal is input to both wiring 1119A and wiring 1119B, wiring 1119A The wiring 1119B may be connected to the other wiring. Alternatively, in this case, the wiring may be connected as shown in Figure 48. The same wiring (wiring 1119) may be used for both wiring 1119A and wiring 1119B. Alternatively, wiring Separate signals or separate voltages may be input to 1119A and wiring 1119B.

[0565] <Shift register operation> An example of the operation of a shift register will be explained with reference to Figure 49. Figure 49 shows the shift This is a timing chart showing an example of register operation. In Figure 49, the signal GCK1, No. GCK2, Signal GSP, Signal GRE, Signal SELA, Signal SELB, Signal GOUTA_ Signals 1 through GOUTA_N and signals GOUTB_1 through GOUTB_N are shown.

[0566] First, the operation of the flip-flop 1101A_i in the k (k is a natural number) frame and This explains the operation of the flip-flop 1101B_i in the k-1 frame.

[0567] First, signals GOUTA_i-1 and GOUTB_i become high. Then, In Embodiment 4, the lip-flop 1101A_i and the flip-flop 1101B_i are... The operation in the described period a1 begins. Therefore, the flip-flop 1101A_i The wire 1111_i outputs an L signal, and the flip-flop 1101B_i is connected to the wire 1111_ Output an L signal to i.

[0568] Subsequently, when signals GCK1 and GCK2 are inverted, flip-flop 1101A_ i and flip-flop 1101B_i are moving during period b1 as described in Embodiment 4. The operation begins. Therefore, the flip-flop 1101A_i sends a high signal to wire 1111_i. The flip-flop 1101B_i outputs a high signal to wire 1111_i.

[0569] Subsequently, when signals GCK1 and GCK2 are inverted again, signals GOUTA_i+1 and The signal GOUTB_i+1 becomes high level. Then, flip-flop 1101A_i And the flip-flop 1101B_i operates during period c1 as described in Embodiment 4. This starts the process. Therefore, the flip-flop 1101A_i sends an L signal to the wire 1111_i. The flip-flop 1101B_i outputs a signal, but does not output a signal to wire 1111_i.

[0570] After that, until signals GOUTA_i-1 and GOUTB_i reach the high level again. The flip-flops 1101A_i and 1101B_i are, in the embodiment The operation described in 4 for period d1 is performed. Therefore, the flip-flop 1101A_i is The wire 1111_i outputs an L signal, and the flip-flop 1101B_i is connected to the wire 1111_ No signal is output to i.

[0571] Next, we will examine the operation of the flip-flop 1101A_i in the k+1 frame, and the k frame This explains the operation of the flip-flop 1101B_i in the M section.

[0572] First, signals GOUTA_i-1 and GOUTB_i become high. Then, In Embodiment 4, the lip-flop 1101A_i and the flip-flop 1101B_i are... The operation in the described period a2 will begin. Therefore, the flip-flop 1101A_i The wire 1111_i outputs an L signal, and the flip-flop 1101B_i is connected to the wire 1111_ Output an L signal to i.

[0573] Subsequently, when signals GCK1 and GCK2 are inverted, flip-flop 1101A_ i and flip-flop 1101B_i move during period b2 as described in Embodiment 4 The operation begins. Therefore, the flip-flop 1101A_i sends a high signal to wire 1111_i. The flip-flop 1101B_i outputs a high signal to wire 1111_i.

[0574] Subsequently, when signals GCK1 and GCK2 are inverted again, signals GOUTA_i+1 and The signal GOUTB_i+1 becomes high level. Then, flip-flop 1101A_i And the flip-flop 1101B_i operates during period c2 as described in Embodiment 4. This starts the process. Therefore, the flip-flop 1101A_i outputs a signal to the wiring 1111_i. Without any intervention, the flip-flop 1101B_i outputs a low signal to the wire 1111_i.

[0575] After that, until signals GOUTA_i-1 and GOUTB_i reach the high level again. The flip-flops 1101A_i and 1101B_i are, in the embodiment The operation described in 4 for period d2 is performed. Therefore, flip-flop 1101A_i No signal is output to wiring 1111_i, and flip-flop 1101B_i is connected to wiring 1111_ Output an L signal to i.

[0576] (Embodiment 7) In this embodiment, with respect to the source driver circuit (also called "source driver"), Please refer to Figures 50(A) to 50(D) for further explanation.

[0577] Figure 50(A) shows an example of the configuration of a source driver circuit. The source driver circuit is It has a path 2001 and a circuit 2002. Circuit 2002 is divided into circuits 2002_1 to 200 It has multiple circuits, numbered 2_N (where N is a natural number). Circuits 2002_1 to 2002_N These are transistors 2003_1 to 2003_k (where k is a natural number) and It has multiple transistors. Transistor 2003_1~Transistor 2003_ k can be an N-channel transistor or a P-channel transistor. Also, transistors 2003_1 to 2003_k are CMOS type switches. It can be used as a chi.

[0578] Regarding the connection relationships between circuits 2002_1 to 2002_N in the source driver circuit. Let's explain using circuit 2002_1 as an example. The transistor 200 in circuit 2002_1 3_1~ Transistor 2003_k has its first terminal connected to the wiring 2004_1~ wiring It is connected to 2004_k, and the second terminals are respectively source lines 2008_1 to source line 20 It is connected to 08_k (indicated as S1, S2, and Sk in Figure 50(B)) and gate This is connected to wiring 2005_1.

[0579] Circuit 2001 outputs a high signal to wiring 2005_1 to wiring 2005_N in sequence. It has a function to control the ming. Alternatively, circuits 2002_1 to 2002_N are used in order. It has a selection function. Thus, circuit 2001 has the function of a shift register. do.

[0580] Alternatively, circuit 2001 may send an H signal to wiring 2005_1 to wiring 2005_N in various sequences. Output is possible. Alternatively, circuits 2002_1 to 2002_N can be selected in various orders. It can be selected. In this way, circuit 2001 has the function of a decoder.

[0581] Circuit 2002_1 consists of wiring 2004_1~, wiring 2004_k, and source wire 2008_1~. It has a function to control the timing of when source line 2008_k and the other line become conductive. Circuit 2002_1 sets the potential of wiring 2004_1 to wiring 2004_k to source wire 2008 _1~It has a function to control the timing of supply to source line 2008_k. Circuit 2002_1 functions as a selector. Note that circuits 2002_2 and beyond are also included. Circuit 2002_N has the same functionality as circuit 2002_1.

[0582] Transistors 2003_1 to 2003_N are connected to wiring 2004_ 1~ Wiring 2004_k and source wire 2008_1~ Source wire 2008_k are electrically connected. It has a function to control the ming. For example, transistor 2003_1 is connected to wiring 2004_ It has a function to control the timing when 1 and source line 2008_1 become conductive. Or, Transistor 2003_1 and transistor 2003_N are connected to wiring 2004_1, respectively. A tie that supplies the potential of wiring 2004_k to source wires 2008_1 and 2008_k. It has a function to control the ming. For example, transistor 2003_1 is connected to wiring 2004_ It has a function to control the timing of supplying a potential of 1 to source line 2008_1. Transistors 2003_1 to 2003_N are switches and It has the function of being a .

[0583] Furthermore, each of the wirings 2004_1 to 2004_k has an analog signal corresponding to the video signal. When signals corresponding to video signals, such as video signals, are input, wiring 2004_1 to wiring 20 04_k functions as a signal line. Alternatively, wiring 2004_1~wiring 2004_ Each of k may be input to a digital signal, an analog voltage, or an analog current. .

[0584] Next, regarding an example of the operation of the source driver circuit shown in Figure 50(A), see Figure 50(B). I will explain this by referring to the timing chart.

[0585] Figure 50(B) shows signals 2015_1 to 2015_N, and signals 2014_1 to signal This shows 2014_k. Signals 2015_1 to 2015_N are respectively from circuit 2001. These are output signals, and signals 2014_1 to 2014_k are connected to wiring 2004_1 to 2014_k respectively. This is the signal input to wiring 2004_k.

[0586] Note that one operating period of the source driver circuit corresponds to one gate selection period in the display device. The gate selection period is divided into, for example, period T0 and periods T1 to TN. Period T0 is for simultaneously applying a pre-charge voltage to the pixels belonging to the selected row. This is a period, also called a precharge period. Periods T1 to TN are each the selected row This is the period for writing a video signal to the pixels belonging to a specific group, and is also called the writing period.

[0587] First, during period T0, circuit 2001 receives the H signal from wiring 2005_1 to wiring 2005 Output to _N. Then, in circuit 2002_1, transistor 2003_1~transistor Since the generator 2003_k will be turned on, connect the wiring 2004_1 to the wiring 2004_k and the signal The power line 2008_1 and source line 2008_k become conductive. At this time, the wiring The precharge voltage Vp is supplied to wiring 2004_k. Therefore, The recharge voltage Vp is obtained via transistors 2003_1 to 2003_k. The output is sent to source lines 2008_1 to 2008_k respectively. Precharge power The pressure Vp is written to the pixels belonging to the selected row, so the pixels belonging to the selected row It will be pre-charged.

[0588] During periods T1 to TN, circuit 2001 receives the H signal from wiring 2005_1 to wiring 20 Outputs are sent to 05_N in order. For example, during period T1, circuit 2001 wires the H signal. Output to 2005_1. Then, transistor 2003_1~transistor 2003_ Since k is turned on, connect wiring 2004_1~ to wiring 2004_k and source wire 2008_1~ The source line 2008_k becomes conductive. At this time, wiring 2004_1 to wiring 2004 _k will contain Data(S1)~Data(Sk). ta(Sk) is determined by the connections between transistors 2003_1 to 2003_k, respectively. Then, the pixels belonging to the selected row, from column 1 to column k, are written. Then, in the period T1 to period TN, the pixels belonging to the selected row are sequentially processed in k columns. The video signal is written.

[0589] As described above, the video signal is written to the pixels in multiple columns, This can reduce the number of pixels, or the number of wires required to write the video signal to the pixels. Therefore, the number of connections between the substrate on which the pixel is formed and the external circuit can be reduced, thus increasing the yield. This can lead to improved performance, increased reliability, reduced number of parts, or reduced costs.

[0590] Furthermore, because the video signal is written to the pixels in multiple columns, the writing time is extended. This can be done. Therefore, it is possible to prevent insufficient writing of the video signal, This can improve the quality of the displays.

[0591] Furthermore, increasing k can reduce the number of connections to external circuits. Furthermore, if k is too large, the writing time to the pixels will be shortened. Therefore, it is preferable that k is 6 or less. More preferably, k is 3 or greater, and even more preferably k is 2.

[0592] In particular, if a pixel has n color elements (where n is a natural number), then k = n, or k = n × d (where d is It is preferable that the color elements of the pixel are red (R), green (G), and blue (B). When divided into three parts, it is preferable that k=3 or k=3×d.

[0593] Furthermore, a pixel may have m (where m is a natural number) subpixels (subpixels are also called sub-pixels or sub-images). Also called a prime element. When divided into ( ), it is preferable that k = m or k = m × d. For example If a pixel is divided into two subpixels, it is preferable that k=2. Alternatively, When there are n color elements, it is preferable that k = m × n or k = m × n × d.

[0594] Furthermore, another example of the source driver circuit configuration will be explained with reference to Figure 50(C). If the drive frequency of path 2001 and the drive frequency of circuit 2002 are low, then circuit 2001 and Since circuit 2002 may be made of a single-crystal semiconductor, as shown in Figure 50(C), circuit 20 01 and circuit 2002 can be formed on the same substrate as the pixel unit 2007. Therefore, the number of connections between the substrate on which the pixel is formed and the external circuit can be reduced, thus increasing the yield. This can lead to improved performance, increased reliability, reduced number of parts, or reduced costs.

[0595] Furthermore, gate driver circuits 2006A and 2006B are also located in the pixel section 2 By forming it on the same substrate as 007, the number of connections to external circuits can be further reduced. It can be done. Note that the gate driver circuit 2006A is the same as the circuit 10A described in the above embodiment. Corresponding to circuit 100A or circuit 200A, the gate driver circuit 2006B is the above implementation. This corresponds to circuits 10B, 100B, or 200B described in terms of their configuration.

[0596] Another example of the source driver circuit configuration will be explained with reference to Figure 50(D). As shown in 50(D), circuit 2001 is formed on a separate substrate from the pixel section 2007, and circuit 2 002 may be formed on the same substrate as the pixel portion 2007. With this configuration, the pixel portion is formed. This reduces the number of connections between the substrate and external circuits, thereby improving yield and reliability. Improvements, reductions in the number of parts, or cost reductions can be achieved. Also, the same as the pixel unit 2007. Since fewer circuits are formed on the substrate, the bezel can be made smaller.

[0597] (Embodiment 8) In a display device, elements provided in the pixels (for example, transistors, display elements, capacitance elements) (Child) electrostatic discharge (ESD) and noise To prevent damage from splatters, etc., a protective circuit is provided on the gate wire or source wire. It can happen.

[0598] In this embodiment, the configuration of the protection circuit and the configuration of the semiconductor device using the protection circuit are described below. I will explain.

[0599] An example of a protection circuit diagram will be explained with reference to Figures 51(A) to 51(G).

[0600] As a protection circuit, the protection circuit 3000 shown in Figure 51(A) may be used. Figure 51(A) The protection circuit 3000 shown below protects against electrostatic discharge (ESD) in the element provided on the pixel connected to the wiring 3011. It is designed to prevent damage from cracks, noise, etc. Protection circuit 300 0 has transistors 3001 and 3002. Transistor 3001 And transistor 3002 is an N-channel type transistor or a P-channel type transistor You can use "ta".

[0601] Transistor 3001 has its first terminal connected to wire 3012 and its second terminal connected to wire 3 It is connected to 011, and its gate is connected to wiring 3011. Transistor 3002 is the first The first terminal is connected to wiring 3013, the second terminal is connected to wiring 3011, and the gate is wired It connects to 3013.

[0602] Wiring 3011 carries signals (e.g., scan signal, video signal, clock signal, start signal). (e.g., a signal, reset signal, or selection signal), and voltage (e.g., negative power supply potential, ground voltage). A voltage (or positive power potential, etc.) is supplied. High power potential (VDD) is supplied to wiring 3012. The wiring 3013 is then supplied with a low power supply potential (VSS) (or ground voltage).

[0603] If the potential of wiring 3011 is between the low power supply potential (VSS) and the high power supply potential (VDD) then Therefore, transistors 3001 and 3002 are turned off. Thus, wiring 3011 The signal or voltage supplied to is supplied to the pixel connected to wiring 3011.

[0604] On the other hand, due to the effects of static electricity, etc., the wiring 3011 may have a potential higher than the high power supply potential (VDD). Alternatively, a potential lower than the low power supply potential (VSS) may be supplied. In this case, this high power Distribution is performed at a potential higher than the source potential (VDD) or lower than the low power supply potential (VSS). Elements located on pixels connected to line 3011 may be damaged.

[0605] To prevent such electrostatic discharge damage, high currents are transmitted to wiring 3011 due to the effects of static electricity, etc. Transistor 3001 turns on when a potential higher than the source potential (VDD) is supplied. Then, the charge on wire 3011 is transferred to wire 3012 via transistor 3001. Therefore, the potential of wiring 3011 decreases.

[0606] Furthermore, due to the effects of static electricity, etc., the wiring 3011 may reach a potential lower than the low power supply potential (VSS). When power is supplied, transistor 3002 turns on. Then the charge on wiring 3011 is Therefore, the potential of wire 3011 rises as it moves through transistor 3002 to wire 3013. To rise.

[0607] As described above, by providing the protection circuit 3000, the picture connected to the wiring 3011 This prevents damage to the element due to static electricity, etc.

[0608] Furthermore, the protection circuit 3000 shown in Figure 51(B) or Figure 51(C) is used as the protection circuit. It is also possible. The configuration shown in Figure 51(B) is the same as the configuration shown in Figure 51(A) with transistor 3 This corresponds to the configuration in which 002 and wiring 3013 are omitted. The configuration shown in Figure 51(C) is the same as in Figure 51 This corresponds to the configuration shown in (A) with transistor 3001 and wiring 3012 omitted. do.

[0609] Alternatively, the protection circuit 3000 shown in Figure 51(D) may be used as a protection circuit. Figure 51 The configuration shown in (D) is the same as the configuration shown in Figure 51(A), but with wiring 3011 and wiring 3012 A transistor 3003 is connected in series between them, and between wiring 3011 and wiring 3013 This corresponds to a configuration where Rangista 3004s are connected in series.

[0610] In Figure 51(D), transistor 3003 has its first terminal connected to wiring 3012. The second terminal is connected to the first terminal of transistor 3001, and the gate is the transistor It is connected to the first terminal of 3001. Transistor 3004 is connected to the first terminal of wire 3 It is connected to 013, and the second terminal is connected to the first terminal of transistor 3002, and the gate It is connected to wiring 3013.

[0611] Alternatively, the protection circuit 3000 shown in Figure 51(E) may be used as a protection circuit. Figure 51 The configuration shown in (E) is the same as the configuration shown in Figure 51(D), where the gate of transistor 3001 This is connected to the gate of transistor 3003, and the gate of transistor 3002 is connected to the transistor This corresponds to the gate connected to ST3004.

[0612] Alternatively, the protection circuit 3000 shown in Figure 51(F) may be used as a protection circuit. Figure 51 The configuration shown in (F) is the same as the configuration shown in Figure 51(A), but with wiring 3011 and wiring 3012 Transistors 3001 and 3003 are connected in parallel between them, and wiring 3011 and Transistors 3002 and 3004 are connected in parallel between wiring 3013 and the circuit. To deal with things.

[0613] In Figure 51(F), transistor 3003 has its first terminal connected to wiring 3012. The second terminal is connected to wiring 3011, and the gate is connected to wiring 3011. Furthermore, transistor 3004 has its first terminal connected to wiring 3013, and its second terminal connected to wiring It is connected to 3011, and the gate is connected to wiring 3013.

[0614] Alternatively, the protection circuit 3000 shown in Figure 51(G) may be used as a protection circuit. Figure 51 The configuration shown in (G) is the same as the configuration shown in Figure 51(A), but the gate of transistor 3001 A capacitive element 3005 and a resistive element 3006 are connected in parallel between the transistor and the first terminal. Between the gate of the Zistor 3002 and the first terminal, there is a capacitive element 3007 and a resistive element 3008. This corresponds to a configuration where these are connected in parallel.

[0615] By applying the configuration shown in Figure 51(G), the destruction or deterioration of the protection circuit 3000 itself can be prevented. It can be prevented.

[0616] For example, if a voltage higher than the power supply potential is supplied to wiring 3011, transistor 30 The potential difference (Vgs) between the gate and source of transistor 01 increases. Therefore, transistor 3 Since 001 is turned on, the voltage across wiring 3011 decreases. However, transistor 3 A large voltage is applied between the gate of 001 and the second terminal, so transistor 300 1 may be destroyed or deteriorated. To prevent this, capacitive element 3005 is used The gate voltage of transistor 3001 is increased, and the gate and source of transistor 3001 are Reduce the potential difference (Vgs) between them.

[0617] Specifically, when transistor 3001 is turned on, the first The voltage at the terminal rises instantaneously. Then, due to the capacitive coupling of the capacitive element 3005, the traction The gate voltage of transistor 3001 increases. Because the potential difference (Vgs) between the source and the transistor can be reduced, This can suppress the destruction or deterioration of 001.

[0618] Similarly, if a voltage lower than the power supply potential is supplied to wiring 3011, transistor 30 The voltage at the first terminal of 02 decreases instantaneously. Then, due to the capacitive coupling of the capacitive element 3007 Then, the gate voltage of transistor 3002 decreases. In this way, transistor 3 Because the potential difference (Vgs) between the gate and source of 002 can be reduced, This can suppress the destruction or deterioration of the radiator 3002.

[0619] Next, regarding the configuration of the semiconductor device equipped with a protection circuit, see Figures 52(A) and 52(B). I will use it to explain.

[0620] Figure 52(A) shows an example of a semiconductor device configuration with a protection circuit on the gate wire. Figure 52 In (A), gate line 3102_1 and gate line 3102_2 are respectively shown in Figure 51( A) This corresponds to wiring 3011 in Figure 51(G).

[0621] Wirings 3012 and 3013 are wiring connected to the gate driver circuit 3100. It is connected to the other side. This configuration activates the protection circuit 3000. Since the power supply voltage of the gate driver circuit can be used as the power supply voltage, The number of types of voltage and the number of wires required to supply power voltage to the protection circuit 3000 can be reduced. Cut.

[0622] Figure 52(B) shows that a protection circuit is provided at the terminals to which signals or voltages are supplied from an external source such as an FPC. An example of the configuration of a semiconductor device is shown. In Figure 52(B), wiring 3012 and wiring 301 3 is connected to one of the external terminals. For example, wiring 3012 is connected to terminal 3101a. In such cases, the protection circuit provided at terminal 3101a omits transistor 3001. It can be omitted. Similarly, if wiring 3013 is connected to terminal 3101b, terminal 3 In the protection circuit provided at 101b, transistor 3002 can be omitted. The same applies to the protection circuits provided at terminals 3101c and 3101d.

[0623] By using this configuration, the number of transistors can be reduced, This allows for a reduction in the footprint.

[0624] (Embodiment 9) In this embodiment, the structure of a display device having a transistor and a display element, and the transistor The structure of the 'Ta' will be explained with reference to Figures 53(A) to 53(C).

[0625] Examples of transistors include field-effect transistors and bipolar transistors. Thin-film transistors (also called "TFTs") are used as field-effect transistors. It is acceptable to have one. Also, as a field-effect transistor, a top-gate type transistor, or A bottom-gate transistor may also be used. Therefore, channel etch type transistors or bottom contact type ("inverse coplanar type") Also known as ), a transistor of the type ) is an example. Field-effect transistors are N-type or P-type. It may also be made into a conductive type.

[0626] Furthermore, a field-effect transistor consists of, for example, a gate electrode, a source region, a channel region, and a semiconductor layer having a drain region, and a cross-sectional view of the gate electrode and the semiconductor layer It is composed of a gate insulating layer and a semiconductor layer. The semiconductor layer uses a semiconductor film or a semiconductor substrate. It is formed by being formed.

[0627] Semiconductor materials applied to semiconductor films or semiconductor substrates include amorphous semiconductors and microcrystalline semiconductors. Examples include solids, single-crystal semiconductors, and polycrystalline semiconductors. Furthermore, oxide semiconductors are also used as semiconductor materials. You may use your body.

[0628] As oxide semiconductors, quaternary metal oxides (In-Sn-Ga-Zn-O metal oxides) ), ternary metal oxides (In-Ga-Zn-O metal oxides, In-Sn-Zn-O metal oxides) Metal oxides, In-Al-Zn-O metal oxides, Sn-Ga-Zn-O metal oxides, Al-Ga-Zn-O metal oxides, Sn-Al-Zn-O metal oxides, etc., and two Element-based metal oxides, etc. (In-Zn-O-based metal oxides, Sn-Zn-O-based metal oxides, Al- Zn-O metal oxide, Zn-Mg-O metal oxide, Sn-Mg-O metal oxide, I n-Mg-O metal oxides, In-Ga-O metal oxides, In-Sn-O metal oxides Examples include, etc. Furthermore, examples of oxide semiconductors include In-O metal oxides and Sn-O metal oxides. Oxides, Zn-O-based metal oxides, etc. can also be used. In addition, as an oxide semiconductor, Oxide semiconductor containing SiO2 in a metal oxide that can be used as an oxide semiconductor. You can also use this.

[0629] In addition, as an oxide semiconductor, InMO3(ZnO) m Materials represented by (m>0) are used. It is possible. Here, M is one selected from Ga, Al, Mn, and Co or It indicates multiple metallic elements. For example, M can be Ga, Ga and Al, Ga and Mn, Ga And Co, etc. are examples.

[0630] Figures 53(A) and 53(B) show the structure of a display device having a transistor and a display element. Here is an example. As a transistor, Figure 53(A) shows a top-gate type transistor, Figure 5 3(B) uses a bottom-gate transistor.

[0631] In Figure 53(A), the substrate 5260 and the insulating layer 5261 provided on the substrate 5260 are shown. And a semiconductor layer 5 provided on the insulating layer 5261, having regions 5262a to 5262e 262, an insulating layer 5263 provided to cover the semiconductor layer 5262, and a semiconductor layer 526 2 and conductive layer 5264 provided on insulating layer 5263, insulating layer 5263 and conductive layer 52 An insulating layer 5265 having an opening is provided on 64, and on the insulating layer 5265 and insulating layer 52 The conductive layer 5266 provided in the opening 65 is shown.

[0632] In Figure 53(B), the substrate 5300 and the conductive layer 5301 provided on the substrate 5300 are shown. The insulating layer 5302 is provided so as to cover the conductive layer 5301, and the conductive layer 5301 and the insulating layer A semiconductor layer 5303a provided on layer 5302, and a semiconductor layer provided on semiconductor layer 5303a Conductor layer 5303b and conductive layer 53 provided on semiconductor layer 5303b and insulating layer 5302 04 and an insulating layer 5302 and an insulating layer 5304 provided on the conductive layer 5304, having an opening 5 and the conductive layer 5306 provided on the insulating layer 5305 and in the opening of the insulating layer 5305, show.

[0633] Furthermore, Figure 53(C) shows another example of the structure of a transistor. A semiconductor substrate 5352 having region 5353 and region 5355, and on the semiconductor substrate 5352 An insulating layer 5356 provided on the semiconductor substrate 5352, and an insulating layer 5354 provided on the semiconductor substrate 5352, A conductive layer 5357 provided on the insulating layer 5356, and the insulating layer 5354, insulating layer 5356, and An insulating layer 5358 having an opening is provided on the conductive layer 5357, and on the insulating layer 5358 and The conductive layer 5359 is provided in the opening of the insulating layer 5358. Figure 53(C) shows, A transistor is provided in both region 5350 and region 5351. Figure 53(C) The transistor structure shown is applied to the transistors shown in Figures 53(A) and 53(B). That's fine.

[0634] Furthermore, as shown in Figure 53(A), the conductive layer 5266 and the insulating layer 5265 are provided, An insulating layer 5267 having an opening, and provided in the insulating layer 5267 and the opening of the insulating layer 5267 A conductive layer 5268 is provided on the insulating layer 5267 and the conductive layer 5268, and has an opening. An insulating layer 5269 and an EL layer provided on the insulating layer 5269 and in the openings of the insulating layer 5269 The 5270, the insulating layer 5269, and the conductive layer 5271 provided on the EL layer 5270 are shown. The display device may also have one. The same applies to the display device in Figure 53(B).

[0635] As shown in Figure 53(B), the insulating layer 5305 and the conductive layer 5306 are arranged on top of each other. The display device has a liquid crystal layer 5307 and a conductive layer 5308 provided on the liquid crystal layer 5307. It may be done as is. The same applies to the display device in Figure 53(A).

[0636] The insulating layer 5261 functions as a base layer. The insulating layer 5354 is an inter-element isolation layer (for example). It functions as a field oxide film. Insulating layer 5263, insulating layer 5302, and insulating layer 5 356 functions as a gate insulating film. Conductive layer 5264, conductive layer 5301, and conductive layer 5357 functions as a gate electrode. Insulating layer 5265, insulating layer 5267, insulating layer 53 05, and the insulating layer 5358 function as an interlayer film or planarizing film. Conductive layer 5266, The electrolytic layer 5304 and the conductive layer 5359 are used for wiring, transistor electrodes, or capacitive element electrodes. It functions as a pixel electrode or reflective electrode. The insulating layer 5269 functions as a partition. The conductive layer 5271 and conductive layer 5308 are It functions as either a counter electrode or a common electrode.

[0637] Substrates 5260 and 5300 include glass substrates, quartz substrates, semiconductor substrates (for example) (Silicon substrate, or single crystal substrate), SOI substrate, plastic substrate, metal substrate, stainless steel Stainless steel substrate, substrate having stainless steel foil, tungsten substrate, tungsten A substrate with foil or a flexible substrate may be used.

[0638] Using barium borosilicate glass, aluminobrosilicate glass, etc. as the glass substrate. This is also good. As a flexible substrate, polyethylene terephthalate (PET), polyethylene Plastics such as phthalates (PEN) and polyethersulfones (PES), Alternatively, flexible synthetic resins such as acrylic may be used. Materials (polypropylene, polyester, vinyl, polyvinyl fluoride, polyvinyl chloride, etc.), fibers Paper containing fibrous materials, base film (polyester, polyamide, polyimide, inorganic vapor deposition) You may also use film, paper, etc.

[0639] As the semiconductor substrate 5352, a single-crystal silicon substrate having an n-type or p-type conductivity is used. It may be used as a semiconductor substrate 5352, or a part or all of the single-crystal silicon substrate may be used as a semiconductor substrate 5352. It may also be used as follows. Region 5353 is a region in which impurity elements are added to the semiconductor substrate 5352. Yes, and it functions as a well. For example, if the semiconductor substrate 5352 has a p-type conductivity. Region 5353 has an n-type conductivity and functions as an n-well. Also, semiconductor substrate 53 If 52 has an n-type conductivity, then region 5353 has a p-type conductivity and as a p-well It works. Region 5355 is a region in which impurity elements are added to the semiconductor substrate 5352. It functions as a source region or drain region. Furthermore, the semiconductor substrate 5352 has an LDD(L A heavily doped drain area may be provided.

[0640] The insulating layer 5261 can be a silicon oxide film, a silicon nitride film, or silicon oxide nitride (SiO₂). x N y )( x>y>0) film, silicon dioxide nitride (SiN x O y (x>y>0) A membrane or the like that contains oxygen or nitrogen This includes films, or laminated structures thereof. This applies when the insulating layer 5261 is provided in a two-layer structure. For example, a silicon nitride film is used as the first insulating layer, and a silicon oxide film is used as the second insulating layer. An example of a girder insulating layer is when the insulating layer 5261 is provided in a three-layer structure. The first insulating layer is a silicon oxide film, the second insulating layer is a silicon nitride film, and the third insulating layer is An example is an insulating layer provided with a silicon oxide film.

[0641] The semiconductor layers 5262, 5303a, and 5303b are non-single crystals. Semiconductors (e.g., amorphous silicon, polycrystalline silicon, microcrystalline silicon, etc.) ), single-crystal semiconductors, compound semiconductors, or oxide semiconductors (for example, ZnO, InGaZn) O, SiGe, GaAs, IZO (Indium Zinc Oxide), ITO (Indium Tin Oxide) Materials, SnO, TiO, AlZnSnO(AZTO), organic semiconductors, or carbon nano Tubes or similar can be used.

[0642] Furthermore, region 5262a is in its intrinsic state where no impurity elements are added to the semiconductor layer 5262. It is in a state and functions as a channel region. Furthermore, when an impurity element is added to region 5262a It is also acceptable. The impurity elements added to region 5262a are those in regions 5262b and 5262c. The concentration of the impurity element added to region 5262d or region 5262e is lower than that of the impurity element added to region 5262e. Preferred. Regions 5262b and 5262d are better than regions 5262c and 5262e. This is a region where even lower concentrations of impurity elements are added to the semiconductor layer 5262, and LDD (Light It functions as a (Tly Doped Drain) region. Note that region 5262b and region 5262d may be omitted. Regions 5262c and 5262e are sources of high-concentration impurities. The element is a region added to semiconductor layer 5262 and functions as either a source region or a drain region. do.

[0643] Furthermore, semiconductor layer 5303b is a semiconductor layer to which phosphorus and other impurity elements are added. It has an n-type conductivity. The semiconductor layer 5303a is an oxide semiconductor or a compound semiconductor. When a body is used, the semiconductor layer 5303b may be omitted.

[0644] Insulating layer 5263 and insulating layer 5356 are silicon oxide film, silicon nitride film, silicon oxide nitride ( SiO x N y (x>y>0) film, silicon nitride (SiN x O y (x>y>0) membranes etc. A membrane containing oxygen or nitrogen, or a laminated structure thereof, may be used.

[0645] Conductive layer 5264, conductive layer 5266, conductive layer 5268, conductive layer 5271, conductive layer 5301 , conductive layer 5304, conductive layer 5306, conductive layer 5308, conductive layer 5357, and conductive layer 53 As for 59, a single-layer conductive film or a laminated structure thereof may be used. Aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo) , tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni), platinum ( Platinum (Pt), gold (Au), silver (Ag), copper (Cu), manganese (Mn), cobalt (Co), Niobium (Nb), silicon (Si), iron (Fe), palladium (Pd), carbon (C), s Candium (Sc), zinc (Zn), gallium (Ga), indium (In), tin (Sn A group consisting of ), zirconium (Zr), and cerium (Ce), selected from this group A single elemental film, or a film containing one or more elements selected from this group. A membrane made of a compound may be used. Note that the elemental membrane or the compound is phosphorus (P) It may also contain boron (B), arsenic (As), or oxygen (O), etc.

[0646] The above compound may be one or more elements selected from the aforementioned multiple elements. Compounds containing (e.g., alloys), one or more elements selected from the aforementioned multiple elements. Compounds of several elements with nitrogen (e.g., nitride films), one selected from the aforementioned multiple elements Compounds of elements or multiple elements with silicon (e.g., silicide films), or nanotubes These include various materials. Alloys include indium tin oxide (ITO) and indium zinc oxide. (IZO), indium tin oxide (ITSO) containing silicon dioxide, zinc oxide (ZnO), acid Tin oxide (SnO), cadmium tin oxide (CTO), aluminum neodymium (Al-Nd), Aluminum tungsten (Al-W), aluminum zirconium (Al-Zr), A Titanium aluminum (Al-Ti), Cerium aluminum (Al-Ce), Magnesium Silver (Mg-Ag), Molybdenum niobium (Mo-Nb), Molybdenum tungsten (Mo- Examples include W), or molybdenum tantalum (Mo-Ta), etc. Examples of nitride films include titanium nitride, Examples include tantalum nitride and molybdenum nitride. As for silicide films, tungsten silicide is used. Titanium silicide, nickel silicide, aluminum silicon, or molybdenum Examples include Ricon. Nanotube materials include carbon nanotubes and organic nanotubes. These include inorganic nanotubes, or metallic nanotubes, etc.

[0647] Insulating layer 5265, insulating layer 5267, insulating layer 5269, insulating layer 5305, and insulating layer 53 For 58, a single-layer insulating layer or a laminated structure thereof may be used. Examples include silicon oxide film, silicon nitride film, or silicon oxide nitride (SiO₂). x N y )(x>y> 0) Film, silicon dioxide nitride (SiN x O y (x>y>0) Membrane containing oxygen or nitrogen , a carbon-containing film such as DLC (diamond-like carbon), or siloxane resin, Poxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, or These include films made of organic materials such as acrylic.

[0648] The EL layer 5270 has a light-emitting layer made of a light-emitting material. In addition to the light-emitting layer, hole injection material A hole injection layer made of a hole transport material, a hole transport layer made of a hole transport material, and an electron transport layer made of an electron transport material. A layer, an electron injection layer made of electron injection materials, or a layer made by mixing multiple of these materials. It may also include, etc. The conductive layer 5268, the EL layer 5270, and the conductive layer 5271, An organic EL element is formed.

[0649] The liquid crystal layer 5307 has a liquid crystal containing multiple liquid crystal molecules. The state of the liquid crystal molecules is mainly determined by the pixels. The voltage applied between the electrode and the counter electrode determines the light transmittance of the liquid crystal, which changes accordingly. Examples of liquid crystals include electrically controlled birefringent liquid crystals (also called ECB type liquid crystals) and dichroic dyes. Using additive liquid crystals (also called GH liquid crystals), polymer-dispersed liquid crystals, discotic liquid crystals, etc. It is possible to use a liquid crystal that exhibits a blue phase. For example, the liquid crystal is composed of a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent. Because liquid crystals exhibiting the blue phase have a short response time of less than 1 msec and are optically isotropic. Furthermore, it does not require alignment processing and has low viewing angle dependence. Therefore, a liquid crystal exhibiting the blue phase is used. This allows for improved operating speed.

[0650] Furthermore, on the insulating layer 5305 and the conductive layer 5306, there is an insulating layer that functions as an alignment film, and a projection. An insulating layer or the like that functions as a starting point may be provided.

[0651] Furthermore, the conductive layer 5308 may have a color filter, a black matrix, or protrusions. An insulating layer or the like that which functions as such may be formed. Below the conductive layer 5308, a film that functions as an alignment layer may be formed. An insulating layer may be formed.

[0652] The display device of this embodiment includes the gate driver circuit and semiconductor circuit described in the above embodiment. Conductor devices can be applied. Also, the transistor described in this embodiment can be used as described above. It can be used in the gate driver circuit and semiconductor device described in the embodiment. In particular, Non-single-crystal semiconductors such as amorphous semiconductors or microcrystalline semiconductors are used as semiconductor layers in transistors. Even when using organic semiconductors or oxide semiconductors, etc., as described in the above embodiment, By having a gate driver circuit and a semiconductor device configuration, transistor degradation is reduced. It is possible to obtain effects such as suppression.

[0653] (Embodiment 10) In this embodiment, the configuration of the display device is shown with reference to Figures 54(A) to 54(C). Let me explain. As an example of the configuration of the display device, Figure 54(A) shows a top view of the display device, Figure 54 Figures (B) and 54(C) show cross-sectional views of AB in Figure 54(A), respectively.

[0654] In Figure 54(A), the substrate 5400 is provided with a drive circuit 5392 and a pixel unit 5393. The drive circuit 5392 includes a gate driver circuit or a source driver circuit, etc. do.

[0655] Figure 54(B) shows a substrate 5400 and a conductive layer 5401 provided on the substrate 5400. An insulating layer 5402 is provided so as to cover the conductive layer 5401, and the conductive layer 5401 and the insulating layer 5 A semiconductor layer 5403a provided on 402, and a semiconductor provided on semiconductor layer 5403a Layer 5403b and conductive layer 5404 provided on semiconductor layer 5403b and insulating layer 5402 And, an insulating layer 5405 having an opening is provided on the insulating layer 5402 and the conductive layer 5404, A conductive layer 5406 provided on the insulating layer 5405 and in the openings of the insulating layer 5405, and insulating layer 5 An insulating layer 5408 is disposed on 405 and the conductive layer 5406, and an insulating layer 5405 is provided on the insulating layer 5405 A liquid crystal layer 5407 and a conductive layer 540 provided on the liquid crystal layer 5407 and the insulating layer 5408. The diagram shows 9 and the substrate 5410 provided on the conductive layer 5409.

[0656] The conductive layer 5401 functions as a gate electrode. The insulating layer 5402 functions as a gate insulating film. It functions as a wiring, transistor electrode, or capacitive element electrode. It functions. The insulating layer 5405 functions as an interlayer film or planarizing film. The conductive layer 5406 is It functions as wiring, pixel electrodes, or reflective electrodes. The insulating layer 5408 acts as a sealing material. The conductive layer 5409 functions as a counter electrode or a common electrode.

[0657] Here, parasitic capacitance may occur between the drive circuit 5392 and the conductive layer 5409. As a result, the output signal of the drive circuit 5392 or the potential of each node may be distorted or delayed. This can lead to problems. Additionally, the power consumption of the drive circuit 5392 will increase.

[0658] On the other hand, as shown in Figure 54(B), on the drive circuit 5392, there is a material that functions as a sealant, and By providing an insulating layer 5408 with a dielectric constant lower than that of the liquid crystal layer, the drive circuit 5392 and The parasitic capacitance between the conductive layer 5409 and the other component can be reduced. Therefore, the drive circuit This can reduce the smearing or delay of the output signal of 5392 or the potential of each node. Alternatively, the power consumption of the drive circuit 5392 can be reduced.

[0659] Furthermore, as shown in Figure 54(C), a sealing material is placed on a part of the drive circuit 5392. The same effect can be obtained by providing an insulating layer 5408 that can perform the function. If there is no concern about the effects of [unspecified factor], the insulating layer 5408 may be omitted.

[0660] In this embodiment, a display device equipped with a liquid crystal element having a liquid crystal layer will be described. However, in addition to liquid crystal elements, display elements of display devices may also use EL elements or electrophoretic elements. It is possible to be there.

[0661] In the display device of this embodiment, the parasitic capacitance of the drive circuit can be reduced, so the output signal or The delay or saturation of the potential at each node can be reduced. Therefore, the transistor's electrical potential Since high current supply capacity is not required, the channel width of the transistor can be reduced. This is possible. Therefore, the layout area of ​​the drive circuit can be reduced, and the bezel of the display device can be narrowed or High resolution can be achieved.

[0662] (Embodiment 11) In this embodiment, the layout diagram (also called the top view) of the semiconductor device will be described. As an example, Figure 55 shows a layout diagram of the semiconductor device shown in Figure 31(B).

[0663] The semiconductor device shown in Figure 55 consists of a conductive layer 901, a semiconductor layer 902, a conductive layer 903, and a conductive layer 9 It has 04 and a contact hole 905. Note that other conductive layers or contact holes, Alternatively, it may have an insulating film or the like. For example, connecting conductive layer 901 and conductive layer 903. Contact holes may be formed for this purpose.

[0664] The conductive layer 901 includes a portion that functions as a gate electrode or wiring. The semiconductor layer 902 is It includes a portion that functions as a semiconductor layer of the transistor. The conductive layer 903 is used for wiring, source, and It includes a portion that functions as a drain. The conductive layer 904 is a transparent electrode, a pixel electrode, or a wiring Includes a portion that functions as such. Through the contact hole 905, conductive layer 901 and conductive layer 9 It is possible to connect 04, or to connect conductive layer 903 and conductive layer 904.

[0665] Furthermore, the semiconductor layer 902 is formed in the portion where the conductive layer 901 and the conductive layer 903 overlap. Therefore, the parasitic capacitance between the conductive layer 901 and the conductive layer 903 can be reduced, Noise can be reduced. For the same reason, the conductive layer 901 and the conductive layer 904 overlap. Even if a semiconductor layer 902 is provided in the portion where the conductive layer 903 and the conductive layer 904 overlap, good.

[0666] Furthermore, a conductive layer 904 is formed on a portion of the conductive layer 901, and a contact hole 905 is used. By connecting the conductive layer 901 and the conductive layer 904, the wiring resistance is reduced. It is possible.

[0667] Furthermore, conductive layers 903 and 904 are formed on a portion of conductive layer 901, and contact The conductive layer 901 and the conductive layer 904 are connected through hole 905, and another contact hole The conductive layer 903 and the conductive layer 904 are connected via the 905, thereby reducing the wiring resistance. It can be lowered even further.

[0668] Furthermore, a conductive layer 904 is formed on a portion of the conductive layer 903, and a contact hole 905 is formed via By connecting conductive layer 903 and conductive layer 904, the wiring resistance is reduced. It is possible.

[0669] Furthermore, a conductive layer 901 or a conductive layer 903 is formed beneath a portion of the conductive layer 904, and contact The conductive layer 904 is connected to the conductive layer 901 or the conductive layer 903 via the hole 905. This can reduce wiring resistance.

[0670] (Embodiment 12) In this embodiment, the gate driver circuit and semiconductor device described in the above embodiment, Alternatively, an example of an electronic device using a display device, and an example of an application of a semiconductor device are shown in Figure 56(A). Refer to Figure 57(H) for further explanation.

[0671] Figures 56(A) to 56(H) and 57(A) to 57(D) show examples of electronic devices. The diagram shows the following electronic devices: housing 5000, display unit 5001, speaker 5003 LED lamp 5004, operation key 5005, connection terminal 5006, sensor 5007, My It has a crossphone 5008, etc. Note that the operation key 5005 is the power switch or operation switch. Includes a touch. The sensor 5007 measures force, displacement, position, velocity, acceleration, angular velocity, and rotational speed. Distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, electric current, voltage, power, It has the function of measuring radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation.

[0672] Figure 56(A) shows a mobile computer, and in addition to the above, it has a switch 5009 It has an infrared port 5010, etc. Figure 56(B) shows a portable image playback device equipped with a recording medium. The device (for example, a DVD player) includes, in addition to the above, a display unit 5002, a recording medium It has a body reading unit 5011, etc. Figure 56(C) is a goggle-type display, and as described above. In addition to the above, it also has a display unit 5002, a support unit 5012, an earphone 5013, etc. Figure 56 ( D) is a portable gaming machine and, in addition to the above-mentioned components, also includes a recording medium reading unit 5011, etc.

[0673] Figure 56(E) shows a projector, which, in addition to the above-mentioned components, includes a light source 5033 and a projection lens. It has 5034, etc. Figure 56(F) is a portable gaming machine, and in addition to the above, it has a display unit It has 5002, a recording medium reading unit 5011, etc. Figure 56(G) is a television receiver, and above In addition to those mentioned above, it also has a tuner, an image processing unit, etc. Figure 56(H) is a portable television. It is a receiver and, in addition to the above, includes a charger 5017 capable of transmitting and receiving signals.

[0674] Figure 57(A) shows a display, which, in addition to the above-mentioned components, also includes a support base 5018, etc. Figure 57(B) shows the camera, and in addition to the above, it has an external connection port 5019, shutter It has a turbuton 5015, an image receiving unit 5016, etc. Figure 57(C) is a computer. In addition to the above, there is a pointing device 5020, an external connection port 5019, and a Lee It has a data / writer 5021, etc. Figure 57(D) is a mobile phone, and in addition to the above, It includes antennas, tuners for 1-segment partial reception services for mobile phones and mobile terminals, etc. do.

[0675] Furthermore, the electronic devices shown in Figures 56(A) to 56(H) and Figures 57(A) to 57(D) It may have various other functions besides those mentioned above.

[0676] For example, a function to display information (still images, videos, text images, etc.) on the display unit, touch panel Functions that display calendar, date, or time, etc., and software (programs, etc.) Functions to control processing, wireless communication functions, and computer networks using wireless communication functions. Functions for connecting to a workpiece, functions for transmitting or receiving data using wireless communication, recording medium It has functions such as reading programs or data recorded in the body and displaying them on the display unit. It's fine if you do that.

[0677] Furthermore, in electronic devices having multiple display units, one display unit primarily displays video information. A function that displays a text information section and primarily displays text information on another display section, or displays text information on multiple display sections. It may also have a function to display a three-dimensional image by displaying an image that takes parallax into account. .

[0678] Furthermore, electronic devices having an image receiving unit may have functions for taking still images and taking videos. Functions include automatically or manually correcting captured images, and storing captured images on a recording medium (external). Functions to save images (either on a device or built into an electronic device), functions to display captured images on a display unit, etc. It is acceptable to have it.

[0679] The electronic device described in this embodiment has a display unit for displaying some kind of information. The display unit of the electronic device of this embodiment is configured with the gate driver described in the above embodiment. By applying this to circuits, semiconductor devices, or display devices, reliability and yield can be improved. This allows for cost reduction, larger display area, and higher resolution display area.

[0680] Next, examples of semiconductor device applications will be explained with reference to Figures 57(E) to 57(H).

[0681] For an example of a semiconductor device installed in a building, refer to Figures 57(E) and 57(F). I will explain. Also, I will show an example of a semiconductor device being integrated with a mobile body in Figure 57(G) and This will be explained with reference to Figure 57(H).

[0682] In Figure 57(E), the semiconductor device is installed as an integral part of the building's wall. Figure 5 In 7(E), the semiconductor device consists of a housing 5022, a display unit 5023, and a remote control unit. Includes a control device 5024, a speaker 5025, etc. The semiconductor device is integrated with the building wall. Therefore, it can be installed without requiring a large space for the semiconductor device.

[0683] In Figure 57(F), the semiconductor device is integrated with the unit bath 5027, which is a building. It is provided as follows: The display panel 5026 that constitutes the semiconductor device is connected to the unit bus 5027 It is installed as an integral part of the bath, allowing bathers to view the display panel 5026.

[0684] Note that in Figures 57(E) and 57(F), walls and unit bathrooms are listed as examples of structures. However, semiconductor devices can also be installed in various other structures.

[0685] In Figure 57(G), the semiconductor device is located on the display panel 5028 of the automobile body 5029. It is installed and displays on demand information about the vehicle's operation or information input from inside or outside the vehicle. This is possible. Furthermore, the semiconductor device may also have a navigation function.

[0686] In Figure 57(H), the semiconductor device is integrated with the passenger aircraft. 57(H) states that a display panel 5031 was installed on the ceiling 5030 above the seats of a passenger aircraft. The following is a diagram showing the shape when in use. The display panel 5031 has a hinge portion 5032 It is attached integrally with the ceiling 5030 via the extension of the hinge portion 5032, allowing passengers to move in and out. This makes it possible to view the display panel 5031. The display panel 5031 can be operated by the passenger. It has the function of displaying information.

[0687] Note that in Figures 57(G) and 57(H), automobiles and airplanes are shown as examples of mobile vehicles, Other vehicles include motorcycles, four-wheeled vehicles (including cars, buses, etc.), and trains (monorails, railways, etc.). Semiconductor devices can be installed on various mobile objects such as ships, etc. [Examples]

[0688] In this embodiment, in a semiconductor device having two gate driver circuits, the gate signal line Circuit simulations confirm that the delay or distortion of the output signal is reduced. To testify.

[0689] In the circuit simulation, the semiconductor device described in Figure 31(B) of Embodiment 5 above is used. Used. In the semiconductor device shown in Figure 31(B), wiring 111 is the gate signal line, circuit 20 Circuits 0A and 200B correspond to gate driver circuits, respectively.

[0690] Figure 59 is a circuit diagram of a semiconductor device used as a comparative example. In Figure 59, Circuit 6200 is connected to transistors 6201, 6202, and 6301. It has transistors 6302, 6401, and 6402.

[0691] Transistor 6201 has its first terminal connected to wire 6112 and its second terminal connected to wire 6 It is connected to 111 and its gate is connected to node C1. Transistor 6202 is the first The terminal is connected to wire 6113, the second terminal is connected to wire 6111, and the gate is node It connects to C2.

[0692] Transistor 6301 has its first terminal connected to wiring 6114 and its second terminal connected to a node It is connected to C1 and its gate is connected to wiring 6114. Transistor 6302 is the first The terminal is connected to wiring 6113, the second terminal is connected to node C1, and the gate is connected to wiring 61 It is connected to 16. Transistor 6401 has its first terminal connected to wiring 6115, and the Terminal 2 is connected to node C2, and the gate is connected to wire 6115. Transistor 6 402 has its first terminal connected to wiring 6113 and its second terminal connected to node C2. The gate is connected to the gate of transistor 6201.

[0693] Figures 60(A) to 61 show the calculation results obtained from circuit simulation. PSpice was used for the process. The transistor threshold voltage was set to 5V, and the field effect was also considered. Movement by 1cm 2 We assumed / Vs. Furthermore, the voltage amplitude of the clock signal CK1 was set to 30V ( We assumed the H level potential to be 30V, the L level potential to be 0V, and the ground potential to be 0V.

[0694] Here, transistors 201A and 201B in Figure 31(B) and Figure The transistor 6201 used in 59 has the same characteristics. Similarly, the transistor Transistor 202A, transistor 202B, transistor 6202, transistor 301A, and Transistor 301B and transistor 6301, transistor 302A and transistor 30 2B and transistor 6302, transistor 401A and transistor 401B and transistor Transistor 6401, transistor 402A, transistor 402B, and transistor 6402, Each of them used materials with the same characteristics.

[0695] Also, wiring 113A and wiring 113B in Figure 31(B), and wiring 6 in Figure 59 The same voltage was applied to wire 113. Similarly, wires 114A, 114B, and 6114 The same start pulse (SP) is input to wires 116A, 116B, and 611. The same reset signal (RE) was input to 6. Also, the signal SELA was input to wiring 115A. The input was made, and the SELB signal was input to wiring 115B. A constant voltage was input to wiring 6115. did.

[0696] Figure 60(A) shows the results of a circuit simulation using the circuit diagram shown in Figure 31(B). The results are shown in Figure 60(B), which is obtained by circuit simulation using the circuit diagram shown in Figure 59. This is the calculation result. In Figure 60(A), the potential Va1 is at node A1 and the potential V is at node A2. a2, Vb1 of node B1, Vb2 of node B2, power of the output signal (OUT) of wiring 111 The position is shown. Also, in Figure 60(B), the potential Vc1 of node C1 and the potential V of node C2 are shown. c2 indicates the potential of the output signal (OUT) of signal line 6111.

[0697] Furthermore, using Figure 61, the potential of the output signal (OUT) of wiring 111 in Figure 60(A) This is compared with the potential of the output signal (OUT) of signal line 6111 in Figure 60(B).

[0698] As shown in Figure 61, the output signal (OUT) that is output to wiring 111 in Figure 60(A) However, the delay is reduced compared to the output signal (OUT) output to signal line 6111 in Figure 60(B). It was confirmed that this would happen. [Explanation of Symbols]

[0699] 10A circuit 10B circuit 10C circuit 10D Circuit 11 Wiring 50-pixel section 51 Gate Driver Circuit 52 Gate Driver Circuits 54 Gate Line 100A circuit 100B circuit 100C circuit 100D Circuit 101A switch 101B Switch 101C switch 101D Switch 102A switch 102B switch 102C switch 102D switch 103A switch 103B switch 111 Wiring 112 Wiring 112A wiring 112B Wiring 112C wiring 112D Wiring 113 Wiring 113A Wiring 113B Wiring 113C wiring 113D Wiring 114A Wiring 114B Wiring 115A wiring 115B Wiring 116A Wiring 116B Wiring 117A wiring 117B Wiring 118A Wiring 118B Wiring Route 121A Route 121B Route 122A Route 122B 200A circuit 200B circuit 201A Transistor 201B transistor 201pA transistor 201pB transistor 202A Transistor 202B transistor 202pA transistor 202pB transistor 203A Capacitive element 203B Capacitive element 204A Transistor 204B transistor 205A Transistor 205B transistor 206A Transistor 206B transistor 207A Transistor 207B transistor 211A diode 211B diode 212A diode 212B diode 300A circuit 300B circuit 301A Transistor 301B transistor 301pA transistor 301pB transistor 302A Transistor 302B Transistor 302pA transistor 302pB transistor 312A diode 312B diode 400A circuit 400B circuit 401A Transistor 401B transistor 401pA transistor 401pB transistor 402A Transistor 402B transistor 402pA transistor 402pB transistor 403A Resistor 403B Resistor 404A transistor 404B transistor 405A Transistor 405B transistor 406A transistor 406B transistor 407A Transistor 407B transistor 408A Transistor 408B transistor 409A Transistor 409B transistor 412A diode 412B diode 500A circuit 500B circuit 501A Transistor 501B transistor 502A Transistor 502B transistor 901 Conductive layer 902 Semiconductor layer 903 Conductive layer 904 Conductive layer 905 Contact Hole 1001 Circuit 1002 Circuit 1002a Circuit 1002b Circuit 1003 Circuit 1004 pixel section 1005 terminal 1006 substrate 1100A Shift Register 1100B Shift Register 1101A Flip-Flop 1101B Flip-Flop 1111 Wiring 1112 Wiring 1112A Wiring 1112B Wiring 1113 Wiring 1113A Wiring 1113B Wiring 1114 Wiring 1114A Wiring 1114B Wiring 1115A Wiring 1115B Wiring 1116 Wiring 1116A Wiring 1116B Wiring 1119 Wiring 1119A Wiring 1119B Wiring 2001 Circuit 2002 Circuit 2003 Transistor 2004 Wiring 2005 Wiring 2006A Gate Driver Circuit 2006B Gate Driver Circuit 2007 Pixel section 2008 Source Line 2014 signal 2015 signal 3000 protection circuit 3001 Transistor 3002 Transistor 3003 Transistor 3004 Transistor 3005 Capacitive element 3006 Resistor element 3007 Capacitive element 3008 Resistor element 3011 Wiring 3012 Wiring 3013 Wiring 3020 pixels 3021 Transistor 3022 liquid crystal element 3023 Capacitive element 3031 Wiring 3032 Wiring 3033 Wiring 3034 Electrode 3100 Gate Driver Circuit 3101a terminal 3101b terminal 3101c terminal 3101d terminal 3102 Gate Line 5000 cabinets 5001 Display section 5002 Display section 5003 Speaker 5004 LED Lamp 5005 Operation Keys 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared Port 5011 Recording medium reading unit 5012 Support part 5013 Earphones 5015 Shutter button 5016 Image receiving unit 5017 charger 5018 Support stand 5019 External connection port 5020 Pointing Device 5021 Leader / Writer 5022 enclosure 5023 Display section 5024 Remote control device 5025 Speaker 5026 Display Panel 5027 Unit Bathroom 5028 Display Panel 5029 Car body 5030 Ceiling 5031 Display Panel 5032 Hinge section 5033 Light source 5034 Projection Lens 5102 pixel section 5108 Gate Driver Circuit 5110 Gate Driver Circuit 5112 Source Driver Circuit 5260 circuit board 5261 Insulating layer 5262 Semiconductor layer 5262a area 5262b area 5262c area 5262d area 5262e area 5263 Insulating layer 5264 Conductive layer 5265 Insulating layer 5266 Conductive layer 5267 Insulating layer 5268 Conductive layer 5269 Insulating layer 5270 EL layer 5271 Conductive layer 5300 circuit boards 5301 Conductive layer 5302 Insulating layer 5303a Semiconductor layer 5303b Semiconductor layer 5304 Conductive layer 5305 Insulating layer 5306 Conductive layer 5307 Liquid crystal layer 5308 Conductive layer 5350 area 5351 area 5352 Semiconductor substrate 5353 area 5354 Insulating layer 5355 area 5356 Insulating layer 5357 Conductive layer 5358 Insulating layer 5359 Conductive layer 5392 Drive Circuit 5393 pixel section 5400 circuit boards 5401 Conductive layer 5402 Insulating layer 5403a Semiconductor layer 5403b Semiconductor layer 5404 Conductive layer 5405 Insulating layer 5406 Conductive layer 5407 Liquid crystal layer 5408 Insulating layer 5409 Conductive layer 5410 circuit board 6111 Wiring 6112 Wiring 6113 Wiring 6114 Wiring 6115 Wiring 6116 Wiring 6200 circuits 6201 Transistor 6202 Transistor 6301 Transistor 6302 Transistor 6401 Transistor 6402 transistor

Claims

[Claim 1] Gate signal line and, A first gate driver circuit and a second gate driver circuit that output a selection signal and a deselection signal to the gate signal line, It has a plurality of pixels that are electrically connected to the gate signal line and to which the selection signal and the deselection signal are input, During the period in which the gate signal line is selected, both the first gate driver circuit and the second gate driver circuit output the selection signal to the gate signal line. A semiconductor device characterized in that, during the period when the gate signal line is not selected, one of the first gate driver circuit and the second gate driver circuit outputs the non-selection signal to the gate signal line, and the other of the first gate driver circuit and the second gate driver circuit does not output the selection signal or the non-selection signal to the gate signal line.

Images