Display devices and electronic equipment

Abstract

The present invention provides a display device having a pixel circuit that generates a PWM signal. [Solution] A display device having a function to generate a PWM signal in its pixels, which can generate a PWM signal by comparing the gate-source voltage or on-resistance of two transistors provided in the pixel. The generated PWM signal is used to control the light emission of a light-emitting device such as a micro-LED or organic EL element on a duty cycle. Since the PWM signal is generated by a circuit composed of a small number of transistors, it is effective for increasing the resolution and area of ​​the display device.

Description

Technical Field

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification or the like relates to an article, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a storage device, an imaging device, an operation method thereof, or a manufacturing method thereof.

[0003] Note that in this specification or the like, the semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one aspect of the semiconductor device. In addition, a storage device, a display device, an imaging device, and an electronic device may include a semiconductor device.

Background Art

[0004] In recent years, display devices and lighting devices equipped with micro light-emitting diodes (hereinafter, micro LEDs (LED: Light Emitting Diode)) have been proposed (for example, Patent Document 1). A display device equipped with micro LEDs can display with high brightness, has high reliability, and is promising as a next-generation display.

[0005] In addition, a technique for constructing a transistor using a metal oxide formed on a substrate has attracted attention. For example, techniques for using a transistor using zinc oxide or an In-Ga-Zn-based oxide as a switching element of a pixel of a display device are disclosed in Patent Document 2 and Patent Document 3.

Prior Art Documents

Patent Documents

[0006] [Patent Document 1] U.S. Patent Application Publication No. 2014 / 0367705 [Patent Document 2] Japanese Patent Publication No. 2007-123861 [Patent Document 3] Japanese Patent Publication No. 2007-96055 [Overview of the project] [Problems that the invention aims to solve]

[0007] In display devices using light-emitting devices (also called light-emitting elements), brightness is changed by controlling the current flowing through the light-emitting device. However, LEDs, one type of light-emitting device, have a characteristic where their chromaticity is easily changed depending on the current density. Therefore, when driving LEDs, it is preferable to keep the current value constant and perform display using pulse width modulation (PWM) control. By using PWM control, the desired brightness can be obtained without causing chromaticity shifts.

[0008] PWM signals are typically generated using comparators. Therefore, in small display devices such as microdisplays, this can be addressed by using a Si wafer as the substrate and forming pixel circuits containing comparators on the Si wafer.

[0009] For relatively large display devices, this can be addressed by implementing an IC chip with a comparator built into each pixel. However, this presents a problem as the cost of the IC chip and its implementation becomes very high. Alternatively, a CMOS-configured comparator can be formed within the pixel using polycrystalline silicon formed on an insulating substrate, but this is unsuitable for high-resolution displays due to the large number of transistors and wiring required.

[0010] Therefore, one aspect of the present invention aims to provide a display device having a pixel circuit that generates a PWM signal with a small number of transistors. Alternatively, one aspect aims to provide a display device having a pixel circuit that generates a PWM signal using only transistors of the same conductivity type. Alternatively, one aspect aims to provide a display device having excellent display characteristics. Alternatively, one aspect aims to provide an inexpensive display device.

[0011] Alternatively, one of the objectives is to provide a low-power display device. Alternatively, one of the objectives is to provide a highly reliable display device. Alternatively, one of the objectives is to provide a novel display device, etc. Alternatively, one of the objectives is to provide an operating method for the above-mentioned display device. Alternatively, one of the objectives is to provide a novel semiconductor device, etc.

[0012] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other problems from the description in the specification, drawings, and claims. [Means for solving the problem]

[0013] One aspect of the present invention relates to a display device having a pixel circuit that generates a PWM signal.

[0014] A first aspect of the present invention is a display device comprising a first transistor, a second transistor, a third transistor, and a light-emitting device, wherein one of the sources or drains of the first transistor is electrically connected to one of the sources or drains of the second transistor and the gate of the third transistor, and one of the sources or drains of the third transistor is electrically connected to the light-emitting device, and the light-emitting device lights up when the on-resistance of the first transistor is less than the on-resistance of the second transistor, and the light-emitting device turns off when the on-resistance of the first transistor is greater than the on-resistance of the second transistor.

[0015] The first transistor's gate can be supplied with a data potential, and the second transistor's gate can be supplied with a ramp wave signal potential.

[0016] It is preferable that the maximum value of the ramp wave signal potential be greater than the maximum value that the data potential can take, and the minimum value of the ramp wave signal potential be less than the minimum value that the data potential can take. Furthermore, it is preferable that the period of the ramp wave be 1 frame.

[0017] A second aspect of the present invention is a display device having a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a capacitor, and a light-emitting device in its pixels, wherein one of the sources or drains of the first transistor is electrically connected to the gate of the second transistor and one electrode of the capacitor, one of the sources or drains of the second transistor is electrically connected to the other electrode of the capacitor, one of the sources or drains of the third transistor, the gate of the fourth transistor, and one of the sources or drains of the fifth transistor, and one of the sources or drains of the fourth transistor is electrically connected to the light-emitting device.

[0018] Furthermore, a third aspect of the present invention is a display device having a first transistor, a second transistor, a third transistor, a fourth transistor, a capacitor, and a light-emitting device in its pixels, wherein the second transistor is a p-channel type transistor, one of the source or drain of the first transistor is electrically connected to the gate of the second transistor and one electrode of the capacitor, one of the source or drain of the second transistor is electrically connected to one of the source or drain of the third transistor and the gate of the fourth transistor, and one of the source or drain of the fourth transistor is electrically connected to the light-emitting device.

[0019] In a third aspect of the present invention, the other electrode of the capacitor can be electrically connected to a power line. Furthermore, it is preferable that the second transistor has silicon in its channel formation region.

[0020] In the second and third embodiments of the present invention, the light-emitting device is an LED, and either the source or drain of the fourth transistor can be electrically connected to the cathode of the LED. Alternatively, the light-emitting device is an organic EL element, and either the source or drain of the fourth transistor can be electrically connected to the anode of the organic EL element.

[0021] In the second and third embodiments of the present invention, the first transistor preferably has a metal oxide in the channel forming region, wherein the metal oxide preferably has In, Zn, and M (where M is one or more selected from Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf). [Effects of the Invention]

[0022] By using one aspect of the present invention, a display device having a pixel circuit that generates a PWM signal with a small number of transistors can be provided. Alternatively, a display device having a pixel circuit that generates a PWM signal using only transistors of the same conductivity type can be provided. Alternatively, a display device having excellent display characteristics can be provided. Alternatively, an inexpensive display device can be provided.

[0023] Alternatively, a low-power display device can be provided. Alternatively, a highly reliable display device can be provided. Alternatively, a novel display device can be provided. Alternatively, a method for operating the above-mentioned display device can be provided. Alternatively, a novel semiconductor device can be provided. [Brief explanation of the drawing]

[0024] [Figure 1] Figure 1 is a diagram illustrating the pixel circuit. [Figure 2] Figure 2 is a timing chart illustrating the operation of the pixels. [Figure 3] Figures 3A to 3C are timing charts illustrating the operation of the pixels. [Figure 4] Figure 4 is a diagram illustrating the operation of a pixel. [Figure 5] Figure 5 is a diagram illustrating the operation of a pixel. [Figure 6] Figure 6 is a diagram illustrating the operation of a pixel. [Figure 7] Figure 7 is a diagram illustrating the pixel circuit. [Figure 8] Figure 8 is a timing chart illustrating the operation of the pixels. [Figure 9] Figure 9 is a timing chart illustrating the operation of the pixels. [Figure 10] Figure 10 is a diagram illustrating the operation of a pixel. [Figure 11] Figure 11 is a diagram illustrating the operation of a pixel. [Figure 12] Figure 12 is a diagram illustrating the operation of a pixel. [Figure 13] Figures 13A and 13B illustrate the pixel circuit. [Figure 14] Figures 14A and 14B illustrate the pixel circuit. [Figure 15] Figure 15 is a block diagram illustrating the display device. [Figure 16] Figure 16 is a diagram illustrating the pixels used in the simulation. [Figure 17] Figures 17A and 17B illustrate the simulation results. [Figure 18] Figures 18A to 18D illustrate the simulation results. [Figure 19] Figures 19A to 19C illustrate the display device. [Figure 20] Figures 20A and 20B illustrate the touch panel. [Figure 21] Figure 21 is a diagram illustrating a display device. [Figure 22] Figure 22 is a diagram illustrating a display device. [Figure 23] Figures 23A to 23C illustrate transistors. [Figure 24] Figures 24A to 24C illustrate a transistor. [Figure 25] Figures 25A and 25B illustrate transistors. [Figure 26] Figures 26A to 26F illustrate electronic devices. [Modes for carrying out the invention]

[0025] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the invention. Therefore, the present invention is not to be interpreted as being limited to the descriptions of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated descriptions may be omitted. In addition, hatching of the same elements constituting the figures may be omitted or changed as appropriate between different drawings.

[0026] Furthermore, even if an element is shown as a single element in a circuit diagram, it may be composed of multiple elements as long as there is no functional disadvantage. For example, multiple transistors that act as switches may be connected in series or parallel. Also, a capacitor may be divided and placed in multiple locations.

[0027] Furthermore, a single conductor may have multiple functions, such as wiring, electrodes, and terminals, and in this specification, multiple designations may be used for the same element. Also, even if elements are shown as directly connected in a circuit diagram, they may actually be connected via one or more conductors, and in this specification, such configurations are included in the category of direct connection.

[0028] (Embodiment 1) In this embodiment, a display device, which is one aspect of the present invention, will be described with reference to the drawings.

[0029] One aspect of the present invention is a display device having a pixel with a function to generate a PWM signal. The PWM signal can be generated by comparing the on-resistances of two transistors provided in the pixel. The generated PWM signal is used to control the emission of light from a light-emitting device such as an LED or an organic EL element.

[0030] LEDs have the characteristic that their chromaticity changes depending on the current density, making analog current control unsuitable in some cases. Furthermore, with analog current control, variations in the threshold voltage (Vth) of the drive transistor affect brightness, so Vth correction circuits may be incorporated into the pixels. PWM control controls brightness using the duty cycle, so the effect of variations in the drive transistor's Vth is minimal. Additionally, in one aspect of the present invention, the PWM signal is generated by a circuit composed of a small number of transistors, which is effective for increasing the resolution and area of ​​display devices.

[0031] Figure 1 is a circuit diagram of a pixel in a display device according to one embodiment of the present invention. Pixel 10a includes transistors 101, 102, 103, 104, and 105, a capacitor 106, and a light-emitting device 108. Here, transistors 101 to 105 can be n-channel transistors. Furthermore, it is preferable to use an LED (for example, a micro-LED) for the light-emitting device 108.

[0032] One of the sources or drains of transistor 101 is electrically connected to one electrode of capacitor 106 and the gate of transistor 102. One of the sources or drains of transistor 102 is electrically connected to the other electrode of capacitor 106, one of the sources or drains of transistor 103, the gate of transistor 104 and one of the sources or drains of transistor 105. One of the sources or drains of transistor 104 is electrically connected to the cathode of the light-emitting device.

[0033] Here, node N1 is defined as the point (wiring) connecting one of the source or drain of transistor 101, one electrode of capacitor 106, and the gate of transistor 102. Also, node N2 is defined as the point (wiring) connecting one of the source or drain of transistor 102, the other electrode of capacitor 106, one of the source or drain of transistor 103, and one of the source or drain of transistor 105.

[0034] The source or drain of transistor 101 is electrically connected to wiring 121. The source or drain of transistor 102 is electrically connected to wiring 125. The source or drain of transistor 103 is electrically connected to wiring 127. The source or drain of transistor 104 is electrically connected to wiring 129. The source or drain of transistor 105 is electrically connected to wiring 128. The anode of light-emitting device 108 is electrically connected to wiring 126. The gates of transistor 101 and transistor 105 are electrically connected to wiring 122. The gate of transistor 103 is electrically connected to wiring 123.

[0035] Wiring 121 is a source line connecting pixel 10a to the source driver that supplies image data. Wirings 125, 126, 127, and 129 are power lines; wires 125 and 126 can be high-potential power lines (wire 126 is also called anode wire, anode electrode, or common electrode), and wires 127 and 129 can be low-potential power lines (wire 129 is also called cathode wire). Wiring 128 is a wire that supplies a constant potential.

[0036] Wires 125 and 126 may be electrically connected. Wires 127 and 128 may also be electrically connected. Wires 127, 128, and 129 can also be electrically connected.

[0037] Wires 122 and 123 are gate lines that control the operation of the transistors they are connected to. Wire 122 can be electrically connected to a gate driver. Wire 123 can be electrically connected to a ramp wave signal generation circuit.

[0038] Here, transistor 101 functions as a switch. Transistors 102, 103, and 105 have the function of generating a PWM signal. Transistor 104 functions as a driver transistor for the light-emitting device 108 and performs switching operations according to the generated PWM signal. Capacitor 106 functions as a retaining capacitor or bootstrap capacitor.

[0039] Next, the generation of the PWM signal in pixel 10a will be described. Transistors 102, 103, and 105 are used to generate the PWM signal. Here, a high potential (DVDD) is supplied to wiring 125, which makes transistor 104 conduct (allowing its on-resistance to be sufficiently low). In addition, a low potential (DVSS) is supplied to wiring 127, which allows transistor 104 to become non-conductive (off state).

[0040] Furthermore, a low potential (V0) is supplied to the wiring 128 to reset the potential of node N2. By resetting node N2 (the source of transistor 102) to V0, the gate-source voltage (Vgs) of transistor 102 can be properly written. In order to reliably reset node N2 to V0, it is preferable to have a higher on-current characteristic of transistor 105 than that of transistor 103.

[0041] First, the data potential (Vdata) is supplied to the gate (node ​​N1) of transistor 102, and V0 is supplied to the source (node ​​N2). Also, the signal potential (Vsweep) of the ramp wave is supplied to the gate of transistor 103.

[0042] It is preferable that the maximum value of Vsweep be greater than the maximum value that Vdata can take, and the minimum value of Vsweep be less than the minimum value that Vdata can take. By setting the value of Vsweep within this range, Vdata can be converted to a PWM signal with high accuracy. In addition, to reduce stress on transistor 103, the minimum value of Vsweep may be set to the value at which transistor 103 turns off.

[0043] Vsweep changes over time, and when Vdata-V0, which is the Vgs of transistor 102, becomes greater than Vsweep-DVSS, which is the Vgs of transistor 103, the potential of node N2 becomes DVDD. Therefore, transistor 104 conducts, and the light-emitting device 108 lights up (emits light). Conversely, when Vdata-V0 becomes less than Vsweep-DVSS, the potential of node N2 becomes DVSS. Therefore, transistor 104 becomes non-conductive, and the light-emitting device 108 turns off.

[0044] Note that the above describes an operation to compare the Vgs of transistors 102 and 103, and is valid under the assumption that both have equivalent current characteristics.

[0045] If transistors 102 and 103 have different current characteristics, this can be rephrased as comparing their on-resistances. That is, if the on-resistance of transistor 102 is greater than that of transistor 103, the potential at node N2 will be DVDD. Conversely, if the on-resistance of transistor 102 is less than that of transistor 103, the potential at node N2 will be DVSS.

[0046] In the above operation, when Vdata is relatively large, the time spent at node N2 in DVDD state is longer than the time spent in DVSS state, and when Vdata is relatively small, the time spent at DVSS state is longer than the time spent in DVDD state. Therefore, it can be said that node N2 is supplied with PWM signals generated by transistors 102, 103, and 105.

[0047] Next, a more detailed explanation of PWM signal generation will be given using the timing charts shown in Figures 2 and 3, and the circuit operation diagrams shown in Figures 4 to 6. Figure 2 shows the operation of pixels 10a arranged in three consecutive rows (rows k, l, and m) in an arbitrary column. It also shows the operation of three consecutive frames (frames n-1 to n+1, where n is an integer greater than or equal to 2), and shows the PWM signals generated when Vdata_H (bright: high brightness) is written in frame n, Vdata_M (intermediate: intermediate brightness) in frame n, and Vdata_L (dark: low brightness) in frame n+1 for all rows.

[0048] The Vdata_(H, M, L)-V0 shown in Figure 2 corresponds to the Vgs of transistor 102. Also, Vsweep-DVSS corresponds to the Vgs of transistor 103. Vsweep is the signal potential of the ramp wave supplied from wiring 123, and DVSS is the constant power supply potential supplied to wiring 127. Therefore, Vsweep-DVSS is equivalent to the waveform of the ramp wave.

[0049] Furthermore, all pixels are supplied with ramp waves of the same phase. Therefore, since there is no need to generate ramp waves with different phases for each row, the circuits for generating and supplying ramp waves can be simplified.

[0050] First, we will explain the generation of the PWM signal at pixel 10a in the kth row. It should be assumed that the current characteristics of transistors 102 and 103 are equivalent.

[0051] In the (n-1)th frame, the potential of wiring 122[k] becomes H (high potential), causing transistors 101 and 105 to conduct, supplying Vdata_H to node N1 and V0 to node N2 (see Figure 4). At this time, the Vgs of transistor 102 becomes Vdata_H - V0.

[0052] In parallel with the above operation, a ramp wave is supplied to wiring 123 (see Fig. 4). For example, the ramp wave can be a triangular wave as shown in Vsweep-DVSS of Fig. 2. Alternatively, it may be a sawtooth wave as shown in Fig. 3A. Or, a sine wave, a trapezoidal waveform, etc. can also be used.

[0053] Also, the period of the ramp wave can be at most one frame period as shown in Fig. 2. Since Vdata is held for one frame period, by setting the period of the ramp wave to one frame period, a PWM waveform of one cycle can be generated. By setting the period of the ramp waveform to the longest one frame period, the number of charge and discharge cycles of the wiring that supplies the signal potential of the ramp waveform becomes the minimum number, so power consumption can be reduced.

[0054] Alternatively, as shown in Figs. 3B and 3C, the period of the ramp waveform may be 1 / 2 frame period, 1 / 4 frame period. Or, the period of the ramp waveform may be further shortened. In PWM control, the brightness is adjusted by dividing the lighting period, but by shortening the period of the ramp waveform, the on and off blinking can be repeated at high speed, and the afterimage sensation can be suppressed.

[0055] Within one frame period, Vdata_H - V0 is constant, but Vsweep-DVSS changes with time. Therefore, there occur a period during which DVSS is supplied to node N2 when Vsweep-DVSS > Vdata_H - V0 (see Fig. 5), and a period during which DVDD is supplied to node N2 when Vsweep-DVSS < Vdata_H - V0 (see Fig. 6).

[0056] In Fig. 2, since Vdata_H is written in the (n - 1)-th frame, the period during which DVSS is supplied to node N2 is short, and the period during which DVDD is supplied to node N2 is long. That is, the duty ratio becomes large, and since the average current in one frame period becomes large, a display with high brightness can be performed.

[0057] In the n-th frame, Vdata_M is written, and the Vgs of transistor 102 becomes Vdata_M - V0. Similar to the description of the (n - 1)-th frame, the comparison operation with Vsweep - DVSS is performed, and the duty ratio becomes smaller than that of the (n - 1)-th frame.

[0058] In the (n + 1)-th frame, Vdata_L is written, and the Vgs of transistor 102 becomes Vdata_L - V0. Similar to the description of the (n - 1)-th frame, the comparison operation with Vsweep - DVSS is performed, and the duty ratio becomes smaller than that of the n-th frame. Since the average current in one frame period becomes smaller, a display with lower brightness can be performed.

[0059] Next, the generation of the PWM signal for pixel 10a in the l-th row will be described. In the l-th row, the writing of the data potential is delayed by one horizontal period compared to the k-th row, and the frame period starts. On the other hand, since the ramp wave supplied to wiring 123 has the same phase waveform for all pixels, even when the same data potential as in the k-th row is written, the timings when Vsweep - DVSS > Vdata_(H, M, L) - V0 and when Vsweep - DVSS < Vdata_(H, M, L) - V0 are different. However, if the written data potentials are the same, the duty ratios of the generated PWM signals are the same.

[0060] The same applies to the m-th row. Even when the same data potential as in the l-th row is written, the timings when Vsweep - DVSS > Vdata_(H, M, L) - V0 and when Vsweep - DVSS < Vdata_(H, M, L) - V0 are different. However, if the written data potentials are the same, the duty ratios of the generated PWM signals are the same.

[0061] In the pixel 10a shown in FIG. 1, the transistor 101 for writing data to the node N1 and the transistor 105 for resetting the node N2 are simultaneously turned on. Therefore, even when Vsweep - DVSS < Vdata_(H, M, L) - V0 during data writing, the potential of the node N2 may become V0, and the light-emitting device may turn off. However, the horizontal period required for data writing is approximately 1 / 1000 of one frame period when the number of pixels is Full HD, and approximately 1 / 2000 of one frame period when the number of pixels is 4K2K. Therefore, it can be said that if the written data potentials are the same, the duty ratios of the generated PWM signals are almost the same.

[0062] Note that for the transistor 101 which is an n-channel type transistor, it is preferable to use a transistor having a metal oxide in the channel formation region (hereinafter referred to as an OS transistor). Since the OS transistor has a large energy gap in the semiconductor layer, it can exhibit an extremely low off-current characteristic of several yA / μm (current value per 1 μm channel width).

[0063] Due to the low off-current characteristic of the OS transistor, the potential of the gate of the transistor 102 can be held for a long time. Therefore, an appropriate PWM signal can be generated even when the frame frequency is reduced. For example, in the case of moving image display, the first frame frequency (e.g., 60 Hz or more) is used, and in the case of still image display, the display device can be made to consume less power by switching to a second frame frequency lower than the first frame frequency (e.g., about 1 to 10 Hz).

[0064] As the semiconductor material used in OS transistors, metal oxides with an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more, can be used. Typical examples include indium-containing oxide semiconductors, such as CAAC-OS or CAC-OS, which will be described later. CAAC-OS has stable atoms constituting the crystal, making it suitable for transistors where reliability is important. In addition, CAC-OS exhibits high mobility characteristics, making it suitable for transistors that require high-speed operation.

[0065] OS transistors have characteristics that differ from transistors with silicon in the channel region (hereinafter referred to as Si transistors), such as the absence of impact ionization, avalanche breakdown, and short-channel effects, and can form highly reliable circuits. In addition, OS transistors are less prone to variations in electrical properties caused by crystalline non-uniformity, which is a problem in Si transistors.

[0066] The semiconductor layer of an OS transistor can be a film represented by an In-M-Zn oxide containing, for example, indium, zinc, and M (a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). In-M-Zn oxides can typically be formed by sputtering, or by ALD (Atomic Layer Deposition).

[0067] The atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn-based oxide by sputtering preferably satisfies In≧M and Zn≧M. As such atomic ratios of the metal elements of the sputtering target, In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, etc. are preferable. Note that the atomic ratio of the semiconductor layer formed includes fluctuations of plus or minus 40% of the atomic ratio of the metal elements contained in the above sputtering target, respectively.

[0068] As the semiconductor layer, an oxide semiconductor with a low carrier concentration is used. For example, the carrier concentration of the semiconductor layer is 1×10 17 / cm 3 or less, preferably 1×10 15 / cm 3 or less, more preferably 1×10 13 / cm 3 or less, even more preferably 1×10 11 / cm 3 or less, still more preferably 1×10 10 / cm 3 less, and an oxide semiconductor having a carrier concentration of 1×10 -9 / cm 3 or more can be used. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. It can be said that the oxide semiconductor has a low density of defect levels and stable characteristics.

[0069] Note that it is not limited to these, and those with an appropriate composition may be used according to the required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. Also, in order to obtain the required semiconductor characteristics of the transistor, it is preferable to make the carrier concentration, impurity concentration, defect density, atomic ratio of metal elements and oxygen, interatomic distance, density, etc. of the semiconductor layer appropriate values.

[0070] In oxide semiconductors that constitute a semiconductor layer, the presence of silicon or carbon, which are Group 14 elements, increases oxygen vacancies and causes n-type semiconductor formation. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 2 × 10⁻¹⁰. 18 atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0071] Furthermore, alkali metals and alkaline earth metals can generate carriers when bonded with oxide semiconductors, which can increase the transistor's off-current. For this reason, the concentration of alkali metals or alkaline earth metals in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0072] Furthermore, if nitrogen is present in the oxide semiconductor constituting the semiconductor layer, electrons, which act as carriers, are generated, increasing the carrier concentration and making it easier for the transistor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Therefore, the nitrogen concentration in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 5 × 10⁻⁶. 18 atoms / cm 3 The following is preferable:

[0073] Furthermore, if the oxide semiconductor constituting the semiconductor layer contains hydrogen, it can react with oxygen bonded to metal atoms to form water, thus potentially creating oxygen vacancies in the oxide semiconductor. If oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor may exhibit normally-on characteristics. Moreover, a defect containing hydrogen can function as a donor, generating electrons as carriers. Additionally, some of the hydrogen may combine with oxygen bonded to metal atoms to generate electrons as carriers. Therefore, transistors using oxide semiconductors with a high hydrogen content tend to exhibit normally-on characteristics.

[0074] Defects where hydrogen fills an oxygen vacancy can function as donors in oxide semiconductors. However, quantitatively evaluating such defects is difficult. Therefore, in oxide semiconductors, evaluation is sometimes done using carrier concentration rather than donor concentration. Accordingly, in this specification, the carrier concentration, assuming no electric field is applied, may be used as a parameter for oxide semiconductors, rather than the donor concentration. In other words, "carrier concentration" as described in this specification may sometimes be rephrased as "donor concentration."

[0075] Therefore, it is preferable that the hydrogen content in the oxide semiconductor be reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 It should be less than [amount]. By using an oxide semiconductor with sufficiently reduced impurities such as hydrogen in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0076] Furthermore, the semiconductor layer may have a non-single-crystal structure, for example. Non-single-crystal structures include, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having crystals oriented along the c axis, polycrystalline structures, microcrystalline structures, or amorphous structures. Among non-single-crystal structures, the amorphous structure has the highest defect level density, while CAAC-OS has the lowest defect level density.

[0077] An amorphous oxide semiconductor film, for example, has a disordered atomic arrangement and does not contain crystalline components. Alternatively, an amorphous oxide film, for example, has a completely amorphous structure and does not contain crystalline parts.

[0078] Furthermore, the semiconductor layer may be a mixed film having two or more regions from among amorphous, microcrystalline, polycrystalline, CAAC-OS, and single-crystal structures. The mixed film may have a single-layer structure or a stacked structure that includes, for example, two or more of the regions described above.

[0079] The following describes the configuration of CAC (Cloud-Aligned Composite)-OS, which is one form of a non-single-crystal semiconductor layer.

[0080] CAC-OS is a material composition in which the elements constituting the oxide semiconductor are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or close to that size. In the following, in an oxide semiconductor, a state in which one or more metal elements are unevenly distributed, and the regions containing the metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0081] Furthermore, the oxide semiconductor preferably contains at least indium. It is particularly preferable that it contains indium and zinc. In addition, it may also contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium.

[0082] For example, CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide within CAC-OS may be specifically called CAC-IGZO) refers to indium oxide (hereinafter, InO X1 (Let X1 be a real number greater than 0.) ) or indium zinc oxide (hereinafter, In X2 Zn Y2 O Z2 (Let X2, Y2, and Z2 be real numbers greater than 0.) and gallium oxide (hereinafter referred to as GaO X3 (Let X3 be a real number greater than 0.) or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (Let X4, Y4, and Z4 be real numbers greater than 0).) The material separates into mosaic-like structures, and the mosaic-like InO X1 , or In X2 Zn Y2 O Z2 However, it is a uniformly distributed structure within the membrane (hereinafter also referred to as a cloud-like structure).

[0083] In other words, CAC-OS is GaO X3 The region in which is the main component, and In X2 Zn Y2 O Z2 , or InO X1 This is a composite oxide semiconductor having a structure in which a region in which is the main component is mixed with another region. In this specification, for example, if the atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region, then the first region is considered to have a higher concentration of In compared to the second region.

[0084] Note that IGZO is a common name and can refer to a single compound composed of In, Ga, Zn, and O. A typical example is InGaO3(ZnO). m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O3(ZnO) m0 Examples include crystalline compounds represented by (-1 ≤ x0 ≤ 1, where m0 is any number).

[0085] The above-mentioned crystalline compounds have a single-crystal structure, a polycrystalline structure, or a CAAC structure. A CAAC structure is a crystalline structure in which multiple IGZO nanocrystals are c-axis oriented and linked together without orientation in the ab-plane.

[0086] On the other hand, CAC-OS refers to the material composition of oxide semiconductors. CAC-OS is a material composition containing In, Ga, Zn, and O, in which regions observed as nanoparticles mainly composed of Ga and regions observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic-like manner. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0087] Furthermore, CAC-OS does not include layered structures of two or more films with different compositions. For example, a structure consisting of two layers, one with In as the main component and the other with Ga as the main component, is not included.

[0088] Note that GaO X3 The region in which is the main component, and In X2 Zn Y2 O Z2 , or InO X1 In some cases, a clear boundary may not be observable in a region where [this component] is the main component.

[0089] Furthermore, if gallium is replaced with one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, CAC-OS refers to a configuration in which regions observed as nanoparticles mainly composed of the said metal element and regions observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern.

[0090] CAC-OS can be formed by sputtering, for example, under conditions where the substrate is not intentionally heated. When forming CAC-OS by sputtering, one or more gases selected from inert gases (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. Furthermore, a lower ratio of oxygen gas flow rate to the total deposition gas flow rate during film formation is preferable; for example, an oxygen gas flow rate ratio of 0% or more and less than 30%, preferably 0% or more and 10% or less, is preferable.

[0091] CAC-OS is characterized by the absence of a clear peak when measured using the θ / 2θ scan method, an out-of-plane X-ray diffraction (XRD) measurement technique. In other words, X-ray diffraction measurements indicate that no orientation in the ab-plane direction or the c-axis direction of the measurement region is observed.

[0092] Furthermore, in the electron diffraction pattern obtained by irradiating CAC-OS with an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam), a ring-shaped region of high brightness (ring region) and multiple bright spots are observed within this ring region. Therefore, from the electron diffraction pattern, it can be seen that the crystal structure of CAC-OS has an nc (nano-crystal) structure that does not have orientation in the planar and cross-sectional directions.

[0093] Furthermore, for example, in CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) revealed that GaO X3 The region in which is the main component, and In X2 Zn Y2 O Z2 , or InO X1 It can be confirmed that the structure has regions in which the main component is unevenly distributed and mixed.

[0094] CAC-OS has a different structure from IGZO compounds in which metal elements are uniformly distributed, and therefore has different properties from IGZO compounds. In other words, CAC-OS is GaO X3 Regions where such are the main components, and In X2 Zn Y2 O Z2 , or InO X1 It has a mosaic-like structure consisting of regions where one element is the main component and regions where each element is the main component, with each region being in a separate phase from the others.

[0095] Here, In X2 Zn Y2 O Z2 , or InO X1 The region in which is the main component is GaO X3 Compared to regions where these are the main components, this region has high conductivity. In other words, In X2 Zn Y2 O Z2 , or InO X1 In the region where this is the main component, the flow of carriers causes conductivity as an oxide semiconductor to emerge. Therefore, In X2 Zn Y2 O Z2 , or InO X1 A high field-effect mobility (μ) can be achieved when regions with this as the main component are distributed in a cloud-like manner within the oxide semiconductor.

[0096] On the other hand, GaO X3 Regions in which these are the main components are, X2 Zn Y2 O Z2 , or InOX1 It is a region with high insulation compared to the region where X1 is the main component. That is, the region where components such as GaO X3 etc. are the main components are distributed in the oxide semiconductor, suppressing the leakage current and enabling a good switching operation.

[0097] Therefore, when CAC-OS is used in a semiconductor device, the insulation caused by GaO X3 etc., and the conductivity caused by In X2 Zn Y2 O Z2 or InO X1 act complementarily to realize a high on-current (I on ) and a high field-effect mobility (μ).

[0098] Also, the semiconductor device using CAC-OS has high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0099] Also, one or more of transistors 102 to 105 may be formed as OS transistors. Alternatively, one or more of transistors 102 to 105 may be formed with a transistor having silicon in the channel formation region (hereinafter, Si transistor).

[0100] For the channel formation region of the Si transistor, amorphous silicon, microcrystalline silicon, polycrystalline silicon, single crystal silicon, etc. can be used. When a transistor is provided on an insulating surface such as on a glass substrate, it is preferable to use polycrystalline silicon.

[0101] High-quality polycrystalline silicon can be easily obtained by using processes such as laser crystallization. Alternatively, high-quality polycrystalline silicon can also be obtained by solid-phase growth, which involves adding a metal catalyst such as nickel or palladium to amorphous silicon and heating it. Furthermore, the crystallinity of polycrystalline silicon formed by solid-phase growth using a metal catalyst may be further enhanced by laser irradiation. Since the metal catalyst remains in the polycrystalline silicon and degrades the electrical properties of the transistor, it is preferable to create regions outside the channel formation area where phosphorus or a noble gas is added, thereby trapping the metal catalyst in these regions.

[0102] Furthermore, to obtain the effects of one aspect of the present invention, the configuration is not limited to those described above; all transistors in the pixel may be formed from Si transistors. Alternatively, one or more transistors in the pixel may be formed from p-channel transistors.

[0103] Figure 7 is a circuit diagram illustrating pixel 10b, which has a different configuration from that shown in Figure 1. It differs from pixel 10a shown in Figure 1 in that transistor 102 is a p-channel type transistor, transistor 105 is omitted, and the connection configuration of capacitor 106 is different.

[0104] In pixel 10b, since transistor 102 is a p-channel transistor, the source of transistor 102 is electrically connected to the wiring 125 that supplies a high potential. Therefore, the transistor 105 that resets the source potential (potential of node N2) of pixel 10a can be omitted. Also, the other electrode of capacitor 106 that holds Vgs is electrically connected to the wiring 125.

[0105] Next, we will explain the generation of the PWM signal in pixel 10b. Transistors 102 and 103 are used to generate the PWM signal. Note that explanations common to pixel 10a will be omitted.

[0106] First, a data potential (Vdata) is supplied to the gate (node ​​N1) of transistor 102. Also, a ramp wave signal potential (Vsweep) is supplied to the gate of transistor 103.

[0107] Vsweep changes over time, and when the absolute value of Vdata-DVDD, which is the Vgs of transistor 102, becomes greater than Vsweep-DVSS, which is the Vgs of transistor 103, the potential of node N2 becomes DVDD. Therefore, transistor 104 conducts, and the light-emitting device 108 lights up (emits light). Conversely, when the absolute value of Vdata-DVDD becomes less than Vsweep-DVSS, the potential of node N2 becomes DVSS. Therefore, transistor 104 becomes non-conductive, and the light-emitting device 108 turns off.

[0108] Note that the above describes an operation to compare the Vgs of transistors 102 and 103, and is valid under the assumption that both have equivalent current characteristics.

[0109] If transistors 102 and 103 have different current characteristics, this can be rephrased as comparing their on-resistances. That is, if the on-resistance of transistor 102 is greater than that of transistor 103, the potential at node N2 will be DVDD. Conversely, if the on-resistance of transistor 102 is less than that of transistor 103, the potential at node N2 will be DVSS.

[0110] In the above operation, when Vdata is relatively small, the time spent in DVSS mode is longer than the time spent in DVDD mode, and when Vdata is relatively large, the time spent in DVSS mode is longer than the time spent in DVDD mode. Therefore, it can be said that node N2 is supplied with PWM signals generated by transistors 102 and 103.

[0111] Next, a more detailed explanation of PWM signal generation will be provided using the timing charts shown in Figures 8 and 9, and the circuit operation diagrams shown in Figures 10, 11, and 12. Note that explanations common to pixel 10a will be omitted as appropriate.

[0112] Figure 8 shows the case of pixels 10b arranged in three consecutive rows (rows k, l, and m) in an arbitrary column. It also shows the operation of three consecutive frames (frames n-1 to n+1, where n is an integer greater than or equal to 2), and shows the PWM signals generated when Vdata_H (dark: low brightness) is written in frame n, Vdata_M (intermediate: intermediate brightness) in frame n, and Vdata_L (bright: high brightness) in frame n+1 for all rows.

[0113] The Vdata_(H, M, L)-DVDD shown in Figure 8 corresponds to the Vgs of transistor 102. Also, Vsweep-DVSS corresponds to the Vgs of transistor 103. Vsweep is the signal potential of the ramp wave supplied from wiring 123.

[0114] First, we will explain the generation of the PWM signal at pixel 10b in the k-th row. It should be assumed that the current characteristics of transistors 102 and 103 are equivalent.

[0115] In the (n-1)th frame, the potential of wiring 122[k] becomes H (high potential), causing transistor 101 to conduct and supplying Vdata_H to node N1 (see Figure 10). At this time, the Vgs of transistor 102 becomes Vdata_H-DVDD.

[0116] In parallel with the above operation, a ramp wave is supplied to wiring 123 (see Figure 10). For example, the ramp wave can be a triangular wave as shown in Vweep-DVSS in Figure 8. Alternatively, it may be a sawtooth wave as shown in Figure 9A. Or, a sine wave, trapezoidal waveform, etc., can be used.

[0117] Furthermore, the period of the ramp wave can be as long as 1 frame, as shown in Figure 8. Alternatively, as shown in Figures 9B and 9C, the period of the ramp waveform may be 1 / 2 frame or 1 / 4 frame. Or, the period of the ramp waveform may be shortened even further.

[0118] Within a single frame period, Vdata_H-DVDD remains constant, but Vsweep-DVSS changes over time. Therefore, there are periods when DVSS is supplied to node N2 because Vsweep-DVSS > |Vdata_H-DVDD| (see Figure 11), and periods when DVDD is supplied to node N2 because Vsweep-DVSS < |Vdata_H-DVDD| (see Figure 12).

[0119] In Figure 8, since Vdata_H is written in the (n-1)th frame, the period during which DVSS is supplied to node N2 is longer, and the period during which DVDD is supplied to node N2 is shorter. In other words, the duty cycle becomes larger, and the average current for one frame period becomes smaller, which allows for a display with lower brightness.

[0120] In the nth frame, Vdata_M is written, and the Vgs of transistor 102 becomes Vdata_M-DVDD. Similar to the explanation for the (n-1)th frame, a comparison operation with Vsweep-DVSS is performed, and the duty cycle is larger than in the (n-1)th frame.

[0121] In the (n+1)th frame, Vdata_L is written, and the Vgs of transistor 102 becomes Vdata_L-DVDD. Similar to the explanation for the (n-1)th frame, a comparison operation with Vsweep-DVSS is performed, and the duty cycle becomes larger than in the nth frame. As a result, the average current for the duration of one frame increases, allowing for a display with higher brightness.

[0122] Next, we will explain the generation of the PWM signal at pixel 10b in the i-th row. In the i-th row, the data potential is written with a delay of one horizontal period compared to the k-th row, and the frame period starts. On the other hand, since the ramp wave supplied to wiring 123 is supplied with the same phase waveform at all pixels, even if the same data potential as in the k-th row is written, the timing of Vsweep-DVSS>|Vdata_(H,M,L)-DVDD| and Vsweep-DVSS<|Vdata_(H,M,L)-DVDD| will be different. However, if the written data potential is the same, the duty cycle of the generated PWM signal will be the same.

[0123] The same applies to the m-th row; even if the same data potential is written as to the l-th row, the timing of Vsweep-DVSS>|Vdata_(H,M,L)-DVDD| and Vsweep-DVSS<|Vdata_(H,M,L)-DVDD| will be different. However, if the written data potential is the same, the duty cycle of the generated PWM signal will be the same.

[0124] Note that in pixel 10b shown in Figure 7, the node N2 is not reset, so if Vsweep-DVSS<|Vdata_(H, M, L)-DVDD| is true when writing data, the light emission operation will occur.

[0125] Furthermore, it is preferable to use a transistor 101, which is an n-channel type transistor similar to pixel 10a, that has a metal oxide in the channel formation region (hereinafter referred to as an OS transistor).

[0126] Furthermore, it is preferable that transistor 102 is a Si transistor with good electrical characteristics even in a p-channel type.

[0127] Furthermore, to obtain the effects of one aspect of the present invention, the configuration is not limited to the one described above, and all transistors in the pixel may be formed from Si transistors. Also, one or more of the transistors in the pixel other than transistor 102 may be formed from p-channel type transistors. Also, among the transistors in the pixel other than transistor 102, OS transistors may be used.

[0128] Furthermore, while an LED can be used for the light-emitting device 108, an organic EL element may also be used. When using an organic EL element, as shown in Figures 13A and 13B, the wiring 126 may be electrically connected to either the source or drain of the transistor 104, and the cathode of the light-emitting device 108 may be connected to the other source or drain. Also, even when using an LED for the light-emitting device 108, the configuration shown in Figures 13A and 13B can be applied.

[0129] Furthermore, when using an OS transistor for the n-channel transistor, a configuration with a back gate may be used, as shown in Figure 14A or Figure 14B. By supplying the same potential to the back gate as to the front gate, the on-current can be increased. Alternatively, a configuration that can supply a constant potential to the back gate may be used. By supplying a constant potential to the back gate, the threshold voltage can be controlled.

[0130] Figure 15 is a block diagram illustrating a display device according to one aspect of the present invention. The display device includes a pixel array 11, a source driver 20, and a gate driver 30. The pixel array 11 has pixels 10 arranged in the column and row directions. The pixels 10 can be either pixels 10a or pixels 10b as described in this embodiment. Note that the wiring is shown in a simplified manner, and wiring is provided to connect to the elements of the pixels 10 according to the aforementioned aspect of the present invention.

[0131] Sequential circuits such as shift registers can be used for the source driver 20 and gate driver 30.

[0132] Furthermore, a ramp wave signal generation circuit 40 that generates triangular waves or sawtooth waves is provided and is electrically connected to the pixel 10.

[0133] The source driver 20, gate driver 30, and ramp wave signal generation circuit 40 can be externally mounted IC chips using methods such as COF (chip on film), COG (chip on glass), or TCP (tape carrier package). Alternatively, they may be fabricated on the same substrate as the pixel array 11 using transistors manufactured using the same process as the pixel array 11.

[0134] The example shown illustrates the gate driver 30 being located on one side of the pixel array 11, but two gate drivers may be placed opposite each other across the pixel array 11 to divide the drive row.

[0135] Next, we will explain the simulation results regarding the operation of the pixels. Figure 16 shows the configuration of the pixel PIX used in the simulation. The pixel PIX is the same as the pixel circuit shown in Figure 1, and transistors Tr1 to Tr5 are n-channel OS transistors. Also, the node corresponding to node N2 in Figure 1 is GPWM. Furthermore, the wiring corresponding to wiring 122 in Figure 1 is G1, and the wiring corresponding to wiring 123 is G2.

[0136] The parameters used in the simulation are as follows: Transistor sizes were W / L=3μm / 3μm (transistor Tr1), W / L=3μm / 6μm (transistors Tr2 and Tr3), W / L=45μm / 3μm (transistor Tr4: driver transistor), and W / L=12μm / 3μm (transistor Tr5). Capacitor CAP had a capacitance of 100fF. The voltage applied to the transistor gate (including the ramp wave) was +15V for "H" and -5V for "L". The anode potential (Vano) was +20V, the cathode potential (Vcat) was 0V, the voltage V0 was -2V, the voltage DVDD was +12V, the voltage DVSS was -2V, and Vdata was +2V to +10V. SPICE was used as the circuit simulation software.

[0137] Figure 17A shows the simulation results of the voltage at node N2 when Vdata is set to +2V to +10V (in 2V steps) within one frame period. The horizontal axis represents time (sec), and it is assumed that the ramp wave (triangular wave) takes its maximum value in the middle of one frame period.

[0138] From these results, it was confirmed that the waveform of the PWM signal output to node GPWM has a pulse width corresponding to the magnitude of Vdata. Furthermore, Figure 17B shows the simulation results of the current flowing through the LED (ILED) according to each PWM signal shown in Figure 17A. It was confirmed that the current flows according to the generated PWM signal.

[0139] Figures 18A to 18D show the simulation results of the PWM signal waveforms for each row corresponding to rows k through m shown in Figure 2. The value of Vdata is set to +2V to +10V (in 2V steps) within one frame period, and 0V before and after. The phase of the supplied ramp wave is the same for rows k through m, but the timing of writing Vdata differs. From these results, it was confirmed that although the phase of the PWM signal differs in each row, the duty cycle depends on the magnitude of Vdata.

[0140] Based on the above simulation results, the effectiveness of one embodiment of the present invention could be confirmed.

[0141] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0142] (Embodiment 2) This embodiment describes an example configuration of a display device using a light-emitting device. Note that in this embodiment, the descriptions of the elements, operation, and functions of the display device described in Embodiment 1 are omitted.

[0143] The display device described in this embodiment can be fitted with the pixel 10 (pixel 10a or pixel 10b) described in Embodiment 1. The scan line driving circuit described below corresponds to a gate driver, and the signal line driving circuit corresponds to a source driver.

[0144] Figures 19A to 19C show the configuration of a display device that can use one embodiment of the present invention.

[0145] In Figure 19A, a sealing material 4005 is provided so as to surround the display unit 215 which is provided on the first substrate 4001, and the display unit 215 is sealed by the sealing material 4005 and the second substrate 4006.

[0146] In Figure 19A, the scan line drive circuit 221a, signal line drive circuit 231a, signal line drive circuit 232a, and common line drive circuit 241a each have multiple integrated circuits 4042 provided on the printed circuit board 4041. The integrated circuits 4042 are formed from single-crystal or polycrystalline semiconductors. The common line drive circuit 241a has the function of supplying a specified potential to the wiring 122, 127, 128, 129, etc., as shown in Embodiment 1.

[0147] The various signals and potentials supplied to the scan line drive circuit 221a, the common line drive circuit 241a, the signal line drive circuit 231a, and the signal line drive circuit 232a are supplied via the FPC (Flexible printed circuit) 4018.

[0148] The integrated circuit 4042 in the scan line drive circuit 221a and the common line drive circuit 241a has the function of supplying selection signals to the display unit 215. The integrated circuit 4042 in the signal line drive circuit 231a and the signal line drive circuit 232a has the function of supplying image data to the display unit 215. The integrated circuit 4042 is mounted in an area different from the area surrounded by the sealing material 4005 on the first substrate 4001.

[0149] The connection method for the integrated circuit 4042 is not particularly limited, and methods such as wire bonding, COF, COG, and TCP can be used.

[0150] Figure 19B shows an example of mounting the integrated circuit 4042 included in the signal line drive circuits 231a and 232a using the COG method. Furthermore, a part or all of the drive circuit can be integrally formed on the same substrate as the display unit 215 to form a system-on-panel.

[0151] Figure 19B shows an example in which the scan line drive circuit 221a and the common line drive circuit 241a are formed on the same substrate as the display unit 215. By forming the drive circuits simultaneously with the pixel circuits in the display unit 215, the number of components can be reduced. Therefore, productivity can be increased.

[0152] Furthermore, in Figure 19B, a sealing material 4005 is provided so as to surround the display unit 215, the scan line drive circuit 221a, and the common line drive circuit 241a, which are provided on the first substrate 4001. A second substrate 4006 is provided on top of the display unit 215, the scan line drive circuit 221a, and the common line drive circuit 241a. Thus, the display unit 215, the scan line drive circuit 221a, and the common line drive circuit 241a are sealed together with the display device by the first substrate 4001, the sealing material 4005, and the second substrate 4006.

[0153] Furthermore, Figure 19B shows an example in which the signal line drive circuits 231a and 232a are formed separately and mounted on the first substrate 4001, but the configuration is not limited to this. The scan line drive circuit may be formed separately and mounted, or a part of the signal line drive circuit or a part of the scan line drive circuit may be formed separately and mounted. Also, as shown in Figure 19C, the signal line drive circuits 231a and 232a may be formed on the same substrate as the display unit 215.

[0154] Furthermore, the display device may include a panel in which the display device is sealed, and a module on which an IC including a controller is mounted.

[0155] Furthermore, the display unit and scan line driving circuit provided on the first substrate have multiple transistors. These transistors can be the Si transistors or OS transistors shown in Embodiment 1.

[0156] The transistors in the peripheral drive circuit and the transistors in the pixel circuit of the display unit may have the same structure or be different. The transistors in the peripheral drive circuit may all have the same structure or may have two or more different structures. Similarly, the transistors in the pixel circuit may all have the same structure or may have two or more different structures.

[0157] Furthermore, an input device 4200 (see Figure 20B), which will be described later, can be provided on the second substrate 4006, as an example. The display device shown in Figures 19A to 19C, with the input device 4200 provided, can function as a touch panel.

[0158] The detection device (also called a sensor element) of a touch panel according to one aspect of the present invention is not limited. Various sensors capable of detecting the proximity or contact of an object to be detected, such as a finger or stylus, can be applied as the detection device.

[0159] Various sensor types can be used, such as capacitive, resistive, surface acoustic wave, infrared, optical, and pressure-sensitive sensors.

[0160] In this embodiment, a touch panel having a capacitive sensing device will be used as an example for explanation.

[0161] Capacitive capacitance methods include surface capacitance and projected capacitance. Projected capacitance methods include self-capacitance and mutual capacitance. Mutual capacitance is preferable because it enables simultaneous multi-point detection.

[0162] A touch panel according to one aspect of the present invention can be configured in various ways, such as a configuration in which a separately manufactured display device and a detection device are bonded together, or a configuration in which electrodes constituting the detection device are provided on one or both of the substrate supporting the display device and the opposing substrate.

[0163] Figures 20A and 20B show examples of touch panels. Figure 20A is a perspective view of the touch panel 4210. Figure 20B is a schematic perspective view of the input device 4200. For clarity, only representative components are shown.

[0164] The touch panel 4210 has a configuration in which a display device and a detection device, which were manufactured separately, are bonded together.

[0165] The touch panel 4210 has an input device 4200 and a display device, which are mounted on top of each other.

[0166] The input device 4200 includes a substrate 4263, electrodes 4227 and 4228, a plurality of wirings 4237, a plurality of wirings 4238, and a plurality of wirings 4239. For example, electrode 4227 can be electrically connected to wiring 4237 or wiring 4239. Also, electrode 4228 can be electrically connected to wiring 4239. The FPC 4272b is electrically connected to each of the plurality of wirings 4237 and the plurality of wirings 4238. IC 4273b can be provided on the FPC 4272b.

[0167] Alternatively, a touch sensor may be provided between the first substrate 4001 and the second substrate 4006 of the display device. If a touch sensor is provided between the first substrate 4001 and the second substrate 4006, in addition to a capacitive touch sensor, an optical touch sensor using a photoelectric conversion element may be applied.

[0168] Figure 21 is a cross-sectional view of the area indicated by the dashed line N1-N2 in Figure 20B. Figure 21 is an example of a display device using an organic EL device, which is a light-emitting device, as the display device. The display device has an electrode 4015, which is electrically connected to the terminals of the FPC 4018 via an anisotropic conductive layer 4019. In Figure 21, the electrode 4015 is also electrically connected to the wiring 4014 at openings formed in the insulating layer 4112, insulating layer 4111, and insulating layer 4110.

[0169] Electrode 4015 is formed from the same conductive layer as the first electrode layer 4030, and wiring 4014 is formed from the same conductive layer as the gate electrodes of transistors 4010 and 4011.

[0170] Furthermore, the display unit 215 and the scan line driving circuit 221a, which are provided on the first substrate 4001, have multiple transistors, with transistor 4010 included in the display unit 215 and transistor 4011 included in the scan line driving circuit 221a being examples. In Figure 21, top-gate type transistors are shown as examples for transistors 4010 and 4011, but bottom-gate type transistors may also be used.

[0171] An insulating layer 4112 is provided on transistors 4010 and 4011. A partition wall 4510 is also formed on the insulating layer 4112.

[0172] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. It is particularly preferable to use a photosensitive resin material and form an opening on the first electrode layer 4030 so that the side surface of the opening is an inclined surface with a continuous curvature.

[0173] The display device also includes a capacitor 4020. The capacitor 4020 is shown as an example comprising an electrode 4021 formed in the same process as the gate electrode of the transistor 4010, an insulating layer 4110, an insulating layer 4111, and an electrode formed in the same process as the source and drain electrodes. The configuration of the capacitor 4020 is not limited to this and may be formed of other conductive and insulating layers.

[0174] Furthermore, the display device has an insulating layer 4111 and an insulating layer 4104. Insulating layers 4111 and 4104 are used, which are less permeable to impurity elements. By sandwiching the semiconductor layer of the transistor between insulating layers 4111 and 4104, the intrusion of impurities from the outside can be prevented.

[0175] The transistor 4010 provided in the display unit 215 is electrically connected to the display device. A light-emitting device can be used as the display device. For example, an EL device that utilizes electroluminescence can be used as the light-emitting device. The EL device has a layer containing a light-emitting compound (also called the "EL layer") between a pair of electrodes. When a potential difference greater than the threshold voltage of the EL device is generated between the pair of electrodes, holes are injected into the EL layer from the anode side and electrons are injected from the cathode side. The injected electrons and holes recombine in the EL layer, and the light-emitting compound contained in the EL layer emits light.

[0176] As EL devices, for example, organic EL devices (also called organic EL elements) or inorganic EL devices (also called inorganic EL elements) can be used.

[0177] In addition to luminescent compounds, the EL layer may also contain materials with high hole injection properties, materials with high hole transport properties, hole blocking materials, materials with high electron transport properties, materials with high electron injection properties, or bipolar materials (materials with high electron transport and hole transport properties).

[0178] The EL layer can be formed by methods such as vapor deposition (including vacuum deposition), transfer, printing, inkjet, and coating.

[0179] Inorganic EL devices are classified into dispersed inorganic EL devices and thin-film inorganic EL devices based on their element configuration. Dispersed inorganic EL devices have an emissive layer in which particles of emissive material are dispersed in a binder, and the emissive mechanism is donor-acceptor recombination type emissive emission utilizing donor and acceptor levels. Thin-film inorganic EL devices have a structure in which the emissive layer is sandwiched between dielectric layers, and then sandwiched between electrodes, and the emissive mechanism is localized type emissive emission utilizing inner-shell electron transitions of metal ions. For the purposes of this explanation, organic EL devices will be used as the emissive devices.

[0180] The light-emitting device only needs to have at least one of its pair of electrodes transparent in order to extract light. The transistor and light-emitting device are formed on a substrate, and the structure can be a top emission structure where light is extracted from the side opposite the substrate, a bottom emission structure where light is extracted from the side facing the substrate, or a dual emission structure where light is extracted from both sides.

[0181] Furthermore, optical components (optical substrates) such as a black matrix (light-shielding layer), a colored layer (color filter), a polarizing member, a phase difference member, and an anti-reflective member may be provided as needed.

[0182] Materials that can be used as a light-shielding layer include carbon black, titanium black, metals, metal oxides, and composite oxides containing solid solutions of multiple metal oxides. The light-shielding layer may be a film containing a resin material or a thin film of an inorganic material such as a metal. In addition, a laminated film containing the material for the colored layer can be used as the light-shielding layer. For example, a laminated structure can be used in which a film containing the material for a colored layer that transmits light of one color and a film containing the material for a colored layer that transmits light of another color are used. It is preferable to use the same materials for the colored layer and the light-shielding layer because it is possible to use the same equipment and simplify the process.

[0183] Materials that can be used for the colored layer include metal materials, resin materials, and resin materials containing pigments or dyes. The light-shielding layer and the colored layer can be formed, for example, using an inkjet method.

[0184] The light-emitting device 4513, which is a display device, is electrically connected to the transistor 4010 provided in the display unit 215. The configuration of the light-emitting device 4513 is a stacked structure consisting of a first electrode layer 4030, a light-emitting layer 4511, and a second electrode layer 4031, but is not limited to this configuration. The configuration of the light-emitting device 4513 can be appropriately changed according to the direction of the light emitted from the light-emitting device 4513.

[0185] The light-emitting layer 4511 may consist of a single layer or multiple layers stacked on top of each other.

[0186] The light-emitting color of the light-emitting device 4513 can be white, red, green, blue, cyan, magenta, or yellow, depending on the material that makes up the light-emitting layer 4511.

[0187] There are two methods for achieving color display: one involves combining a white light-emitting device 4513 with a colored layer, and the other involves providing a different colored light-emitting device 4513 for each pixel. The former method is more productive than the latter. On the other hand, the latter method requires creating a different light-emitting layer 4511 for each pixel, making it less productive than the former method. However, the latter method can produce light-emitting colors with higher color purity than the former method. In addition to the latter method, color purity can be further improved by adding a microcavity structure to the light-emitting device 4513.

[0188] The light-emitting layer 4511 may also contain inorganic compounds such as quantum dots. For example, quantum dots can be used in the light-emitting layer to function as a light-emitting material.

[0189] A protective layer may be formed on the second electrode layer 4031 and the partition wall 4510 to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting device 4513. The protective layer can be made of silicon nitride, silicon oxide nitride, aluminum oxide, aluminum nitride, aluminum oxide nitride (oxygen > nitrogen), aluminum oxide nitride (nitrogen > oxygen), DLC (Diamond Like Carbon), etc. Furthermore, a filler material 4514 is provided and sealed in the space enclosed by the first substrate 4001, the second substrate 4006, and the sealing material 4005. Thus, it is preferable to package (encapsulate) the device with a protective film (laminated film, UV-curing resin film, etc.) or cover material that is highly airtight and minimizes degassing, so as not to expose it to the outside air.

[0190] As the filler 4514, in addition to inert gases such as nitrogen or argon, ultraviolet-curing resins or thermosetting resins can be used, and PVC (polyvinyl chloride), acrylic resins, polyimide, epoxy resins, silicone resins, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. Furthermore, the filler 4514 may contain a desiccant.

[0191] The sealant 4005 can be a glass material such as glass frit, a two-component resin that hardens at room temperature, a photocurable resin, or a thermosetting resin. The sealant 4005 may also contain a desiccant.

[0192] Furthermore, if necessary, optical films such as polarizers, circular polarizers (including elliptical polarizers), phase difference plates (λ / 4 plates, λ / 2 plates), and color filters may be appropriately provided on the emission surface of the light-emitting device. An anti-reflective coating may also be provided on the polarizer or circular polarizer. For example, an anti-glare treatment can be applied that diffuses reflected light due to surface irregularities, thereby reducing reflections.

[0193] Furthermore, by using a microcavity structure for the light-emitting device, it is possible to extract light with high color purity. In addition, by combining the microcavity structure with a color filter, reflections can be reduced, improving the visibility of the displayed image.

[0194] In the first and second electrode layers (also called pixel electrode layers, common electrode layers, or counter electrode layers) that apply voltage to the display device, the light transmittance and reflectivity can be selected based on the direction of the extracted light, the location where the electrode layers are provided, and the pattern structure of the electrode layers.

[0195] The first electrode layer 4030 and the second electrode layer 4031 can be made of a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with silicon oxide added.

[0196] Furthermore, the first electrode layer 4030 and the second electrode layer 4031 can be formed using one or more of the following metals, alloys thereof, or metal nitrides, such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag).

[0197] Furthermore, the first electrode layer 4030 and the second electrode layer 4031 can be formed using a conductive composition containing a conductive polymer (also called a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. Examples include polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers or derivatives thereof consisting of two or more of aniline, pyrrole, and thiophene.

[0198] Figure 22 shows an example of a display device using micro-LEDs as the display device. The same reference numerals are used for elements identical to those in Figure 21. While LED is a general term for light-emitting diodes, LEDs with a side length greater than 100 μm but less than or equal to 1 mm can be called mini-LEDs, and those with a side length of 100 μm or less can be called micro-LEDs. The configuration in Figure 22 can be applied to all types of LEDs, regardless of the LED chip size.

[0199] The micro-LED 4600 has a semiconductor layer 4610, a light-emitting layer 4620, and a semiconductor layer 4630. The light-emitting layer 4620 is sandwiched between semiconductor layers 4610 and 4630. In the light-emitting layer 4620, electrons and holes combine to emit light. An n-type semiconductor layer can be used for semiconductor layer 4610, and a p-type semiconductor layer can be used for semiconductor layer 4630. Furthermore, an n-type, i-type, or p-type semiconductor layer can be used for the light-emitting layer 4620.

[0200] A laminated structure comprising a semiconductor layer 4610, an emissive layer 4620, and a semiconductor layer 4630 is formed to emit light such as red, green, blue, blue-violet, violet, or ultraviolet light. For example, compounds containing group 13 and group 15 elements (also called group 3-5 compounds) can be used in this laminated structure. Examples of group 13 elements include aluminum, gallium, and indium. Examples of group 15 elements include nitrogen, phosphorus, arsenic, and antimony.

[0201] For example, a pn junction or pin junction can be formed using gallium-phosphorus compounds, gallium-arsenide compounds, gallium-aluminum-arsenide compounds, aluminum-gallium-indium-phosphorus compounds, gallium nitride, indium-gallium nitride compounds, selenium-zinc compounds, etc., to produce a light-emitting diode that emits the desired light. Other compounds may also be used.

[0202] Furthermore, the pn junction or pin junction may be a homojunction, a heterojunction, or a double heterojunction. Other options include using LEDs with quantum well junctions or LEDs using nanocolumns.

[0203] For example, light-emitting diodes (LEDs) that emit light in the ultraviolet to blue wavelength range can use materials such as gallium nitride. Light-emitting diodes that emit light in the ultraviolet to green wavelength range can use materials such as indium-gallium nitride compounds. Light-emitting diodes that emit light in the green to red wavelength range can use materials such as aluminum-gallium-indium-phosphorus compounds or gallium-arsenide compounds. Light-emitting diodes that emit light in the infrared wavelength range can use materials such as gallium-arsenide compounds.

[0204] If multiple micro-LEDs 4600 arranged on the same surface are configured to emit light of different colors, such as R (red), G (green), and B (blue), then color images can be displayed without using a color conversion layer. Therefore, the process of forming a color conversion layer becomes unnecessary, and the manufacturing cost of the display device can be reduced.

[0205] Furthermore, all micro-LEDs 4600 arranged on the same surface may emit light of the same color. In this case, the light emitted from the light-emitting layer 4620 is taken out of the display device via one or both of the color conversion layer and the coloring layer. For example, quantum dots can be used for the color conversion layer.

[0206] The semiconductor layer 4630 is electrically connected to the wiring layer 4730 via the wiring layers 4710 and 4720. The wiring layer 4730 can supply the cathode potential.

[0207] Furthermore, since transistors are susceptible to damage from static electricity and other factors, it is preferable to provide a protection circuit to protect the drive circuit. The protection circuit is preferably constructed using nonlinear elements.

[0208] Furthermore, the configuration shown in Figure 22 can also be used for the backlight of a liquid crystal display device. By superimposing the configuration shown in Figure 22 with pixels containing liquid crystal elements, local dimming can be performed, enabling display with extremely high contrast.

[0209] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0210] (Embodiment 3) In this embodiment, an example of a transistor that can be used as a replacement for each of the transistors shown in the above embodiment will be described with reference to the drawings.

[0211] A display device according to one aspect of the present invention can be manufactured using various types of transistors, such as bottom-gate transistors or top-gate transistors. Therefore, the semiconductor layer material and transistor structure used can be easily replaced to match existing manufacturing lines.

[0212] [Bottom-gate transistor] Figure 23A is a cross-sectional view in the channel length direction of a channel-protected transistor 810, a type of bottom-gate transistor. In Figure 23A, the transistor 810 is formed on a substrate 771. The transistor 810 also has an electrode 746 on the substrate 771 via an insulating layer 772. The electrode 746 also has a semiconductor layer 742 via an insulating layer 726. The electrode 746 can function as a gate electrode. The insulating layer 726 can function as a gate insulating layer.

[0213] Furthermore, an insulating layer 741 is provided on the channel-forming region of the semiconductor layer 742. Also, electrodes 744a and 744b are provided on the insulating layer 726 in contact with a portion of the semiconductor layer 742. Electrode 744a can function as either a source electrode or a drain electrode. Electrode 744b can function as either a source electrode or a drain electrode. A portion of electrode 744a and a portion of electrode 744b are formed on the insulating layer 741.

[0214] The insulating layer 741 can function as a channel protection layer. By providing the insulating layer 741 on the channel formation region, exposure of the semiconductor layer 742 that occurs during the formation of electrodes 744a and 744b can be prevented. Therefore, etching of the channel formation region of the semiconductor layer 742 can be prevented during the formation of electrodes 744a and 744b.

[0215] Furthermore, the transistor 810 has an insulating layer 728 on electrodes 744a and 744b and insulating layer 741, and an insulating layer 729 on insulating layer 728.

[0216] When an oxide semiconductor is used for the semiconductor layer 742, it is preferable to use a material capable of removing oxygen from a part of the semiconductor layer 742 and creating an oxygen vacancy in at least the portion of electrodes 744a and 744b that is in contact with the semiconductor layer 742. The oxygen vacancy in the semiconductor layer 742 increases in carrier concentration, and the region becomes n-type, and the n-type region (n + This region is therefore capable of functioning as either a source region or a drain region. When an oxide semiconductor is used for the semiconductor layer 742, examples of materials that can remove oxygen from the semiconductor layer 742 and create an oxygen vacancy include tungsten and titanium.

[0217] By forming source and drain regions in the semiconductor layer 742, the contact resistance between electrodes 744a and 744b and the semiconductor layer 742 can be reduced. Therefore, the electrical characteristics of the transistor, such as field-effect mobility and threshold voltage, can be improved.

[0218] When a semiconductor such as silicon is used for the semiconductor layer 742, it is preferable to provide layers that function as n-type or p-type semiconductors between the semiconductor layer 742 and electrode 744a, and between the semiconductor layer 742 and electrode 744b. The layers that function as n-type or p-type semiconductors can function as the source region or drain region of the transistor.

[0219] The insulating layer 729 is preferably formed using a material that has the function of preventing or reducing the diffusion of impurities from the outside to the transistor. The insulating layer 729 may be omitted if necessary.

[0220] An electrode 723, which can function as a back gate electrode, is provided on the insulating layer 729. The electrode 723 can be formed using the same material and method as the electrode 746. Alternatively, the electrode 723 may be omitted.

[0221] Generally, the back gate electrode is formed from a conductive layer and is positioned so as to sandwich the channel formation region of the semiconductor layer between the gate electrode and the back gate electrode. Therefore, the back gate electrode can function in the same way as the gate electrode. The potential of the back gate electrode may be the same as that of the gate electrode, the ground potential (GND potential), or any other potential. Furthermore, by changing the potential of the back gate electrode independently of the gate electrode, the threshold voltage of the transistor can be changed.

[0222] Both electrodes 746 and 723 can function as gate electrodes. Therefore, insulating layers 726, 728, and 729 can each function as gate insulating layers. Electrode 723 may be placed between insulating layer 728 and insulating layer 729.

[0223] Furthermore, when one of the electrodes, 746 or 723, is referred to as the "gate electrode," the other is referred to as the "back gate electrode." For example, in transistor 810, when electrode 723 is referred to as the "gate electrode," electrode 746 is referred to as the "back gate electrode." Also, when electrode 723 is used as the "gate electrode," transistor 810 can be considered a type of top-gate transistor. In addition, one of the electrodes, 746 or 723, may be referred to as the "first gate electrode," and the other as the "second gate electrode."

[0224] By providing electrodes 746 and 723 on either side of the semiconductor layer 742, and further by setting electrodes 746 and 723 to the same potential, the region in the semiconductor layer 742 where carriers flow becomes larger in the film thickness direction, thus increasing the amount of carrier movement. As a result, the on-current of the transistor 810 increases, and the field-effect mobility also increases.

[0225] Therefore, transistor 810 is a transistor that has a large on-current relative to its occupied area. In other words, the occupied area of ​​transistor 810 can be reduced relative to the required on-current.

[0226] Furthermore, since the gate electrode and back gate electrode are formed from conductive layers, they have the function of preventing electric fields generated outside the transistor from acting on the semiconductor layer where the channel is formed (particularly an electric field shielding function against static electricity). The electric field shielding function can be enhanced by making the back gate electrode larger than the semiconductor layer and covering the semiconductor layer with the back gate electrode.

[0227] Furthermore, by forming the back gate electrode with a light-shielding conductive film, it is possible to prevent light from entering the semiconductor layer from the back gate electrode side. Therefore, photodegradation of the semiconductor layer can be prevented, and deterioration of electrical characteristics such as a shift in the transistor's threshold voltage can be prevented.

[0228] Figure 23B is a cross-sectional view in the channel length direction of a channel-protected transistor 820 with a different configuration from Figure 23A. Transistor 820 has a structure almost identical to transistor 810, except that the insulating layer 741 covers the edge of the semiconductor layer 742. In addition, the semiconductor layer 742 and electrode 744a are electrically connected at an opening formed by selectively removing a portion of the insulating layer 741 that overlaps with the semiconductor layer 742. Furthermore, the semiconductor layer 742 and electrode 744b are electrically connected at another opening formed by selectively removing a portion of the insulating layer 741 that overlaps with the semiconductor layer 742. The region of the insulating layer 741 that overlaps with the channel formation region can function as a channel protection layer.

[0229] By providing the insulating layer 741, exposure of the semiconductor layer 742 that occurs during the formation of electrodes 744a and 744b can be prevented. Therefore, thinning of the semiconductor layer 742 during the formation of electrodes 744a and 744b can be prevented.

[0230] Furthermore, in transistor 820, the distance between electrode 744a and electrode 746, and the distance between electrode 744b and electrode 746, are longer than in transistor 810. Therefore, the parasitic capacitance between electrode 744a and electrode 746 can be reduced. Also, the parasitic capacitance between electrode 744b and electrode 746 can be reduced.

[0231] Figure 23C is a cross-sectional view in the channel length direction of a channel-etched transistor 825, which is a type of bottom-gate transistor. Transistor 825 forms electrodes 744a and 744b without using an insulating layer 741. Therefore, a portion of the semiconductor layer 742 that is exposed during the formation of electrodes 744a and 744b may be etched. On the other hand, because an insulating layer 741 is not provided, the productivity of the transistor can be increased.

[0232] [Top-gate transistor] The transistor 842 illustrated in Figure 24A is a top-gate type transistor. Electrodes 744a and 744b are electrically connected to the semiconductor layer 742 at openings formed in the insulating layers 728 and 729.

[0233] Furthermore, by removing a portion of the insulating layer 726 that does not overlap with the electrode 746, and using the electrode 746 and the remaining insulating layer 726 as a mask to introduce impurities into the semiconductor layer 742, an impurity region can be formed in the semiconductor layer 742 in a self-aligned manner. Transistor 842 has a region where the insulating layer 726 extends beyond the edge of the electrode 746. The impurity concentration in the region of the semiconductor layer 742 where impurities are introduced via the insulating layer 726 is lower than the impurity concentration in the region where impurities are introduced without going through the insulating layer 726. Therefore, in the semiconductor layer 742, an LDD (Lightly Doped Drain) region is formed in the region that overlaps with the insulating layer 726 but does not overlap with the electrode 746.

[0234] Furthermore, the transistor 842 has an electrode 723 formed on the substrate 771. The electrode 723 has a region that overlaps with the semiconductor layer 742 via the insulating layer 772. The electrode 723 can function as a back gate electrode. Note that a configuration without the electrode 723 is also possible.

[0235] Alternatively, as shown in Figure 24B for transistor 844, the insulating layer 726 in the region that does not overlap with the electrode 746 may be completely removed. Alternatively, as shown in Figure 24C for transistor 846, the insulating layer 726 may be left in place.

[0236] Figure 25A shows a cross-sectional view of transistor 810 in the channel width direction, and Figure 25B shows a cross-sectional view of transistor 842 in the channel width direction.

[0237] In the structures shown in Figures 25A and 25B, the gate electrode and the back gate electrode are connected, and the potentials of the gate electrode and the back gate electrode are the same. Furthermore, the semiconductor layer 742 is sandwiched between the gate electrode and the back gate electrode.

[0238] The length of each gate electrode and back gate electrode in the channel width direction is longer than the length of the semiconductor layer 742 in the channel width direction, and the entire channel width direction of the semiconductor layer 742 is covered by the gate electrode or back gate electrode with each insulating layer in between.

[0239] With this configuration, the semiconductor layer 742 included in the transistor can be electrically surrounded by the electric fields of the gate electrode and the back gate electrode.

[0240] Thus, the device structure of a transistor that electrically surrounds the semiconductor layer 742 in which the channel formation region is formed by the electric fields of the gate electrode and the back gate electrode can be called a Surrounded channel (S-channel) structure.

[0241] By adopting the S-channel structure, an electric field for inducing a channel by one or both of the gate electrode and the back gate electrode can be effectively applied to the semiconductor layer 742. Therefore, the current driving ability of the transistor is improved, and high on-current characteristics can be obtained. Also, since the on-current can be increased, the transistor can be miniaturized. Further, by adopting the S-channel structure, the mechanical strength of the transistor can be enhanced.

[0242] Note that the gate electrode and the back gate electrode may not be connected and different potentials may be supplied to each of them. For example, by supplying a constant potential to the back gate electrode, the threshold voltage of the transistor can be controlled.

[0243] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0244] (Embodiment 4) Electronic devices that can use a display device according to one aspect of the present invention include display devices, personal computers, image storage devices or image playback devices equipped with recording media, mobile phones, game consoles including portable ones, portable data terminals, e-book readers, cameras such as video cameras and digital cameras, goggle-type displays (head-mounted displays), navigation systems, sound playback devices (car audio systems, digital audio players, etc.), photocopiers, facsimile machines, printers, printer-multifunction devices, automated teller machines (ATMs), and vending machines. Specific examples of these electronic devices are shown in Figures 26A to 26F.

[0245] Figure 26A shows a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a speaker 967, a display unit 965, operation keys 966, a zoom lever 968, a lens 969, etc. A display device according to one embodiment of the present invention can be used for the display unit 965.

[0246] Figure 26B shows a portable data terminal, which includes a housing 911, a display unit 912, a speaker 913, operation buttons 914, a camera 919, etc. Information can be input and output using the touch panel function of the display unit 912. A display device according to one embodiment of the present invention can be used in the display unit 912.

[0247] Figure 26C shows a mobile phone, which includes a housing 951, a display unit 952, operation buttons 953, an external connection port 954, a speaker 955, a microphone 956, a camera 957, etc. The mobile phone is equipped with a touch sensor on the display unit 952. All operations, such as making a phone call or entering text, can be performed by touching the display unit 952 with a finger or stylus. Furthermore, the housing 951 and the display unit 952 are flexible and can be bent for use as shown in the figure. A display device according to one embodiment of the present invention can be used in the display unit 952.

[0248] Figure 26D shows a drive recorder comprising a housing 931, a display unit 932, operation buttons 933, a microphone 934, a lens 935, and mounting parts 936. By fixing it to the front windshield of a car via the mounting parts 936, it can record the scenery ahead while driving. The display unit 932 can display the recorded image. A display device according to one embodiment of the present invention can be applied to the display unit 932.

[0249] Figure 26E shows a television, which includes a housing 971, a display unit 973, operation buttons 974, a speaker 975, a communication connection terminal 976, an optical sensor 977, etc. The display unit 973 is equipped with a touch sensor, allowing for input operations. A display device according to one embodiment of the present invention can be used in the display unit 973.

[0250] Figure 26F shows a digital signage system, which has a large display unit 922. The digital signage system is mounted, for example, on the side of a column 921. A display device according to one embodiment of the present invention can be used for the display unit 922.

[0251] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. [Explanation of Symbols]

[0252] Tr1: Transistor, Tr2: Transistor, Tr3: Transistor, Tr4: Transistor, Tr5: Transistor, 10: Pixel, 10a: Pixel, 10b: Pixel, 11: Pixel array, 20: Source driver, 30: Gate driver, 40: Ramp wave signal generation circuit, 101: Transistor, 102: Transistor, 103: Transistor, 104: Transistor, 105: Transistor, 106: Capacitor, 108: Light-emitting device, 121: Wiring, 122: Wiring, 123: Wiring, 125: Wiring, 126: Wiring, 127: Wiring, 128: Wiring, 129 :Wiring, 215:Display unit, 221a:Scan line drive circuit, 231a:Signal line drive circuit, 232a:Signal line drive circuit, 241a:Common line drive circuit, 723:Electrode, 726:Insulating layer, 728:Insulating layer, 729:Insulating layer, 741:Insulating layer, 742:Semiconductor layer, 744a:Electrode, 744b:Electrode, 746:Electrode, 771:Substrate, 772:Insulating layer, 810:Transistor, 820:Transistor, 825:Transistor, 842:Transistor, 844:Transistor, 846:Transistor, 911:Housing, 912:Display unit, 913:Speaker, 914:Operation button 919: Camera, 921: Pillar, 922: Display unit, 931: Housing, 932: Display unit, 933: Operation buttons, 934: Microphone, 935: Lens, 936: Parts, 951: Housing, 952: Display unit, 953: Operation buttons, 954: External connection port, 955: Speaker, 956: Microphone, 957: Camera, 961: Housing, 962: Shutter button, 963: Microphone, 965: Display unit, 966: Operation keys, 967: Speaker, 968: Zoom lever, 969: Lens, 971: Housing, 973: Display unit, 974: Operation buttons, 975: Speaker, 976: Communication port Terminal, 977: Optical sensor, 4001: Substrate, 4005: Sealing material, 4006: Substrate, 4010: Transistor, 4011: Transistor, 4014: Wiring, 4015: Electrode, 4018: FPC, 4019: Anisotropic conductive layer, 4020: Capacitor, 4021: Electrode, 4030: Electrode layer, 4031: Electrode layer, 4041: Printed circuit board, 4042: Integrated circuit, 4104: Insulating layer, 4110: Insulating layer, 4111: Insulating layer, 4112: Insulating layer, 4200: Input device, 4210: Touch panel, 4227: Electrode, 4228: Electrode, 4237: Wiring, 4238: Wiring,4239: Wiring, 4263: Substrate, 4272b: FPC, 4273b: IC, 4510: Partition, 4511: Light-emitting layer, 4513: Light-emitting device, 4514: Filler, 4600: Micro-LED, 4610: Semiconductor layer, 4620: Light-emitting layer, 4630: Semiconductor layer, 4710: Wiring layer, 4720: Wiring layer, 4730: Wiring layer,

Claims

1. A display device having a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a capacitor, and a light-emitting device in each pixel, The first transistor, the third transistor, and the fourth transistor are n-channel transistors. The second transistor is a p-channel transistor, The second transistor has silicon in the channel formation region, The source or drain of the first transistor is electrically connected to the gate of the second transistor and to one electrode of the capacitor. The source or drain of the first transistor, the other of which is electrically connected to the source line, The gate of the first transistor is electrically connected to the gate wire. Either the source or drain of the second transistor is electrically connected to either the source or drain of the third transistor and to the gate of the fourth transistor. The source or drain of the second transistor, the other of which is electrically connected to a high-potential power line, The source or drain of the third transistor, the other of which is electrically connected to a low-voltage power line, The gate of the third transistor is electrically connected to the wiring to which the ramp wave is supplied. Either the source or the drain of the fourth transistor is electrically connected to the light-emitting device. The source or drain of the fourth transistor, the other of which is electrically connected to the low-potential power line, Either the source or the drain of the fifth transistor is electrically connected to the gate of the fourth transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the low-voltage power line, The gate of the fifth transistor is electrically connected to the gate line of the display device.

2. In claim 1, The first transistor has a metal oxide in the channel formation region. The metal oxide is a display device containing In.

3. In claim 1, The first transistor has a metal oxide in its channel-forming region, and the metal oxide is a display device comprising In, Zn, and M (where M is one or more selected from Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf).

4. In any one of claims 1 to 3, The other electrode of the capacitor is electrically connected to a power line and is a display device.

5. In any one of claims 1 to 4, The light-emitting device is an LED, and one of the source or drain of the fourth transistor is electrically connected to the cathode of the LED in this display device.

6. In any one of claims 1 to 4, The light-emitting device is an organic EL element, and the source or drain of the fourth transistor is electrically connected to the anode of the organic EL element in this display device.

7. An electronic device having a display device according to any one of claims 1 to 6, and a camera.

Images