Semiconductor equipment

Abstract

To provide a highly reliable semiconductor device using an oxide semiconductor, or to provide a semiconductor device using an oxide semiconductor that achieves miniaturization while maintaining good electrical characteristics. [Solution] The transistor 100 includes a first protective insulating layer 111, an oxide semiconductor layer 102 on the first protective insulating layer, a pair of source and drain electrodes 103 electrically connected to the oxide semiconductor layer, a gate insulating layer 104 located on the source and drain electrodes and overlapping the oxide semiconductor layer, a gate electrode 105 overlapping the oxide semiconductor layer via the gate insulating layer, and a second protective insulating layer 112 covering the source, drain, and gate electrodes. Furthermore, the first and second protective insulating layers include an aluminum oxide film having an oxygen-rich region and have regions that are in contact with each other in regions where the source, drain, and gate electrodes are absent.

Description

Technical Field

[0001] The invention disclosed in this specification etc. relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002] In this specification etc., the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, including transistors, semiconductor circuits, arithmetic units, storage devices, imaging devices, electro-optical devices, power generation devices (including thin film solar cells, organic thin film solar cells, etc.), and electronic devices are one aspect of semiconductor devices.

Background Art

[0003] Techniques for constructing transistors using semiconductor thin films formed on substrates having insulating surfaces have attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.

[0004] For example, techniques for manufacturing transistors using zinc oxide or In-Ga-Zn-based oxide semiconductors as oxide semiconductors are disclosed (see Patent Document 1 and Patent Document 2).

[0005] Also, techniques for laminating oxide semiconductor layers having different electron affinities (or conduction band lower level positions) for the purpose of improving the carrier mobility of transistors are disclosed (see Patent Document 3 and Patent Document 4).

Prior Art Documents

Patent Documents

[0006] [Patent Document 1] Japanese Patent Publication No. 2007-123861 [Patent Document 2] Japanese Patent Publication No. 2007-96055 [Patent Document 3] Japanese Patent Publication No. 2011-124360 [Patent Document 4] Japanese Patent Publication No. 2011-138934 [Overview of the project] [Problems that the invention aims to solve]

[0007] In semiconductor devices having transistors made of oxide semiconductors, achieving high reliability is difficult. This is a crucial point for commercialization. In particular, fluctuations or degradation in the electrical characteristics of semiconductor devices lead to low reliability. This is one of the factors that leads to the decline.

[0008] In view of these problems, one aspect of the present invention is a semiconductor device using an oxide semiconductor, One of our objectives is to provide highly reliable semiconductor devices.

[0009] Furthermore, it is possible to increase the speed of transistor operation, reduce the power consumption of transistors, lower the cost, and increase integration. Miniaturization of transistors is essential to achieve such advancements.

[0010] Therefore, one aspect of the present invention is a semiconductor device using an oxide semiconductor, which has good electrical characteristics One of the objectives is to provide a semiconductor device that achieves miniaturization while maintaining performance.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention It is not necessary to solve all of these problems. Furthermore, any other problems not mentioned above are clearly defined. This will become clear from the details and other descriptions, and any issues other than those mentioned above will not be identified from the specifications and other descriptions. It is possible to extract it. [Means for solving the problem]

[0012] A semiconductor device according to one aspect of the present invention comprises a first protective insulating layer and an oxide layer on the first protective insulating layer. A semiconductor layer, source electrodes and drain electrodes electrically connected to the oxide semiconductor layer, and A gate insulating layer located on the drain electrode and the gate electrode, overlapping the oxide semiconductor layer, and the gate A gate electrode overlapping the oxide semiconductor layer via an insulating layer, a source electrode, a drain electrode, and It also has a first protective insulating layer and a second protective insulating layer covering the gate electrode. The protective insulating layer includes an aluminum oxide film having an oxygen-rich region, and the source electrode, drain It has regions that are in contact with each other in the region where there are no electrodes and gate electrodes.

[0013] Furthermore, the gate electrode covers the top and side surfaces of the oxide semiconductor layer via the gate insulating layer. It is preferable to have such a configuration.

[0014] Furthermore, the above oxide semiconductor layer has a thickness of 0.1 times or more and 10 times or less the channel width. It is preferable to have one.

[0015] Furthermore, in the above, a first protective insulating layer is provided between the oxide semiconductor layer and the oxide semiconductor layer. A first oxide layer comprising at least one metallic element of the body layer, and an oxide semiconductor layer It is provided between the gate insulating layer and the oxide semiconductor layer and is composed of at least one of the metal elements of the oxide semiconductor layer. A configuration having a second oxide layer is also possible. Here, the first oxide layer and the second The energy at the bottom of the conduction band of the oxide layer is greater than the energy at the bottom of the conduction band of the oxide semiconductor layer. Furthermore, it is preferable to have a configuration that is close to the vacuum level in the range of 0.05 eV to 2 eV.

[0016] Furthermore, the upper surface of the second oxide layer is the lower surface of the source electrode, the lower surface of the drain electrode, and the gate It may also be configured to be in contact with the lower surface of the insulating layer.

[0017] Alternatively, the lower surface of the second oxide layer is the upper surface of the source electrode, the upper surface of the drain electrode, and The upper surface of the oxide semiconductor layer in the region where source electrodes and drain electrodes are not provided and It may also be configured to be in contact with the side.

[0018] Furthermore, another embodiment of the present invention provides a semiconductor device comprising an insulating layer having grooves, and the sides of the grooves and A first protective insulating layer is provided to cover the bottom surface, and a groove is embedded on the first protective insulating layer. An oxide semiconductor layer is provided as such, and a source electrode is electrically connected to the oxide semiconductor layer. The drain electrode and the source electrode and drain electrode are located on top of the oxide semiconductor layer. A gate insulating layer, a gate electrode that overlaps with the oxide semiconductor layer via the gate insulating layer, and a source electrode The configuration includes a electrode, a drain electrode, and a second protective insulating layer covering the gate electrode. Furthermore, the first protective insulating layer and the second protective insulating layer are made of aluminum oxide having an oxygen-rich region. A region containing a nium film and lacking a source electrode, drain electrode, and gate electrode They have areas that touch each other. [Effects of the Invention]

[0019] According to one aspect of the present invention, a semiconductor device using an oxide semiconductor, wherein a highly reliable semiconductor... A conductive device can be provided.

[0020] Furthermore, according to one aspect of the present invention, a semiconductor device using an oxide semiconductor provides good electrical performance. This makes it possible to provide a semiconductor device that achieves miniaturization while maintaining its gas characteristics. [Brief explanation of the drawing]

[0021] [Figure 1] An example of the configuration of a semiconductor device according to an embodiment. [Figure 2] A diagram illustrating an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 3] An example of the configuration of a semiconductor device according to an embodiment. [Figure 4] An example of the configuration of a semiconductor device according to an embodiment. [Figure 5] An example of the configuration of a semiconductor device according to an embodiment. [Figure 6] A diagram illustrating an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] An example of the configuration of a semiconductor device according to an embodiment. [Figure 8] An example of the configuration of a semiconductor device according to an embodiment. [Figure 9] An example configuration and circuit diagram of a semiconductor device according to an embodiment. [Figure 10] An example of the configuration of a semiconductor device according to an embodiment. [Figure 11] A diagram illustrating a band diagram according to an embodiment. [Figure 12] An example of the configuration of a semiconductor device according to an embodiment. [Figure 13] An example of the configuration of a semiconductor device according to an embodiment. [Figure 14] An example of the configuration of a semiconductor device according to an embodiment. [Figure 15] An example of the configuration of a semiconductor device according to an embodiment. [Figure 16] An example configuration and circuit diagram of a semiconductor device according to an embodiment. [Figure 17] An example of the configuration of a semiconductor device according to an embodiment. [Figure 18] An equivalent circuit diagram of a semiconductor device according to an embodiment. [Figure 19] Circuit diagram of a semiconductor device according to an embodiment. [Figure 20] A block diagram of a semiconductor device according to an embodiment. [Figure 21] A circuit diagram illustrating a storage device according to an embodiment. [Figure 22] An electronic device according to an embodiment. [Figure 23] Cross-sectional TEM images and local Fourier transform images of oxide semiconductors. [Figure 24] A diagram showing the nanobeam electron diffraction pattern of an oxide semiconductor film, and a diagram showing an example of a transmission electron diffraction measurement device. [Figure 25] A figure and a planar TEM image illustrating an example of structural analysis by transmission electron diffraction measurement. [Figure 26] An example of the configuration of a semiconductor device according to an embodiment. [Figure 27] An example of the configuration of a semiconductor device according to an embodiment. [Figure 28] An example of the configuration of a semiconductor device according to an embodiment. [Figure 29] An example of the configuration of a semiconductor device according to an embodiment. [Modes for carrying out the invention]

[0022] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, its form and details may be modified in various ways. Those skilled in the art will readily understand what is possible. Therefore, the present invention is as shown in the following embodiments. It should not be interpreted as being limited to the contents described herein.

[0023] In the configuration of the invention described below, the same part or part having a similar function is The same reference numerals are used consistently across different drawings, and explanations of their repetition are omitted. When referring to the function of [this], the hatch pattern is the same, and sometimes no specific symbol is assigned.

[0024] In each figure described herein, the size, layer thickness, or area of ​​each component is as follows: It may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. stomach.

[0025] In this specification, ordinal numbers such as "the first," "the second," etc., are used to avoid confusion of constituent elements. This is added for the purpose of providing a numerical limit, and is not intended to limit the number of items.

[0026] A transistor is a type of semiconductor device that amplifies current and voltage, and controls conduction or non-conductivity. It is possible to realize controlled switching operations, etc. Transistors in this specification are , IGFET(Insulated Gate Field Effect Trans istors and thin-film transistors (TFTs) ) includes.

[0027] (Embodiment 1) In this embodiment, as an example of a semiconductor device according to one aspect of the present invention, a transistor configuration example is provided. An example of the manufacturing method will be explained with reference to the drawings.

[0028] When fabricating transistors using oxide semiconductors, the source of carriers in the oxide semiconductor... One example is oxygen deficiency. If there are many oxygen vacancies in the conductor, electrons will be generated in the channel formation region, Normally-on operation of the zista, increased leakage current, and fluctuation of threshold voltage due to stress application. (Shifting, etc.) can be a factor that causes electrical defects.

[0029] Furthermore, in the oxide semiconductor layer, hydrogen, silicon, nitrogen, carbon, and metal elements other than the main component The element becomes an impurity. For example, in an oxide semiconductor layer, some of the hydrogen forms a donor level, and Increase the carrier density.

[0030] Therefore, in order to obtain stable electrical characteristics in semiconductor devices using oxide semiconductors, By supplying sufficient oxygen to the oxide semiconductor layer, oxygen deficiency is reduced, and impurities such as hydrogen are also reduced. Measures to reduce the concentration of the substance are required.

[0031] Therefore, in a semiconductor device according to one aspect of the present invention, an oxygen-rich region surrounds the oxide semiconductor layer. A protective insulating layer is provided, which includes an aluminum oxide film having the following properties, and a channel is formed from the protective insulating layer. By supplying oxygen to the region, it compensates for any oxygen deficiencies that may form in the channel formation region. Furthermore, the protective insulating layer suppresses the release of oxygen from the oxide semiconductor layer, thereby suppressing the formation of oxygen vacancies. do.

[0032] In one aspect of the present invention, as a protective insulating layer for supplying oxygen to the channel-forming region This shall involve applying an insulating layer having an aluminum oxide film containing excess oxygen. Here, Excess oxygen refers to, for example, oxygen present in amounts exceeding the stoichiometric composition, or the production of semiconductor devices. This refers to oxygen that can be released from heating at temperatures below the heat treatment temperature applied during the manufacturing process. For example, As an aluminum oxide film containing excess oxygen, AlO x Use a membrane (where x is greater than 3 / 2). This is possible. Excess oxygen contained in the aluminum oxide film is released by heating and oxide Because it can be supplied to the semiconductor layer, such an insulating film containing aluminum oxide is By providing layers below and above the oxide semiconductor layer, oxygen can be effectively supplied to the channel formation region. It can be supplied.

[0033] Furthermore, aluminum oxide films containing excess oxygen can be sputtered, for example, in an oxygen-containing atmosphere. It can be formed by depositing a film using methods such as the ring method.

[0034] Furthermore, aluminum oxide films can be used as insulating layers such as silicon oxide films and silicon oxide nitride films, This is an insulating layer with lower permeability to oxygen and hydrogen compared to an oxide semiconductor layer. In other words... Therefore, it is an insulating layer that has barrier properties against oxygen and hydrogen. By providing an insulating layer containing [a specific substance], oxygen deficiency due to oxygen desorption in the region surrounded by the insulating layer is prevented. This makes it possible to suppress the formation of hydrogen and to suppress the inclusion of hydrogen or hydrogen compounds.

[0035] In one embodiment of the present invention, protective insulating layers provided above and below the oxide semiconductor layer are An oxide semiconductor layer, and source electrodes and drain electrodes electrically connected to the oxide semiconductor layer. In a region where none exist, there are regions that are in contact with each other. That is, half of one aspect of the present invention The conductive device has a configuration in which an aluminum oxide film is provided so as to surround an oxide semiconductor layer. This configuration allows the front channel and back channels of the oxide semiconductor layer to be configured as follows: In addition to the channel-side interface, oxygen desorption and / or hydrogen desorption occur on the side surface of the oxide semiconductor layer. This makes it possible to suppress the inclusion of impurities and supply oxygen. This suppresses fluctuations in the electrical characteristics of transistors in which channels are formed in the conductor layer, resulting in highly reliable semiconductors. This makes it possible to form a conductive device.

[0036] Therefore, in one aspect of the present invention, the oxygen vacancy in the channel formation region is reduced. As a result, a highly reliable semiconductor with good electrical properties and suppressed fluctuations in electrical properties is achieved. The device can be realized.

[0037] The effects of the configuration according to one aspect of the present invention can be explained, for example, as follows.

[0038] A semiconductor device according to one aspect of the present invention comprises an insulating layer containing an aluminum oxide film having excess oxygen. The oxide semiconductor layer is enclosed within it. The excess oxygen contained in the aluminum oxide film is In the semiconductor device manufacturing process, heat treatment in an oxide semiconductor layer forms channels. It is supplied to [the facility]. Furthermore, the aluminum oxide film has barrier properties against oxygen and hydrogen. Therefore, oxygen is removed from the oxide semiconductor layer encased in an insulating layer containing an aluminum oxide film, and This makes it possible to suppress the incorporation of impurities such as hydrogen into the oxide semiconductor layer. The supplied oxide semiconductor layer, with the inclusion of impurities such as hydrogen suppressed, is purified to a high purity. It is an oxide semiconductor layer.

[0039] Furthermore, in the above semiconductor device, the gate overlaps with the oxide semiconductor layer via the gate insulating layer. The electrode is provided so as to overlap with the side and top surfaces of the channel formation region of the oxide semiconductor layer. This is preferable. With this configuration, the oxide semiconductor layer has a direction perpendicular to the side surface. Since an electric field is applied from a direction perpendicular to the upper surface, the threshold voltage of the transistor can be controlled effectively. It can be controlled and the subthreshold coefficient (also called the S value) can be improved.

[0040] Here, in order to achieve high density (high integration) of semiconductor devices, the miniaturization of transistors is necessary. Miniaturization is essential. On the other hand, the miniaturization of transistors worsens their electrical characteristics. It is known that this can sometimes happen.

[0041] For example, in a silicon transistor, shortening the channel length results in a subthreshold. It is known that short-channel effects such as degradation of the Jord coefficient (S value) and fluctuations in threshold voltage can occur. It is being done.

[0042] However, transistors using oxide semiconductors store electrons as the majority carriers. Because it is a type transistor, compared to inverting transistors such as silicon, it is suitable for short channels. DIBL (Drain-Induced Barrier Lowering) occurs. It is difficult. Transistors using oxide semiconductors have resistance to short-channel effects. It can also be rephrased.

[0043] Furthermore, reducing the channel width of a transistor raises concerns about a decrease in on-current. To improve flow, the active layer is thickened so that channels are formed on the sides of the active layer as well. Although the method is known, the channel formation region increases as the surface area where channels are formed increases. Because carrier scattering increases at the interface between the zone and the gate insulating layer, a sufficient improvement in on-current is not observed. It's not easy to get in.

[0044] However, in a transistor according to one aspect of the present invention, the oxidative stress that forms the channel A material semiconductor layer is enclosed by an insulating layer containing an aluminum oxide film containing excess oxygen. By doing so, excess oxygen contained in the aluminum oxide film is supplied to the oxide semiconductor layer, and, This can suppress the desorption of oxygen from the oxide semiconductor layer and the incorporation of impurities such as hydrogen. For a semiconductor layer, oxygen vacancies and hydrogen are factors that generate carriers, therefore excess oxygen By providing an aluminum oxide film, channels are formed at the interface of the oxide semiconductor layer. This can suppress the scattering of carriers that may occur.

[0045] Therefore, even when the channel width is reduced, the thickness of the oxide semiconductor layer can be increased. By increasing the surface area overlapping with the gate electrode, the on-current can be significantly improved. This is possible. In order to sufficiently apply an electric field from the gate electrode in the lateral direction of the oxide semiconductor layer It is preferable that the thickness of the oxide semiconductor layer be greater than or equal to the channel width.

[0046] Furthermore, the oxide semiconductor layer is in contact with the oxide semiconductor layer and contains at least one of the metal elements of the oxide semiconductor layer. By providing the oxide layer, the scattering of the carriers mentioned above can be further suppressed. It is effective.

[0047] Furthermore, when the channel length and channel width of a transistor are miniaturized, a resist mask is used. The edges of wiring, semiconductor layers, etc., that are processed may be rounded (have curved surfaces). A thin insulating layer (e.g., a gate insulating layer) is formed to cover the film-formed oxide semiconductor layer. In such cases, a decrease in coverage can lead to shape defects, and stable electrical characteristics may not be obtained. However, because the edge face of the oxide semiconductor layer has a curved surface, the insulating layer provided on the oxide semiconductor layer This is preferable because it can improve the coverage of the layer.

[0048] Furthermore, some of the hydrogen in the oxide semiconductor layer is trapped in oxygen vacancies, making the oxide semiconductor layer n-type As a result, the Fermi level (Ef) approaches the lower end of the conduction band (Ec). Therefore, a large amount of hydrogen... While the oxide semiconductor layer contained within raises concerns about fluctuations in electrical properties, the transistor's electric field... An improvement in effective mobility is expected. On the other hand, if the oxide semiconductor layer is made intrinsically or substantially intrinsically The Fermi energy of the oxide semiconductor layer is the midgap (energy of the oxide semiconductor layer). It matches, or approaches very closely, the energy of the intermediate gap. In this case, oxide semiconductors A decrease in the number of carriers in the body layer raises concerns about a decline in field-effect mobility.

[0049] However, in a transistor according to one aspect of the present invention, the oxide semiconductor layer is perpendicular to the direction In addition to the gate electric field from the outside, a gate electric field is applied from the side. That is, oxide The gate field is applied to the entire semiconductor layer, and the current flows through the bulk of the oxide semiconductor layer. It flows. This achieves the suppression of fluctuations in electrical properties due to high-purity intrinsic ionization, and This makes it possible to improve the field-effect mobility of the inverter.

[0050] More specifically, the configuration can be as follows:

[0051] [Configuration Example 1] Figure 1(A) shows a schematic top view of the transistor 100 illustrated in this configuration example. (B) and (C) are schematic cross-sectional diagrams at the cutting lines AB and CD in Figure 1(A), respectively. This is shown. Note that some components are not explicitly shown in Figure 1(A) for clarity.

[0052] The transistor 100 is provided on the substrate 101 and has an island-shaped semiconductor layer 102 and a semiconductor layer A pair of electrodes 103 electrically connected to 102, and a semiconductor layer located on the pair of electrodes 103. A gate insulating layer 104 overlaps with 102, and a semiconductor layer 102 is located on the gate insulating layer 104. It has a gate electrode 105 that overlaps with it.

[0053] Furthermore, a first protective insulating layer 111 is provided between the substrate 101 and the semiconductor layer 102. Furthermore, a second protective insulating layer 112 is provided on the pair of electrodes 103 and gate electrode 105. It is provided. Furthermore, the first protective insulating layer 111 and the second protective insulating layer 112 are a pair In the region where electrodes 103 and gate electrode 105 are not provided, they are provided in contact with each other. It is being done.

[0054] The semiconductor layer 102 contains an oxide semiconductor. The semiconductor layer 102 also contains at least indi- It is preferable to include in (In) or zinc (Zn). Alternatively, it may contain both In and Zn. It is preferable to use an In-M-Zn oxide (where M is Al, Ti, Ga, Includes oxides represented by metals such as Ge, Y, Zr, Sn, La, Ce, or Hf.

[0055] Of the pair of electrodes 103, one functions as the source electrode of the transistor 100, and the other This functions as a drain electrode. Also, in Figure 1(B), the pair of electrodes 103 are each half It is provided in contact with the upper and side surfaces of the conductor layer 102.

[0056] The gate electrode 105 is connected to the top and side surfaces of the semiconductor layer 102 via the gate insulating layer 104. It is constructed in a way that encloses it.

[0057] Here, the channel length (L length) of a transistor is the distance between the opposing source and drain. Let's assume that the channel width (W length) of the transistor is defined as the direction perpendicular to the channel length direction. This refers to the width of the semiconductor layer in the transistor. Note that this also refers to the source electrode, drain electrode, and gate electrode of the transistor. Depending on the shape of the poles and semiconductor layers, the channel length and channel width may vary depending on the region (location). These can sometimes differ. In such cases, the average or minimum values ​​of these can be used as transitions. It can be applied as the channel length or channel width of a stylus.

[0058] Since the gate electrode 105 is provided so as to surround the side surface of the semiconductor layer 102, the semiconductor layer 10 The second side can also function as a channel formation region. The thickness of the semiconductor layer 102 is preferably 0.05 times or more and 20 times or less the channel width. It is preferable that the ratio be between 0.1 and 10 times. By having such a shape, Even when the panel width is reduced, the decrease in on-current is suppressed, resulting in finer and faster operation. This makes it possible to create a transistor capable of doing so.

[0059] In this way, the gate electrode surrounds the top and sides of the semiconductor layer of the transistor. By actively utilizing the channels provided and formed near the side surface of the semiconductor layer, ON-Electrification The structure of a transistor with enhanced current flow is called Surrounded Channel (SC) It can also be called a hannel structure.

[0060] The first protective insulating layer 111 and the second protective insulating layer 112 have oxygen-rich regions, and An insulating material that has the function of suppressing the diffusion of oxygen (also called oxygen blocking properties) It can be used. For example, a first protective insulating layer 111 and a second protective insulating layer 112 Therefore, a layer containing an aluminum oxide film can be used. In addition, aluminum oxide Aluminum oxide nitride, gallium oxide, gallium oxide nitride, yttrium oxide, nitrogen oxide Yttrium oxide, hafnium oxide, hafnium nitride oxide, yttria-stabilized zirconia ( A film containing an oxygen-containing insulating material such as YSZ can also be applied.

[0061] An insulating film having an oxygen-rich region is, for example, one with more oxygen than that satisfying the stoichiometric composition. It is preferable to use an oxide insulating film containing oxygen. In oxide insulating films containing a large amount of oxygen, some of the oxygen is removed upon heating.

[0062] Furthermore, the first protective insulating layer 111 and the second protective insulating layer 112 have an extremely low hydrogen content. It is preferable to use an insulating material with low thermal conductivity. For example, secondary ion mass spectrometry (SIMS): Hydrogen detected by Secondary Ion Mass Spectrometry The content is 5 x 10 21 atoms / cm 3 Less than 2 × 10 21 atoms / cm 3 Less than 1 × 10 21 atoms / cm 3 An absolute region including the area less than Edge material can be used.

[0063] Furthermore, the insulating material applied to the first protective insulating layer 111 and the second protective insulating layer 112 is also used. Furthermore, materials containing silicon oxide in the aforementioned oxides can also be used. For example, silicon oxide Recon in the range of 0.1% to 30% by weight (e.g., 5% or 10% by weight). Aluminum oxide containing silicon oxide can be used. By doing so, it is possible to desorb it by heating without reducing its blocking properties against oxygen. This allows for an increase in the amount of oxygen and a reduction in membrane stress.

[0064] [Regarding each component] The following describes each component of transistor 100.

[0065] [Semiconductor layer] As an oxide semiconductor included in semiconductor layer 102, it has a wider band gap than silicon. Furthermore, when using an oxide semiconductor with a low carrier density, the off state of the transistor This is preferable because it allows for a reduction in current.

[0066] Furthermore, the semiconductor used in the semiconductor layer 102 can be an amorphous semiconductor or a crystalline semiconductor. semiconductors (microcrystalline semiconductors, polycrystalline semiconductors, single-crystal semiconductors, or semiconductors with crystalline parts in part or all) Any of the semiconductors having the properties may be used. Having it present is preferable because it suppresses the degradation of the transistor's characteristics.

[0067] In particular, the semiconductor layer 102 has multiple crystalline portions, and the c-axis of the crystalline portion is aligned with the semiconductor layer 10 On the surface to be formed (the upper surface of the first protective insulating layer 111 in Figure 1) or the upper surface of the semiconductor layer 102 In contrast, it is preferable to use layers that are oriented roughly perpendicularly and that do not have grain boundaries between adjacent crystal regions. It's nice.

[0068] By using such a material as the semiconductor layer 102, fluctuations in electrical properties are suppressed. This enables the creation of a highly reliable transistor 100.

[0069] Furthermore, the semiconductor layer 102 may be a single-layer structure or a stacked structure of two or more layers. In such cases, two or more oxide semiconductor films with different compositions may be combined.

[0070] Furthermore, regarding preferred forms of oxide semiconductors applicable to the semiconductor layer 102 and methods for forming them... This will be explained in detail in a later embodiment.

[0071] 〔substrate〕 There are no major restrictions on the material of the substrate 101, but it must be able to withstand the heat treatment during the manufacturing process. A material with a certain degree of heat resistance is used. For example, a glass substrate, a ceramic substrate, a quartz substrate, etc. A fire substrate, an yttria-stabilized zirconia (YSZ) substrate, etc., can be used as substrate 101. It may be present. Also, single-crystal semiconductor substrates such as silicon or silicon carbide or polycrystalline semiconductors. Substrates, compound semiconductor substrates such as silicon germanium, and SOI substrates can also be used. can.

[0072] Furthermore, semiconductor elements are provided on various semiconductor substrates and SOI substrates, and the substrate 101 and It may be used in this way. In that case, the transistor 100 is placed on the substrate 101 via an interlayer insulating layer. To form. At this time, the connecting electrodes embedded in the interlayer insulating layer form the transistor 10 At least one of the gate electrode 105 and the pair of electrodes 103 is electrically connected to the semiconductor element. The configuration should be such that it is connected to the semiconductor element via an interlayer insulating layer. By providing this, the increase in area caused by adding transistor 100 is suppressed. It is possible.

[0073] [ ] The gate electrode 105 is made of aluminum, chromium, copper, tantalum, titanium, molybdenum, and A metal selected from ngsten, or an alloy containing the above-mentioned metals, or the above-mentioned metals It can be formed using a combination of alloys, etc. Also, manganese, zirconium You may use one or more metals selected from the available options. Furthermore, impurity elements such as phosphorus may be removed. Semiconductors such as polycrystalline silicon with pinning, and silicides such as nickel silicide. It may be used. Also, the gate electrode 105 may be a single-layer structure or a stacked structure of two or more layers. Good. For example, a single-layer structure of an aluminum film containing silicon, or a titanium film on top of an aluminum film. A two-layer structure in which a titanium film is stacked on top of a titanium nitride film, a two-layer structure in which a titanium film is stacked on top of a titanium nitride film A two-layer structure with stacked tungsten films, a tantalum nitride film, or tungsten nitride film with tungsten film on top. A two-layer structure consisting of stacked gusten films, a titanium film, and an aluminum film stacked on top of the titanium film. Furthermore, there are three-layer structures, such as one in which a titanium film is formed on top of the aluminum. Selected from tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. An alloy film made up of one or more metals, or a nitride film made from these metals, may be used.

[0074] Furthermore, the electrode 105 contains indium tin oxide and tungsten oxide. Indium zinc oxide containing oxides, tungsten oxide, and indium acid containing titanium oxide Indium tin oxide containing titanium oxide, indium zinc oxide, and silicon oxide are added. It is also possible to apply conductive materials with light-transmitting properties, such as indium tin oxide. Alternatively, a laminated structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal can be used.

[0075] Furthermore, between the gate electrode 105 and the gate insulating layer 104, an In-Ga-Zn oxynitride is provided. Semiconductor films, In-Sn oxynitride semiconductor films, In-Ga oxynitride semiconductor films, In-Zn Sn-based oxynitride semiconductor films, Sn-based oxynitride semiconductor films, In-based oxynitride semiconductor films, metal nitride films ( These films may be provided with InN, ZnN, etc. The film thickness should be 5 eV or higher, preferably 5.5 eV. It has the above work function, and since it is greater than the electron affinity of oxide semiconductors, The threshold voltage of a transistor using a conductor can be shifted to a positive value, which is known as normalization. This enables the realization of switching elements with re-off characteristics. For example, In-Ga-Zn oxynitride semiconductors When using a conductor film, an In-Ga-Zn-based oxynitride semiconductor film having a nitrogen concentration of at least higher than that of the semiconductor layer 102, specifically 7 atomic % is used.

[0076] 〔Gate insulating layer〕 The gate insulating layer 104 may be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, gallium oxide or a Ga-Zn-based metal oxide, silicon nitride, etc., and may be provided in a stacked or single-layer structure.

[0077] Also, as the gate insulating layer 104, hafnium silicate (HfSiO x ), hafnium silicate (HfSi with nitrogen added (HfSi x O y N z ), hafnium aluminate (HfAl with nitrogen added (HfAl x O y N z ), high- k materials such as hafnium oxide and yttrium oxide are used to reduce the gate leakage of the transistor.

[0078] 〔Pair of electrodes〕 The pair of electrodes 103 may be made of a single metal composed of aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten as a conductive material, or an alloy having this as a main component may be used in a single-layer structure or a stacked structure. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked on an aluminum film, a two-layer structure in which a copper film is stacked on a titanium film, a two-layer structure in which a titanium film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a titanium film or a titanium nitride film, and a titanium film or a titanium nitride film stacked thereon can be used. A two-layer structure in which a titanium film is stacked on an aluminum film, a two-layer structure in which a copper film is stacked on a titanium film, a two-layer structure in which a titanium film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a titanium film or a titanium nitride film, and a titanium film or a titanium nitride film stacked thereon can be used. a two-layer structure, a titanium film or a titanium nitride film, and a titanium film or a titanium nitride film stacked thereon An aluminum film or copper film is laminated, and then a titanium film or titanium nitride film is formed on top of it. A three-layer structure comprising a molybdenum film or molybdenum nitride film, and the molybdenum film or molybdenum nitride film. An aluminum film or copper film is laminated on top of the ribdenum film, and then a molybdenum film is placed on top of that. Alternatively, there are three-layer structures that form a molybdenum nitride film. Furthermore, indium oxide, tin oxide, etc. Alternatively, a transparent conductive material containing zinc oxide may be used.

[0079] The above is an example of the configuration of transistor 100 and a description of each component.

[0080] [Example of manufacturing method 1] The following describes an example of a method for fabricating transistor 100 as illustrated in Figure 1, with reference to the diagram. Let's explain. Figure 2 is a schematic cross-sectional view of each step in the manufacturing method exemplified below.

[0081] [Formation of the first protective insulating layer] First, a first protective insulating layer 111 is formed on the substrate 101 (Figure 2(A)).

[0082] The first protective insulating layer 111 is deposited by, for example, sputtering in an oxygen-containing atmosphere. It can be formed by CVD (Chemical Vapor Deposition) in an oxygen-containing atmosphere. al Vapor Deposition) method, MBE (Molecular Beam) Epitaxy) method, ALD (Atomic Layer Deposition) method or by PLD (Pulsed Laser Deposition) or the like to deposit the film. That's fine.

[0083] For example, when an aluminum oxide film is used as the first protective insulating layer 111, Aluminum can be used as a sputtering target, and a film can be deposited in an oxygen-containing atmosphere. It is possible to include inert gases such as noble gases in the film-forming gas. For example, the entire film-forming gas The oxygen flow rate relative to the total flow rate is 20% or more, preferably 30% or more, more preferably 40% or less. The above is preferable. Furthermore, the reactive when using aluminum as a sputtering target. Although an aluminum oxide film may be deposited by sputtering, Using it as a puttering target allows for the inclusion of more oxygen in the film. Therefore, it is preferable.

[0084] [Formation of semiconductor layer] Next, a semiconductor film is deposited on the first protective insulating layer 111. After that, photolithography A resist mask is formed on the semiconductor film using methods such as etching, and unwanted parts of the semiconductor film are etched. It is removed by [a specific method]. After that, by removing the resist mask, the island-shaped semiconductor layer 102 This can be formed (Figure 2(B)).

[0085] Semiconductor film deposition can be performed using sputtering, CVD, MBE, ALD, or PLD. Methods such as the sol-gel method, spray method, or mist method can be used for liquid materials. Thin film formation techniques using materials can also be employed. For semiconductor film deposition, sputtering is used. It is preferable to use the following sputtering methods: RF sputtering method, DC sputtering method. Sputtering and AC sputtering methods can be used. In particular, the slag generated during film formation DC sputtering is used because it can reduce dust and also ensure a uniform film thickness distribution. It is preferable.

[0086] After deposition of the semiconductor film, heat treatment may be performed. The heat treatment temperature should be between 250°C and 650°C. Preferably at a temperature of 300°C to 500°C, in an inert gas atmosphere, with an oxidizing gas added. The process should be carried out in an atmosphere containing ppm or more, or under reduced pressure. After heat treatment in an oxidizing gas atmosphere, an oxidizing gas of 10 ppm or less is added to replenish the desorbed oxygen. It may be carried out in an atmosphere including the above. By heat treatment, the semiconductor film is removed from the first protective insulating layer 111. Alternatively, oxygen is supplied to the semiconductor layer 102, and in the oxide semiconductor contained in the semiconductor layer 102 Oxygen deficiency can be reduced. Note that the heat treatment may be performed immediately after the semiconductor film is formed. This may also be done after processing a semiconductor film to form island-shaped semiconductor layers 102.

[0087] The light used to form the resist mask is, for example, i-line (wavelength 365 nm) and g-line (wavelength 43 nm). Light can be used that emits 6nm light, h-line light (wavelength 405nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, or ArF laser light can also be used. Alternatively, exposure may be performed using immersion lithography. Furthermore, the light used for exposure may be extreme ultraviolet light. Light (EUV: Extreme Ultra-violet) or X-rays may also be used. Alternatively, an electron beam can be used instead of the light used for exposure. Extreme ultraviolet light, X-rays or Using an electron beam is preferable because it enables extremely fine processing. When exposure is performed by scanning a beam, such as those mentioned above, a photomask is not required.

[0088] Here, as shown in Figure 2(B), the first protective insulating layer 111 during etching of the semiconductor film In some cases, a portion of it may be etched, resulting in a thin film in a region that does not overlap with the semiconductor layer 102. The first protective insulating layer 111 around the semiconductor layer 102 is above the lower surface of the conductor layer 102. As the surface becomes lower, the gate electrode 105 that is formed later will be on the side surface of the semiconductor layer 102 The lower part can be enclosed. As a result, the gate extends to the lower part of the side surface of the semiconductor layer 102. The electric field applied by electrode 105 is sufficient to increase the on-current of transistor 100. This can be done. Similarly, as shown in Figure 26, the gate electrode 10 is lower than the bottom surface of the semiconductor layer 102. Etching a portion of the first protective insulating layer 111 so that the lower surface of 5 is lower results in more traction This is preferable because it allows for an increase in the on-current of the inverter 100.

[0089] Furthermore, the material used for the first protective insulating layer 111 and the etching conditions for the semiconductor film may also affect the results. In some cases, the first protective insulating layer 111 may not be etched. 2 is preferable because it improves the coverage of the film formed on the surface.

[0090] Furthermore, as shown in Figure 2(B), the semiconductor layer 102 has a gently curved surface at its upper corner. It is preferable to process it in such a way. In particular, when the semiconductor layer 102 is finely processed, It often takes on a shape like this. By making the semiconductor layer 102 have this shape, Because the coverage of the film provided on top is improved, the variation in the electrical characteristics of transistor 100 This is preferable because it can suppress fluctuations.

[0091] [Formation of a pair of electrodes] Next, a conductive film is formed on the first protective insulating layer 111 and the semiconductor layer 102. A resist mask is formed on a conductive film using photolithography or other methods, eliminating the need for a conductive film. The portion is removed by etching. Then, by removing the resist mask, a pair Electrode 103 can be formed (Figure 2(C)).

[0092] Conductive films can be formed by methods such as sputtering, vapor deposition, and CVD. ru.

[0093] Here, as shown in Figure 2(C), during etching of the conductive film, the upper part of the semiconductor layer 102 Some parts may be etched, and the areas that do not overlap with the pair of electrodes 103 may become thin. Therefore, the thickness of the semiconductor film that will become the semiconductor layer 102 is determined by considering the etching depth. It is preferable to form it thickly.

[0094] Furthermore, although not explicitly shown in the diagram, the first preservation process also occurs during etching of the conductive film, similar to the above. A portion of the protective insulating layer 111 may be etched and thinned.

[0095] [Formation of gate insulating layer and gate terminal] Next, an insulating film is formed on the semiconductor layer 102, the pair of electrodes 103, and the first protective insulating layer 111. A film is formed. Furthermore, a conductive film is deposited on the insulating film. After that, photolithography or similar methods are used. A resist mask is formed on the conductive film using this method, and unwanted parts of the conductive film and insulating film are etched. Removed by [method]. Then, by removing the resist mask, the gate electrode 105 and A gate insulating layer 104 can be formed (Figure 2(D)).

[0096] The insulating film that forms the gate insulating layer 104 is produced by sputtering, CVD, MBE, or ALD. It can be formed using methods such as CVD or PLD. In particular, the insulating film can be formed using CVD or PLD. Alternatively, deposition by plasma CVD can improve coverage, making it preferable. It seems so.

[0097] Furthermore, the conductive film that forms the gate electrode 105 can be produced by, for example, sputtering, evaporation, or CVD. The film can be formed by methods such as the above.

[0098] In this case, the gate insulating layer 104 is etched simultaneously with the formation of the gate electrode 105. When processing the gate insulating layer 104 to have the same upper surface shape as the gate electrode 105, I will now explain, but the gate insulating layer 104 extends outward beyond the gate electrode 105. Each part may be processed individually to achieve the desired top surface shape. Note that in this case, photolithography may be used. Examples of exposure masks used in methods such as roughing include gray tone masks and halftone masks. Using a multi-tone mask is preferable because it simplifies the process.

[0099] [Formation of the second protective insulating layer] Next, the first protective insulating layer 111, the pair of electrodes 103, the gate insulating layer 104, and the gate A second protective insulating layer 112 is formed on the electrode 105 (Figure 2(E)).

[0100] The second protective insulating layer 112 is formed in the same manner as the first protective insulating layer 111. It is possible.

[0101] Here, the second protective insulating layer 112 is provided with a pair of electrodes 103 and a gate electrode 105. In areas that are not covered, it is provided so as to be in contact with the first protective insulating layer 111. Therefore, The semiconductor layer 102 is surrounded by a first protective insulating layer 111 and a second protective insulating layer 112. It is possible.

[0102] By following the above steps, transistor 100 can be manufactured.

[0103] [Heat treatment] After the formation of the second protective insulating layer 112, a heat treatment may be performed. The heat treatment will remove the first Oxygen is supplied to the semiconductor layer 102 from the protective insulating layer 111 and the second protective insulating layer 112. This reduces oxygen vacancies in the semiconductor layer 102. Also, at this time, the first protective insulation The edge layer 111 and the second protective insulating layer 112 suppress the release of oxygen from the semiconductor layer 102. This can control and suppress the formation of oxygen vacancies in the semiconductor layer 102.

[0104] The above is an explanation of an example of the manufacturing process for transistor 100.

[0105] [Modified version of Configuration Example 1] The following describes a transistor whose configuration differs in part from the transistor exemplified in Configuration Example 1 above. This section explains an example of its configuration. Note that explanations of parts that overlap with the above will be omitted, and the differences will be explained. We will explain in detail only the following. Also, even if the components have different positions or shapes, their function If they are identical, the same code may be assigned, and the explanation may be omitted.

[0106] [Variation 1] Figures 3(A) and (B) show schematic cross-sectional diagrams of the transistors illustrated below. A schematic diagram can be found in Figure 1(A). The transistor shown in Figure 3 mainly consists of semiconductor layer 102 and It differs in that it has an insulating layer 106 between it and the first protective insulating layer 111.

[0107] The insulating layer 106 provided below the semiconductor layer 102 is made of a material that releases oxygen when heated. It is preferable to include an oxide insulating material. An insulating layer 106 is provided below the semiconductor layer 102. Therefore, the heat generated during the heating process in the transistor manufacturing process causes more oxygen to be absorbed by half. It becomes possible to supply to the conductive layer 102. Also, the structure includes an insulating layer 106 and a semiconductor layer 102. By surrounding the component with a first protective insulating layer 111 and a second protective insulating layer 112, Oxygen released from the insulating layer 106 is directed to the outside (substrate 101 side or second protective insulating layer 112 side). This suppresses the release of oxygen (upwards), allowing for a more effective supply of oxygen to the semiconductor layer 102. It is possible.

[0108] Furthermore, the insulating layer 106 can also be provided so as to cover the upper surface of the first protective insulating layer 111. However, as shown in Figure 3, the upper surface shapes of the semiconductor layer 102 and the insulating layer 106 are made to be approximately the same. Preferably, the processing is done using the same resist mask. As a result, the first protective insulating layer 111 and the second protective insulating layer 112 are connected to the gate electrode 105 and Because contact occurs in an area where the pair of electrodes 103 are not provided, the oxygen diffusion pathway is blocked, effectively Oxygen can be supplied to the semiconductor layer 102.

[0109] The insulating layer 106 is an oxide insulating film containing more oxygen than satisfies the stoichiometric composition. It is preferable to use an oxide insulating material containing more oxygen than the oxygen that satisfies the stoichiometric composition. When heated, some oxygen is removed from the membrane. Oxide insulating films containing these materials are analyzed by thermal desorption gas spectroscopy (TDS). In ion spectroscopy analysis, the amount of oxygen removed, converted to oxygen atoms, was 1 .0 × 10 18 atoms / cm 3 Preferably 3.0 × 10 20 atoms / cm 3 The above describes the oxide insulating film.

[0110] As the insulating layer 106, a silicon oxide film or a silicon oxide nitride film is applied by plasma CVD. When forming, silicon-containing sedimentary gases and oxidizing gases are used as raw material gases. This is preferable. Typical examples of silicon-containing sedimentary gases include silane, disilane, and tri Examples include silanes and silane fluorides. Oxidizing gases include oxygen, ozone, nitrous oxide, and dinitrate. Examples include nitric oxide.

[0111] For example, a substrate placed in the vacuum-evacuated processing chamber of a plasma CVD apparatus is subjected to temperatures of 180°C or higher. Maintain the temperature at 260°C or lower, more preferably 200°C to 240°C, and place the raw material gas in the processing chamber. By introducing a suction device, the pressure inside the processing chamber is set to 100 Pa or more and 250 Pa or less, more preferably. The pressure should be between 100 Pa and 200 Pa, and 0.17 W / cm² should be applied to the electrode installed in the processing chamber. 2 Below Upper 0.5W / cm 2 More preferably, 0.25 W / cm² 2 More than 0.35W / cm 2 Under the following conditions for supplying high-frequency power, a silicon oxide film or silicon oxide nitride film is formed. To accomplish.

[0112] As a film deposition condition, high-frequency power of the above power density is supplied in the processing chamber at the above pressure. As a result, the decomposition efficiency of the raw material gas in the plasma increases, oxygen radicals increase, and the acid of the raw material gas As the chemical reaction progresses, the oxygen content in the oxide insulating film becomes higher than the stoichiometric ratio. However, when the substrate temperature is at the above temperature, the bonding force between silicon and oxygen is weak, so heating Some of the oxygen is eliminated. As a result, it contains more oxygen than the oxygen required to satisfy the stoichiometric composition. Furthermore, an oxide insulating film can be formed in which some of the oxygen is desorbed by heating.

[0113] [Variation 2] Figure 4 shows an example in which a capacitive element 120 is formed adjacent to the transistor 100.

[0114] Capacitive element 120 is connected to one of the pair of electrodes 103 of transistor 100 and gate electrode 10 Between the electrode 125, which is formed by processing the same conductive film as 5, and the gate insulating layer 104, the same It has a dielectric layer 124 formed by processing an insulating film.

[0115] In this way, the capacitive element 120 is formed by processing the film used to fabricate the transistor 100. By doing so, the capacitor element 120 can be manufactured simultaneously with the transistor 100 without increasing the number of steps. It can be manufactured.

[0116] In Figure 4, one of the pair of electrodes 103 of transistor 100 is connected to the capacitive element 120. Although a configuration using one electrode has been shown, it is not limited to this, and one electrode of the capacitive element 120 As such, the same conductive film as the pair of electrodes 103 of the transistor 100 is processed to form a different An electrode such as the gate electrode 105, electrode 125, and gate insulating layer 1 may also be used. At least one of 04 and the dielectric layer 124 may be made into a continuous, integrated unit and used in common. .

[0117] Here, the material used for the insulating film constituting the gate insulating layer 104 and the dielectric layer 124 is For example, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, titanium oxide It is preferable to use high dielectric constant materials such as strontium titanate and barium titanate. It is also delicious. In addition, these materials include lantern, aluminum, yttrium, or tungsten. Metals such as ions, or materials containing oxides of these metals, may be used. The film may be used in a laminated form.

[0118] Further, it is preferable to use an oxide insulating film that contains more oxygen than oxygen satisfying the stoichiometric composition. By using such an insulating film, oxygen can be supplied from the gate insulating layer 104 to the semiconductor layer 102 by heat such as heat treatment in the manufacturing process of the transistor.

[0119] The above is the description of the modified example. <>

[0120] [Configuration Example 2] Hereinafter, a configuration example of a transistor having a configuration partially different from that of the above Configuration Example 1 and the like will be described. Note that the description may be omitted for parts overlapping with the above.

[0121] FIG. 5(A) shows a schematic top view of a transistor 200 illustrated in this configuration example. FIGS. 5(B) and 5(C) show schematic cross-sectional views taken along cutting lines E-F and G-H in FIG. 5(A), respectively. Note that some components are not explicitly shown in FIG. 5(A) for clarity.

[0122] The transistor 200 includes an insulating layer 207 having a groove provided on a substrate 201, a semiconductor layer 202 provided on the insulating layer 207 and provided so as to fill the groove, a pair of electrodes 203 provided on the semiconductor layer 202 and electrically connected to the semiconductor layer 202, a gate insulating layer 204 located on the pair of electrodes 203 and overlapping the semiconductor layer 202, and a gate electrode 205 located on the gate insulating layer 204 and overlapping the semiconductor layer 202.

[0123] How Further, a first protective insulating layer 211 is provided below the semiconductor layer 202 so as to cover the side surface and the bottom surface of the groove of the insulating layer 207. The first protective insulating layer 211 is as shown in FIG. 5 ​​​​​​​​​​​It is provided covering the upper surface in the region where grooves are not provided in the insulating layer 207. This is preferable. Also, a second protection covering the pair of electrodes 203 and gate electrode 205. An insulating layer 212 is provided. Furthermore, a first protective insulating layer 211 and a second protective insulating layer 21 2 is a region where a pair of electrodes 203 and gate electrode 205 are not provided, It is located adjacent to the [unclear].

[0124] The semiconductor layer 202, the pair of electrodes 203, the gate insulating layer 204, the gate electrode 205, etc. Each of the semiconductor layer 102, pair of electrodes 103, gate insulating layer 104, and gate in configuration example 1 The same material as that used for electrode 105 can be used. Also, the first protective insulating layer 211 and The second protective insulating layer 212 is the first protective insulating layer 111 and the second protective layer in Configuration Example 1. The same material as that used for the insulating layer 112 can be used.

[0125] The first protective insulating layer 211 covers the side and bottom surfaces of the grooves provided in the insulating layer 207. A semiconductor layer 202 is provided and further embedded in the groove. The side and bottom surfaces of the body layer 202 are surrounded by the first protective insulating layer 211. Therefore, the diffusion of impurities such as hydrogen from the insulating layer 207 to the semiconductor layer 202 is suppressed. In both cases, the release of oxygen from the semiconductor layer 202 toward the insulating layer 207 is suppressed. It will be done.

[0126] Furthermore, by adjusting the depth of the groove, the thickness of the semiconductor layer 202 can be increased. This increases the on-current of transistor 200 and improves the source-drain breakdown voltage. This becomes easier. For example, when a thick semiconductor layer is formed on a flat surface, the upper layer is provided The film may have difficulty covering the semiconductor layer, and the film may be broken or a low-density region may be formed in the film. On the other hand, in this configuration example, the semiconductor layer 202 is provided so as to fill the groove portion, and the height of the upper surface thereof and the height of the upper surface of the first protective insulating layer 211 are formed to be substantially the same. Therefore, the semiconductor layer 202 can be formed thick without adversely affecting the covering property of the film provided in the upper layer thereof. This is the end of the description of the configuration example of the transistor 200. The above is the description of the configuration example of the transistor 200. The above is the description of the configuration example of the transistor 200. The above is the description of the configuration example of the transistor 200.

[0127] The above is the description of the configuration example of the transistor 200.

[0128] [Fabrication Method Example 2] Hereinafter, an example of the manufacturing method of the transistor 200 illustrated in FIG. 5 will be described with reference to the drawings. FIG. 6 is a schematic cross-sectional view in each step of the manufacturing method illustrated below. The above is the description of the configuration example of the transistor 200.

[0129] [Formation of Insulating Layer] First, an insulating layer 207 is formed on the substrate 201.

[0130] The insulating layer 207 can be formed by a sputtering method, a CVD method, an evaporation method, or the like. The insulating layer 207 can be formed by a sputtering method, a CVD method, an evaporation method, or the like.

[0131] As the insulating layer 207, an insulating material such as silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc. can be used. As the insulating layer 207, an insulating material such as silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc. can be used. As the insulating layer 207, an insulating material such as silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc. can be used. As the insulating layer 207, an insulating material such as silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc. can be used.

[0132] Also, as the insulating layer 207, a film made of different insulating materials may be laminated and used. By forming the insulating layer 207 into a laminated structure, the film provided below can be protected from the etching during the formation of the groove portion in the later step. By forming the insulating layer 207 into a laminated structure, the film provided below can be protected from the etching during the formation of the groove portion in the later step. It can function as a sliding stopper.

[0133] [Formation of grooves] Next, a resist mask is formed on the insulating layer 207 using a photolithography method or the like. The upper part of the insulating layer 207 is removed by etching. Then the resist mask is removed. This allows grooves to be formed in the insulating layer 207.

[0134] Here, as described above, by making the insulating layer 207 a multilayer structure made of different materials, This makes etching easier. Furthermore, etching the layer provided below Using it as a topping is preferable because it allows the bottom surface of the groove to be made flat.

[0135] Furthermore, if the groove depth is made deeper, the resist mask will disappear during the etching process. There is a risk of loss. In that case, etching occurs during the etching of the insulating layer 207. Thin film made of a material that is difficult to work with (i.e., a material with a high selectivity ratio for the insulating layer 207 relative to the thin film) A thin film is formed in advance, and then etched using a resist mask. After that, the thin film is hard The grooves may be formed by etching the upper part of the insulating layer 207 using it as a mask. i. If the thin film used as a hard mask is insulating, after forming the grooves, the hard mask It is acceptable to leave it as is.

[0136] [Formation of the first protective insulating layer] Next, a first protective insulating layer 21 is applied on the insulating layer 207 so as to cover the sides and bottom of the groove. Forms 1 (Figure 6(A)).

[0137] The deposition of the first protective insulating layer 211 is the same as that of the first protective insulating layer 111 in manufacturing method example 1. To form in a certain way.

[0138] [Formation of semiconductor layer] Next, a semiconductor film is formed on the first protective insulating layer 211. The grooves are then filled with the semiconductor film. When fully embedded, the height of the upper surface of the portion overlapping with the groove of the semiconductor film is the height of the first protective insulating layer. It is preferable to deposit the film so that its height is equal to or greater than the height of the portion that does not overlap with the groove portion of 211. It's nice.

[0139] The semiconductor film can be deposited in the same manner as in Example 1 of the above manufacturing method.

[0140] After the semiconductor film is formed, a heat treatment may be performed. The heat treatment may be carried out in the same manner as in Example 1 of the manufacturing method described above. This can be done. By heat treatment, the semiconductor film (or semiconductor) is removed from the first protective insulating layer 211. Oxygen is supplied to layer 202, reducing oxygen vacancies in the oxide semiconductor contained in semiconductor layer 202. It can be reduced. Note that the heat treatment may be performed immediately after the semiconductor film is formed, or after the semiconductor film is added. This may be done after forming island-shaped semiconductor layers 202.

[0141] Next, a planarization process is performed so that the upper surface of the semiconductor film overlaps with the groove of the first protective insulating layer 211. By machining it to match the upper surface of the missing part, island-shaped semiconductors are embedded in the groove. Layer 202 can be formed (Figure 6(B)).

[0142] For example, a planarization process can be performed using CMP (Chemical Mechanical Po Polishing or etching processes such as lishing can be used.

[0143] Here, aluminum oxide or the like is used as the first protective insulating layer 211, and a planarization treatment is performed. When polishing treatments such as CMP are used, the first protective insulating layer 211 is etched with an etching stopper. This allows it to function. Therefore, the thickness of the semiconductor layer 202 is reduced by the planarization process. This can suppress the thinning process and also reduce variations in thickness.

[0144] [Formation of a pair of electrodes] Next, a conductive film is formed on the first protective insulating layer 211 and the semiconductor layer 202. A resist mask is formed on a conductive film using photolithography or other methods, eliminating the need for a conductive film. The portion is removed by etching. Then, by removing the resist mask, a pair Electrode 203 can be formed (Figure 6(C)).

[0145] Conductive films can be formed by methods such as sputtering, vapor deposition, and CVD. ru.

[0146] Here, as shown in Figure 6(C), during etching of the conductive film, the upper part of the semiconductor layer 202 Some parts may be etched, and the areas that do not overlap with the pair of electrodes 203 may become thin. Therefore, the thickness of the semiconductor film that will become the semiconductor layer 202 (i.e., the depth of the groove) is determined by etching. It is preferable to form it thickly in advance, taking into account the depth to which it will be inserted.

[0147] Also, although not explicitly shown in the diagram, during etching of the conductive film, a portion of the first protective insulating layer 211 is also affected. It can also be etched and become a thin film.

[0148] [Formation of gate insulating layer and gate terminal] Next, an insulating film is formed on the semiconductor layer 202, the pair of electrodes 203, and the first protective insulating layer 211. A film is formed. Furthermore, a conductive film is deposited on the insulating film. After that, a photolithography method is used. Then, a resist mask is formed on the conductive film, and unnecessary parts of the conductive film and insulating film are etched. It is removed by the following. Then, by removing the resist mask, the gate electrode 205 and A gate insulating layer 204 can be formed (Figure 6(D)).

[0149] The insulating film that forms the gate insulating layer 204 and the conductive film that forms the gate electrode 205 are as shown in the example of the above manufacturing method. It can be formed by the same method as in 1.

[0150] In this case, the gate insulating layer 204 is etched simultaneously with the formation of the gate electrode 205. When processing the gate insulating layer 204 to have the same upper surface shape as the gate electrode 205, I will now explain, but the gate insulating layer 204 extends outward beyond the gate electrode 205. Each part may be processed individually to achieve the desired top surface shape. Note that in this case, photolithography may be used. Examples of exposure masks used in methods such as roughing include gray tone masks and halftone masks. Using a multi-tone mask is preferable because it simplifies the process.

[0151] [Formation of the second protective insulating layer] Next, the first protective insulating layer 211, the pair of electrodes 203, the gate insulating layer 204, and the gate A second protective insulating layer 212 is formed on the electrode 205 (Figure 6(E)).

[0152] The second protective insulating layer 212 is formed in the same manner as the first protective insulating layer 211. It is possible.

[0153] Here, the second protective insulating layer 212 is provided with a pair of electrodes 203 and a gate electrode 205. In areas that are not covered, it is provided so as to be in contact with the first protective insulating layer 211. Therefore, The semiconductor layer 202 is surrounded by a first protective insulating layer 211 and a second protective insulating layer 212. It is possible.

[0154] By following the above steps, transistor 200 can be manufactured.

[0155] [Heat treatment] After the formation of the second protective insulating layer 212, a heat treatment may be performed. The heat treatment will cause the first Oxygen is supplied to the semiconductor layer 202 from the protective insulating layer 211 and the second protective insulating layer 212. This reduces oxygen vacancies in the semiconductor layer 202. Also, at this time, the first protective insulation The edge layer 211 and the second protective insulating layer 212 suppress the release of oxygen from the semiconductor layer 202. This can control and suppress the formation of oxygen vacancies in the semiconductor layer 202.

[0156] The above is an explanation of an example of the manufacturing process for transistor 200.

[0157] [Modified version of Configuration Example 2] The following describes a transistor whose configuration differs in part from the transistor exemplified in Configuration Example 2 above. This section explains an example of its configuration. Note that explanations of parts that overlap with the above will be omitted, and the differences will be explained. We will explain in detail only the following. Also, even if the components have different positions or shapes, their function If they are identical, the same code may be assigned, and the explanation may be omitted.

[0158] [Variation 1] Figures 7(A) and (B) show schematic cross-sectional diagrams of the transistors illustrated below. A schematic diagram can be found in Figure 5(A). The transistor shown in Figure 7 mainly consists of semiconductor layer 202 and It differs in that it has an insulating layer 206 between it and the first protective insulating layer 211.

[0159] In the grooves provided in the insulating layer 207, the insulating layer 206 is the first protective insulating layer 211 It is provided covering the sides and top. The insulating layer 206 is also provided covering the sides of the semiconductor layer 202. It is provided to cover the lower surface.

[0160] The insulating layer 206 provided below the semiconductor layer 202 is made of a material that releases oxygen when heated. It is preferable to include an oxide insulating material. An insulating layer 206 is provided below the semiconductor layer 202. Therefore, the heat generated during the heating process in the transistor manufacturing process causes more oxygen to be absorbed by half. It becomes possible to supply to the conductive layer 202. Also, a structure including an insulating layer 206 and a semiconductor layer 202 By surrounding the component with a first protective insulating layer 211 and a second protective insulating layer 212, Oxygen released from insulating layer 206 to the outside (towards insulating layer 207 or second protective insulating layer 212) This suppresses the release of oxygen (above) and more effectively supplies oxygen to the semiconductor layer 202. It is possible.

[0161] Furthermore, the insulating layer 206 also covers the upper surface of the region of the first protective insulating layer 211 that does not overlap with the groove. It can be installed in this way, but it is processed by a flattening treatment so that it is installed on the inside of the groove. It is preferable that the first protective insulating layer 211 and the second The protective insulating layer 212 is in contact with the region where the gate electrode 205 and the pair of electrodes 203 are not provided. Therefore, the oxygen diffusion pathway is blocked, and oxygen can be effectively supplied to the semiconductor layer 202. Cut.

[0162] The insulating layer 206, like the insulating layer 106, contains more oxygen than satisfies the stoichiometric composition. It is preferable to use an oxide insulating film containing oxygen.

[0163] [Variation 2] Figure 8 shows an example in which a capacitive element 220 is formed adjacent to the transistor 200.

[0164] The capacitive element 220 connects to one of the pair of electrodes 203 of the transistor 200 and the gate electrode 20 Between the electrode 225, which is formed by processing the same conductive film as 5, and the gate insulating layer 204, the same It has a dielectric layer 224 formed by processing an insulating film.

[0165] In this way, the capacitive element 220 is formed by processing the film used to fabricate the transistor 200. By doing so, the capacitor element 220 can be manufactured simultaneously with the transistor 200 without increasing the number of steps. It can be manufactured.

[0166] In Figure 8, one of the pair of electrodes 203 of transistor 200 is connected to the capacitive element 220. Although a configuration using one side has been shown, it is not limited to this, and one electrode of the capacitive element 220 can be used as , different electrodes formed by processing the same conductive film as the pair of electrodes 203 of transistor 200 A electrode may also be used. In addition, the gate electrode 205 and the electrode 225, and the gate insulating layer 204 and At least one of the dielectric layers 224 may be made into a continuous, integrated unit and used in common.

[0167] Here, the material used for the insulating film constituting the gate insulating layer 204 and the dielectric layer 224 is For example, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, titanium oxide It is preferable to use high dielectric constant materials such as strontium titanate and barium titanate. It is also delicious. In addition, these materials include lantern, aluminum, yttrium, or tungsten. Metals such as ions, or materials containing oxides of these metals, may be used. The film may be used in a laminated form.

[0168] Furthermore, the insulating film is an oxide insulating film containing more oxygen than satisfactorily satisfying the stoichiometric composition. It is preferable to use a film. By using such an insulating film, the transistor fabrication process Due to the heat generated during internal heat treatment, oxygen is transferred from the gate insulating layer 204 to the semiconductor layer 202. It can be supplied.

[0169] [Variation 3] When multiple transistors are placed on a substrate, one groove is provided for each transistor. Instead of providing a groove for multiple transistors, the configuration is designed to provide a single groove for each transistor. This allows for higher density integration of transistors.

[0170] As an example, Figure 9 shows the case where four transistors 200 are connected in series. In the field where four transistors 200 are formed on the upper part of one groove provided in the insulating layer 207 This shows the relationship. Figure 9(A) is a schematic top view, and Figure 9(B) shows the cutting line in Figure 9(A). This is a schematic cross-sectional view of an IJ (Injection Jet).

[0171] As shown in Figure 9(B), there are four tigers on the upper part of one groove formed in the insulating layer 207 A transistor 200 is formed. In addition, in two adjacent transistors 200, Because a common electrode 203 is provided, the two transistors 200 are connected in series. It is continued. On the other hand, the gate electrode 205 is provided independently for each transistor 200. It is.

[0172] The first protective insulating layer 211 and the second protective insulating layer 212 are connected by electrodes 203 provided at both ends. It is positioned to make contact in the outer region and surround the four transistors 200.

[0173] An example of a circuit configuration to which such series-connected transistors 200 can be applied is shown in Figure 9. As shown in C). The circuit shown in Figure 9(C) has four transistors and three capacitive elements. In two touching transistors, if the source or drain of one transistor is connected to the other transistor... The source or drain of one transistor is electrically connected to form a node, and the node One electrode of the capacitive element is electrically connected to the dot.

[0174] For example, the capacitive element can be configured to be the same as the capacitive element 220 exemplified in the above modified example 2. Cut.

[0175] The circuit shown in Figure 9(C) can be used, for example, as a shift register by applying the following potential. It can be made to function as such.

[0176] A common potential is applied to the other electrode of each of the three capacitive elements. Also, four Of the transistors in the transistors, the gates of the first and third transistors from the left have the same clock signal. Given clock signal (CLK1), the gates of the second and fourth transistors are connected to the same clock signal. A signal (CLK2) is applied. Also, one of the sources or drains of the first transistor... The input terminal to which the input potential (IN) is applied, the source or drain of the fourth transistor One of the inputs is designated as the output terminal where the output potential (OUT) is output. These are designated as CLK1 and CLK2. Then, the potentials that turn the transistors on alternately without overlap (for example, high By using a clock signal that results in a level potential, the potential applied to the input terminal can be controlled. The information can be shifted from left to right.

[0177] Furthermore, the configuration shown in Figure 9(D) is a configuration in which multiple readouts are connected in series to the circuit in Figure 9(C). This configuration includes the addition of transistor 260. Each of the transistors 260 is a capacitive element. It is electrically connected to the node of one electrode. Also, the other electrode of each capacitive element is A readout potential is applied. With this configuration, the circuit shown in Figure 9(D) The potential information held at the node to which one electrode of the capacitive element is connected can be read out at any time. It can function as a NAND-type memory device. Here, for example, transistor 26 0 can also be a transistor using an oxide semiconductor, similar to transistor 200. Furthermore, as illustrated in the following embodiments, transistors to which different semiconductors are applied are used. It's okay to be there.

[0178] The above is an explanation of the variations.

[0179] This embodiment may be implemented in appropriate combination with other embodiments described herein. It is possible.

[0180] (Embodiment 2) In this embodiment, the transistor has a configuration that differs in some respects from the transistor exemplified in Embodiment 1. This section describes an example of a generator configuration. Note that explanations of parts that overlap with the above will be omitted. Furthermore, we will only explain the differences in detail. Also, even if the components differ in position or shape If the functions are identical, the same code may be assigned, and the explanation may be omitted.

[0181] A semiconductor device according to one aspect of the present invention comprises an oxide semiconductor layer and a gate that overlaps the oxide semiconductor layer. Between the insulating layer and the protective insulating layer, at least one of the metal elements constituting the oxide semiconductor layer It is preferable to have an oxide layer containing one metal element as a constituent element. A trap level is formed at the interface between the material semiconductor layer and the insulating layer overlapping the oxide semiconductor layer. Because this can be suppressed, the degradation of the transistor's electrical characteristics can be suppressed. .

[0182] In other words, one aspect of the present invention is that at least the upper and lower surfaces of the oxide semiconductor layer are oxide semiconductor Covered by an oxide layer that functions as a barrier film to prevent the formation of interfacial states between layers, The top and side surfaces of the oxide semiconductor layer in the width direction of the gate are connected to the gate electrode via the gate insulating layer. The oxide semiconductor layer is thus covered and an insulating layer containing an aluminum oxide film encloses it. It is more preferable to have a configuration that includes this. With such a configuration, the oxide semiconductor layer To suppress the generation of oxygen vacancies and the incorporation of impurities, which are factors in carrier generation, at the intermediate and interface. This makes it possible to make the oxide semiconductor layer highly pure and intrinsic. "Conversion" refers to making an oxide semiconductor layer intrinsically or substantially intrinsically. Therefore, the oxidation This invention suppresses fluctuations in the electrical characteristics of transistors containing a semiconductor layer, thereby providing highly reliable semiconductor devices. It will become possible to provide it.

[0183] In this specification, when we refer to something as substantially intrinsic, the carrier density of the oxide semiconductor layer is , 1 x 10 17 / cm 3 Less than 1 × 10 15 / cm 3 Less than, or 1 × 10⁻⁶ 13 / cm 3 It is less than. By making the oxide semiconductor layer highly pure and intrinsic, the transistor has stable electrical properties. It is possible to assign gender to it.

[0184] More specifically, the configuration can be as follows:

[0185] [Configuration Example 1] Figures 10(A) and (B) show schematic cross-sectional views of the transistor 150 exemplified below. Oh, for the top schematic diagram, Figure 1(A) can be used. Transistor 150 shown in Figure 10 The embodiment mainly has a first oxide layer 151 and a second oxide layer 152. This differs from the transistor 100 exemplified in state 1.

[0186] The first oxide layer 151 is provided between the first protective insulating layer 111 and the semiconductor layer 102. Furthermore, the second oxide layer 152 is provided between the semiconductor layer 102 and the gate insulating layer 104. It's being kicked.

[0187] More specifically, the second oxide layer 152 has its upper surface on the lower surface of the pair of electrodes 103, and It is provided in contact with the lower surface of the gate insulating layer 104.

[0188] The first oxide layer 151 and the second oxide layer 152 are identical to the semiconductor layer 102. It contains oxides that include one or more of the following metallic elements.

[0189] Furthermore, the boundary between the semiconductor layer 102 and the first oxide layer 151, or between the semiconductor layer 102 and the second The boundary with the oxide layer 152 may be unclear.

[0190] For example, the first oxide layer 151 and the second oxide layer 152 contain In or Ga. Typical examples include In-Ga oxides, In-Zn oxides, and In-M-Zn oxides. M is Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf, and is a semiconductor layer. Materials are used in which the energy at the lower end of the conduction band is closer to the vacuum level than 10². Typically, the first The energy at the lower end of the conduction band of the first oxide layer 151 or the second oxide layer 152, and the semiconductor The energy difference from the lower end of the conduction band in layer 102 is 0.05 eV or more, 0.07 eV or more, 0.1eV or higher, or 0.15eV or higher and 2eV or lower, 1eV or lower, 0.5eV or lower It is preferable to set it to below or 0.4 eV or less.

[0191] A first oxide layer 151 and a second oxide layer 1 are provided so as to sandwich the semiconductor layer 102. 52 contains an oxide with a higher Ga content that functions as a stabilizer compared to semiconductor layer 102. By using this method, the release of oxygen from the semiconductor layer 102 can be suppressed.

[0192] For the semiconductor layer 102, for example, atoms in In:Ga:Zn = 1:1:1 or 3:1:2 When using a numerical ratio of In-Ga-Zn oxides, the first oxide layer 151 or the second oxide For material layer 152, for example, In:Ga:Zn = 1:3:2, 1:3:4, 1:3:6, 1 In-Ga- Zn-based oxides can be used. Furthermore, the semiconductor layer 102, the first oxide layer 151 and The atomic ratios of the first and second oxide layers 152 are, respectively, plus or minus the above atomic ratios as an error. Includes a 20% variation in eggplant. Also, the first oxide layer 151 and the second oxide layer 152 have a composition The same materials may be used, or materials with different compositions may be used.

[0193] Furthermore, when an In-M-Zn oxide is used as the semiconductor layer 102, the semiconductor layer 102 and The target used to form the semiconductor film is the metal element contained in the target. When the atomic ratio is In:M:Zn=x1:y1:z1, the value of x1 / y1 is less than 1 / 3. The upper limit is 6 or less, preferably 1 or more and 6 or less, and z1 / y1 is 1 / 3 or more and 6 or less, preferably It is preferable to use an oxide having an atomic ratio of 1 or more and 6 or less. Note that by setting z1 / y1 to 6 or less, it becomes easier to form the CAAC-OS film described later. Representative examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:1:1, 3:1:2, and the like.

[0194] Further, when an In-M-Zn-based oxide is used as the first oxide layer 151 and the second oxide layer 152, for forming the oxide films that become the first oxide layer 151 and the second oxide layer 152, the target used has an atomic ratio of the metal elements contained in the target of In:M:Zn = x2:y2:z2. When this is the case, x2 / y2 < x1 / y1, and it is preferable to use an oxide having an atomic ratio where the value of z2 / y2 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less. Note that by setting z2 / y2 to 6 or less, it becomes easier to form the CAAC-OS film described later. Representative examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:3:4, 1:3:6, 1:3:8, and the like.

[0195] Further, by using a material in the first oxide layer 151 and the second oxide layer 152 whose energy at the lower end of the conduction band is closer to the vacuum level than that of the semiconductor layer 102, a channel is mainly formed in the semiconductor layer 102, and the semiconductor layer 102 becomes the main current path. In this way, by sandwiching the semiconductor layer 102 in which the channel is formed with the first oxide layer 151 and the second oxide layer 152 containing the same metal element, the generation of these interface levels is suppressed, and the reliability in the electrical characteristics of the transistor is improved.

[0196] Note that it is not limited to these, and depending on the required semiconductor characteristics and electrical characteristics (field effect ​A suitable composition should be used depending on the fruit mobility, threshold voltage, etc. To obtain the semiconductor characteristics of the transistor, a semiconductor layer 102, a first oxide layer 151, and Carrier density, impurity concentration, defect density, and atomic ratio of metal elements to oxygen in oxide layer 152 of 2. It is preferable to ensure that the interatomic distance, density, etc., are appropriate.

[0197] Here, the thickness of the semiconductor layer 102 is formed to be at least thicker than the first oxide layer 151. It is preferable that the semiconductor layer 102 is thicker, the higher the on-current of the transistor can be. Yes, it is possible. In addition, the first oxide layer 151 has the effect of suppressing the generation of interface states in the semiconductor layer 102. The thickness should be such that the first oxide is not lost. For example, the thickness of the semiconductor layer 102 is such that the first oxide A thickness greater than 1x the thickness of layer 151, preferably 2x or more, and more preferably 4x or more. More preferably, it should be 6 times or more.

[0198] Furthermore, the second oxide layer 152, like the first oxide layer 151, is at the interface of the semiconductor layer 102. The thickness should be such that the effect of suppressing the formation of energy levels is not lost. For example, the first oxide The thickness of the second oxide layer 152 should be the same as or less than that of layer 151. If the second oxide layer 152 is thick, Because the electric field from electrode 105 may not reach the semiconductor layer 102 easily, the second acid It is preferable to form the oxide layer 152 thinly. However, it is not limited to this, and the second oxide layer 15 The thickness of 2 is determined considering the breakdown voltage of the gate insulating layer 104, and the voltage required to drive the transistor 150. You can adjust the settings as needed.

[0199] Furthermore, as shown in Figure 10(B), the periphery of the oxide layer 151 is lower than the lower surface of the oxide layer 151. The upper surface of the first protective insulating layer 111 in the enclosure is lowered, and the gate electrode 105 is connected to the semiconductor layer 102 It is preferable to have a configuration that surrounds the lower part of the side surface. As a result, the lower part of the side surface of the semiconductor layer 102 The electric field from the gate electrode 105 is sufficiently applied to this point, increasing the on-current of the transistor 150. It can be made larger. Similarly, as shown in Figure 27, the lower surface of the oxide layer 151 is larger than the gauge. Lowering the lower surface of electrode 105 will further increase the on-current of transistor 150. This is preferable because it allows for this.

[0200] Here, we will describe the band structure in the channel formation region of transistor 150. .

[0201] Figures 11(A) and (B) show the energy band structure in the thickness direction of the channel formation region. This is a schematic representation.

[0202] In Figures 11(A) and (B), EcI1, EcS1, EcS2, EcS3, EcI2 These are the first protective insulating layer 111, the first oxide layer 151, the semiconductor layer 102, and the second acid The energy at the lower end of the conduction band of the ionized layer 152 and the gate insulating layer 104 is schematically shown. For convenience, the thickness of each layer is not considered here.

[0203] Here, the difference between the energy of the vacuum level and the energy of the lower end of the conduction band (also called electron affinity) is the vacuum level The difference between the energy of the position and the energy of the upper end of the valence band (also called the ionization potential) is used to determine the energy This is the value after subtracting the gap. Note that the energy gap is calculated using a spectroscopic ellipsometer (for example). Measurement can be performed using the HORIBA JOBIN YVON UT-300. The energy difference between the vacant level and the upper end of the valence band is determined by ultraviolet photoelectron spectroscopy (UPS). iolet Photoelectron Spectroscopy) apparatus (e.g., P Measurements can be taken using HI's VersaProbe.

[0204] As shown in Figure 11(A), the first oxide layer 151, the semiconductor layer 102, and the second oxide layer At 152, the energy at the lower end of the conduction band changes continuously without any barriers between them. This is because the compositions of the first oxide layer 151, the semiconductor layer 102, and the second oxide layer 152 are similar. This allows oxygen to diffuse more easily between the two layers, forming a layer that could be called a mixed layer between them. I understand that it's for that reason.

[0205] Note that in Figure 11(A), the first oxide layer 151 and the second oxide layer 152 have similar energy We have shown the case where the oxide layer has an energy gap, but each has a different energy It is also acceptable for the oxide layer to have a G-gap. For example, EcS3 is better than EcS1. When the energy is high, part of the band structure is shown as in Figure 11(B). Although not shown in the diagram, it is acceptable for EcS1 to have a higher energy than EcS3.

[0206] From Figures 11(A) and (B), the semiconductor layer 102 in the channel formation region is a well. ) and it can be seen that a channel is formed in the semiconductor layer 102. Note that the first oxide layer 151, the semiconductor layer 102, and the second oxide layer 152 have continuous energy at the lower end of the conduction band. Because it is shaped in a specific way, it can also be called a U-shaped well. Channels formed in this configuration can also be called embedded channels.

[0207] The first oxide layer 151 and the second oxide layer 152 are metal elements that constitute the semiconductor layer 102. Since it is an oxide containing one or more elements, the first oxide layer 151, the semiconductor layer 102 and the second The laminated structure in which the oxide layers 152 are stacked is also called an oxide laminate with a common main component. (The following describes the stacking of the first oxide layer 151, semiconductor layer 102, and second oxide layer 152.) The layered structure is also referred to as an oxide layer. The layers are not simply stacked on top of each other, but rather continuous junctions (here, especially the energy at the lower end of the conduction band). The structure is designed to form a U-shaped well structure in which the temperature changes continuously between each layer. This is preferable because it forms defect levels such as trap centers and recombination centers at the interface of each layer. If impurities like these are present, the continuity of the energy bands is lost, and carriers are lost at the interface. This is because they disappear due to trapping or recombination.

[0208] To form continuous bonding, a multi-chamber type film deposition system equipped with a load lock chamber is required. Using a device (for example, a sputtering device), each layer is continuously laminated without being exposed to the atmosphere. It is preferable to do so. Each chamber in the sputtering apparatus is suitable for oxide semiconductors. To remove as much impurity as possible, such as water, an adsorption-type vacuum exhaust pump such as a cryopump is used. Using a pump to evacuate to a high vacuum (5 x 10 -7 Pa~1×10 -4 It is preferable to do so (up to about Pa). It seems so. Alternatively, you can combine a turbomolecular pump and a cold trap to remove air from the exhaust system. It is preferable to prevent gas from flowing back into the bar.

[0209] In order to obtain high-purity intrinsic oxide semiconductors, not only is the chamber evacuated to a high vacuum, but also... It is also necessary to increase the purity of the sputtering gas. Oxygen gas and argon gas used as sputtering gas. The dew point is -40°C or lower, preferably -80°C or lower, more preferably -100°C or lower. By using highly purified gas, the amount of moisture and other substances incorporated into the oxide semiconductor can be minimized. It can be prevented.

[0210] A first oxide layer 151 and a second oxide layer are provided above or below the semiconductor layer 102. Layer 152 functions as a barrier layer and is in contact with the oxide laminate (first protective insulating layer 111). The influence of trap levels formed at the interface between the gate insulating layer 104) and the oxide laminate is The main carrier path of the transistor extends to semiconductor layer 102. It can be suppressed.

[0211] For example, oxygen vacancies contained in a semiconductor layer are deep within the energy gap of an oxide semiconductor. It manifests as a localized level at an energy position. Carriers enter such a localized level. Because the reliability of the transistor decreases when trapped, oxygen contained in the semiconductor layer It is necessary to reduce defects. In oxide stacking, compared to semiconductor layer 102, acid By providing oxide layers that are less prone to elementary defects in contact with the top and bottom of the semiconductor layer 102, the semiconductor layer 1 Oxygen deficiency in 02 can be reduced. For example, the semiconductor layer 102 is a constant current measuring Measurement by the standard method (CPM: Constant Photocurrent Method) The absorption coefficient due to the defined localized level is 1 × 10 -3 Less than / cm, preferably 1 × 10 -4 / It can be less than 1 cm.

[0212] Furthermore, the semiconductor layer 102 is an insulating layer with different constituent elements (for example, an insulating layer containing a silicon oxide film). When in contact with another layer, an interface state is formed at the interface between the two layers, and this interface state forms a channel. This can happen. In such cases, a second transistor with a different threshold voltage appears, and the transistor The apparent threshold voltage of the inverter may fluctuate. However, in oxide layers In this case, the semiconductor layer 102 contains one or more metal elements and has a first oxide layer 151. Therefore, it is difficult to form interface states at the interface between the first oxide layer 151 and the semiconductor layer 102. Therefore, by providing the first oxide layer 151, the threshold voltage of the transistor can be reduced. This can reduce variations in electrical characteristics.

[0213] Furthermore, if a channel is formed at the interface between the gate insulating layer 104 and the semiconductor layer 102, Interfacial scattering occurs at the interface, reducing the field-effect mobility of the transistor. However, acid In the oxide layer, the second oxide contains one or more metal elements that constitute the semiconductor layer 102. Because it has layer 152, carriers are present at the interface between semiconductor layer 102 and second oxide layer 152. This reduces scattering of A and allows for a higher field-effect mobility of the transistor.

[0214] [Configuration Example 2] Figures 12(A) and (B) show schematic cross-sectional views of the transistor 160 exemplified below. Oh, for the top schematic view, Figure 1(A) can be used. Transistor 160 shown in Figure 12 It differs from the transistor 150 in that the shape of the second oxide layer 152 is different. Yes, they are.

[0215] In transistor 160, the second oxide layer 152 has a lower surface that faces a pair of electrodes 103 It is provided in contact with the upper surface of each of them. Furthermore, a pair of electrodes 103 is provided. In the region, it is provided in contact with the upper and side surfaces of the semiconductor layer 102.

[0216] In the configuration shown in Figure 12, the upper surface shapes of the second oxide layer 152 and the gate insulating layer 104 are The same photomask was used to process the gate electrode 105 so that its upper surface shape would roughly match that of the gate electrode 105. Furthermore, the second protective insulating layer 112 is the second oxide layer 152 and gate insulating layer. It is provided adjacent to each end of layer 104. By having this configuration, Acid from the semiconductor layer 102 through the edges of the second oxide layer 152 and the gate insulating layer 104 This can suppress the removal of elements.

[0217] Furthermore, as shown in Figure 12(B), the semiconductor layer 102 of the transistor 160 is on its upper surface Furthermore, the sides are also in contact with the second oxide layer 152. That is, the semiconductor layer The channel-forming region 102 is surrounded by the first oxide layer 151 and the second oxide layer 152. It is structured as follows.

[0218] With this configuration, the second oxide is provided in contact with the side surface of the semiconductor layer 102. The layer 152 can suppress the formation of interface states even on the side surface of the semiconductor layer 102. As a result, when actively using channels formed near the side surface of semiconductor layer 102, Even if present, it can suppress fluctuations in the electrical characteristics of the transistor, resulting in high on-current and high reliability. This makes it possible to create a transistor that is both reliable and high-performance.

[0219] Furthermore, as shown in Figure 12(B), the circumference of the oxide layer 151 is lower than the bottom surface of the oxide layer 151. The upper surface of the first protective insulating layer 111 in the enclosure is lowered, and the gate electrode 105 is connected to the semiconductor layer 102 It is preferable to have a configuration that surrounds the lower part of the side surface. As a result, the lower part of the side surface of the semiconductor layer 102 The electric field from gate electrode 105 is sufficiently applied to this point, increasing the on-current of transistor 160. It can be made larger. Similarly, as shown in Figure 28, the lower surface of the oxide layer 151 is larger than the gauge. Lowering the lower surface of electrode 105 will further increase the on-current of transistor 160. This is preferable because it allows for this.

[0220] Furthermore, by applying the insulating layer 106 that releases oxygen upon heating, as exemplified in Embodiment 1... It can also be done this way.

[0221] Figures 13(A) and (B) show a transistor 17 with a different configuration from the transistor 160 described above. A schematic cross-sectional view of point 0 is shown.

[0222] The transistor 170 is mainly located between the first oxide layer 151 and the first protective insulating layer 111. It differs from the transistor 160 in that it has an insulating layer 106.

[0223] As shown in Figures 13(A) and (B), the semiconductor layer 102, the first oxide layer 151, and The insulating layer 106 is processed into an island shape, and a second oxide layer 152 is provided to cover them, and further By providing the first protective insulating layer 111 on the lower side, the oxygen released by the insulating layer 106 is reduced This allows for effective supply to the semiconductor layer 102 via the first oxide layer 151.

[0224] Furthermore, as shown in Figure 13(B), the area around the insulating layer 106 is greater than the lower surface of the insulating layer 106. The upper surface of the first protective insulating layer 111 is lowered, and the gate electrode 105 is on the side of the semiconductor layer 102. It is preferable to have a configuration that surrounds the lower part of the surface. As a result, the lower part of the side surface of the semiconductor layer 102 The electric field applied by the gate electrode 105 is sufficient, increasing the on-current of the transistor 170. It can be done. Similarly, as shown in Figures 29(A)(B), the lower surface of the oxide layer 151 Lowering the lower surface of the gate electrode 105 further increases the on-current of the transistor 170. This is preferable because it allows for this.

[0225] Also, Figures 13(C) and (D) show a transistor with a configuration that differs in some respects from transistor 170. This shows a schematic cross-sectional view of transistor 180. Transistor 180 is not processed into an island shape. It has an insulating layer 106, a first oxide layer 151, and a second oxide layer 152. As the oxide layer 151 and the second oxide layer 152, a material with a sufficiently large band gap This configuration can be achieved by using [this method].

[0226] Furthermore, in the configuration of transistor 180, the insulating layer 106 is located in a region not shown in the diagram. The first oxide layer 151 and the second oxide layer 152 are etched, and the first protective insulation It is preferable to provide a region where the edge layer 111 and the second protective insulating layer 112 are in contact. Multiple transients are present in the region surrounded by the first protective insulating layer 111 and the second protective insulating layer 112. A configuration with a station is also acceptable.

[0227] Furthermore, as shown in Figure 13(D), the periphery of the semiconductor layer 102 is greater than the lower surface of the semiconductor layer 102. The upper surface of the first protective insulating layer 111 in the enclosure is lowered, and the gate electrode 105 is connected to the semiconductor layer 102 It is preferable to have a configuration that surrounds the lower part of the side surface. As a result, the lower part of the side surface of the semiconductor layer 102 The electric field from the gate electrode 105 is sufficiently applied to this point, increasing the on-current of the transistor 180. It can be enlarged. Similarly, as shown in Figures 29(C)(D), below the semiconductor layer 102 Lowering the lower surface of the gate electrode 105 below the surface will increase the on-current of the transistor 180. This is preferable because it allows for a larger size.

[0228] [Configuration Example 3] Figures 14(A) and (B) show schematic cross-sectional views of the transistor 250 exemplified below. Oh, for the top schematic view, Figure 1(A) can be used. Transistor 250 shown in Figure 14 The embodiment mainly has a first oxide layer 251 and a second oxide layer 252. This differs from transistor 200, which was exemplified in state 1.

[0229] The first oxide layer 251 is provided between the first protective insulating layer 211 and the semiconductor layer 202. Furthermore, the second oxide layer 252 is provided between the semiconductor layer 202 and the gate insulating layer 204. It's being kicked.

[0230] More specifically, in the grooves provided in the insulating layer 207, the first oxide layer 251 is It is provided covering the side and top surfaces of the protective insulating layer 211. Also, the first oxide layer 2 51 is provided in contact with the lower surface and side surface of the semiconductor layer 202.

[0231] Furthermore, the lower surface of the second oxide layer 252 is in contact with the upper surfaces of each of the pair of electrodes 203. It is provided as follows. Furthermore, in the region where the pair of electrodes 203 is not provided, semiconductor It is provided in contact with the upper surface of layer 202.

[0232] The first oxide layer 251 and the second oxide layer 252 are identical to the semiconductor layer 202. It contains oxides that include one or more of the following metallic elements.

[0233] Furthermore, the boundary between the semiconductor layer 202 and the first oxide layer 251, or between the semiconductor layer 202 and the second The boundary with the oxide layer 252 may be unclear.

[0234] For example, the first oxide layer 251 and the second oxide layer 252 are the first oxide layer. The same material as that used for layer 151 and the second oxide layer 152 can be used.

[0235] In the configuration shown in Figure 14, the upper surface shapes of the second oxide layer 252 and the gate insulating layer 204 are The same photomask was used to process the gate electrode 205 so that its upper surface shape would roughly match that of the gate electrode 205. Furthermore, the second protective insulating layer 212 is the second oxide layer 252 and gate insulating layer. It is provided adjacent to each end of layer 204. By using this configuration, Acid from the semiconductor layer 202 through the edges of the second oxide layer 252 and the gate insulating layer 204 This can suppress the removal of elements.

[0236] Furthermore, as shown in Figure 14(B), the semiconductor layer 202 of transistor 250 is on its lower surface Furthermore, the side surface is in contact with the first oxide layer 251, and the upper surface of the semiconductor layer 202 It is provided in contact with the second oxide layer 252. That is, the channel of the semiconductor layer 202 The formation region is surrounded by a first oxide layer 251 and a second oxide layer 252. .

[0237] With this configuration, in the channel formation region of the semiconductor layer 202, its surface The formation of interface states can be suppressed. Therefore, the variation in the electrical characteristics of the transistor can be reduced. This can be suppressed, enabling the realization of highly reliable transistors.

[0238] Here, the thickness of the semiconductor layer 202 is formed to be at least thicker than the first oxide layer 251. It is preferable that the semiconductor layer 202 is thicker, the higher the on-current of the transistor can be. Yes, it is possible. In addition, the first oxide layer 251 has the effect of suppressing the generation of interface states in the semiconductor layer 202. The thickness should be such that the first oxide is not lost. For example, the thickness of the semiconductor layer 202 is such that the first oxide A thickness greater than 1x the thickness of layer 251, preferably 2x or more, and more preferably 4x or more. More preferably, it should be 6 times or more.

[0239] Furthermore, the depth of the grooves provided in the insulating layer 207 is determined by the first protective insulating layer 211 and the first oxidation The settings should be adjusted appropriately, taking into account the processed thicknesses of the physical layer 251 and the semiconductor layer 202. Furthermore, the width of the groove is appropriately adjusted according to the channel length and channel width of the transistor 250. You just need to configure it.

[0240] Furthermore, the second oxide layer 252, like the first oxide layer 251, is at the interface of the semiconductor layer 202. The thickness should be such that the effect of suppressing the formation of energy levels is not lost. For example, the first oxide The thickness of the second oxide layer 252 should be equal to or less than that of layer 251. If the second oxide layer 252 is thick, Because the electric field from electrode 205 may not reach the semiconductor layer 202 easily, the second acid It is preferable to form the oxide layer 252 thinly. However, it is not limited to this, and the second oxide layer 25 The thickness of 2 is determined considering the breakdown voltage of the gate insulating layer 204, and the voltage used to drive the transistor 250. You can adjust the settings as needed.

[0241] Furthermore, the insulating layer 206 that releases oxygen upon heating, as exemplified in Modification 1 of Embodiment 1, It can also be applied.

[0242] Figures 14(C) and (D) show a transistor 27 with a different configuration from the transistor 250 described above. A schematic cross-sectional view of point 0 is shown.

[0243] The transistor 270 is mainly located between the first oxide layer 251 and the first protective insulating layer 211. In that it has an insulating layer 206 and a semiconductor layer 202 is provided covering the groove, It is different from the transistor 250.

[0244] In this way, by providing the first oxide layer 251 so as to fill the groove, the channel In the formation region, the physical distance between the semiconductor layer 202 and the insulating layer 206 can be increased. Yes, it is possible. Therefore, in the channel formation region, the interface formed at the interface of the semiconductor layer 202 The surface energy levels can be further reduced.

[0245] Figure 15 shows transistor 28, which has a different configuration from transistors 250 and 270 described above. This shows the case where 0 is connected in series. Transistor 280 is mainly the first oxide It differs from the transistor 270 in that layer 251 is provided covering the groove.

[0246] Thus, an insulating layer 206 is embedded in the groove, and a first oxide layer 251 and are placed on top of it. By providing a semiconductor layer 202, the volume of the insulating layer 206 can be easily increased. As a result, the amount of oxygen supplied to the semiconductor layer 202 can be increased. Therefore, with this configuration, no step is formed on the upper surface of the insulating layer 206, This does not reduce the coverage of the first oxide layer 251 and semiconductor layer 202 provided in the layer. This allows for the formation of a thicker insulating layer 206.

[0247] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0248] (Embodiment 3) In this embodiment, an oxide semiconductor suitable for use in a semiconductor device according to one aspect of the present invention is provided. Let's explain conductors.

[0249] Oxide semiconductors have a large energy gap of 3.0 eV or more, making oxide semiconductors suitable for An oxide semiconductor film obtained by processing under certain conditions and sufficiently reducing its carrier density is applied. In a transistor, the leakage current between the source and drain in the off state (off current) This can be made extremely low compared to conventional silicon-based transistors. .

[0250] Applicable oxide semiconductors include at least indium (In) or zinc (Zn). It is preferable that the oxide semiconductor contains ) and is particularly preferable that it contains In and Zn. As stabilizers to reduce variations in the electrical characteristics of transistors using these, In addition, gallium (Ga), tin (Sn), hafnium (Hf), and zirconium (Zr) Titanium (Ti), scandium (Sc), yttrium (Y), lanthanides (for example) One of the following is selected from cerium (Ce), neodymium (Nd), and gadolinium (Gd). It is preferable that multiple species are included.

[0251] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and in-Zn-based acids. compounds, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, Sn-Mg acids In-Mg oxides, In-Ga oxides, In-Ga-Zn oxides (IGZO (Also written as), In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga- Zn oxides, Al-Ga-Zn oxides, Sn-Al-Zn oxides, In-Hf-Z n-based oxides, In-Zr-Zn oxides, In-Ti-Zn oxides, In-Sc-Zn oxides In-Y-Zn oxides, In-La-Zn oxides, In-Ce-Zn oxides In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides Materials, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, In-Lu-Zn ​​oxides, I n-Sn-Ga-Zn oxides, In-Hf-Ga-Zn oxides, In-Al-Ga- Zn oxides, In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, I n-Hf-Al-Zn oxides can be used.

[0252] Here, an In-Ga-Zn oxide is an oxide having In, Ga, and Zn as its main components. It refers to the material itself, and the ratio of In, Ga, and Zn is irrelevant. Also, other than In, Ga, and Zn... It may contain metallic elements.

[0253] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0, and m is not an integer) Materials represented by ) may also be used. Note that M is selected from Ga, Fe, Mn, and Co. This refers to one or more metallic elements, or the elements used as stabilizers as described above. Also, as an oxide semiconductor, In2SnO5(ZnO) n (n > 0, and n is an integer) You may use the materials indicated as follows.

[0254] For example, In:Ga:Zn=1:1:1, In:Ga:Zn=1:3:2, In:Ga :Zn=1:3:4, In:Ga:Zn=1:3:6, In:Ga:Zn=3:1:2A or In-Ga-Zn oxides with an atomic ratio of In:Ga:Zn=2:1:3 and their composition It is preferable to use an oxide from the vicinity of [the specified location].

[0255] When an oxide semiconductor film contains a large amount of hydrogen, it combines with the oxide semiconductor, causing water to form. Some of the elements become donors, generating electrons, which are carriers. This causes the transistor The threshold voltage of the film shifts in the negative direction. Therefore, the formation of oxide semiconductor films is affected. Subsequently, a dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or water from the oxide semiconductor film. It is preferable to remove impurities and purify the material to a high degree to minimize its content.

[0256] Furthermore, by dehydrating (dehydrogenating) the oxide semiconductor film, Oxygen levels may also decrease at the same time. Therefore, dehydration treatment of oxide semiconductor films (dehydration) A process to add oxygen to an oxide semiconductor film to compensate for the increased oxygen deficiency caused by the chemical treatment. It is preferable to do so. In this specification, etc., when oxygen is supplied to an oxide semiconductor film, This is sometimes referred to as oxygenation treatment, or the stoichiometric composition of oxygen contained in oxide semiconductor films. When the amount is increased more than that, it is sometimes referred to as a peroxygenation treatment.

[0257] Thus, oxide semiconductor films undergo dehydration treatment (dehydrogenation treatment) to remove hydrogen or water. The oxygen deficiency is removed and compensated for by oxygenation treatment, resulting in type i (true) and This can be an oxide semiconductor film that is very close to type i and is essentially type i (intrinsic). Furthermore, "substantially true" means that there are very few donor-derived carriers in the oxide semiconductor film. (Close to zero), carrier density is 1 × 10⁻⁶ 17 / cm 3 Below, 1 x 10 16 / cm 3 below , 1 x 10 15 / cm 3 Below, 1 x 10 14 / cm 3 Below, 1 x 10 13 / cm 3 Below To say something

[0258] Furthermore, transistors having an oxide semiconductor film that is of type i or substantially type i are This enables extremely excellent off-current characteristics. For example, a transient using an oxide semiconductor film The drain current when the switch is off is 1 × 10⁻¹⁰ at room temperature (approximately 25°C). -18 Below A, Preferably 1 × 10 -21 A or less, more preferably 1 × 10 -24 A or lower, or 85 1 × 10°C -15 A or less, preferably 1 × 10 -18 A or less, more preferably 1× 10 -21 It can be less than or equal to A. Note that the transistor being in the off state is n-channel. In the case of a transistor of this type, this refers to the state where the gate voltage is sufficiently lower than the threshold voltage. Specifically, if the gate voltage is 1V, 2V, or 3V lower than the threshold voltage The transistor then turns off.

[0259] The structure of oxide semiconductor films will be described below.

[0260] Oxide semiconductor films are broadly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. Non-single-crystal oxide semiconductor films are CAAC-OS (C Axis Aligned Crystal Sturtine Oxide Semiconductor film, polycrystalline oxide semiconductor This refers to films, microcrystalline oxide semiconductor films, amorphous oxide semiconductor films, etc.

[0261] First, let's explain the CAAC-OS membrane.

[0262] In this specification, "parallel" means that two lines are at an angle of -10° or more and 10° or less. This refers to a state in which the positions are arranged. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "Perpendicular" refers to a state where two straight lines are positioned at an angle between 80° and 100°. Therefore, this also includes cases where the angle is between 85° and 95°.

[0263] Furthermore, in this specification, if the crystal is trigonal or rhombohedral, it is listed as hexagonal. vinegar.

[0264] CAAC-OS film is an oxide semiconductor film having multiple c-axis oriented crystalline regions. .

[0265] CAAC-OS film is examined using a transmission electron microscope (TEM). When observed with a tron ​​microscope, a clear boundary between crystalline regions is observed, i.e. The grain boundaries (also called crystal grain boundaries) cannot be identified. Therefore, C AAC-OS films are less susceptible to the decrease in electron mobility caused by grain boundaries.

[0266] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM view). (Inference) It can be confirmed that in the crystalline part, metal atoms are arranged in layers. Each of these layers has a concave surface on the surface (also called the surface to be formed) or upper surface that forms the CAAC-OS film. The shape reflects a convexity and is arranged parallel to the surface or top surface of the CAAC-OS film to be formed.

[0267] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (plane T). EM observation reveals that in the crystalline region, metal atoms are arranged in a triangular or hexagonal shape. This can be confirmed. However, no regularity is observed in the arrangement of metal atoms between different crystalline regions. do not have.

[0268] Figure 23(a) is a cross-sectional TEM image of the CAAC-OS film. Figure 23(b) is a cross-sectional image of the CAAC-OS film. This is a further magnified cross-sectional TEM image of 23(a), with the atomic arrangement exaggerated for easier understanding. The key signature is indicated.

[0269] Figure 23(c) shows the area circled (diameter approximately 4) between AO and A' in Figure 23(a). This is a local Fourier transform image of nm. From Figure 23(c), c-axis orientation is observed in each region. This can be confirmed. Also, since the orientation of the c-axis is different between A and O and between O and A', different G This suggests it is rain. Also, between A and O, the c-axis angles are 14.3° and 16°. It can be seen that it changes gradually and continuously, such as 6° and 26.4°. Similarly, OA In between, the angle of the c-axis is -18.3°, -17.6°, and -15.9° in a gradual, continuous manner. It is clear that things are changing.

[0270] Furthermore, when electron diffraction is performed on the CAAC-OS film, oriented spots (bright spots) appear. Observed. For example, on the upper surface of the CAAC-OS film, for example, between 1 nm and 30 nm. When electron diffraction using an electron beam (also called nanobeam electron diffraction) is performed, a spot is observed. (See Figure 24(A)).

[0271] Cross-sectional TEM observation and planar TEM observation revealed that the crystalline portion of the CAAC-OS film exhibits orientation. It can be seen that this is the case.

[0272] Furthermore, most of the crystalline parts contained in the CAAC-OS film are cubes with sides less than 100 nm long. It is small enough to fit inside the body. Therefore, the crystalline portion contained in the CAAC-OS membrane has sides of 10. This also includes cases where the size is less than nm, less than 5 nm, or less than 3 nm and fits within a cube. Furthermore, multiple crystalline regions contained in the CAAC-OS film connect to form one large crystalline region. A region may be formed. For example, in a planar TEM image, at 2500 nm 2 Above 5μm 2 or greater than 1000 μm 2 In some cases, crystal regions exceeding the above size may be observed.

[0273] X-ray diffraction (XRD) of CAAC-OS film When structural analysis is performed using the instrument, for example, CAAC-OS having InGaZnO4 crystals is found. Out-of-plane analysis of the film showed a peak at a diffraction angle (2θ) of around 31°. This peak may appear. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is on the surface to be formed or on the upper surface. It can be confirmed that it is oriented in a roughly vertical direction.

[0274] On the other hand, in the CAAC-OS film, X-rays are incident from a direction approximately perpendicular to the c-axis in an in-p In analysis using the lane method, a peak may appear when 2θ is around 56°. This is attributed to the (110) plane of the InGaZnO4 crystal. For a crystalline semiconductor film, fix 2θ to approximately 56° and use the normal vector of the sample surface as the axis (φ axis). When the analysis (φ scan) is performed while rotating the sample, a crystal plane equivalent to the (110) plane is found. Six peaks attributable to this are observed. In contrast, in the case of the CAAC-OS film, 2θ Even when fixed at approximately 56° and scanned using the φ scan function, no clear peak appears.

[0275] From the above, it can be concluded that in CAAC-OS films, the orientation of the a-axis and b-axis between different crystalline regions is Although irregular, it has c-axis orientation, and the c-axis is parallel to the normal vector of the formed surface or the upper surface. It can be seen that it is oriented in a specific direction. Therefore, the layered structure confirmed by the aforementioned cross-sectional TEM observation is Each layer of arranged metal atoms is a plane parallel to the ab-plane of the crystal.

[0276] Furthermore, the crystalline portion is formed when the CAAC-OS film is deposited, or during crystallization treatments such as heat treatment. It is formed when the process is carried out. As mentioned above, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed. Or it is oriented in a direction parallel to the normal vector of the upper surface. Therefore, for example, the CAAC-OS film When the shape is altered by etching or other means, the c-axis of the crystal becomes the target area for CAAC-OS film formation. The normal vector may not be parallel to the normal vector of the face or top surface.

[0277] Furthermore, the distribution of c-axis oriented crystalline regions in the CAAC-OS film does not need to be uniform. For example, the crystalline portion of the CAAC-OS film may be formed by crystal growth from near the top surface of the CAAC-OS film. When formed in this manner, the region near the top surface will have a more c-axis-oriented crystal structure than the region near the surface being formed. The proportion of impurities can increase. Also, CAAC-OS films with added impurities may have higher impurities. The region to which the substance is added is altered, and regions with a different proportion of partially c-axis-oriented crystals are formed. Sometimes that happens.

[0278] Furthermore, the out-of-plane CAAC-OS film having InGaZnO4 crystals Analysis using this method revealed that in addition to the peak near 2θ = 31°, there is also a peak near 2θ = 36°. In some cases, this may occur. Peaks near 2θ of 36° indicate c-axis orientation in a portion of the CAAC-OS film. This indicates the presence of crystals that do not possess properties. The CAAC-OS film has a 2θ of approximately 31°. It is preferable that a peak is shown and that no peak is shown near 36° for 2θ.

[0279] CAAC-OS films are oxide semiconductor films with low impurity concentrations. The impurities include hydrogen and carbon. These are elements other than the main components of oxide semiconductor films, such as silicon and transition metal elements. In particular, silicon Elements such as condensate, which have a stronger bonding force with oxygen than the metal elements that make up oxide semiconductor films, are acidic. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. This is a contributing factor. Also, heavy metals such as iron and nickel, argon, and carbon dioxide have a high atomic ratio. Because of its large diameter (or molecular radius), when it is contained within an oxide semiconductor film, the oxide semiconductor film This disrupts the atomic arrangement and reduces crystallinity. Pure substances can act as carrier traps or carrier sources.

[0280] Furthermore, CAAC-OS films are oxide semiconductor films with a low defect level density. For example, oxide Oxygen vacancies in semiconductor films can act as carrier traps or capture hydrogen. This can sometimes become a source of carrier transmission.

[0281] A low impurity concentration and low defect level density (few oxygen vacancies) are referred to as high-purity intrinsic or This is essentially called high-purity intrinsic. Oxide semiconductors that are high-purity intrinsic or substantially high-purity intrinsic. Because the membrane has fewer carrier sources, the carrier density can be lowered. A transistor using this oxide semiconductor film exhibits electrical characteristics such as a negative threshold voltage ( - Also called Marieion.) It rarely becomes high purity genuine or substantially high purity. Intrinsic oxide semiconductor films have few carrier traps. Therefore, the oxide semiconductor... Transistors using film have small variations in electrical characteristics and are highly reliable. Furthermore, the charge trapped in the carrier trap of the oxide semiconductor film requires time to be released. It can last for a long time and behave as if it were a fixed charge. Therefore, when the impurity concentration is high... Furthermore, transistors using oxide semiconductor films with a high defect level density tend to have unstable electrical properties. There are cases where this occurs.

[0282] Furthermore, transistors using CAAC-OS films exhibit electrical properties when irradiated with visible light or ultraviolet light. Sexual variation is small.

[0283] Next, we will explain microcrystalline oxide semiconductor films.

[0284] Microcrystalline oxide semiconductor films can be clearly observed using TEM. In some cases, this may not be possible. The crystalline portion contained in the microcrystalline oxide semiconductor film is between 1 nm and 100 nm. They are often smaller than 1 nm, or between 1 nm and 10 nm in size. In particular, between 1 nm and 10 nm Nanocrystals (nc: nanocrystals) are microcrystals of a size of 1 nm or less, or between 1 nm and 3 nm. An oxide semiconductor film having tal is made nc-OS (nanocrystalline O It is called an xide Semiconductor film. Also, an nc-OS film is, for example, T In some cases, grain boundaries may not be clearly visible in images obtained using EM (Electromagnetic Wave) imaging.

[0285] nc-OS films are used in minute regions (for example, regions between 1 nm and 10 nm, especially regions between 1 nm and 10 nm). The atomic arrangement has periodicity in the region of 3 nm or less. In addition, the nc-OS film is different There is no regularity in the crystal orientation between the crystalline regions. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS films may be indistinguishable from amorphous oxide semiconductor films. There are cases where this occurs. For example, XRD using X-rays with a diameter larger than that of the crystalline region on an nc-OS film. When structural analysis is performed using the apparatus, the out-of-plane method analyzes the crystal planes. The indicated peak is not detected. Also, the probe diameter is larger than that of the crystalline region in the nc-OS film. Electron diffraction (also called limited-field electron diffraction) is performed using an electron beam (for example, 50 nm or longer). Then, a diffraction pattern resembling a halo pattern is observed. On the other hand, for nc-OS films, Nanobeam electron diffractometers use electron beams with a probe diameter close to or smaller than the size of the crystal. When this is performed, a spot is observed. Furthermore, nanobeam electron diffraction is performed on the nc-OS film. In some cases, a region of high brightness may be observed in a circular (ring-shaped) pattern. Also, n When nanobeam electron diffraction is performed on a c-OS film, multiple spots are observed within a ring-shaped region. It may be measured.

[0286] nc-OS films are oxide semiconductor films with higher orderliness than amorphous oxide semiconductor films. Therefore, nc-OS films have a lower defect level density than amorphous oxide semiconductor films. However, Furthermore, the nc-OS film does not show any regularity in crystal orientation between different crystalline regions. Therefore, nc- OS films have a higher defect level density compared to CAAC-OS films.

[0287] Note that oxide semiconductor films include, for example, amorphous oxide semiconductor films, microcrystalline oxide semiconductor films, and C The AAC-OS film may be a multilayer film having two or more types.

[0288] When an oxide semiconductor film has multiple structures, the structural solution can be obtained using nanobeam electron diffraction. Analysis may be possible in some cases.

[0289] Figure 24(C) shows the electron gun chamber 10, the optical system 12 below the electron gun chamber 10, and below the optical system 12. The sample chamber 14, the optical system 16 below the sample chamber 14, the observation chamber 20 below the optical system 16, and observation A camera 18 installed in room 20 and a film room 22 below the observation room 20 are included in the transmission electric field. This shows the particle diffraction measurement device. Camera 18 is installed facing the inside of the observation room 20. It is not necessary to have a room 22.

[0290] Furthermore, Figure 24(D) shows the internal structure of the transmission electron diffraction measurement device shown in Figure 24(C). Inside the transmission electron diffraction measuring device, electrons emitted from the electron gun installed in the electron gun chamber 10 However, it is irradiated onto the substance 28 placed in the sample chamber 14 via the optical system 12. The resulting electrons are incident on a fluorescent screen 32 installed inside the observation room 20 via the optical system 16. On the light plate 32, a pattern appears corresponding to the intensity of the incident electrons, forming a transmitted electron diffraction pattern. It can measure n.

[0291] Camera 18 is positioned facing the fluorescent board 32 and captures the patterns that appear on the fluorescent board 32. It is possible to cast a shadow. A straight line passing through the center of the lens of camera 18 and the center of the fluorescent screen 32. The angle between the line and the top surface of the fluorescent board 32 is, for example, between 15° and 80°, or between 30° and above. The angle should be 75° or less, or between 45° and 70°. The smaller the angle, the more likely it is that the camera 18 will capture the image. The transmitted electron diffraction pattern that is shadowed will be greatly distorted. However, if the angle is known in advance... If so, it is also possible to correct the distortion of the obtained transmission electron diffraction pattern. In some cases, camera 18 may be placed in the film chamber 22. It may also be installed in the room chamber 22 so as to be opposite to the direction of incidence of electrons 24. In this case, a fluorescent screen A low-distortion transmission electron diffraction pattern can be captured from the back surface of the 32-lens microscope.

[0292] A holder for fixing the sample substance 28 is installed in the sample chamber 14. The holder has a structure that allows electrons to pass through material 28. The holder is, for example, a material The holder may have a function to move quality 28 along the X, Y, and Z axes. For example, 1nm to 10nm, 5nm to 50nm, 10nm to 100nm Move within ranges such as m or less, 50 nm to 500 nm, and 100 nm to 1 μm. It is sufficient to have a certain level of precision. These ranges should be determined by setting the optimal range based on the structure of material 28. Yes.

[0293] Next, the transmission electron diffraction pattern of the material is measured using the transmission electron diffraction measuring device described above. I will explain the method.

[0294] For example, as shown in Figure 24(D), the irradiation position of electrons 24, which are a nanobeam, in a material. By changing (scanning) the material, we can observe how the structure of the material changes. Yes, it is possible. In this case, if substance 28 is a CAAC-OS film, then as shown in Figure 24(A) A diffraction pattern is observed. Alternatively, if material 28 is an nc-OS film, then Figure 24(B) shows... The diffraction pattern shown is observed.

[0295] By the way, even if substance 28 is a CAAC-OS film, it may be partially an nc-OS film, etc. Similar diffraction patterns may be observed. Therefore, the quality of the CAAC-OS film is , the percentage of the region in which the diffraction pattern of the CAAC-OS film is observed within a certain range (CAA It can sometimes be expressed as (also called the carbonization rate). For example, with a good quality CAAC-OS film If present, the CAAC conversion rate should be 50% or more, preferably 80% or more, and more preferably 90%. More preferably, the diffraction pattern is 95% or higher. The region in which this is observed is referred to as the non-CAAC rate.

[0296] For example, immediately after film deposition (denoted as-sputtered), or in an oxygen-containing atmosphere. On the upper surface of each sample having a CAAC-OS film after heat treatment at 450°C in the air, a scan was performed. A transmission electron diffraction pattern was acquired while scanning. Here, scanning was performed at a speed of 5 nm / second for 60 seconds. The diffraction pattern is observed while scanning, and the observed diffraction pattern is captured as a still image every 0.5 seconds. The CAAC conversion rate was derived by converting to [a specific format]. Note that the electron beam used had a probe diameter of 1n. A nanobeam of m was used. Similar measurements were performed on six samples. Then, CAAC conversion was performed. The mean value across six samples was used to calculate the rate.

[0297] The CAAC conversion rate for each sample is shown in Figure 25(A). The CAAC-OS film immediately after deposition is C The AAC conversion rate was 75.7% (the non-CAAC conversion rate was 24.3%). Furthermore, heating at 450°C was performed. The CAAC conversion rate of the CAAC-OS film after treatment was 85.3% (the non-CAAC conversion rate was 14.7%). The results showed that the CAAC conversion rate was higher after the 450°C heat treatment compared to immediately after film formation. In other words, heat treatment at high temperatures (e.g., 400°C or higher) results in a lower non-CAAC conversion rate. It can be seen that the CAAC conversion rate increases. Also, when heat treatment is performed below 500°C, It can be seen that a CAAC-OS film with a high CAAC conversion rate can be obtained.

[0298] Here, most of the diffraction patterns that differ from those of the CAAC-OS film are similar to those of the nc-OS film. It was a folded pattern. Furthermore, the amorphous oxide semiconductor film could not be confirmed in the measurement area. It was not possible. Therefore, by heat treatment, a region having a structure similar to that of the nc-OS film was created. However, it is suggested that the structure of adjacent regions influences rearrangement and CAAC formation. .

[0299] Figures 25(B) and 25(C) show CAAC- immediately after film deposition and after heat treatment at 450°C. This is a planar TEM image of the OS film. By comparing Figure 25(B) and Figure 25(C), 4 The CAAC-OS film after heat treatment at 50°C shows that the film quality is more homogeneous. It can be seen that the film quality of the CAAC-OS film is improved by heat treatment at high temperatures.

[0300] Using this measurement method, it is possible to analyze the structure of oxide semiconductor films that have multiple structures. This can sometimes happen.

[0301] (Embodiment 4) In this embodiment, an example of a circuit utilizing a transistor according to one aspect of the present invention is shown in Figure I will explain by referring to the page.

[0302] Figure 16(A) shows the circuit diagram of the semiconductor device, and Figures 16(C) and (D) show cross-sectional views of the semiconductor device. These are shown below. Figures 16(C) and (D) show the channels of transistor 100 on the left side, respectively. The diagram shows a cross-sectional view in the longitudinal direction, and on the right, a cross-sectional view in the channel width direction. The circuit diagram also includes: To clearly indicate that it is a transistor using an oxide semiconductor, the designation "OS" is used. It is attached.

[0303] The semiconductor device shown in Figures 16(C) and (D) has a transient in the lower part using a first semiconductor material. It has a 2200 transistor and a transistor made of a second semiconductor material on top. As a transistor using a second semiconductor material, the transistor exemplified in Embodiment 1 is also used. Let's explain an example where 100 is applied.

[0304] Figures 17(A) and (B) show transistors using the second semiconductor material, as demonstrated in the implementation. This shows an example of a cross-sectional configuration when the transistor 200 exemplified in Form 1 is applied.

[0305] Here, the first semiconductor material and the second semiconductor material are materials with different band gaps. This is desirable. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (silicon, galvanic oxide). (e.g., luminum, silicon germanium, silicon carbide, or gallium arsenide, etc.) The second semiconductor material can be the oxide semiconductor described in Embodiment 1. Transistors that use single-crystal silicon or other materials besides conductors are easy to operate at high speeds. On the other hand, transistors using oxide semiconductors have a low off-current.

[0306] Here, we will explain assuming that transistor 2200 is a p-channel type transistor. However, it goes without saying that different circuits can be constructed using n-channel transistors. No. Furthermore, other than using a transistor like the one shown in Embodiment 1 using an oxide semiconductor, This section describes the specific configuration of semiconductor devices, including the materials used and the structure of the semiconductor device. It is not necessary to limit the scope to what is shown here.

[0307] The configurations shown in Figures 16(A), (C), and (D) are p-channel transistors and n-channel transistors. This is a so-called CM (Combined Multi-Purpose) transistor, where two transistors of type 1 are connected in series, and their gates are connected. An example of an OS circuit configuration is shown.

[0308] A transistor to which an oxide semiconductor according to one aspect of the present invention is applied has an increased on-current. Therefore, high-speed operation of the circuit becomes possible.

[0309] In the configuration shown in Figure 16(C), an insulating layer 2201 is placed on top of the transistor 2200. A transistor 100 is provided. Also, transistor 2200 and transistor 1 Multiple wires 2202 are provided between 00. Also, multiple are embedded in various insulating layers. The plug 2203 electrically connects the wiring and electrodes located in the upper and lower layers, respectively. Furthermore, an insulating layer 2204 covers the transistor 100, and wiring is placed on the insulating layer 2204. 2205 and wiring 220 formed by processing the same conductive film as the pair of electrodes of the transistor. 6 and are provided.

[0310] In this way, stacking two transistors reduces the circuit's footprint. Multiple circuits can be arranged at a higher density.

[0311] Figure 16(C) shows either the source or drain of transistor 100 and the transistor Either the source or drain of the 2200 is connected to the electrical wiring 2202 or plug 2203. They are connected precisely. Also, the gate of transistor 100 is connected to wiring 2205 and wiring 220 6. The gate of transistor 2200 via plug 2203 and wiring 2202, etc. It is electrically connected to it.

[0312] In the configuration shown in Figure 16(D), the plug 2203 is attached to the gate insulating layer of transistor 100. An opening for embedding is provided, and the gate of transistor 100 and plug 2203 are in contact. This configuration makes it easy to integrate circuits, in addition to Compared to the configuration shown in Figure 16(C), this allows for a reduction in the number and length of wiring and plugs involved. This allows the circuit to operate at a faster speed.

[0313] Here, in the configuration shown in Figures 16(C) and (D), transistor 100 and transistor By changing the connection configuration of the electrodes of the Ta2200, various circuits can be constructed. For example, as shown in Figure 16(B), the source and drain of each transistor are connected. By using a continuous circuit configuration, it can function as a so-called analog switch. Cut.

[0314] Furthermore, using the transistor shown as an example in either Embodiment 1 or 2, the object A semiconductor device with an image sensor function for reading information can be fabricated.

[0315] Figure 18 shows an example of an equivalent circuit of a semiconductor device having an image sensor function.

[0316] Photodiode 602 has one electrode connected to the photodiode reset signal line 658. The other electrode is electrically connected to the gate of transistor 640. Transistor 64 0 means that either the source or the drain is connected to the photosensor reference signal line 672, or the source or the drain The other end of the circuit is electrically connected to either the source or the drain of transistor 656. Transistor 656 has its gate connected to the gate signal line 659, and the other of its source or drain connected to the gate signal line 659. It is electrically connected to the photo sensor output signal line 671.

[0317] The photodiode 602 includes, for example, a semiconductor layer having a p-type conductivity and a high-resistance ( A pin-type semiconductor layer having an i-type conductivity and a n-type conductivity layer stacked together. A photodiode can be applied.

[0318] By detecting the light incident on the photodiode 602, information about the detected object can be read. It can be obtained. Note that when reading information about the detected object, a light source such as a backlight is used. It is possible to be there.

[0319] Furthermore, transistors 640 and 656 are provided by either Embodiment 1 or Embodiment 2. As shown in one example, it is possible to use a transistor in which a channel is formed in an oxide semiconductor. In Figure 18, transistors 640 and 656 include oxide semiconductors. To make this clear, the symbol for transistors is denoted with "OS".

[0320] Transistors 640 and 656 are examples of transistors shown in the above embodiment. The oxide semiconductor layer, which is a DISTA and forms a channel, contains excess oxygen-containing aluminum oxide. It has a structure in which it is encased in an insulating layer containing a nium film. In addition, an oxide semiconductor layer is used as the gate electrode. Therefore, it is preferable to have a configuration that electrically encloses the transistor 640 and The transistor 656 is an electrically stable transistor with suppressed fluctuations in its electrical characteristics. By including a transistor, it can be used as a semiconductor device having the image sensor function shown in Figure 18. We can provide highly reliable semiconductor devices.

[0321] This embodiment may be implemented in appropriate combination with other embodiments described herein. It is possible.

[0322] (Embodiment 5) In this embodiment, a transistor according to one aspect of the present invention is used, and power is not supplied. A semiconductor device (memory) that can retain its contents even under certain conditions and has no limit on the number of write cycles. An example of the apparatus will be explained using drawings.

[0323] Figure 19 shows the circuit diagram of the semiconductor device.

[0324] The semiconductor device shown in Figure 19 consists of a transistor 3200 using a first semiconductor material and a second semiconductor material It has a transistor 3300 and a capacitive element 3400 made of semiconductor material. The transistor 3300 is the transistor described in the above embodiment. It is possible.

[0325] Transistor 3300 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. It is a transistor. The 3300 transistor is used because it has a low off-current. It is possible to retain memory content for a longer period of time. In other words, refresh operations are unnecessary. To create a semiconductor memory device that does not require refresh operations, or one that requires extremely infrequent refresh operations. This makes it possible to significantly reduce power consumption.

[0326] In Figure 19, the first wiring 3001 is electrically connected to the source electrode of transistor 3200. The second wire 3002 is connected and electrically connected to the drain electrode of transistor 3200. Furthermore, the third wiring 3003 is the source electrode or drain of transistor 3300. The fourth wire 3004 is electrically connected to one of the electrodes and is connected to the gate of transistor 3300. It is electrically connected to the electrodes. And the gate electrode of transistor 3200, and The source electrode or drain electrode of the lampistor 3300, the other of which is the electrode of the capacitive element 3400. One side is electrically connected to the other side of the electrode of the capacitive element 3400, and the fifth wiring 3005 is electrically connected to the other side of the electrode of the capacitive element 3400. They are directly connected.

[0327] In the semiconductor device shown in Figure 19, the potential of the gate electrode of transistor 3200 can be maintained. By taking advantage of these characteristics, it is possible to write, store, and read information as follows.

[0328] The writing and retention of information will be explained. First, the potential of the fourth wiring 3004 is set to The potential is set to turn on transistor 3300, thereby turning on transistor 3300. This causes the potential of the third wiring 3003 to be the gate electrode of transistor 3200. And is supplied to the capacitance element 3400. That is, the gate electrode of transistor 3200 is supplied Then, a predetermined charge is applied (written). Here, two different potential levels are given by electricity. A charge (hereinafter referred to as Low-level charge or High-level charge) is given to a device Then, the potential of the fourth wiring 3004 is set to the point where transistor 3300 is in the off state. By setting it to the OFF state, transistor 3300 is turned OFF. The charge applied to the gate electrode is retained (held).

[0329] Because the off-current of transistor 3300 is extremely small, the gate of transistor 3200 The charge on the electrodes is retained for a long period of time.

[0330] Next, we will explain how to read the information. A predetermined potential (constant potential) is applied to the first wiring 3001. When the appropriate potential (readout potential) is applied to the fifth wiring 3005 while the current is being applied, the transient Depending on the amount of charge held at the gate electrode of terminal 3200, the second wiring 3002 will have different powers. To take a position. Generally, if transistor 3200 is an n-channel type, then transistor 320 Apparent threshold V when a high level charge is applied to a terminal station with zero charge. th_ H This is the case when a low level charge is applied to the gate electrode of transistor 3200. The threshold value V th_L This is because it becomes lower. Here, the apparent threshold voltage is The potential of the fifth wire 3005, which is necessary to turn on transistor 3200, Therefore, the potential of the fifth wiring 3005 is set to V th_H and V th_L During By setting the potential V0, the charge applied to the gate electrode of transistor 3200 can be determined. They can be separated. For example, in the case of writing, if a high-level charge is given, The potential of the fifth wire 3005 is V0 (>V th_H) In that case, transistor 3200 is " It becomes "on". If a low-level charge is applied, the fifth wiring 3005 The potential is V0( <V th_L Even if this happens, transistor 3200 remains in the "off state". Therefore, by determining the potential of the second wiring 3002, the information being held can be read. It is possible to break free.

[0331] Furthermore, when memory cells are arranged in an array, only the information of the desired memory cell can be read. It becomes necessary to be able to extract the information. If the information is not read in this way, the state of the gate electrode Regardless, the potential at which transistor 3200 is in the "off state" is V th_ H A smaller potential should be applied to the fifth wire 3005. Alternatively, depending on the state of the gate electrode... The potential at which transistor 3200 remains "on" is, that is, V th_L Yo A larger potential should be applied to the fifth wiring 3005.

[0332] In the semiconductor device shown in this embodiment, an oxide semiconductor is used in the channel formation region for off-voltage applications. By using transistors with extremely low current, it is possible to retain memory content for extremely long periods of time. It is possible to do so. In other words, a refresh operation will become unnecessary, or a refresh will be required. Because the frequency of operation can be made extremely low, power consumption can be significantly reduced. It is possible. Also, in the absence of power supply (however, it is desirable that the potential be fixed). Even if memory is impaired, it is possible to retain the contents of that memory over a long period of time.

[0333] Furthermore, the semiconductor device shown in this embodiment does not require a high voltage for writing information. There are no issues with element degradation. For example, unlike conventional non-volatile memory, floating-point memory... Because there is no need to inject electrons into the gate or extract electrons from the floating gate. Furthermore, problems such as deterioration of the gate insulating layer do not occur at all. In other words, the semiconductor according to the disclosed invention In this device, there is no limitation on the number of rewrite cycles, which is a problem with conventional non-volatile memory. Reliability improves dramatically. Furthermore, information is obtained depending on the on and off states of the transistor. Because data is written to the system, high-speed operation can be easily achieved.

[0334] This embodiment may be implemented in appropriate combination with other embodiments described herein. It is possible.

[0335] (Embodiment 6) In this embodiment, at least the transistors described in the embodiments can be used. Next, we will describe a CPU including the memory device described in the previous embodiment.

[0336] Figure 20 shows a CPU that uses at least some of the transistors described in Embodiment 1. This is a block diagram showing the example configuration.

[0337] The CPU shown in Figure 20 is an ALU1191 (ALU: Arithmetic) mounted on board 1190. tic logic unit (arithmetic circuit), ALU controller 1192, instruction Action decoder 1193, interrupt controller 1194, timing controller R1195, Register 1196, Register Controller 1197, Bus Interface 1198 (Bus I / F), rewritable ROM1199, and ROM interface It has a face 1189 (ROM I / F). The substrate 1190 is a semiconductor substrate, SOI A circuit board, glass substrate, etc. are used. ROM1199 and ROM interface1189 This may be provided on a separate chip. Of course, the CPU shown in Figure 20 has a simplified configuration. This is just one example; actual CPUs have a wide variety of configurations depending on their application. For example, a configuration including the CPU or arithmetic circuit shown in Figure 20 is considered one core, and multiple such cores are... It is also possible to configure the CPU so that each core operates in parallel. The number of bits that can be handled by arithmetic circuits and data buses is, for example, 8 bits, 16 bits, 32 bits, 6 bits. It can be set to 4 bits, for example.

[0338] Instructions input to the CPU via the bus interface 1198 are instructions The signal is input to the decoder 1193, decoded, and then sent to the ALU controller 1192. Trap controller 1194, register controller 1197, timing controller This is entered into Ra1195.

[0339] ALU controller 1192, interrupt controller 1194, register controller The driver 1197 and timing controller 1195 perform various operations based on the decoded instructions. It performs control. Specifically, the ALU controller 1192 controls the operation of the ALU 1191. It generates a signal to do so. In addition, the interrupt controller 1194 generates a signal to the CPU's program. During RAM execution, interrupt requests from external input / output devices and peripheral circuits are processed based on their priority and mass. The system determines and processes based on the state. The register controller 1197 processes the state of register 1196. It generates a dress and reads or writes to register 1196 depending on the CPU state. .

[0340] Furthermore, the timing controller 1195 is connected to the ALU 1191 and the ALU controller 11 92, Instruction decoder 1193, Interrupt controller 1194, It generates signals to control the timing of the operation of the register controller 1197. The timing controller 1195 uses the reference clock signal CLK1 to determine the internal clock signal It is equipped with an internal clock generation unit that generates the CLK2 signal, and the internal clock signal CLK2 is raised It supplies power to the various circuits listed.

[0341] In the CPU shown in Figure 20, a memory cell is located in register 1196. The transistor shown in the previous embodiment can be used as the memory cell of TA1196. Cut.

[0342] In the CPU shown in Figure 20, the register controller 1197 receives from ALU 1191. Following the instructions, select the hold operation in register 1196. That is, register 1 In the memory cell of 196, data is retained by a flip-flop, or Select whether to use quantitative elements for data retention. (Data retention using flip-flops) If selected, power voltage is supplied to the memory cells in register 1196. If data retention in the capacitive element is selected, the data will not be rewritten to the capacitive element. This process can be performed to stop the supply of power voltage to the memory cell in register 1196. ru.

[0343] Figure 21 is an example of a circuit diagram of a memory element that can be used as register 1196. The memory element 700 has a circuit 701 in which the stored data volatilizes when the power is cut off, and when the power is cut off the stored data Circuit 702 that prevents the data from volatilizing, switch 703, switch 704, and logic element 706 The circuit 702 includes a capacitive element 707 and a circuit 720 having a selection function. It has element 708, transistor 709, and transistor 710. Child 700 can, if necessary, add other elements such as diodes, resistors, inductors, etc. It is also acceptable to have them.

[0344] Here, the memory device described in the previous embodiment can be used in circuit 702. When the power supply voltage to the memory element 700 is stopped, the gate of transistor 709 in circuit 702 The input to the terminal is continuously set to ground potential (0V) or a potential that turns off transistor 709. The configuration is such that the gate of transistor 709 is grounded via a load such as a resistor. It is considered complete.

[0345] Switch 703 uses a single-conductivity (e.g., n-channel) transistor 713 The switch 704 is configured to handle a transistor with a conductivity type opposite to that of a single-conductivity type (e.g., a p-channel type). An example configuration using the inverter 714 is shown. Here, the first terminal of the switch 703 is connected to the transistor. Corresponding to either the source or drain of the converter 713, the second terminal of the switch 703 is connected to the transistor. The switch 703 corresponds to the source and drain of transistor 713, and the other to transistor 713. The control signal RD input to gate 3 determines the continuity between the first terminal and the second terminal. Non-conductivity (i.e., the ON or OFF state of transistor 713) is selected. The first terminal of transistor 704 corresponds to either the source or the drain of transistor 714, and the switch The second terminal of transistor 704 corresponds to the source and drain of transistor 714, and the switch The first terminal of transistor 704 is controlled by the control signal RD input to the gate of transistor 714. Conduction or non-conductivity between the child and the second terminal (i.e., the ON state or the ON state of transistor 714) The "Off" state is selected.

[0346] One of the sources and drains of transistor 709 is one of the pair of electrodes of capacitive element 708. One side is electrically connected to the gate of transistor 710. Here, the connection part This node is designated as M2. One of the sources and drains of transistor 710 is supplied with a low-voltage power supply. It is electrically connected to a wire that can do this (e.g., a GND wire), and the other is switch 703 It is electrically connected to the first terminal (one of the source and drain of transistor 713). The second terminal of switch 703 (the other of the source and drain of transistor 713) is the switch Electrically connected to the first terminal of transistor 704 (one of the source and drain of transistor 714). The second terminal of switch 704 (the other of the source and drain of transistor 714) It is electrically connected to wiring that can supply the power potential VDD. Switch 703 The second terminal (the other of the source and drain of transistor 713) and the first terminal of switch 704 The terminals (one of the source and drain of transistor 714) and the input terminal of logic element 706 And, one of the pair of electrodes of the capacitive element 707 is electrically connected. Here, connection Let the portion be called node M1. The other electrode of the pair of electrodes of the capacitive element 707 is subjected to a constant potential. It can be configured to be powered by a low power supply potential (GND, etc.) or a high power supply potential ( A configuration can be made in which VDD, etc. is input. The other side is electrically connected to wiring (e.g., a GND wire) that can supply a low-potential power supply. The other electrode of the pair of electrodes in the capacitive element 708 is configured to receive a constant potential input. This is possible. For example, when a low power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. This configuration can be achieved. The other electrode of the pair of electrodes of the capacitive element 708 is connected to a low-potential power supply. It is electrically connected to a power supply (e.g., a ground wire).

[0347] Furthermore, capacitive elements 707 and 708 accumulate parasitic capacitances of transistors and wiring, etc. It was possible to omit it by using it to its fullest extent.

[0348] The control signal WE is input to the first gate (first gate electrode) of transistor 709. Switches 703 and 704 are controlled by a different control signal RD than control signal WE. Then, the conductive or non-conductive state between the first terminal and the second terminal is selected, and one of the switches When there is conductivity between the first and second terminals of the switch, the first and second terminals of the other switch The area between the terminals becomes non-conductive.

[0349] The source and drain of transistor 709 are connected to the data held in circuit 701. The corresponding signal is input. In Figure 21, the signal output from circuit 701 is the transistor An example is shown where the source and drain of switch 709 are input to the other end. The signal output from the child (the other side of the source and drain of transistor 713) is sent to logic element 7 The logic value is inverted by 06, becoming an inverted signal, which is then sent to circuit 701 via circuit 720. It will be entered.

[0350] Note that in Figure 21, the second terminal of switch 703 (source and drain of transistor 713) The signal output from the other side of the input is sent to circuit 70 via logic element 706 and circuit 720. An example of inputting to 1 is shown, but it is not limited to this. The second terminal of switch 703 (transition The signals output from the source and drain (other side) of the 713 can have their logic values ​​inverted. It may be input to circuit 701 without any further processing. For example, input from the input terminal into circuit 701 If there is a node that holds a signal inverted from the logical value of the signal, switch 70 The signal output from the second terminal of 3 (the other of the source and drain of transistor 713) Input can be made to the node in question.

[0351] In Figure 21, transistor 709 uses the transistor described in Embodiment 1. It is possible. Also, a second gate is provided on the opposite side of the semiconductor layer from the first gate. It is preferable to have a configuration having a second gate electrode. The first gate is provided with a control signal WE. The input can be made, and the control signal WE2 can be input to the second gate. The control signal WE2 is It should be a signal with a constant potential. This constant potential can be, for example, the ground potential (GND) or a transient A potential smaller than the source potential of ST709 is selected. The control signal WE2 is a transient This is a potential signal used to control the threshold voltage of transistor 709, and the Ic of transistor 709. ut can be further reduced. Note that transistor 709 has a second gate. It is also possible to use transistors that do not produce transistors.

[0352] Furthermore, in Figure 21, among the transistors used in the memory element 700, Transistors other than T709 are made of a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. A transistor can be formed in which a channel is formed in a silicon layer or a silicon layer. A transistor can be used to form a channel on the recon substrate. Also, memory element 7 All transistors used in 00 are transistors whose channels are formed by an oxide semiconductor layer. It can also be a starter. Alternatively, the memory element 700 can also have a transistor 709, or a chip. The channel may include a transistor formed of an oxide semiconductor layer, and the remaining transistor The st is a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor in which a channel is formed. It can also be called a Rangista.

[0353] For example, a flip-flop circuit can be used for circuit 701 in Figure 21. Furthermore, logic elements 706 can be, for example, inverters or clocked inverters. It is possible.

[0354] In one aspect of the present invention, in a semiconductor device, when the power supply voltage is not supplied to the memory element 700 The data stored in circuit 701 is transferred by the capacitive element 708 provided in circuit 702. It can be held in that way.

[0355] Furthermore, transistors with channels formed in the oxide semiconductor layer exhibit extremely low off-current. For example, the off-current of a transistor in which a channel is formed in an oxide semiconductor layer is due to its crystalline properties. It is significantly lower than the off-current of a transistor in which a channel is formed in silicon. Therefore, by using the transistor as transistor 709, the memory element 7 The signal held by the capacitive element 708 will remain in place for a long period of time even when no power supply voltage is supplied to 00. It drips. In this way, the memory element 700 retains its stored contents (data) even when the power supply voltage is interrupted. It is possible to hold it.

[0356] Furthermore, by providing switches 703 and 704, pre-charge operation Because it is a memory element characterized by performing the following, after the power supply voltage is restored, the circuit 701 returns to its original state This can shorten the time it takes to re-store the data.

[0357] Furthermore, in circuit 702, the signal held by the capacitive element 708 is transmitted to transistor 7 The signal is input to gate 10. As a result, the power supply voltage to memory element 700 is restored. Then, the signal held by the capacitive element 708 is controlled by the state of transistor 710 (on state, It can be converted to (or off state) and read out from circuit 702. Therefore, the capacitive element Even if the potential corresponding to the signal held in 708 fluctuates slightly, the original signal can be read out accurately. It is possible to do so.

[0358] Such memory elements 700 are stored in registers and cache memory of the processor. By using it in a storage device, it prevents the loss of data in the storage device due to a power supply interruption. This is possible. Furthermore, after the power supply voltage is restored, the system will quickly return to the state it was in before the power supply was interrupted. Therefore, the entire processor, or one of the components of the processor, This allows for power-off even for short periods in multiple logic circuits, thus reducing power consumption. It can be suppressed.

[0359] In this embodiment, the memory element 700 was described as an example of being used in a CPU, but the memory element 7 00 is DSP (Digital Signal Processor), custom LS I, LSIs such as PLDs (Programmable Logic Devices), RF - Can also be applied to ID (Radio Frequency Identification). It is Noh.

[0360] This embodiment may be implemented in appropriate combination with other embodiments described herein. It is possible.

[0361] (Embodiment 7) In this embodiment, the transistor, memory device, or CPU described in the above embodiment is used. By using semiconductor devices such as DSPs, custom LSIs, PLDs, and RFIDs. Examples of electronic devices that can do this will be explained.

[0362] The transistors, memory devices, or CPUs exemplified in the above embodiments are used in various applications. It can be applied to sub-devices (including amusement machines). Examples of electronic devices include televisions, monitors, etc. Display devices, lighting devices, personal computers, word processors, image playback devices, Portable audio players, radios, tape recorders, stereos, telephones, cordless phones Telephone, mobile phone, car phone, transceiver, radio, game console, calculator, personal digital assistant, Children's notebooks, e-books, electronic translators, voice input devices, video cameras, digital still cameras, Electric shavers, IC chips, high-frequency heating devices such as microwave ovens, electric rice cookers, electric washing machines, Vacuum cleaners, air conditioning equipment such as air conditioners, dishwashers, dish dryers, clothes dryers Machines, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, DNA storage freezers, radiation Examples include medical devices such as radiation measuring instruments, dialysis machines, and X-ray diagnostic equipment. Also, smoke detectors, Other examples include alarm devices such as heat detectors, gas alarms, and security alarms. Furthermore, emergency lights, Traffic lights, conveyor belts, elevators, escalators, industrial robots, power storage systems Industrial equipment such as steam engines can also be cited. Furthermore, fuel-powered engines and non-aqueous secondary batteries can also be used. Mobile devices propelled by electric motors using force are also included in the category of electronic equipment. Examples of the above-mentioned mobile devices include electric vehicles (EVs) and hybrid vehicles that combine internal combustion engines and electric motors. Hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), these vehicles have no tires or wheels. Tracked vehicles converted to tracked vehicles, motorized bicycles including electric assist bicycles, motorcycles, electric Wheelchairs, golf carts, small or large vessels, submarines, helicopters, aircraft, rockets Examples include artificial satellites, space probes and planetary probes, and spacecraft. Some of these are electronic devices. A specific example is shown in Figure 22.

[0363] The television device 8000 shown in Figure 22(A) has a display unit 8002 assembled in a housing 8001. It is integrated, and displays images via the display unit 8002 and outputs sound via the speaker unit 8003. It is possible to do so. The transistor exemplified in the previous embodiment is assembled into the housing 8001. The embedded display unit 8002 can be used as a drive circuit or pixel for operation. .

[0364] The display unit 8002 is a light-emitting device equipped with light-emitting elements such as liquid crystal display devices and organic EL elements in each pixel. Equipment, electrophoresis display device, DMD (Digital Micromirror Display) Using semiconductor display devices such as ce, PDP (Plasma Display Panel) It is possible to be there.

[0365] The television system 8000 may include a receiver, modem, etc. Device 8000 can receive general television broadcasts using a receiver, and also has a modem. By connecting to a wired or wireless communication network via this, one-way communication (sender or Information communication is conducted in two directions (between the sender and receiver, or between receivers). It is also possible to do so.

[0366] Furthermore, the television equipment 8000 includes a CPU 8004 for information communication and memory. It may also be equipped with the transistors shown in the previous embodiment in the CPU 8004 and memory. Power saving can be achieved by using a memory device or a CPU.

[0367] The alarm device 8100 shown in Figure 22(A) is a residential fire alarm that detects smoke or heat. This is an example of an electronic device using part 8102 and microcomputer 8101. Computer 8101 is a transistor, memory device, or CP as shown in the previous embodiment. Includes U

[0368] Furthermore, an air conditioner having an indoor unit 8200 and an outdoor unit 8204 as shown in Figure 22(A) The processor includes an electric transistor, memory device, or CPU as shown in the previous embodiment. This is an example of a sub-unit. Specifically, the indoor unit 8200 consists of a housing 8201, an air outlet 8202, and C It has a PU8203, etc. In Figure 22(A), the CPU8203 is the indoor unit 8200 The example shows the case where it is located in the outdoor unit 8204, but the CPU 8203 is located in the outdoor unit 8204. It may be present. Alternatively, CPU 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. It may be used. The transistor shown in the previous embodiment is used in the CP of the air conditioner. By using it in U, power consumption can be reduced.

[0369] Furthermore, the electric refrigerator 8300 shown in Figure 22(A) is a transceiver as shown in the previous embodiment. This is an example of an electronic device including a gista, memory device, or CPU. Specifically, an electric refrigeration device. The storage unit 8300 consists of the chassis 8301, the refrigerator door 8302, the freezer door 8303, and the CPU 83 It has 04, etc. In Figure 22(A), the CPU 8304 is provided inside the housing 8301. The transistor shown in the previous embodiment is used in the CPU 830 of the electric refrigerator 8300. Using it in step 4 can help reduce power consumption.

[0370] Figures 22(B) and (C) show an example of an electronic device: an electric vehicle. The 9700 is equipped with a secondary battery 9701. The power of the secondary battery 9701 is supplied to circuit 9 The output is adjusted by 702 and supplied to the drive unit 9703. Circuit 9702 is shown in the figure. It is controlled by a processing unit 9704 having ROM, RAM, CPU, etc. By using the transistor shown in the example in the CPU of the electric vehicle 9700, power saving is achieved. It can be made more powerful.

[0371] The drive unit 9703 consists of a DC motor or an AC motor alone, or a motor and an internal combustion engine. It is composed of a combination of the following. The processing unit 9704 controls the operation of the driver of the electric vehicle 9700. Information (acceleration, deceleration, stopping, etc.) and driving information (information such as uphill and downhill slopes, and the influence on the drive wheels) Based on input information (such as load information), a control signal is output to circuit 9702. 2 is the electrical energy supplied from the secondary battery 9701 by the control signal of the processing unit 9704. Adjust the gear to control the output of the drive unit 9703. If an AC motor is installed, Although not shown in the diagram, it also incorporates an inverter that converts DC to AC.

[0372] This embodiment may be implemented in appropriate combination with other embodiments described herein. It is possible. [Explanation of symbols]

[0373] 100 transistors 101 circuit board 102 Semiconductor layer 103 Electrode 104 Gate Insulation Layer 105 Guard Station 106 Insulating layer 111 Protective insulating layer 112 Protective insulating layer 120 Capacitive elements 124 Dielectric layer 125 electrode 150 transistors 151 Oxide layer 152 Oxide layer 160 transistors 170 transistors 180 transistors 200 transistors 201 circuit board 202 Semiconductor layer 203 Electrode 204 Gate Insulation Layer 205 Terminal 206 Insulating layer 207 Insulating layer 211 Protective insulating layer 212 Protective insulating layer 220 capacity 224 Dielectric layer 225 Electrode 250 transistors 251 Oxide layer 252 Oxide layer 260 transistors 270 transistors 280 transistors 602 Photodiode 640 transistors 656 transistors 658 Photodiode reset signal line 659 Gate signal line 671 Photosensor output signal line 672 Photosensor Reference Signal Line 700 memory elements 701 Circuit 702 Circuit 703 Switch 704 Switch 706 Logical Component 707 Capacitive element 708 Capacitive element 709 Transistors 710 transistors 713 Transistors 714 transistors 720 circuits 1189 ROM Interface 1190 circuit board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM 2200 transistors 2201 Insulating layer 2202 Wiring 2203 Plug 2204 Insulating layer 2205 Wiring 2206 Wiring 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 transistors 3300 transistors 3400 Capacitive element 8000 Television equipment 8001 enclosure 8002 Display section 8003 Speaker section 8004 CPU 8100 Alarm device 8101 Microcomputer 8102 Detection Unit 8200 indoor unit 8201 enclosure 8202 Air vent 8203 CPU 8204 Outdoor unit 8300 Electric Refrigerator / Freezer 8301 enclosure 8302 Refrigerator door 8303 Freezer door 8304 CPU 9700 Electric Vehicles 9701 Secondary battery 9702 Circuit 9703 Drive unit 9704 Processing Unit

Claims

1. A semiconductor device having a first transistor and a second transistor, It comprises a first insulating layer, an oxide semiconductor layer, a first conductive layer, a second insulating layer, a second conductive layer, and a third insulating layer. The first insulating layer has a region located above the third conductive layer which functions as the gate electrode of the first transistor. The oxide semiconductor layer has a region located above the first insulating layer, The oxide semiconductor layer has a channel formation region for the second transistor, The first conductive layer has a region located above the oxide semiconductor layer, The first conductive layer functions as the source electrode or drain electrode of the second transistor. The second insulating layer has a region located above the oxide semiconductor layer, The second insulating layer functions as the gate insulating layer of the second transistor. The second conductive layer has a region that overlaps with the oxide semiconductor layer via the second insulating layer. The second conductive layer functions as the gate electrode of the second transistor. The third insulating layer has a region located above the second conductive layer, A semiconductor device in which, in a cross-sectional view of a cross-section cut along the channel length direction of the second transistor, the surface of the first insulating layer has a recess, and the oxide semiconductor layer has a region located inside the recess.

2. A semiconductor device having a first transistor and a second transistor, It comprises a first insulating layer, an oxide semiconductor layer, a first conductive layer, a second insulating layer, a second conductive layer, and a third insulating layer. The first insulating layer has a region located above the third conductive layer which functions as the gate electrode of the first transistor. The oxide semiconductor layer has a region located above the first insulating layer, The oxide semiconductor layer has a channel formation region for the second transistor, The first conductive layer has a region located above the oxide semiconductor layer, The first conductive layer functions as the source electrode or drain electrode of the second transistor. The second insulating layer has a region located above the oxide semiconductor layer, The second insulating layer functions as the gate insulating layer of the second transistor. The second conductive layer has a region that overlaps with the oxide semiconductor layer via the second insulating layer. The second conductive layer functions as the gate electrode of the second transistor. The third insulating layer has a region located above the second conductive layer, In a cross-sectional view of the cross-section of the second transistor cut along the channel length direction, the surface of the first insulating layer has a recess, and the oxide semiconductor layer has a region located inside the recess. A semiconductor device wherein the oxide semiconductor layer overlaps with the third conductive layer via the first insulating layer.

3. In claim 1 or claim 2, The aforementioned oxide semiconductor layer contains indium, wherein the semiconductor device is a semiconductor device.

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