Image sensor

Abstract

Perform appropriate processing in areas with different imaging conditions. [Solution] The image sensor comprises a first substrate having a plurality of pixels, each containing a photoelectric conversion unit that converts light into electric charge; a second substrate laminated with the first substrate and having a first comparison unit used to convert a signal output from a first pixel among the plurality of pixels into a digital signal; a third substrate laminated with the first substrate and having a first storage unit that stores a first digital signal converted from a signal output from the first pixel using the first comparison unit; and a fourth substrate laminated with the first substrate and having a second storage unit that stores a second digital signal converted from a signal output from the first pixel using the first comparison unit.

Description

Technical Field

[0001] The present invention relates to an imaging device.

Background Art

[0002] There is known an imaging device that performs analog-digital conversion on signals from pixels and stores the digital signals in a storage unit (Patent Document 1). However, in the prior art, when a plurality of storage units are arranged, the chip area of the imaging device increases.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] According to one aspect of the present invention, an imaging device includes a first substrate having a plurality of pixels each including a photoelectric conversion unit that converts light into electric charges, a second substrate laminated together with the first substrate and having a first comparison unit used to convert a signal output from a first pixel among the plurality of pixels into a digital signal, a third substrate laminated together with the first substrate and having a first storage unit that stores a first digital signal converted from the signal output from the first pixel into a digital signal using the first comparison unit, and a fourth substrate laminated together with the first substrate and having a second storage unit that stores a second digital signal converted from the signal output from the first pixel into a digital signal using the first comparison unit.

Brief Description of the Drawings

[0005] [Figure 1] A block diagram showing the configuration of an imaging device according to the first embodiment. [Figure 2] A diagram showing a cross-sectional structure of an imaging device according to the first embodiment. [Figure 3]A block diagram showing the configuration of the image sensor according to the first embodiment. [Figure 4] A circuit diagram showing the pixel configuration according to the first embodiment. [Figure 5] A block diagram showing the details of the configuration of the image sensor according to the first embodiment. [Figure 6] (a) is a diagram showing the configuration of the AD conversion unit and global counter according to the first embodiment. (b) is a timing chart showing an example of operation of the AD conversion unit according to the first embodiment. [Figure 7] A block diagram showing the details of the configuration of the image sensor according to the second embodiment. [Figure 8] A diagram illustrating the configuration of digital signals stored by the first and second storage units according to the second embodiment. [Figure 9] A block diagram showing the detailed configuration of the image sensor according to Modification Example 1. [Modes for carrying out the invention]

[0006] (First Embodiment) Figure 1 is a block diagram showing the configuration of an imaging device according to the first embodiment. The imaging device 1 comprises an imaging optical system 2, an image sensor 3, and a control unit 4. The imaging device 1 is, for example, a camera. The imaging optical system 2 forms an image of a subject on the image sensor 3. The image sensor 3 captures the image of the subject formed by the imaging optical system 2 and generates an image signal. The image sensor 3 is, for example, a CMOS image sensor. The control unit 4 outputs control signals to the image sensor 3 to control its operation. The control unit 4 also functions as an image generation unit that performs various image processing on the image signal output from the image sensor 3 to generate image data. The imaging optical system 2 may be detachable from the imaging device 1.

[0007] Figure 2 shows a cross-sectional structure of an image sensor according to the first embodiment. The image sensor 3 shown in Figure 2 is a back-illuminated image sensor. The image sensor 3 comprises a first substrate 111, a second substrate 112, a third substrate 113, and a fourth substrate 114. The first substrate 111, second substrate 112, third substrate 113, and fourth substrate 114 are each made of a semiconductor substrate or the like. The first substrate 111 is laminated onto the second substrate 112 via wiring layers 140 and 141. The second substrate 112 is laminated onto the third substrate 113 via wiring layers 142 and 143. The third substrate 113 is laminated onto the fourth substrate 114 via wiring layers 144 and 145. The incident light L, indicated by the white arrow, is incident in the positive Z-axis direction. Furthermore, as shown in the coordinate axes, the direction to the right of the paper perpendicular to the Z axis is defined as the positive X-axis direction, and the direction towards the front of the paper perpendicular to both the Z and X axes is defined as the positive Y-axis direction. The image sensor 3 is constructed by stacking the first substrate 111, the second substrate 112, the third substrate 113, and the fourth substrate 114 in the direction from which the incident light L is incident.

[0008] The image sensor 3 further includes a microlens layer 101, a color filter layer 102, and a passivation layer 103. These passivation layer 103, color filter layer 102, and microlens layer 101 are sequentially stacked on the first substrate 111. The microlens layer 101 has multiple microlenses ML. The microlenses ML focus the incident light onto the photoelectric conversion unit 12, which will be described later. The color filter layer 102 has multiple color filters F. The passivation layer 103 is composed of a nitride film or an oxide film.

[0009] The first substrate 111, the second substrate 112, the third substrate 113, and the fourth substrate 114 each have a first surface 105a, 106a, 107a, and 108a on which gate electrodes and gate insulating films are provided, and a second surface 105b, 106b, 107b, and 108b that is different from the first surface. Various elements such as transistors are provided on the first surface 105a, 106a, 107a, and 108a, respectively. Wiring layers 140, 141, 144, and 145 are laminated on the first surface 105a of the first substrate 111, the first surface 106a of the second substrate 112, the first surface 107a of the third substrate 113, and the first surface 108a of the fourth substrate 114, respectively. Furthermore, wiring layers (inter-substrate connection layers) 142 and 143 are laminated on the second surface 106b of the second substrate 112 and the second surface 107b of the third substrate 113, respectively. Wiring layers 140 to 145 are layers containing a conductive film (metal film) and an insulating film, and each has multiple wirings and vias arranged on it.

[0010] The elements on the first surface 105a of the first substrate 111 and the elements on the first surface 106a of the second substrate 112 are electrically connected via wiring layers 140 and 141 by connection parts 109 such as bumps and electrodes. Similarly, the elements on the first surface 107a of the third substrate 113 and the elements on the first surface 108a of the fourth substrate 114 are electrically connected via wiring layers 144 and 145 by connection parts 109 such as bumps and electrodes. The second substrate 112 and the third substrate 113 also have multiple through-electrodes 110, such as silicon through-electrodes. The through-electrodes 110 of the second substrate 112 connect the circuits provided on the first surface 106a and the second surface 106b of the second substrate 112 to each other, and the through-electrodes 110 of the third substrate 113 connect the circuits provided on the first surface 107a and the second surface 107b of the third substrate 113 to each other. The circuits provided on the second surface 106b of the second substrate 112 and the circuits provided on the second surface 107b of the third substrate 113 are electrically connected via inter-substrate connecting layers 142 and 143 by connection parts 109 such as bumps and electrodes.

[0011] Figure 3 is a block diagram showing the configuration of an image sensor according to the first embodiment. The first substrate 111 has a plurality of pixels 10 arranged in two dimensions. Multiple pixels 10 are arranged in the X-axis direction and the Y-axis direction as shown in Figure 2. The pixels 10 output a signal based on the charge generated by the photoelectric conversion unit, which will be described later, to the second substrate 112. The second substrate 112 has a plurality of comparison units 40. A comparison unit 40 is provided for each pixel 10 and is composed of a comparator circuit or the like. The comparison unit 40 compares the signal output from the pixel 10 with a reference signal that changes at a constant rate of change over time and outputs the comparison result to the third substrate 113 and the fourth substrate 114.

[0012] The third board 113 has a plurality of first storage units 50. The fourth board 114 has a plurality of second storage units 60 and an output unit 100. The first storage units 50 and second storage units 60 are provided for each pixel 10 and are configured by latch circuits and the like. As will be described in detail later, the comparison unit 40, the first storage unit 50 and the second storage unit 60 constitute an integral type analog / digital conversion unit (AD conversion unit) 70 that converts the analog signal output from the pixel 10 into a digital signal of a predetermined number of bits. The first storage unit 50 stores the digital signal of the lower bits of the predetermined number of bits, and the second storage unit 50 stores the digital signal of the upper bits of the predetermined number of bits.

[0013] The first storage unit 50 stores a digital signal based on the time it takes for the relative magnitudes of the signal output from the pixel 10 and the reference signal to change, measured using a first-frequency clock signal, when the comparison unit 40 compares the signal output from the pixel 10 with the reference signal. The second storage unit 60 stores a digital signal based on the time it takes for the relative magnitudes of the signal output from the pixel 10 and the reference signal to change, measured using a second-frequency clock signal with a lower frequency than the first-frequency clock signal. The digital signals stored in the first storage unit 50 and the second storage unit 60 are output to the output unit 100. The fourth substrate 114 of the image sensor 3 may also be provided with multiple ALUs (Arithmetic and Logic Units), i.e., arithmetic units 80, in addition to the output unit 100. If the fourth substrate 114 has arithmetic units 80, the digital signals stored in the first storage unit 50 and the second storage unit 60 are output to the arithmetic units 80. An arithmetic unit 80 is provided for each of the 10 pixels and performs calculations (arithmetic operations) between the digital signals generated for each of the 10 pixels. The arithmetic unit 80 is composed of an adder circuit, a subtractor circuit, a flip-flop circuit, and a shift circuit, etc. Each arithmetic unit 80 is connected to each other via signal lines, switches, etc. For example, when the signal of a pixel is selected by turning on a predetermined switch, the arithmetic unit 80 processes the signals of the selected multiple pixels.

[0014] In this embodiment, of the first and second storage units 50, the first storage unit 50, which stores the lower bits of the digital signal, is positioned closer to the comparison unit 40 than to the second storage unit 60. That is, the first storage unit 50 is located between the comparison unit 40 and the second storage unit 60. In Figure 3, the third board 113, which has the first storage unit 50, is located between the second board 112, which has the comparison unit 40, and the fourth board 114, which has the second storage unit 60. By positioning the first storage unit 50, which stores the digital signal based on a clock signal with a first frequency higher than the second frequency, closer to the comparison unit 40 than to the second storage unit 60, the influence of signal delay from the comparison unit 40 can be reduced. This enables high-precision AD conversion.

[0015] Figure 4 is a circuit diagram showing the pixel configuration of an image sensor according to the first embodiment. The pixel 10 has a photoelectric conversion unit 12, such as a photodiode (PD), and a readout unit 20. The photoelectric conversion unit 12 has the function of converting incident light into electric charge and accumulating the photoelectrically converted charge. The readout unit 20 has a transfer unit 13, an output unit 14, a floating diffusion (FD) 15, an amplification unit 16, and a current source 17.

[0016] The transfer unit 13 is controlled by the signal Vtx and transfers the charge photoelectrically converted by the photoelectric conversion unit 12 to the floating diffusion 15. In other words, the transfer unit 13 forms a charge transfer path between the photoelectric conversion unit 12 and the floating diffusion 15. The floating diffusion 15 holds (stores) the charge. The amplification unit 16 amplifies the signal from the charge held in the floating diffusion 15 and outputs it to the signal line 18. In the example shown in Figure 4, the amplification unit 16 is composed of a transistor M3 whose drain terminal, gate terminal, and source terminal are connected to the power supply VDD, the floating diffusion 15, and the current source 17, respectively.

[0017] The discharge unit (reset unit) 14 is controlled by the signal Vrst and discharges the charge from the floating diffusion 15, resetting the potential of the floating diffusion 15 to the reset potential (reference potential). The transfer unit 13 and the discharge unit 14 are composed of, for example, transistors M1 and M2, respectively. The readout unit 20 reads out a signal (photoelectric conversion signal) corresponding to the charge transferred from the photoelectric conversion unit 12 to the floating diffusion 15 by the transfer unit 13 onto the signal line 18.

[0018] FIG. 5 is a block diagram showing details of the configuration of the image sensor according to the first embodiment. The image sensor 3 includes a plurality of pixels 10, an AD conversion unit 70 provided for each pixel 10, an output unit 100, a timing generator 200, a DA conversion unit 210, a global counter 220, a sense amplifier 300, a line memory 310, and an input / output unit 320. The AD conversion unit 70 includes a comparison unit 40, a first storage unit 50, and a second storage unit 60. The first storage unit 50 and the second storage unit 60 are each composed of a latch circuit. In the present embodiment, for convenience, FIGS. 3 and 5 only show the first storage unit 50 and the second storage unit 60. The image sensor 3 is provided with a plurality of latch circuits (storage units) corresponding to the number of bits of the digital signal to be stored. Each of the plurality of latch circuits stores a 1-bit digital signal. In the present embodiment, for example, the third substrate 113 has five latch circuits in addition to the first storage unit 50, and a 6-bit digital signal is stored by the six latch circuits. The fourth substrate 114 has five latch circuits in addition to the second storage unit 60, and a 6-bit digital signal is stored by the six latch circuits. Therefore, the latch circuits included in the third substrate 113 and the fourth substrate 114 store a total of 12-bit digital signals.

[0019] In the first layer of the image sensor 3, that is, the first substrate 111, the pixel 10 and a part of the timing generator 200 are provided. The timing generator 200 is composed of a plurality of circuits and is arranged separately on the first substrate 111 to the fourth substrate 114. In FIG. 5, the first substrate 111, the second substrate 112, the third substrate 113, and the fourth substrate 114 are respectively referred to as the first layer, the second layer, the third layer, and the fourth layer. Each circuit constituting the timing generator 200 is arranged in the peripheral part of the region where the pixel 10 and the AD conversion unit 70 are arranged. In the second layer, that is, the second substrate 112, the comparison unit 40, the DA conversion unit 210, the global counter 220, and a part of the timing generator 200 are provided. When the arithmetic unit 80 is provided, similar to each circuit constituting the timing generator 200, the arithmetic unit 80 is arranged in the peripheral part.

[0020] The third substrate 113 is provided with a first memory unit 50 and a part of the timing generator 200. The fourth substrate 114 is provided with a second memory unit 60, an output unit 100, a part of the timing generator 200, a sense amplifier 300, a line memory 310, and an input / output unit 320. Also, the DA conversion unit 210, the global counter 220, the sense amplifier 300, the line memory 310, and the input / output unit 320 are arranged in the peripheral part of the area where the AD conversion unit 70 is arranged on each substrate.

[0021] The timing generator 200 is composed of a pulse generation circuit or the like, generates a pulse signal (clock signal) based on the register setting value output from the control unit 4 of the imaging device 1, and outputs it to each pixel 10, the comparison unit 40, the DA conversion unit 210, the global counter 220, etc. The register setting value is set according to, for example, the shutter speed (charge accumulation time of the photoelectric conversion unit), the ISO sensitivity, the presence or absence of image correction, etc. The DA conversion unit 210 generates a ramp signal whose signal level changes as a reference signal based on the pulse signal from the timing generator 200. Also, the DA conversion unit 210 is commonly connected to each comparison unit 40 provided for each pixel 10 and outputs the reference signal to each comparison unit 40. The global counter 220 generates a signal (e.g., a clock signal) indicating a count value based on the pulse signal from the timing generator 200 and outputs it to the first memory unit 50 and the second memory unit 60. The digital signals stored in the first memory unit 50 and the second memory unit 60 can be output to the signal line 122 by the output unit 100 provided for each pixel 10. When an arithmetic unit 80 is provided, it performs arithmetic operations (arithmetic operations) between the digital signals for each pixel 10 provided for each pixel 10 and output from the first memory unit 50 and the second memory unit 60. After the arithmetic operation between pixels, the arithmetic unit 80 outputs the signal obtained by the arithmetic operation to the sense amplifier 300 via the signal line 122.

[0022] The sense amplifier 300 is connected to the signal line 122 and reads the signal input to the signal line 122 at high speed by amplifying and reading it. The line memory 310 stores the signal read by the sense amplifier 300. The input / output unit 320 performs signal processing on the signal output from the line memory 310, such as adjusting the bit width of the signal and adding a synchronization code, and outputs it as an image signal to the control unit 4 of the imaging device 1. The input / output unit 320 is configured with input / output circuits that support high-speed interfaces such as LVDS and SLVS, and transmits signals at high speed.

[0023] Figure 6(a) shows the configuration of the AD conversion unit and global counter according to the first embodiment. In the example shown in Figure 6(a), the comparison unit 40 of the AD conversion unit 70 is composed of a comparator circuit. The first input terminal 41 of the comparison unit 40 receives the signal output from the pixel 10 via the signal line 18, and the second input terminal 42 receives the reference signal (ramp signal) from the DA conversion unit 210. The comparison unit 40 compares the signal output from the pixel 10 with the ramp signal, and when the level of the signal from the pixel 10 matches the level of the ramp signal, it shifts the potential of the output signal. The comparator output signal, which is the comparison result from the comparison unit 40, is input to the first storage unit 50 and the second storage unit 60 via a level shifter (not shown) and a signal line 121.

[0024] The first storage unit 50 and the second storage unit 60 store a count value as a digital signal based on the comparator output signal, corresponding to the elapsed time from the start of comparison by the comparison unit 40 until the inversion of the comparator output signal. In other words, the first storage unit 50 and the second storage unit 60 store a count value as a digital signal based on the signal output from the comparison unit 40, corresponding to the time until the relative magnitude relationship between the level of the signal output from the pixel 10 and the level of the ramp signal changes (inverts). The global counter 220 outputs multiple clock signals of different frequencies and measures the time until the relative magnitude relationship between the level of the signal from the pixel 10 and the level of the ramp signal changes using clock signals of different frequencies. The first storage unit 50 and the second storage unit 60 store the measured results as digital signals. In other words, multiple latch circuits, including the first storage unit 50 and the second storage unit 60, each store a digital signal based on the results measured with multiple clock signals of different frequencies.

[0025] Figure 6(b) is a timing chart showing an example of operation of the AD conversion unit according to the first embodiment. In Figure 6(b), the vertical axis represents the voltage level of the signal, and the horizontal axis represents time. Counter outputs 1 to 12 schematically represent the clock signals indicating the count values ​​output from the global counter 220. For example, counter outputs 1 to 6 indicate counter values ​​that constitute a part of the lower bits of the digital data and are input to a plurality of latch circuits, including the first storage unit 50. Counter outputs 7 to 12 indicate counter values ​​that constitute a part of the upper bits of the digital data and are input to a plurality of latch circuits, including the second storage unit 60. Here, the lower bits refer to the bits of the digital signal generated by the counter values ​​from counter outputs 1 to 6 among the counter outputs 1 to 12 output from the global counter 220. The frequency of the clock signals of counter outputs 1 to 6 is higher than the frequency of the clock signals of counter outputs 7 to 12. The upper bits refer to the bits of the digital signal generated by the counter values ​​from counter outputs 7 to 12 among the counter outputs 1 to 12 output from the global counter 220. The clock signal frequencies for counter outputs 7-12 are lower than those for counter outputs 1-6.

[0026] After the signal output from pixel 10 is input to the first input terminal 41 of the comparison unit 40, at time t1, the DA conversion unit 210 starts inputting a ramp signal (reference signal) whose signal level changes over time to the comparison unit 40. Also, the global counter 220 starts inputting counter outputs 1 to 12 to multiple latch circuits, including the first storage unit 50 and the second storage unit 60. During the period from time t1 to time t3, the potential (level) of the ramp signal decreases over time.

[0027] At time t2, when the potential of the signal from the pixel and the potential of the ramp signal are approximately equal, the comparison unit 40 transitions the potential of the comparator output signal to a high level. Multiple latch circuits, including the first storage unit 50 and the second storage unit 60, each store (hold) the count values ​​from counter outputs 1 to 12 when the comparator output signal changes from a low level to a high level. For example, the count value from counter output 1 is stored in the 1st bit latch circuit, the count value from counter output 2 is stored in the 2nd bit latch circuit, and the count value from counter output 12 is stored in the 12th bit latch circuit.

[0028] The signal line 121 through which the comparator output signal is transmitted connects the comparison unit 40 of the second substrate 112, the first storage unit 50 of the third substrate 113, and the second storage unit 60 of the fourth substrate 114, and is a signal line using through electrodes 110 and bumps as shown in Figure 2. On the fourth substrate 114, which is located far from the comparison unit 40 of the second substrate 112, delays, blurring, and variations between pixels occur in the comparator output signal due to parasitic capacitance of the wiring and interlayer junction capacitance. This causes a shift in the latch timing for the latch operation. In this embodiment, the first storage unit 50, which latches the lower bits of the digital signal, is placed on the third substrate 113, which is close to the comparison unit 40 of the second substrate 112. That is, the first storage unit 50, which latches using signals with relatively high frequencies among counter outputs 1 to counter outputs 12, is placed on the third substrate 113, which is close to the comparison unit 40, and the second storage unit 60, which latches using signals with relatively low frequencies, is placed on the fourth substrate 114.

[0029] The dashed line 45 in Figure 6(b) schematically shows the latch timing due to the comparator output signal input to the second storage unit 60 of the fourth board 114. The input timing of the comparator output signal to the second storage unit 60 may be delayed as shown by the dashed line 45. However, since the frequency of the signal indicating the count value input to the second storage unit 60 (for example, counter output 12) is low, that is, the change in the count value of the higher bits is slow, the effect of the latch timing shift can be reduced, and the conversion error of the AD conversion can be reduced. In this way, the effect of the signal delay of the comparator output signal from the comparison unit 40 can be reduced, and the accuracy of the AD conversion can be improved. Furthermore, in this embodiment, the first storage unit 50, which performs latching with a relatively high frequency signal, is placed on the same second board 112 as the global counter 220. Therefore, the effect of the signal delay of the count value from the global counter 220 can be reduced, and the accuracy of the AD conversion can be improved.

[0030] In this embodiment, the first storage unit 50 for lower bits is provided on the third layer 113, and the second storage unit 60 for higher bits is provided on the fourth layer 114. However, the reverse is also possible: the first storage unit 50 for lower bits is provided on the fourth layer 114, and the second storage unit 60 for higher bits is provided on the third layer 113. By arranging the first storage unit 50 and the second storage unit 60 on different substrates in this way, multiple storage units can be arranged without increasing the chip area, and the number of bits (resolution) of the AD conversion can be improved. Furthermore, the first storage unit 50 and the second storage unit 60 are stacked on the corresponding pixels 10. This prevents a decrease in the aperture ratio of the pixels 10.

[0031] According to the above-described embodiment, the following effects and advantages can be obtained. (1) The image sensor 3 includes a photoelectric conversion unit 12 that converts incident light into electric charge, a readout unit (readout unit 20) that reads out a signal based on the charge generated by the photoelectric conversion unit 12, a comparison unit 40 that outputs a signal based on a comparison between the signal read out by the readout unit and a reference signal, a first circuit layer (third substrate 113, wiring layer 143, wiring layer 144) having a first storage unit 50 that stores a first signal based on the signal output from the comparison unit 40, and a second circuit layer (fourth substrate 114, wiring layer 145) that is stacked on the first circuit layer and has a second storage unit 60 that stores a second signal based on the signal output from the comparison unit 40. In this embodiment, the first storage unit 50 and the second storage unit 60 are arranged on different substrates. Therefore, multiple storage units can be arranged without increasing the chip area, and the resolution of AD conversion can be improved.

[0032] (2) In this embodiment, of the first storage unit 50 and the second storage unit 60, the first storage unit 50, which stores the lower bits of the digital signal, is positioned close to the comparison unit 40. This reduces the influence of signal delay from the comparison unit 40 and enables high-precision AD conversion. (3) The first storage unit 50 and the second storage unit 60 are stacked on the corresponding pixels 10. This prevents a decrease in the aperture ratio of the pixels 10.

[0033] (4) The image sensor 3 includes an AD conversion unit 70 which has a photoelectric conversion unit 12 that converts incident light into electric charge, a readout unit (readout unit 20) that reads out a signal based on the charge generated by the photoelectric conversion unit 12, a comparison unit 40 that outputs a signal based on a comparison between the signal read out by the readout unit and a reference signal, a first circuit layer (third substrate 113, wiring layer 143, wiring layer 144) having a first storage unit 50 that stores a first signal based on the signal output from the comparison unit 40, and a second circuit layer (fourth substrate 114, wiring layer 145) that is stacked on the first circuit layer and has a second storage unit 60 that stores a second signal based on the signal output from the comparison unit 40. In this way, multiple storage units can be arranged without increasing the chip area, and the resolution of the AD conversion can be improved.

[0034] (5) The AD conversion unit 70 converts the signal read from the photoelectric conversion unit 12 into a digital signal of a predetermined number of bits. The first storage unit 50 stores the digital signals of the relatively lower bits of the predetermined number of bits as the first digital signal. The second storage unit 60 stores the digital signals of the relatively higher bits of the predetermined number of bits as the second digital signal. The first storage unit 50 is stacked between the photoelectric conversion unit 12 and the second storage unit 60. In this embodiment, the first storage unit 50, which stores the digital signals of the lower bits of the first storage unit 50 and the second storage unit 60, is stacked between the photoelectric conversion unit 12 and the second storage unit 60 and positioned close to the comparison unit 40. This reduces the influence of signal delay from the comparison unit 40 and enables high-precision AD conversion.

[0035] (Second Embodiment) The image sensor 3 according to the second embodiment will be described with reference to Figure 7. In the figure, parts that are the same as or equivalent to those in the first embodiment are given the same reference numerals, and the differences from the image sensor 3 according to the first embodiment will be mainly described. Figure 7 is a block diagram showing the details of the configuration of the image sensor according to the second embodiment. The image sensor 3 has a plurality of latch circuits including a signal storage unit 51 and a dark storage unit 52 that constitute the first storage unit 50, and a plurality of latch circuits including a signal storage unit 61 and a dark storage unit 62 that constitute the second storage unit 60.

[0036] The readout unit 20 of each pixel 10 sequentially reads out to the signal line 18 a signal corresponding to the charge transferred from the photoelectric conversion unit 12 to the floating diffusion 15 by the transfer unit 13 (photoelectric conversion signal) and a dark signal (noise signal) when the potential of the floating diffusion 15 is reset to the reset potential. The dark signal is used to correct the photoelectric conversion signal. The AD conversion unit 70 sequentially performs AD conversion on the photoelectric conversion signal and the dark signal, respectively. When performing AD conversion on the photoelectric conversion signal, the AD conversion unit 70 outputs the comparison result between the photoelectric conversion signal and the reference signal to the signal storage unit 51 and the signal storage unit 61 via the demultiplexers 53 and 63. When performing AD conversion on the dark signal, the AD conversion unit 70 outputs the comparison result between the dark signal and the reference signal to the dark storage unit 52 and the dark storage unit 62 via the demultiplexers 53 and 63.

[0037] The AD conversion unit 70 converts the photoelectric conversion signal into a digital signal of a predetermined number of bits and the dark signal into a digital signal of a predetermined number of bits. The AD conversion unit 70 stores the digital signal from the photoelectric conversion signal in the signal storage unit 51 and the signal storage unit 61, and stores the digital signal from the dark signal in the dark storage unit 52 and the dark storage unit 62. The operation of the AD conversion unit 70, the digital signals stored in the plurality of latch circuits including the signal storage unit 51 and the dark storage unit 52, and the digital signals stored in the plurality of latch circuits including the signal storage unit 61 and the dark storage unit 62 are the same as in the first embodiment.

[0038] Figure 8 is a diagram illustrating the configuration of digital signals stored by the first storage unit 50 and the second storage unit 60. In the example shown in Figures 7 and 8, the signal storage unit 51, the signal storage unit 61, the dark storage unit 52, and the dark storage unit 62 are composed of latch circuits, and the digital signals stored in each are 1-bit signals. In this embodiment, for convenience, Figure 7 only shows the signal storage unit 51, the signal storage unit 61, the dark storage unit 52, and the dark storage unit 62. Similar to the first embodiment, the image sensor 3 is provided with multiple latch circuits (storage units) corresponding to the number of bits of the digital signals to be stored. Each of the multiple latch circuits stores a 1-bit digital signal. In this embodiment, for example, the third substrate 113 has five latch circuits in addition to the signal storage unit 51, and five latch circuits in addition to the dark storage unit 52. The six latch circuits for signals store 6-bit digital signals generated using photoelectric conversion signals. The six latch circuits for the dark signal store a 6-bit digital signal generated using the dark signal. Similarly, the fourth board 114 has five latch circuits in addition to the signal storage unit 61, and five latch circuits in addition to the dark signal storage unit 62. The six latch circuits for the signal store a 6-bit digital signal generated using the photoelectric conversion signal. The six latch circuits for the dark signal store a 6-bit digital signal generated using the dark signal. The signal storage unit 61 and the dark signal storage unit 62 are located on the fourth board 114, which is further from the comparison unit 40 than the signal storage unit 51 and the dark signal storage unit 52. Therefore, AD conversion errors due to delays in the comparator output signal may occur in the signals stored in the signal storage unit 61 and the dark signal storage unit 62.

[0039] Multiple latch circuits, including the signal storage unit 51, store the lower 6 bits of the digital signal S1 obtained from the photoelectric conversion signal. Multiple latch circuits, including the signal storage unit 61, store the signal (S2+N) which is the sum of the upper 6 bits of the signal S2 obtained from the photoelectric conversion signal and the delay error N which is the AD conversion error. In addition, multiple latch circuits, including the dark signal storage unit 52, store the lower 6 bits of the digital signal D1 obtained from the dark signal. Multiple latch circuits, including the dark signal storage unit 62, store the signal (D2+N) which is the sum of the upper 6 bits of the signal D2 obtained from the dark signal and the delay error N which is the AD conversion error. Therefore, as shown in Figure 8(a), signal S1 and signal (S2+N) constitute a 12-bit digital signal obtained from the photoelectric conversion signal. Also, as shown in Figure 8(b), signal D1 and signal (D2+N) constitute a 12-bit digital signal obtained from the dark signal.

[0040] The arithmetic unit 80 performs correlated double sampling (CDS), or digital CDS, by subtracting the digital signal of the photoelectric conversion signal from the digital signal of the dark signal. The arithmetic unit 80 generates a correction signal by subtracting the digital signal corresponding to the photoelectric conversion signal output from multiple latch circuits including the signal storage unit 51 and multiple latch circuits including the signal storage unit 61 from the digital signal corresponding to the dark signal output from multiple latch circuits including the dark storage unit 52 and multiple latch circuits including the dark storage unit 62. For example, the arithmetic unit 80 subtracts the signal S1 from multiple latch circuits including the signal storage unit 51 from the signal D1 from multiple latch circuits including the dark storage unit 52 to obtain a signal A1 (=S1-D1) that constitutes the lower 6 bits of the correction signal. Furthermore, the arithmetic unit 80 subtracts the signals (S2+N) from multiple latch circuits, including the signal storage unit 61, from the signals (D2+N) from multiple latch circuits, including the dark memory unit 62, to obtain signal A2 (=S2-D2), which constitutes the upper 6 bits of the correction signal. By subtracting the signals (S2+N) from the signals (D2+N), the delay error N, which is the AD conversion error, can be removed. As a result, the correction signal after CDS processing is composed of signals A1 (=S1-D1) and A2 (=S2-D2).

[0041] If the storage unit for storing the digital signal of the photoelectric conversion signal and the storage unit for storing the digital signal of the dark signal are placed on different substrates, a delay error N will be included in either the digital signal or the dark signal, making it impossible to remove the delay error N by CDS processing. In this embodiment, the signal storage unit 51 for storing the lower bit signal and the dark signal storage unit 52 are placed on the third substrate 113, and the signal storage unit 61 for storing the upper bit signal and the dark signal storage unit 62 are placed on the fourth substrate 114. Therefore, the delay error N can be removed by CDS processing, and the accuracy of AD conversion can be improved.

[0042] In the second embodiment, a signal storage unit 51 for the lower bits of the digital signal of the photoelectric conversion signal and a dark storage unit 52 for the lower bits of the digital signal of the dark signal are provided on the third substrate 113, and a signal storage unit 61 for the upper bits of the digital signal of the photoelectric conversion signal and a dark storage unit 62 for the upper bits of the digital signal of the dark signal are provided on the fourth substrate 114. Alternatively, the signal storage unit 51 for the lower bits of the digital signal of the photoelectric conversion signal and the dark storage unit 52 for the lower bits of the digital signal of the dark signal may be provided on the fourth substrate 114, and the signal storage unit 61 for the upper bits of the digital signal of the photoelectric conversion signal and the dark storage unit 62 for the upper bits of the digital signal of the dark signal may be provided on the third substrate 113. Even in this case, there is a risk of errors occurring in the signal storage unit 51 for lower bits and the dark memory unit 52 for lower bits of the fourth substrate 114 due to signal delay. However, these signal delay errors are approximately equal in the signal storage unit 51 and the dark memory unit 52 for lower bits, which are provided on the same substrate, and can be removed by CDS processing.

[0043] According to the above-described embodiment, in addition to the same effects and advantages as in the first embodiment, the following effects and advantages can be obtained. (6) The signal read out from the photoelectric conversion unit 12 includes a photoelectric conversion signal and a noise signal. The image sensor 3 has a first storage unit for the photoelectric conversion signal (signal storage unit 51) and a first storage unit for the noise signal (dark storage unit 52), which store the first digital signal of the photoelectric conversion signal and the first digital signal of the noise signal, respectively, based on the comparison result of the comparison unit 40. The image sensor 3 also has a second storage unit for the photoelectric conversion signal (signal storage unit 61) and a second storage unit for the noise signal (dark storage unit 62), which store the second digital signal of the photoelectric conversion signal and the second digital signal of the noise signal, respectively, based on the comparison result of the comparison unit 40. The first storage unit for the photoelectric conversion signal and the first storage unit for the noise signal are provided on the same substrate (first circuit layer), and the second storage unit for the photoelectric conversion signal and the second storage unit for the noise signal are provided on the same substrate (second circuit layer). By doing so, the delay error N can be removed by CDS processing, thereby improving the accuracy of AD conversion.

[0044] (7) The image sensor 3 further includes a calculation unit (calculation unit 80) that calculates the difference between the first digital signal of the photoelectric conversion signal and the first digital signal of the noise signal stored in the first memory unit 50, and calculates the difference between the second digital signal of the photoelectric conversion signal and the second digital signal of the noise signal stored in the second memory unit 60. In this way, the delay error N can be removed by the calculation unit 80.

[0045] The following modifications are also within the scope of the present invention, and it is possible to combine one or more of these modifications with the embodiments described above.

[0046] (Variation 1) Figure 9 is a block diagram showing the details of the configuration of the image sensor according to Modification 1. In the image sensor 3 according to Modification 1, a delay error N due to the delay of the comparator output signal is calculated, and the digital signal is corrected using the delay error N. The image sensor 3 has a first switch unit 31, a second switch unit 32, an error amount calculation unit 340, and an error amount correction unit 350. The first switch unit 31 and the second switch unit 32 are each composed of transistors or the like. When calculating the delay error N, the first switch unit 31 is turned on and the second switch unit 32 is turned off. As a result, the same clock signal is input from the global counter 220 to the first storage unit 50 of the third board 113 and the second storage unit 60 of the fourth board 114. The first storage unit 50 and the second storage unit 60 each perform latching operations using clock signals that indicate the same count value to each other. The digital signals stored in the first storage unit 50 and the second storage unit 60 are output to the line memory 310 via the sense amplifier 300.

[0047] The error amount calculation unit 340 reads the count value from the first storage unit 50 and the count value from the second storage unit 60 from the line memory 310 and calculates the delay error N by subtracting each count value. The error amount calculation unit 340 stores the calculated delay error N in the memory 341. Note that the delay error N in the memory 341 may be stored in advance at the time of product shipment or before shooting. During the actual shooting, the first switch unit 31 is turned off and the second switch unit 32 is turned on. Once the actual shooting is performed and the digital signal is stored in the line memory 310, the error amount correction unit 350 corrects the signal using the delay error N stored in the error amount calculation unit 340. For example, the delay error N is subtracted from the digital data stored in the line memory 310. The error amount correction unit 350 also outputs the corrected signal as an image signal to the input / output unit 320. In this way, the delay error N caused by the delay of the comparator output signal can be removed.

[0048] (Modification 2) In the image sensor 3 according to Modification 1, an example was described in which the error amount calculation unit 340 calculates the delay error N due to the delay of the comparator output signal, and the error amount correction unit 350 corrects the digital signal using the delay error N. However, the arithmetic unit 80 may be configured to calculate the delay error N and correct the digital signal using the delay error N. That is, the arithmetic unit 80 functionally has the error amount calculation unit 340 and the error amount correction unit 350. In this case, as in Modification 1, the first storage unit 50 and the second storage unit 60 are made to perform latching operations using a clock signal indicating the same count value, and the digital signals stored in each are output to the arithmetic unit 80.

[0049] The arithmetic unit 80 calculates the delay error N by subtracting the count value from the first storage unit 50 and the count value from the second storage unit 60. The arithmetic unit 80 also stores the calculated delay error N in an internal latch circuit or the like. The storage of the delay error N may be done in advance at the time of product shipment or before shooting. During actual shooting, the arithmetic unit 80 corrects the signal using the delay error N. For example, it subtracts the delay error N from the digital signal from the second storage unit 60. In this way, the delay error N caused by the delay of the comparator output signal can be removed.

[0050] (Variation 3) In the embodiment described above, an example was described in which four substrates are stacked, with the first substrate 111 having pixels 10, the second substrate 112 having a comparison unit 40, the third substrate 113 having multiple storage units (latch circuits) including the first storage unit 50, and the fourth substrate 114 having multiple storage units (latch circuits) including the second storage unit 60. However, the number of substrates is not limited to four. The image sensor 3 only needs to have two or more substrates stacked. For example, the pixels 10 and the comparison unit 40 may be provided on the same substrate. Also, the comparison unit 40 and the first storage unit 50 may be provided on the same substrate. The photoelectric conversion unit 12, the comparison unit 40, and the first storage unit 50 may be provided on the same substrate. Also, the first storage unit 50 and the second storage unit 60 may be provided on the same substrate. In this case, the first storage unit 50 is provided in a position closer to the comparison unit 40 than to the second storage unit 60. The image sensor may be configured by stacking a substrate having a comparison unit 40 and a substrate having a memory unit (latch circuit). By using a stacked AD conversion unit with a circuit layer having a comparison unit 40 and a circuit layer having a memory unit, multiple memory units can be arranged without increasing the chip area, and the resolution of the AD conversion can be improved. Furthermore, there may be three or more boards having memory units (latch circuits), including the third board 113 and the fourth board 114. For example, 12 memory units (latch circuits) for storing 12-bit digital signals may be provided in groups of four on each of the three boards, or in groups of one on each of the twelve boards.

[0051] In the embodiment described above, an example was described in which a first storage unit 50 corresponding to the lower bits and a second storage unit 60 corresponding to the upper bits are provided. However, a third storage unit may be provided to store the digital signals of the middle bits relative to the upper and lower bits. In this case, based on the signal output from the comparison unit 40, the time until the relative magnitudes of the signal output from the pixel 10 and the reference signal change is measured using a third-frequency clock signal with a lower frequency than the second-frequency clock signal. The third storage unit stores the third signal based on the result measured with the third-frequency clock signal. The digital signal based on the first-frequency clock signal is the digital signal of the lower bits, the digital signal based on the second-frequency clock signal is the digital signal of the middle bits, and the digital signal based on the third-frequency clock signal is the digital signal of the upper bits.

[0052] The first, second, and third storage units may be arranged on different substrates. The substrate having the second storage unit 60 may be provided between the substrate having the first storage unit 50 and the substrate having the third storage unit, such that the second storage unit 60 is located between the first storage unit 50 and the third storage unit. The first storage unit 50 and the second storage unit 60 may be provided on the same substrate, while only the third storage unit is provided on a different substrate. The first storage unit 50 is provided closer to the comparison unit 40 than the second storage unit 60. Furthermore, the substrate having the first storage unit 50 and the second storage unit 60 may be provided between the substrate having the comparison unit 40 and the substrate having the third storage unit. The second storage unit 60 and the third storage unit may be provided on the same substrate.

[0053] (Modification 4) The above-described embodiment explained an example of performing AD conversion to a 12-bit digital signal. However, the same method can be applied to AD conversion of any number of bits. Multiple latch circuits (storage units) corresponding to any number of bits may be provided. The number of latch circuits in the third board 113 and the fourth board 114 can be any number. For example, in the first embodiment, the number of latch circuits in the third board 113 and the fourth board 114 is not limited to 6. The number of latch circuits in the third board 113 and the fourth board 114 may be less than 6 or 6 or more. Therefore, the total number of digital signals stored in the latch circuits of the third board 113 and the fourth board 114 may be less than 12 bits or 12 bits or more.

[0054] Furthermore, when the first storage unit 50 and the second storage unit 60 are arranged on different substrates, multiple latch circuits, etc., corresponding to any number of bits, may be arranged separately on different substrates. The number of latch circuits including the first storage unit 50 on the third substrate 113 may be different from the number of latch circuits including the second storage unit 60 on the fourth substrate 114. For example, the third substrate 113 may have eight latch circuits including the first storage unit 50, and the fourth substrate 114 may have six latch circuits including the second storage unit 60. Similarly, in the second embodiment, even when the photoelectric conversion signal is converted to a 12-bit digital signal and the dark signal is converted to an 8-bit digital signal, the number of latch circuits is not limited. The number of latch circuits for the dark signal including the dark storage unit 52 on the third substrate 113 may be different from the number of latch circuits for the dark signal including the dark storage unit 62 on the fourth substrate 114. For example, the third substrate 113 may have six signal latch circuits including the signal storage unit 51 and six dark latch circuits including the dark storage unit 52. The fourth board 114 may have six signal latch circuits, including a signal memory unit 61, and two dark latch circuits, including a dark memory unit 62. Alternatively, the dark memory unit 52 may be provided only on the third board 113. The fourth board 114 does not need to have a dark memory unit 62. The number of signal memory units and the number of dark memory units on the third board 113 or the fourth board 114 may differ.

[0055] (Variation 5) In the embodiment described above, an example was described in which the image sensor 3 is a back-illuminated type. However, the image sensor 3 may also be a front-illuminated type in which the wiring layer 140 is provided on the incident surface side into which light enters.

[0056] (Experimental variation 6) In the embodiment described above, an example was given in which a photodiode is used as the photoelectric conversion unit 12. However, a photoelectric conversion film may also be used as the photoelectric conversion unit 12.

[0057] (Example 7) The image sensor 3 described in the above embodiment may be applied to cameras, smartphones, tablets, cameras built into PCs, in-vehicle cameras, etc.

[0058] Although various embodiments and modifications have been described above, the present invention is not limited to these. Other embodiments conceivable within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention.

[0059] The disclosures of the following priority application are incorporated herein by reference. Japanese Patent Application No. 65491 of 2016 (filed March 29, 2016) [Explanation of symbols]

[0060] 3 Image sensor, 12 Photoelectric conversion unit, 10 Pixel, 40 Comparison unit, 50 First memory unit, 60 Second memory unit, 70 AD conversion unit, 80 Processing unit

Claims

[Claim 1] A first substrate having multiple pixels, each containing a photoelectric conversion unit that converts light into electric charge, A second substrate laminated together with the first substrate, having a first comparison unit used to convert a signal output from a first pixel among the plurality of pixels into a digital signal, A third substrate laminated together with the first substrate, having a first storage unit that stores a first digital signal converted from a signal output from the first pixel using the first comparison unit, A fourth substrate laminated together with the first substrate, the fourth substrate having a second storage unit that stores a second digital signal converted from a signal output from the first pixel using the first comparison unit. An image sensor equipped with the following features.

Images