Successive approximation register analog-to-digital converter

Abstract

A SAR ADC is provided that converts a received analog input signal into a digital output signal, including a DAC that converts the received analog signal into a DAC output signal; the pre-amplifier circuit comprises a plurality of pre-amplifiers which are arranged in series; a primary latch comparator comparing the received final preamplifier output signal with a primary reference voltage to generate a primary latch output signal; the secondary latch comparator is used for comparing the received preamplifier output signal with a secondary reference voltage to generate a secondary latch output signal; and an SAR engine receiving the latched output signals from the primary latched comparator and the secondary latched comparator and generating a digital output code representing the analog input signal, the SAR engine determining each of the plurality of bits using one latched output signal, the SAR engine determining at least the MSB using the secondary latched output signal.

Description

Technical Field

[0001] This disclosure relates to a successive approximation register analog-to-digital converter (SAR ADC) configured to convert a received analog input signal into a digital output signal comprising multiple bits. This disclosure also relates to an apparatus including a SAR ADC. Background Technology

[0002] SAR ADCs are popular due to their high resolution and accuracy. The figure of merit (FoM) can be used for rapid comparisons between similar ADCs. FoM provides insight into trade-offs between various parameters such as power consumption, signal bandwidth, and spectral purity. FoM can also be used to highlight performance trends and indicate architectural strengths and weaknesses. One such FoM is equivalent to SNDR. dB +10*log(2f sig / P). SNDR dB Signal-to-noise ratio (SNR) is measured in decibels. This term quantifies the quality of an ADC output by comparing the power of the desired signal with the power of the noise and distortion components. sig This is the frequency of the input analog signal converted by the ADC. P represents the ADC's power consumption. The comparator in a SAR ADC typically determines the power consumption. The number of clock cycles and the clock frequency used for conversion affect the conversion speed itself. Typical ADC solutions are limited by power and speed constraints imposed by the least significant bit conversion. Summary of the Invention

[0003] According to a first aspect of this disclosure, a successive approximation register analog-to-digital converter (SAR ADC) is provided, the SAR ADC being configured to convert a received analog input signal into a digital output signal comprising a plurality of bits, the plurality of bits including bits from the most significant bit (MSB) to the least significant bit (LSB), the SAR ADC... The ADC includes: a digital-to-analog converter (DAC) configured to convert the received analog signal into a DAC output signal; a preamplifier circuit including a plurality of preamplifiers arranged in series, wherein: each preamplifier is configured to apply a gain to a signal received at its input node; a first preamplifier of the plurality of preamplifiers is configured to receive the DAC output signal from the DAC at its input node and provide a first preamplifier output signal at its output node; each of the other preamplifiers of the plurality of preamplifiers is configured to receive an output signal from the preceding preamplifier of the plurality of preamplifiers arranged in series; and a final preamplifier of the plurality of preamplifiers is configured to provide a final preamplifier output signal at the output node of the preamplifier circuit; a primary latch comparator receiving the final preamplifier output signal from the output node of the preamplifier circuit, wherein the primary latch comparator is configured to receive the received final preamplifier output signal... A primary latch comparator is compared with a primary reference voltage, and wherein the primary latch comparator is further configured to generate a primary latch output signal based on the comparison; a secondary latch comparator receives a preamplifier output signal from one of the plurality of preamplifiers other than the final preamplifier, and wherein the secondary latch comparator is configured to compare the received preamplifier output signal with a secondary reference voltage, and wherein the secondary latch comparator is further configured to generate a secondary latch output signal based on the comparison; a SAR engine is configured to receive the primary latch output signal from the primary latch comparator and the secondary latch output signal from the secondary latch comparator, and is further configured to generate a digital output code representing the analog input signal based on the primary latch output signal and the secondary latch output signal, wherein the SAR engine is configured to use only one of the latch output signals to determine each of the plurality of bits, and wherein the SAR engine is configured to use the secondary latch output signal to determine at least the MSB.

[0004] In one or more embodiments, the secondary latch comparator may be configured to receive a first preamplifier signal from the first preamplifier.

[0005] In one or more embodiments, the SAR engine can be configured to use the secondary latch output signal to determine I most significant bits among the plurality of bits, where I is greater than 1 but less than the number of bits among the plurality of bits.

[0006] In one or more embodiments, the preamplifier circuit may further include at least three preamplifiers; the SAR ADC may further include a three-stage latch comparator configured to receive a preamplifier output signal from a later preamplifier among the series-connected plurality of preamplifiers, the later preamplifier being arranged after the preamplifier from which the secondary latch comparator receives the preamplifier output signal, and wherein the three-stage latch comparator is configured to compare the received preamplifier output signal with a three-stage reference voltage; and wherein the three-stage latch comparator is further configured to generate a three-stage latch output signal based on the comparison; and wherein the three-stage latch comparator may be configured to provide the three-stage latch output signal to the SAR engine for J second-most significant bits, wherein M is at least equal to 1 and wherein M is at most equal to NI, wherein N is equal to the number of bits among the plurality of bits.

[0007] In one or more embodiments, for each bit of the secondary latch output signal used by the SAR engine, one or more of the preamplifiers arranged after the preamplifier from which the preamplifier output signal can be received by the secondary latch comparator are configured to operate in a low-power mode.

[0008] In one or more embodiments, for each bit of the secondary latch output signal used by the SAR engine, current may be shunted from one or more of the preamplifiers configured to operate in low-power mode to the secondary latch comparator.

[0009] In one or more embodiments, for each bit of the SAR engine using the three-stage latch output signal, one or more of the preamplifiers arranged after the preamplifier from which the preamplifier output signal can be received by the three-stage latch comparator are configured to operate in low-power mode.

[0010] In one or more embodiments, each latch comparator may be configured to compare the received amplified output signal with a corresponding reference voltage within one or more clock cycles to generate the latched output signal, wherein the primary latch comparator compares the received amplified output signal with the primary reference voltage within more clock cycles than the clock cycles used by the secondary latch comparator to compare the received amplified output signal with the secondary reference voltage.

[0011] In one or more embodiments, the DAC may include one or more redundant bits.

[0012] In one or more embodiments, the DAC may be a capacitive digital-to-analog converter.

[0013] In one or more embodiments, the SAR engine may be an asynchronous SAR engine.

[0014] According to a second aspect of this disclosure, an apparatus is provided, comprising a SAR ADC as described in any of the preceding technical solutions.

[0015] While this disclosure allows for various modifications and alternatives, details have been illustrated by way of example in the drawings and will be described in detail. However, it should be understood that other embodiments besides the specific embodiments described are also possible. All modifications, equivalents, and alternative embodiments falling within the spirit and scope of the appended claims are also covered.

[0016] The foregoing discussion is not intended to represent every exemplary embodiment or every implementation within the scope of the present or future claims. Various exemplary embodiments are further illustrated in the following figures and detailed description. A more comprehensive understanding of these various exemplary embodiments can be achieved by considering the following detailed description in conjunction with the figures. Attached Figure Description

[0017] One or more embodiments will now be described with reference to the accompanying drawings, by way of example only, in which:

[0018] Figure 1 An example embodiment of the SAR ADC of this disclosure is shown;

[0019] Figure 2 An example capacitive digital-to-analog converter is shown;

[0020] Figure 3 Another example timing diagram of the SAR ADC of this disclosure is shown; and

[0021] Figure 4 An example device incorporating the SAR ADC of this disclosure is shown. Detailed Implementation

[0022] Figure 1An example SAR ADC 100, according to this disclosure, is illustrated and configured to convert a received analog input signal into a digital output signal comprising multiple bits. The multiple bits include bits from the most significant bit (MSB) to the least significant bit (LSB). For example, the SAR ADC 100 can be configured to convert an analog signal (VIN) (e.g., a momentary held value of an analog signal) into a digital output code, which is a digital signal representing the analog input signal. The number of bits can be selected based on the implementation, but can be, for example, 8 bits or 12 bits.

[0023] The SAR ADC 100 includes a digital-to-analog converter (DAC) 101 for converting a received analog signal into a DAC output signal. In one or more embodiments, the DAC may be a capacitive digital-to-analog converter (CDAC). Other DAC types, such as a resistor DAC (RDAC), may also be used. The DAC 101 may also receive one or more reference voltages (VH, VL) and an input voltage VIN used in the SAR ADC 100. The DAC 101 can perform sampling and holding of the analog input voltage. Sampling and holding of the received analog input voltage can be performed in any suitable manner, such as through a capacitor array.

[0024] Figure 2 An example CDAC 200 is shown, where a capacitor is capable of sampling and holding the input voltage, and successive approximation is performed using bits from bit n-1 to bit 0. The DAC may include one or more redundant bits. Redundant bits can reduce or eliminate any accuracy loss that may be introduced by offset errors due to the use of different preamplifier and latch combinations. Although Figure 2 The example embodiment depicted illustrates a differential DAC, but a single-ended DAC can be used in other embodiments.

[0025] Return to Figure 1The SAR ADC 100 further includes a preamplifier circuit 102 comprising a plurality of preamplifiers connected in series, each configured to apply a gain to a signal received at its input node. Each preamplifier includes an input node configured to receive a signal and an output node from which it provides the preamplifier's output signal. The gain can be any suitable gain that increases the amplitude of the input signal. A first preamplifier 102A of the plurality of preamplifiers is configured to receive a DAC output signal from the DAC 101 at its input node. The first preamplifier 102A also provides a first preamplifier output signal at its output node. Each preamplifier other than the first preamplifier 102A is configured to receive an output signal from the preceding preamplifier of the plurality of preamplifiers arranged in series and provide a corresponding output signal at its output node. A final preamplifier 102D of the plurality of preamplifiers is configured to provide a final preamplifier output signal at the output node of the preamplifier circuit 102.

[0026] Multiple preamplifiers may include two, three, four, or any other suitable number of preamplifiers to achieve the desired signal amplification. In an embodiment where multiple preamplifiers include two preamplifiers, the first preamplifier is a first preamplifier, and the second preamplifier is a final preamplifier.

[0027] In one or more embodiments, each preamplifier can amplify the input signal received at its input node based on the difference between the input signal and a reference voltage. The reference voltage can be a reference voltage generated by DAC 101.

[0028] The SAR ADC 100 further includes a primary latch comparator 103 configured to receive a final preamplifier output signal from the output node of the preamplifier circuit 102. The primary latch comparator 103 is configured to compare the received final preamplifier output signal with a primary reference voltage, and based on the comparison, the primary latch comparator 103 is configured to generate a primary latch output signal. The primary latch output signal may be a digital signal, such as a binary signal, indicating whether the input signal is higher or lower than the reference voltage.

[0029] The SAR ADC 100 also includes a secondary latch comparator 104 configured to receive a preamplifier output signal from one of a plurality of preamplifiers, excluding the final preamplifier. The secondary latch comparator 104 is configured to compare the received first preamplifier output signal with a secondary reference voltage, and based on the comparison, the secondary latch comparator 104 is configured to generate a secondary latch output signal. The secondary latch output signal may be a digital signal, such as a binary signal, indicating whether the input signal is higher or lower than the reference voltage.

[0030] The secondary latch comparator can be positioned between two preamplifiers in a plurality of preamplifiers. When the signal amplitude of the preamplifier output signal from the preamplifier immediately preceding the secondary latch comparator 104 is sufficiently large, the secondary latch comparator 104 can be used to generate the secondary latch output signal instead of the primary latch comparator 103. This approach allows the preamplifier following the preamplifier whose output signal is supplied to the secondary latch comparator to be turned off or operated in a low-power mode. Operation of one or more preamplifiers in low-power mode can include reducing the current supplied to the preamplifier. In one or more examples, when one or more preamplifiers operate in low-power mode, current can be shunted from one or more preamplifiers configured to operate in low-power mode to the secondary latch comparator 104. By implementing this current shunting, the secondary latch comparator 104 can improve the operation of the secondary comparator output signal. Implementing current shunting reduces the response time of the latch comparator, thereby allowing the latch comparator to make decisions more quickly. This can improve the overall speed of the SAR ADC 100, thereby enabling a higher sampling rate.

[0031] In one or more embodiments, the secondary latch comparator 104 may be configured to receive a first preamplifier signal from a first preamplifier 102A. That is, the secondary latch comparator 104 may be arranged between the first preamplifier 102A and the second preamplifier 102B in a plurality of preamplifiers. It should be understood that, in other embodiments, the secondary latch comparator 104 may be arranged between any two other preamplifiers in a plurality of preamplifiers arranged in series to receive the preamplifier output signal of the first preamplifier in two selected preamplifiers.

[0032] The SAR ADC 100 may further include a SAR engine 106, which is configured to receive a primary latch output signal from a primary latch comparator 103 and a secondary latch output signal from a secondary latch comparator 104. The SAR engine 160 may be configured to generate a digital output code representing the analog input signal based on the primary and secondary latch output signals. That is, the final digital output code, comprising multiple bits, will be based on the signals received from both the primary latch comparator 103 and the secondary latch comparator 104.

[0033] SAR engine 106 is further configured to use only one latch output signal to determine each of the plurality of bits. SAR engine 106 is also configured to use a secondary latch output signal to determine at least the MSB. Therefore, for each bit, SARADC 100 can be configured to determine whether the bit is processed by primary latch comparator 103 or secondary latch comparator 104 (or any additional latch comparators described below). In one or more embodiments, this determination can be made dynamically based on a comparison of the signal amplitude of each bit with an acceptable signal amplitude threshold.

[0034] In one or more embodiments, SAR engine 106 may be an asynchronous SAR engine.

[0035] In other embodiments, the ADC engine 106 may be pre-determined for each bit to use the primary latch comparator 104, the secondary latch comparator, or any other latch comparator. In one or more embodiments, for example, the SAR engine 106 may be configured to use the secondary latch output signal to determine I most significant bits out of a plurality of bits, where I is greater than 1 but less than the number of bits in the plurality of bits. That is, in one or more embodiments, the SAR engine 106 may be configured to use the primary latch output signal to determine at least one bit out of a plurality of bits. The pre-determination of which latch comparator to use for each bit may be user-selectable or based on the means in which the SAR ADC is used. Thus, the SAR ADC of this disclosure can provide a flexible SAR ADC that can be tuned or otherwise adapted to meet user or specification requirements related to trade-offs between speed, power, and accuracy.

[0036] In one or more embodiments of this disclosure, the preamplifier circuit 102 may include at least three preamplifiers. The preamplifier circuit may additionally include a three-stage latch comparator 105 configured to receive a preamplifier output signal from a later preamplifier among a plurality of preamplifiers arranged in series, the later preamplifier being arranged after the preamplifier from which the secondary latch comparator 104 receives the preamplifier output signal. That is, the three-stage latch comparator 105 may be arranged downstream of the secondary latch comparator 104. The three-stage latch comparator 105 may be configured to compare the received preamplifier output signal with a three-stage reference voltage and generate a three-stage latched output signal based on the comparison. The three-stage latch comparator 105 may be configured to provide the three-stage latched output signal to the SAR engine 106 for J most significant bits, where M is at least equal to 1 and where M is at most equal to NI, where N is the number of bits in the plurality of bits. In other words, the three-stage latch output signal provided by the three-stage latch comparator 105 can be used by the SAR engine 106 for bits following the I most significant bits. The bits for which the three-stage latch output signal is used can be the remaining bits, or a subset of the remaining bits. The number of bits processed by the three-stage latch comparator 106 can be J bits. The J bits processed by the three-stage latch comparator 106 can be the bits immediately following the I bits processed by the secondary latch comparator 104.

[0037] In yet another embodiment, each preamplifier other than the final preamplifier 102D may include a latch comparator disposed thereafter, such that each preamplifier other than the final latch comparator 102D can provide its preamplifier output signal to the corresponding latch comparator. Each corresponding latch comparator may be configured to receive the preamplifier output signal from its preceding preamplifier and compare the received preamplifier output signal with a corresponding reference voltage. Based on the comparison, each latch comparator may be configured to provide a corresponding latched output signal to the SAR engine 106. The features and functionality described above with respect to the secondary latch comparator 104 or the tertiary latch comparator 105 are equally applicable to the additional latch comparators.

[0038] By providing a three-stage latch comparator 105 disposed between two preamplifiers, a three-stage latched output signal can be generated using the three-stage latch comparator 105 instead of the primary latch comparator 103, provided that the signal amplitude of the preamplifier output signal from the preamplifier immediately preceding the three-stage latch comparator 105 is sufficiently large. This approach allows the preamplifier following the preamplifier that provides the preamplifier output signal to the three-stage latch comparator 105 to be turned off or operated in a low-power mode. Operation of one or more preamplifiers in low-power mode may include reducing the current supplied to the latch comparator.

[0039] Figure 3 Timing diagram 300 is shown, illustrating the number of clock cycles required for each process during the operation of the SAR ADC. It should be noted that an asynchronous solution utilizing an asynchronous SAR engine can also be used when bit timing is not clock-dependent. In this asynchronous solution, the preamplifier and latch are self-tied. The SAR engine moves from preamplifier to latch based on self-generated preamplifier timing, and then moves to the next bit decision when the latch signals its completion.

[0040] The first line, 301, shows the SAR ADC clock signal as a repetitive signal that synchronizes the operation within the SAR ADC. Each rising or falling edge of the clock signal can trigger a specific action during the conversion process. In asynchronous solutions utilizing an asynchronous SAR engine, the timing ratio may be similar, but the specific actions of the conversion process (after sampling is complete) will be triggered by a self-timing signal.

[0041] Line 2, 302, shows the sampling signal, indicating when the analog input signal is sampled. During the high state of this signal, the ADC can capture the analog input voltage. As mentioned earlier, this can be achieved using a capacitor array or other methods.

[0042] The third line, 303, shows the auto-zero (az) signal, which can be used to calibrate the ADC's internal circuitry to reduce or eliminate offset errors. When this signal is high, the ADC performs auto-zeroing.

[0043] The fourth line, 304, shows the comparator signal, which indicates when the SAR ADC operates in comparator mode, during which an n-bit data decision is made.

[0044] Line 5, 305, shows the preamplifier reset signal, which is configured to reset the preamplifier and prepare the corresponding preamplifier for high-speed amplification of its input voltage. When the signal is high, the corresponding preamplifier remains in the reset state. The reset signal can be set high after each bit transition of the multi-bit signal.

[0045] Line 6, 306, shows a low-level active reset latch signal, configured to hold the latch in a reset state until a comparison is to be performed. The rising edge of these signals triggers the corresponding latch to perform a comparison. The operating state of the latch comparator can also be controlled based on the reset latch signal.

[0046] Line 7, 307 shows the Comparator Output (CMPO) signal, which indicates the result of a comparison performed at each bit level by a latch comparator used for that bit. The transition between high and low states indicates whether the input voltage is higher or lower than the reference voltage at each step of the successive approximation process.

[0047] Line 8, 308, shows the Ccode=n-1:0 signal, which indicates the digital output code after all bits have been determined through a successive approximation process. (Symbol) <n-1:0>The specified code includes all bits from MSB (bit n-1) to LSB (bit 0).

[0048] The timing diagram 300 is divided into three columns 309, 310, and 311. The first column 309 represents the processing of bits n-1 (MSB) to ni (the i-th most significant bit, as described above). These bits can be processed by the secondary latch comparator 104 and can be processed, for example, within 3 clock cycles. The second column 310 shows bits n-(i+1) to n-(i+j), which, as described above, are the N+1 and I+J bits. These bits can be processed by the third-level latch comparator 105 within, for example, 5 clock cycles. The third column 311 shows bits n-(i+j+1) to n-(i+j+k). These bits can be processed by the primary latch comparator 103 (in embodiments that do not include additional latch comparators) and can be processed, for example, within 8 clock cycles.

[0049] More generally, each latch comparator 103, 104, 105 can be configured to compare the received amplified output signal with a corresponding reference voltage within one or more clock cycles to generate its latched output signal. The primary latch comparator 103 can compare the received amplified output signal with the primary reference voltage within more clock cycles than the secondary latch comparator 104 uses to compare the received amplified output signal with the secondary reference voltage. Similarly, the tertiary latch comparator 105 can compare the received amplified output signal with the primary reference voltage within more clock cycles than the secondary latch comparator and fewer clock cycles than the primary latch comparator 103. Therefore, among all latch comparators 103, 104, 105, the secondary latch comparator 104 can compare its received amplified output signal with the secondary reference voltage within fewer clock cycles than any of the other latch comparators 103, 105, because the secondary latch comparator 104 processes the MSB, optionally processing the N most significant bits.

[0050] Figure 4 An example device 400 including the SAR ADC 401 according to any of the preceding technical solutions is shown. Device 400 can be any suitable electronic device that benefits from the SAR ADC 401. For example, device 400 can be a vehicle such as an automobile, a smartphone or tablet computer, a medical device such as a computer monitoring system, a consumer electronic device such as a digital camera, audio equipment or game console, an Internet of Things (IoT) device or another type of electronic product.

[0051] Unless a specific order is explicitly stated, the instructions and / or flowchart steps in the above figures may be performed in any order. Similarly, those skilled in the art will recognize that while an example set of instructions / methods has been discussed, the material in this specification can be combined in various ways to produce other examples, and should be understood within the context provided in the detailed description herein.

[0052] In some example embodiments, the instruction set / method steps described above are implemented as functional and software instructions embodied in an executable instruction set, which is implemented on a computer or a machine programmed with and controlled by the executable instructions. Such instructions are loaded to execute on a processor (e.g., one or more CPUs). The term processor includes a microprocessor, microcontroller, processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing device. A processor may refer to a single component or multiple components.

[0053] In other examples, the instruction sets / methods illustrated herein, along with their associated data and instructions, are stored in appropriate storage devices, which are implemented as one or more non-transitory machine- or computer-readable or computer-usable storage media. Such computer-readable or computer-usable storage media are considered part of an article (or article of manufacture). An article or article of manufacture can refer to any single or multiple manufactured components. Non-transitory machine- or computer-usable media as defined herein do not include signals, but such media are capable of receiving and processing information from signals and / or other transient media.

[0054] Example embodiments of the materials discussed in this specification may be implemented, in whole or in part, via a network, computer, or data-based device and / or service. The network, computer, or data-based device and / or service may include the cloud, the Internet, an intranet, a mobile device, a desktop computer, a processor, a lookup table, a microcontroller, a consumer device, infrastructure, or other enabled devices and services. The following non-exclusive definitions are provided as may be used herein and in the claims.

[0055] In one example, automating one or more instructions or steps discussed herein. The terms automation or automaticity (and similar variations) mean controlling the operation of equipment, systems, and / or processes using computers and / or mechanical / electrical devices without human intervention, observation, effort, and / or decision-making.

[0056] It should be understood that any components that are allegedly to be coupled can be coupled or connected directly or indirectly. In the case of indirect coupling, an additional component may be positioned between the two components that are allegedly to be coupled.

[0057] In this specification, exemplary embodiments have been presented according to a selected set of details. However, those skilled in the art will understand that many other exemplary embodiments, including different sets of these details, can be practiced. It is intended that the appended claims cover all possible exemplary embodiments.

Claims

1. A successive approximation register analog-to-digital converter (SAR ADC), the SAR ADC being configured to convert a received analog input signal into a digital output signal comprising multiple bits, the multiple bits including bits from the most significant bit (MSB) to the least significant bit (LSB), characterized in that, The SAR ADC includes: A digital-to-analog converter (DAC), the DAC being configured to convert the received analog signal into a DAC output signal; The preamplifier circuit includes multiple preamplifiers arranged in series, wherein: Each preamplifier is configured to apply gain to the signal received at its input node; The first preamplifier of the plurality of preamplifiers is configured to receive the DAC output signal from the DAC at its input node and to provide a first preamplifier output signal at its output node; Each of the other preamplifiers in the plurality of preamplifiers is configured to receive an output signal from the preceding preamplifier in the plurality of preamplifiers arranged in series; and The final preamplifier of the plurality of preamplifiers is configured to provide a final preamplifier output signal at the output node of the preamplifier circuit; A primary latch comparator is configured to receive the final preamplifier output signal from the output node of the preamplifier circuit, wherein the primary latch comparator is configured to compare the received final preamplifier output signal with a primary reference voltage, and wherein the primary latch comparator is further configured to generate a primary latch output signal based on the comparison. A secondary latch comparator is configured to receive a preamplifier output signal from one of the plurality of preamplifiers other than the final preamplifier, and wherein the secondary latch comparator is configured to compare the received preamplifier output signal with a secondary reference voltage, and wherein the secondary latch comparator is further configured to generate a secondary latch output signal based on the comparison. A SAR engine, configured to receive a primary latch output signal from the primary latch comparator and a secondary latch output signal from the secondary latch comparator, and further configured to generate a digital output code representing the analog input signal based on the primary latch output signal and the secondary latch output signal. The SAR engine is configured to use only one of the latch output signals to determine each of the plurality of bits, and the SAR engine is configured to use the secondary latch output signal to determine at least the MSB.

2. The SAR ADC according to claim 1, characterized in that, The secondary latch comparator is configured to receive a first preamplifier signal from the first preamplifier.

3. The SAR ADC according to any one of the preceding claims, characterized in that, The SAR engine is configured to use the secondary latch output signal to determine I most significant bits among the plurality of bits, where I is greater than 1 but less than the number of bits among the plurality of bits.

4. The SAR ADC according to claim 3, characterized in that: The preamplifier circuit further includes at least three preamplifiers; The SAR ADC further includes a three-stage latch comparator configured to receive a preamplifier output signal from a more recent preamplifier among the series-arranged plurality of preamplifiers, the more recent preamplifier being arranged after the preamplifier from which the secondary latch comparator receives the preamplifier output signal, and wherein the three-stage latch comparator is configured to compare the received preamplifier output signal with a three-stage reference voltage; and wherein the three-stage latch comparator is further configured to generate a three-stage latch output signal based on the comparison. and The three-level latch comparator is configured to provide the three-level latch output signal to the SAR engine for J second-most significant bits, wherein M is at least equal to 1 and wherein M is at most equal to NI, and wherein N is equal to the number of bits in the plurality of bits.

5. The SAR ADC according to any one of the preceding claims, characterized in that, For each bit of the secondary latch output signal used by the SAR engine, one or more of the preamplifiers arranged after the preamplifier from which the secondary latch comparator receives the preamplifier output signal are configured to operate in low-power mode.

6. The SAR ADC according to claim 5, characterized in that, For each bit of the SAR engine's output signal using the secondary latch, current is shunted from one or more of the preamplifiers configured to operate in low-power mode to the secondary latch comparator.

7. The SAR ADC according to any one of claims 3 to 6, characterized in that, For each bit of the SAR engine using the three-stage latch output signal, one or more of the preamplifiers arranged after the preamplifier from which the three-stage latch comparator receives the preamplifier output signal are configured to operate in low-power mode.

8. The SAR ADC according to any one of the preceding claims, characterized in that, Each latch comparator is configured to compare the received amplified output signal with a corresponding reference voltage within one or more clock cycles to generate the latched output signal, wherein the primary latch comparator compares the received amplified output signal with the primary reference voltage within more clock cycles than the clock cycles used by the secondary latch comparator to compare the received amplified output signal with the secondary reference voltage.

9. The SAR ADC according to any one of the preceding claims, characterized in that, The DAC includes one or more redundant bits.

10. An apparatus, characterized in that, Includes the SAR ADC as described in any of the preceding claims.

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