AD conversion circuit, photoelectric converter, imaging device, mobile body, and method for driving the AD conversion circuit

Abstract

This technology provides advantages in reducing the circuit size of ΔΣ type AD conversion circuits. [Solution] An AD conversion circuit that converts an analog signal applied to an input terminal into a digital signal, comprising: a ΔΣ type AD converter including an integration circuit for integrating a difference signal; a switching circuit that, in a first period, supplies the analog signal supplied to the input terminal to the ΔΣ type AD converter, and in a second period following the first period, switches the supply of a voltage signal corresponding to the voltage output from the integration circuit at the end of the first period to the ΔΣ type AD converter; and a holding circuit that holds the voltage signal corresponding to the voltage output from the integration circuit at the end of the first period and provides the voltage signal to the ΔΣ type AD converter via the switching circuit in the second period, wherein the integration circuit includes a continuous-time integrator and a discrete-time integrator connected to the output of the continuous-time integrator.

Description

[Technical Field]

[0001] The present invention relates to an AD conversion circuit, a photoelectric conversion device, an imaging device, a mobile body, and a method for driving an AD conversion circuit. [Background technology]

[0002] Analog-to-digital converters (ADCs) are known for converting analog signals from pixel outputs in solid-state imaging devices into digital signals. Delta-sigma (ΔΣ) type ADCs are also known. Patent Document 1 describes a ΔΣ type ADC using a loop filter connecting a continuous-time integrator and a discrete-time integrator. By using a continuous-time integrator before the loop filter, the analog signal input to the ΔΣ type ADC is bandwidth-limited, resulting in reduced noise. Furthermore, by using a discrete-time integrator after the loop filter, compared to using only a continuous-time integrator, noise caused by clock jitter, a problem with continuous-time integrators, and characteristic variations due to manufacturing variations of passive elements such as capacitors can be suppressed. Non-Patent Document 1 discloses a two-stage continuous-time ΔΣ type ADC as a technique for increasing the speed of the ΔΣ type ADC. In this two-stage continuous-time ΔΣ type ADC, an ADC that performs AD conversion corresponding to the higher-order bit sequence and an ADC that performs AD conversion corresponding to the lower-order bit sequence using the residual voltage of the ADC corresponding to the higher-order bits as input are connected in cascaded order. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2017-005716 [Non-patent literature]

[0004] [Non-Patent Document 1] S. Tao et.al., “A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems”, IEEE Transactions on Circuits and Systems I: Regular Papers(Volume:62,Issue:6,June 2015) [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] A two-stage ΔΣ ADC equipped with a loop filter connecting a continuous-time integrator and a discrete-time integrator may be useful as a technique for achieving high-speed AD conversion while suppressing noise and characteristic variations. On the other hand, the two-stage ΔΣ ADC shown in Non-Patent Document 1 requires an ADC to perform AD conversion corresponding to the higher bit sequence and an ADC to perform AD conversion corresponding to the lower bit sequence, which results in a large circuit implementation area.

[0006] The present invention aims to provide a technology that is advantageous for reducing the circuit size of a ΔΣ type AD conversion circuit. [Means for solving the problem]

[0007] In view of the above problems, an AD conversion circuit according to an embodiment of the present invention is an AD conversion circuit that converts an analog signal applied to an input terminal into a digital signal, and includes a ΔΣ type AD converter that integrates a differential signal, and in a first period, the analog signal supplied to the input terminal is supplied to the ΔΣ type AD converter, and in a second period after the first period, a voltage signal corresponding to the voltage output from the integration circuit at the end of the first period is supplied to the ΔΣ type AD converter A switching circuit for switching, and a holding circuit for holding the voltage signal corresponding to the voltage output from the integration circuit at the end of the first period and providing the voltage signal to the ΔΣ type AD converter via the switching circuit in the second period. The integration circuit includes a continuous-time integrator and a discrete-time integrator connected to an output of the continuous-time integrator.

Effect of the Invention

[0008] According to the present invention, it is possible to provide a technology advantageous for reducing the circuit scale of a ΔΣ type AD conversion circuit.

Brief Description of the Drawings

[0009] [Figure 1] A diagram showing a configuration example of the AD conversion circuit of this embodiment. [Figure 2] A diagram showing the operation timing of the AD conversion circuit of FIG. 1. [Figure 3] A diagram showing a configuration example of the second-order hybrid ΔΣ type AD converter of the AD conversion circuit of FIG. 1. [Figure 4] A diagram showing a configuration example of the second-order hybrid ΔΣ type AD converter of the AD conversion circuit of FIG. 1. [Figure 5] A diagram showing another example of the integrator of the ΔΣ type AD converter of the AD conversion circuit of FIG. 1. [Figure 6] A diagram showing a configuration example of the four-input comparator of the AD conversion circuit of FIG. 1. [Figure 7] A diagram showing another example of the integrator of the ΔΣ type AD converter of FIG. 3. [Figure 8] A diagram showing a configuration example of the residual voltage holding circuit of the AD conversion circuit of FIG. 1. [Figure 9]A diagram showing an operation example of the residual voltage holding circuit of the AD conversion circuit in FIG. 1. [Figure 10] A diagram showing a configuration example of the AD conversion circuit of this embodiment. [Figure 11] A diagram showing a configuration example of the buffer circuit having a voltage holding function of the AD conversion circuit in FIG. 10. [Figure 12] A diagram showing a configuration example and an operation timing of the buffer circuit having a voltage holding function of the AD conversion circuit in FIG. 10. [Figure 13] A diagram showing a configuration example of the AD conversion circuit of this embodiment. [Figure 14] A diagram showing a configuration example of the second-order hybrid ΔΣ type AD converter of the AD conversion circuit in FIG. 13. [Figure 15] A diagram showing a configuration example of the second-order hybrid ΔΣ type AD converter of the AD conversion circuit in FIG. 13. [Figure 16] A diagram showing a configuration example of the voltage adjustment circuit of the AD conversion circuit in FIG. 13. [Figure 17] A diagram showing a configuration example of the AD conversion circuit of this embodiment. [Figure 18] A diagram showing a configuration example of an optoelectronic conversion device including the AD conversion circuit of this embodiment. [Figure 19] A diagram showing a configuration example of an optoelectronic conversion system including the AD conversion circuit of this embodiment. [Figure 20] A diagram showing a configuration example of a moving body including the AD conversion circuit of this embodiment.

Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, all of these plurality of features are not necessarily essential to the invention, and the plurality of features may be arbitrarily combined. Further, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant descriptions are omitted.

[0011] An analog-to-digital (AD) conversion circuit according to an embodiment of the present disclosure will be described with reference to Figures 1 to 17. Figure 1 shows the configuration of the AD conversion circuit 1 of the first embodiment of the present disclosure. The AD conversion circuit 1 is configured as a two-stage ΔΣ type AD conversion circuit. The AD conversion circuit 1 converts an analog signal supplied to the input terminal IN into a digital signal and outputs the digital signal from the output terminal OUT. The AD conversion circuit 1 may include a ΔΣ type AD converter 10 and a switching circuit 30 (hereinafter, the ΔΣ type AD converter may be referred to as a ΔΣ type ADC). The AD conversion circuit 1 may also include a residual voltage holding circuit 20, a digital demodulation circuit 40, and a reconstruction circuit 50. The ΔΣ type AD converter 10 may include an integration circuit that integrates the difference signal. The switching circuit 30 supplies the analog signal supplied to the input terminal IN to the ΔΣ type AD converter 10 during the first period. Furthermore, in the second period following the first period, the switching circuit 30 supplies a voltage signal to the ΔΣ-type AD converter 10 corresponding to the voltage output from the integrating circuit of the ΔΣ-type AD converter 10 at the end of the first period. The first period is a period in which AD conversion is performed to generate the upper bit sequence of a digital signal corresponding to the analog signal applied to the input terminal IN. The second period is a period in which AD conversion is performed to generate the lower bit sequence of a digital signal corresponding to the analog signal applied to the input terminal IN. The upper bit sequence may consist of multiple bits. The lower bit sequence may also consist of multiple bits.

[0012] The residual voltage holding circuit 20 holds (samples) a voltage signal corresponding to the residual voltage output from the ΔΣ type AD converter 10 at the end of the first period, and provides that voltage signal to the switching circuit 30 during the second period. The residual voltage holding circuit 20 can be controlled, for example, by a holding circuit reset signal and a sample signal.

[0013] In the first period, the ΔΣ-type AD converter 10 performs AD conversion corresponding to the upper bit sequence, and at the end of the first period, the voltage signal corresponding to the residual voltage held by the residual voltage holding circuit 20 is supplied to the ΔΣ-type AD converter 10 by the switching circuit 30. Subsequently, in the second period, the ΔΣ-type AD converter 10 performs AD conversion corresponding to the lower bit sequence. In the first period, the time-series ΔΣ-modulated signal (upper bit sequence) output from the ΔΣ-type AD converter 10 is demodulated into a multi-bit digital signal by the digital demodulation circuit 40. Similarly, in the second period, the time-series ΔΣ-modulated signal (lower bit sequence) output from the ΔΣ-type AD converter 10 is demodulated into a multi-bit digital signal by the digital demodulation circuit 40. The reconstruction circuit 50 generates an output digital signal based on the digital signal of the upper bit sequence and the digital signal of the lower bit sequence demodulated by the digital demodulation circuit 40. The internal signals of the ΔΣ-type AD converter 10 and the internal signals of the digital demodulation circuit 40 are reset according to the reset signal before the start of the first period and before the start of the second period. With this configuration, an AD conversion circuit 1 can be realized as a two-stage ΔΣ-type AD conversion circuit by using one ΔΣ-type AD converter 10 and a residual voltage holding circuit 20. In other words, the circuit size of the ΔΣ-type AD conversion circuit is reduced.

[0014] Figure 2 shows the operating timing diagram of the AD conversion circuit 1 shown in Figure 1. As an example of the operation of the two-stage AD conversion circuit 1, the processing flow in which the reconstruction circuit 50 outputs the final ADC result (0) will be explained.

[0015] Between time t1 and time t2, the reset signal becomes high, and the ΔΣ type AD converter 10 and the digital demodulation circuit 40 are reset. Simultaneously, the hold circuit reset signal becomes high, and the residual voltage hold circuit 20 is reset. At time t2, from the moment the reset signal transitions to a low level, the ΔΣ type AD converter 10 starts AD conversion corresponding to the higher bits, and the residual voltage hold circuit 20 starts sampling the residual voltage. Furthermore, the digital demodulation circuit 40 starts demodulation processing of the higher bits. At time t3, after the completion of AD conversion corresponding to the higher bits, the residual voltage hold circuit 20 starts holding the residual voltage of the ΔΣ type AD converter 10. At the same time, the reconstruction circuit 50 acquires the multi-bit demodulated signal corresponding to the higher bits.

[0016] Next, during the period from time t3 to t4, the reset signal becomes high again, and the ΔΣ type AD converter 10 and the digital demodulation circuit 40 are reset. At time t4, from the moment the reset signal transitions to a low level, the ΔΣ type AD converter 10 starts AD conversion corresponding to the lower bits, and the digital demodulation circuit 40 starts demodulating the lower bits. At time t5, after the AD conversion corresponding to the lower bits is completed, the reconstruction circuit 50 acquires a multi-bit demodulated signal corresponding to the lower bits. Subsequently, the reconstruction circuit 50 performs reconstruction processing using the multi-bit demodulated signal corresponding to the upper bit sequence and the multi-bit demodulated signal corresponding to the lower bit sequence. As a result, the final AD conversion result corresponding to the digital output signal is output. The two-stage AD conversion circuit 1 performs ΔΣ type AD conversion on any analog input signal by repeating the above AD conversion flow. Here, it is assumed that the input analog signal during the AD conversion period corresponding to the upper bit sequence is constant.

[0017] Figure 3 shows a detailed example of the configuration of a ΔΣ type AD converter 10, specifically the circuit configuration of a second-order hybrid type ΔΣ type AD converter. More specifically, the ΔΣ type AD converter 10 has a second-order hybrid configuration that includes a continuous-time integrator 110 and a discrete-time integrator 120 connected to the output of the continuous-time integrator 110 as the integrating circuit. The ΔΣ type AD converter 10 also includes a comparator 180 that compares the output of the discrete-time integrator 120 with a reference signal, and a digital-to-analog converter (DA converter) 190 connected to the output of the comparator 180. The output of the DA converter 190 is supplied to the resistor 1102 of the continuous-time integrator 110 and the switch 1211 of the discrete-time integrator 120. R1 ~V R3 V represents a reference voltage, such as ground potential. In Figure 3, each circuit block is configured to supply a different reference voltage, R1 ~V R3 The voltages may be the same.

[0018] The continuous-time integrator 110 may include resistors 1101, 1102, capacitor 1104, switch 1103, and amplifier 1105. The discrete-time integrator 120 may include capacitors 1203, 1213, 1251, switches 1201, 1202, 1204, 1205, 1211, 1212, 1214, 1215, 1250, and amplifier 1252. Capacitors 1203 and switches 1201, 1202, 1204, and 1205 constitute a sample circuit connected to the output of the continuous-time integrator 110. Capacitors 1213 and switches 1211, 1212, 1214, and 1215 constitute a sample circuit connected to the output of the DA converter 190. Here, the capacitors described herein can preferably be formed as capacitive elements. For example, MIS capacitors in the Metal-Insulator-Semiconductor format, MIM capacitors in the Metal-Insulator-Metal format, and MOM capacitors in the Metal-Oxide-Metal format can be used. These capacitive element formats are just examples; any element that functions as a capacitor can be used as appropriate.

[0019] In the ΔΣ type AD converter 10 shown in Figure 3, capacitors 1104 and 1251 are reset when the reset signal is high. When the reset signal is low, the continuous-time integrator 110 integrates the difference signal between the analog signal input to the ΔΣ type AD converter 10 and the output of the DA converter 190. The discrete-time integrator 120 integrates the difference signal between the output of the continuous-time integrator 110 and the output of the DA converter 190 using a clock signal (not shown). The comparator 180 integrates the output of the discrete-time integrator 120 with a reference signal (reference voltage V R3 The DA converter 190 receives a difference signal from the comparator 180 and performs a comparison operation using a clock signal (not shown). The DA converter 190 outputs an analog voltage according to the output signal of the comparator 180. The DA converter 190 may be configured to output an analog voltage according to the input signal according to a 1-bit transfer function shown, for example, equation (1).

[0020]

number

[0021] Here, DACin is the output signal of comparator 180, Vr is a reference signal (not shown) in the ΔΣ type AD converter 10, and DACout is the output signal of DA converter 190, with the reference signal being 0. The second-order hybrid type ΔΣ type AD converter 10 shown in Figure 3 repeatedly performs integration, comparison, and digital-to-analog conversion during the period from when the reset signal goes from a low level to a high level.

[0022] In the configuration example shown in Figure 3, the AD conversion circuit 1 is configured as a second-order hybrid ΔΣ type AD conversion circuit. Also in the configuration example shown in Figure 3, the ΔΣ type AD converter 10 has a 1-bit configuration for both the comparator 180 and the DA converter 190. However, the comparator 180 and DA converter 190 may be configured with multiple bits, and the circuits corresponding to the resistor 1102 of the continuous-time integrator 110 and the switches 1211, 1212, 1214, 1215 and capacitor 1213 of the discrete-time integrator 120 may be increased in proportion to the resolution of the comparator 180 and DA converter 190 and connected in parallel. By configuring the comparator 180 and DA converter 190 with multiple bits, the AD conversion speed of the ΔΣ type AD converter 10 can be increased. Furthermore, by adding one or more discrete-time integrators between the discrete-time integrator 120 and the comparator 180, it may be configured as a third-order or higher hybrid ΔΣ type AD converter. By increasing the number of integrators, the AD conversion speed of the hybrid ΔΣ type AD converter 10 can be increased.

[0023] Figure 4 shows a second-order hybrid ΔΣ type AD converter 10 with a feedforward path as an example of a configuration different from the one shown in Figure 3 for the ΔΣ type AD converter 10. The ΔΣ type AD converter 10 shown in Figure 4 may include a continuous-time integrator 110, a discrete-time integrator 130, a four-input comparator 181, and a DA converter 190. The continuous-time integrator 110 may include resistors 1101, 1102, capacitor 1104, switch 1103, and amplifier 1105. The discrete-time integrator 130 may include capacitors 1203, 1251, switches 1201, 1202, 1204, 1205, 1250, and amplifier 1252. Capacitors 1203 and switches 1201, 1202, 1204, and 1205 constitute a sample circuit connected to the output of the continuous-time integrator 110.

[0024] Comparator 181 receives the output of discrete-time integrator 130 and a reference signal (reference voltage V R3In addition to , the output of the continuous-time integrator 110 and the analog signal supplied to the continuous-time integrator 110 are supplied. Therefore, the comparator 181 compares, in addition to the output of the discrete-time integrator 130, the output of the continuous-time integrator 110 and the analog signal supplied to the continuous-time integrator 110 with a reference signal. The output of the comparator 181 is supplied to the DA converter 190, and the output of the DA converter 190 is supplied to the resistor 1102 of the continuous-time integrator 110. V shown in FIG. 3 R1 ~V R3 means a reference voltage such as a ground potential, for example. In FIG. 3, although it is configured to supply different reference voltages for each circuit block, V R1 ~V R3 may be the same voltage.

[0025] The operation of the AD conversion circuit 1 including the ΔΣ type AD converter 10 shown in FIG. 4 is the same as that of the AD conversion circuit 1 including the ΔΣ type AD converter 10 shown in FIG. 3. In the configuration shown in FIG. 4, the signal input to the ΔΣ type AD converter 10 is supplied to the 4-input comparator 181. Thereby, the amplitudes of the signals output from the continuous-time integrator 110 and the discrete-time integrator 130 can be suppressed, and the influence of the non-linearity of the amplifiers 1105 and 1252 is suppressed. Thereby, the non-linear distortion characteristics of the ΔΣ type AD converter 10 can be improved.

[0026] In the configuration example shown in Figure 4, the AD conversion circuit 1 is configured as a second-order hybrid ΔΣ type AD conversion circuit. Also in the configuration example shown in Figure 4, the ΔΣ type AD converter 10 has a 1-bit comparator 181 and a DA converter 190. However, the comparator 181 and DA converter 190 may be configured with multiple bits, and the resistor 1102 of the continuous-time integrator 110 may be increased in proportion to the resolution of the comparator 181 and DA converter 190, and connected in parallel. By configuring the comparator 181 and DA converter 190 with multiple bits, the AD conversion speed of the ΔΣ type AD converter 10 can be increased. Furthermore, by adding one or more discrete-time integrators between the discrete-time integrator 120 and the comparator 181, it may be configured as a third-order or higher hybrid ΔΣ type AD converter. By increasing the number of integrators, the AD conversion speed of the hybrid ΔΣ type AD converter 10 can be increased.

[0027] Figure 5 shows the configuration of a Gm-C type integrator 140 as another example of a continuous-time integrator configuration in the ΔΣ type AD converter 10. The Gm-C type integrator 140 may include switches 141, 142, a capacitor 143, a transconductance 144, and an inverter 145. V shown in Figure 5 R This refers to a reference voltage, such as ground potential. Switch 141 is controlled by a reset signal, and switch 142 is controlled by a reset signal inverted by inverter 145. When the reset signal is high level, capacitor 143 is reset by releasing its stored charge. When the reset signal is low level, integration is performed by the difference current between the current generated by the transconductance 144 in response to the input signal and the output signal current of the DA converter 190, and capacitor 143. When the Gm-C type integrator 140 is used as a continuous-time integrator for the ΔΣ type AD converter 10, the output of the DA converter 190 is connected to the output of the transconductance 144. In this configuration, power consumption can be reduced while achieving the same functionality as an integrator composed of a resistor, capacitor, and amplifier.

[0028] Figure 6 shows an example configuration of a 4-input comparator 181. Comparator 181 may be configured to include a latching comparator 650 and an SR flip-flop 660. The latching comparator 650 may include, for example, PMOS transistors 601, 602, 603, 604, 605, NMOS transistors 610, 611, 612, and NMOS transistors 620, 621, 622, 630, 631, 632. The SR flip-flop 660 may be configured to include NAND gates 640, 641. In the example configuration shown in Figure 6, when the clock signal is low, the latching comparator 650 is in a reset state, the output signals, comparison result 1 and comparison result 2, are high levels, and the SR flip-flop 660 is in a hold state. When the clock signal is high level, the latching comparator 650 generates an internal signal corresponding to the voltage difference between each of the three input signals and the reference signal, and outputs the results corresponding to the generated internal signals as comparison results 1 and 2. The SR flip-flop 660 also outputs signals corresponding to comparison results 1 and 2. In the 4-input comparator 181, if the sum of the voltages of input signal 1-reference signal, input signal 2-reference signal, and input signal 3-reference signal is a positive voltage, then comparison result 1 will be low level, comparison result 2 will be high level, and the output signal will be high level.

[0029] In the example configuration shown in Figure 6, a four-input comparator 181 is shown, and the input signals are connected to NMOS transistors 620, 621, 622, 630, 631, and 632. By increasing the number of these transistors that function as input transistors, a configuration that supports third-order or higher ΔΣ type AD converters can be achieved. Although a configuration with three input signals and a reference signal is shown, a configuration in which the reference signal is omitted and each of the three input signals is input as a differential signal is also possible.

[0030] Figure 7(a) shows an example configuration of discrete-time integrator 131, which has a different configuration from discrete-time integrator 130 shown in Figure 4, and Figure 7(b) shows an example of operation of discrete-time integrator 131. Discrete-time integrator 131 may be configured to include capacitors 1203, 1213, 1251, switches 1201, 1202, 1204, 1205, 1211, 1212, 1214, 1215, 1250, and amplifier 1252. Discrete-time integrator 131 includes sample circuit 1 configured to include capacitor 1203 and switches 1201, 1202, 1204, 1205, and sample circuit 2 configured to include capacitor 1213 and switches 1211, 1212, 1214, 1215. R This refers to a reference voltage, such as ground potential. Sample circuits 1 and 2 are connected to the output of the continuous-time integrator 110.

[0031] Sample circuit 1 has one main terminal of switch 1201 and one main terminal of switch 1204 connected to one main terminal of capacitor 1203, and one main terminal of switch 1205 and one main terminal of switch 1202 connected to the other main terminal of capacitor 1203. The other main terminal of switch 1204 and the other main terminal of 1205 are connected to a reference voltage V R The following is connected. Sample circuit 2 is connected to one main terminal of switch 1211 and one main terminal of switch 1214, and one main terminal of switch 1215 and one main terminal of switch 1212, and the other main terminal of capacitor 1213. The other main terminal of switch 1214 and the other main terminal of switch 1215 are connected to a reference voltage V R It connects to the network.

[0032] Sample circuit 1 samples the input signal when switches 1201 and 1205 are ON (conducting) and switches 1202 and 1204 are OFF (non-conducting). When switches 1201 and 1205 are OFF and switches 1202 and 1204 are ON, the sampled charge is transferred to capacitor 1251. In the discrete-time integrator 131, switch 1211 of sample circuit 2 is also connected to the input signal. The operation of sample circuit 2 is substantially the same as that of sample circuit 1, except that the operation of switches 1211 and 1215 is the inverse of that of switches 1201 and 1205 in sample circuit 1. Similarly, the operation of switches 1212 and 1214 in sample circuit 2 is the inverse of that of switches 1202 and 1204 in sample circuit 1.

[0033] The circuit operation of sample circuit 1 and sample circuit 2 will be explained using the timing chart in Figure 7(b). Here, the circuit operation when the output signal of continuous-time integrator 110 is input to discrete-time integrator 131 will be explained. During the period from time t1 to time t2, sample circuit 1 of discrete-time integrator 131 samples the output signal (1) of continuous-time integrator 110. During the period from time t2 to time t3, the charge sampled by sample circuit 1 is transferred to the capacitor 1251 of the integrator, and integration is performed. During the same period from time t2 to time t3, sample circuit 2 of discrete-time integrator 131 samples the output signal (2) of continuous-time integrator 110. Then, during the period from time t3 to time t4, the charge sampled by sample circuit 2 is transferred to the capacitor 1251 of the integrator, and integration is performed. In this way, the output of continuous-time integrator 110 is sampled alternately by sample circuit 1 and sample circuit 2. The discrete-time integrator 131 can also be described as performing time interleaving operation by complementaryly sampling and accumulating the output signal of the continuous-time integrator 110 using two sample circuits 1 and 2. Due to this operation, the discrete-time integrator 131 can reduce the power consumption in the amplifier 1252 compared to the discrete-time integrator 130 shown in Figure 4.

[0034] Herein, this embodiment is not limited to this form. For example, a capacitor can be added between the other main terminal of switch 1202 (the main terminal of switch 1202 not connected to capacitor 1203) and the other main terminal of switch 1212 (the main terminal of switch 1212 not connected to capacitor 1213) and the input terminal of amplifier 1252. Furthermore, one main terminal of switch 1250 can be connected to the input terminal of amplifier 1252, and the other main terminal of switch 1250 can be connected to the output terminal of amplifier 1252. Furthermore, one main terminal of capacitor 1251 can be connected to the other main terminal of switch 1202 and the other main terminal of switch 1212, and the other main terminal of capacitor 1251 can be connected to the output terminal of amplifier 1252. With this configuration, the offset component during the accumulation operation of amplifier 1252 in discrete-time integrator 131 can be reduced with high accuracy.

[0035] Figure 8 shows an example configuration of the residual voltage holding circuit 20. Figure 9 is a timing chart showing an example of the operation of the residual voltage holding circuit 20. The residual voltage holding circuit 20 may be configured to include switches 701 and 702 controlled by a switching signal, a switch 703 controlled by a sample signal, switches 710 and 711 controlled by an inverted switching signal, a switch 720 controlled by a holding circuit reset signal, an amplifier 730, and a sample capacitor 740. RThis refers to a reference voltage, such as ground potential. The residual voltage holding circuit 20 resets the sample capacitor 740 when the switching signal is high level, the holding circuit reset signal is high level, and the sample signal is low level. When the switching signal is high level, the holding circuit reset signal is low level, and the sample signal is high level, a voltage approximately equivalent to the input signal is sampled into the sample capacitor 740. The voltage sampled at this time becomes the residual voltage after 1-bit AD conversion corresponding to the higher bits. When the switching signal is low level, the holding circuit reset signal is low level, and the sample signal is high level, the sampled voltage is held in the sample capacitor 740. In this configuration, by realizing the input signal sampling operation and the holding of the sampled input signal with a single amplifier, it is possible to reduce power consumption and mounting area. Here, an example of operation is shown in which the switching signal is high level during the higher-bit AD conversion period (first period). However, this is not the only option; by setting the switching signal to a high level at any time until the completion of the upper-bit AD conversion, the operating period of the residual voltage holding circuit 20 can be reduced, thereby lowering power consumption.

[0036] The digital demodulation circuit 40 shown in Figure 1 outputs a multi-bit demodulated signal by performing digital signal processing according to equation (2) on a 1-bit time-series ΔΣ modulated signal corresponding to the upper bit sequence of the ΔΣ type AD converter 10.

[0037]

number

[0038] Here, M represents the oversampling ratio in the AD conversion corresponding to the upper bit sequence in the ΔΣ type AD converter 10, and i represents the time index of the comparison result output in time series. The digital demodulation circuit 40 outputs a multi-bit demodulated signal by performing digital signal processing according to equation (3) on the 1-bit time series ΔΣ modulated signal corresponding to the lower bit sequence in the ΔΣ type AD converter 10.

[0039]

number

[0040] Here, N represents the oversampling ratio in the AD conversion corresponding to the lower bits of the ΔΣ type AD converter 10, and i represents the time index of the comparison result output in the time series.

[0041] The reconstruction circuit 50 shown in Figure 1 performs a reconstruction process on the upper-bit demodulated signal and the lower-bit demodulated signal according to equation (4). This reconstruction process normalizes the combined signal of the upper-bit demodulated signal and the lower-bit demodulated signal so that, if it were assumed to be a decimal number (it is actually a binary signal), the maximum value in decimal would be 1. For example, if a signal is generated that would have a value of 15 if assumed to be a decimal number, this reconstruction process multiplies the upper-bit demodulated signal and the lower-bit demodulated signal by 1 / 15. In this way, the final digital signal, which is the final A / D conversion result for M+L bits, is obtained, normalized so that the maximum value when assumed to be a decimal number is 1.

[0042]

number

[0043] Here, M and N may be the same or they may be different from each other.

[0044] Next, the AD conversion circuit 1 of the second embodiment of this disclosure will be described using Figures 10 to 12(a) and 12(b). Figure 10 shows the AD conversion circuit 1 of this embodiment. Although not shown in Figure 10, a digital demodulation circuit 40 and a reconstruction circuit 50 may be arranged after the ΔΣ type AD converter 10, similar to the configuration shown in Figure 1.

[0045] As shown in Figure 10, compared to the configuration example shown in Figure 1, the AD conversion circuit 1 of this embodiment has a buffer circuit 70 with residual voltage holding function instead of a residual voltage holding circuit 20. The switching circuit 30 controls the switching between the input analog signal and the output signal of the buffer circuit 70 with voltage holding function. The analog signal selected by the switching circuit 30 is input to the buffer circuit 70, and the buffer circuit 70 outputs the buffered signal to the ΔΣ type AD converter 10. The ΔΣ type AD converter 10 is the above-mentioned second-order or higher hybrid type ΔΣ type AD converter.

[0046] During the first period, the switching circuit 30 supplies the analog signal applied to the input terminal IN to the buffer circuit 70, and during the second period following the first period, it supplies the buffer circuit 70 with the residual voltage output from the ΔΣ type AD converter 10 at the end of the first period. The first period is the period during which AD conversion is performed to generate the upper bit sequence of the digital signal corresponding to the analog signal applied to the input terminal IN. The second period is the period during which AD conversion is performed to generate the lower bit sequence of the digital signal corresponding to the analog signal applied to the input terminal IN. The upper bit sequence may consist of multiple bits. The lower bit sequence may also consist of multiple bits.

[0047] The buffer circuit 70 has the function of holding the residual voltage supplied from the ΔΣ type AD converter 10 via the switching circuit 30 at the end of the first period over the second period. The buffer circuit 70 is controlled by a holding circuit reset signal and a sample signal. During the first period, when A / D conversion is performed to generate the upper bit sequence, the buffer circuit 70 buffers the analog signal supplied to the input terminal IN of the switching circuit 30 and output from the switching circuit 30, and outputs it to the ΔΣ type AD converter 10. The buffer circuit 70 holds the residual voltage output from the ΔΣ type AD converter 10 at the end of the first period for generating the upper bit sequence. Subsequently, in the second period, the buffer circuit 70 outputs the buffered voltage, in other words, a voltage corresponding to the residual voltage, to the ΔΣ type AD converter 10. In other words, the buffer circuit 70 has the function of holding a voltage signal corresponding to the residual voltage output from the integrating circuit of the ΔΣ type AD converter 10 at the end of the first period.

[0048] The second-order hybrid ΔΣ type AD converter 10 includes a continuous-time integrator 110 in the input stage, as illustrated in Figures 3 and 4. When the continuous-time integrator 110 has a voltage-to-current conversion circuit, a DC voltage corresponding to the input analog signal voltage flows through this voltage-to-current conversion circuit. For example, when a source follower circuit is used as the circuit that supplies the analog signal to the ΔΣ type AD converter 10, a DC current corresponding to the voltage value of the analog signal flows in addition to the bias current. As a result, a gain deviation occurs in the source follower circuit, and the linearity of the analog signal may deteriorate. On the other hand, as in this embodiment, by arranging a buffer circuit 70 in the input path of the analog signal, the DC current flowing in the source follower circuit according to the voltage value of the analog signal is suppressed, thereby improving linearity. In addition, by sharing the circuit that holds the residual voltage with the amplifier of the buffer circuit 70, linearity can be improved without increasing the number of circuit components and power consumption.

[0049] Figure 11 shows a detailed configuration example of a buffer circuit 70 having a residual voltage holding function. The buffer circuit 70 comprises an amplifier 800 and a voltage holding circuit 810. The voltage holding circuit 810 is controlled by a holding circuit reset signal and a sample signal, and holds and outputs the residual voltage supplied from the ΔΣ type AD converter 10. The buffer circuit 70 can be realized, for example, by using a 2-input 1-output amplifier 800 in a voltage follower configuration.

[0050] During the first period, the analog signal applied to the input terminal IN is buffered using amplifier 800. During the second period, the voltage held by the voltage holding circuit 810 at the end of the first period is held and buffered using amplifier 800 to generate a voltage signal.

[0051] Figure 12(a) shows a more specific example of the configuration of the buffer circuit 70 having a residual voltage holding function, and Figure 12(b) shows the operating timing of the buffer circuit 70. The voltage holding circuit 810 may be configured to include switches 811, 812 and a capacitor 813. RThis refers to a reference voltage, such as ground potential. During the period when the switching signal is low level, the analog signal supplied to the input terminal IN is supplied to a buffer circuit 70, which is composed of an amplifier 800 (voltage follower circuit), and the analog signal buffered by the voltage follower circuit is supplied to the ΔΣ type AD converter 10. During the first period in which the ΔΣ type AD converter 10 performs AD conversion to generate the higher bit sequence, the voltage follower circuit continues to buffer the analog signal until the integrator accumulation of the AD conversion of the last bit of the higher bit sequence is completed. After that, the sample signal becomes high level and the residual voltage is accumulated in the capacitor 813, and after the sample signal becomes low level, the accumulated residual voltage is held until the hold circuit reset signal becomes high level. During the second period in which the switching circuit 30 performs AD conversion to generate the lower bit sequence, the output signal of the voltage hold circuit 810 is supplied to the ΔΣ type AD converter 10. The hold circuit reset signal is high at the start of the first period, when the AD conversion to generate the higher bit sequence is performed, and can be low at any point before the final integrator storage operation in the first period.

[0052] The AD conversion circuit 1 of the third embodiment of this disclosure will be described with reference to Figures 13 to 16. Figure 13 shows the AD conversion circuit 1 of this embodiment. Although not shown in Figure 13, a digital demodulation circuit 40 and a reconstruction circuit 50 may be arranged after the ΔΣ type AD converter 10, similar to the configuration shown in Figure 1. The AD conversion circuit 1 shown in Figure 13 is based on the configuration and operation shown in Figure 10, but a voltage adjustment circuit 90 is added.

[0053] The voltage adjustment circuit 90 supplies a signal voltage approximately equivalent to the adjustment signal to the ΔΣ-type AD converter 10 according to the adjustment signal. During the AD conversion period of the ΔΣ-type AD converter 10, the voltage of the internal node is kept within a range near the signal value of the adjustment signal by the voltage adjustment circuit 90. By adding a circuit to the ΔΣ-type AD converter 10 that adjusts the voltage of the internal node within a predetermined range, as in this configuration, the following advantages are provided in addition to the advantages described in the first and second embodiments. That is, even if the operating point of the buffer circuit 70 and the operating point of the internal voltage in the ΔΣ-type AD converter 10 are different, the operating point of the internal voltage in the analog circuit of the ΔΣ-type AD converter 10 is adjusted within a range near the signal value of the adjustment signal. This improves linearity.

[0054] Figure 14 shows a detailed configuration example of a second-order hybrid ΔΣ type AD converter 10 and a voltage adjustment circuit 90. The ΔΣ type AD converter 10 may include a continuous-time integrator 110, a discrete-time integrator 120, a comparator 180, and a DA converter 190, similar to the configuration shown in Figure 3. The continuous-time integrator 110 may include resistors 1101, 1102, capacitor 1104, switch 1103, and amplifier 1105. The discrete-time integrator 120 may include capacitors 1203, 1213, 1251, switches 1201, 1202, 1204, 1205, 1211, 1212, 1214, 1215, 1250, and amplifier 1252. The voltage adjustment circuit 90 may include an integrator internal voltage adjustment circuit 910. Figure 14 shows V R1 ~V R3 V represents a reference voltage, such as ground potential. In Figure 14, each circuit block is configured to supply a different reference voltage, R1 ~V R3 The voltages may be the same. The circuit operation of the ΔΣ type AD converter 10 shown in Figure 14 may be similar to the circuit shown in the configuration examples in Figures 1 and 10.

[0055] The output of the continuous-time integrator 110 is supplied to the discrete-time integrator 120, and the output of the discrete-time integrator 120 is supplied to the comparator 180. The output of the comparator 180 is supplied to the DA converter 190, and the output of the DA converter 190 is supplied to the resistor 1102 of the continuous-time integrator 110 and the switch 1211 of the discrete-time integrator 120. The output of the discrete-time integrator 120 is output as the residual voltage of the ΔΣ type AD converter 10.

[0056] In the continuous-time integrator 110, the internal signal at internal node N, to which resistors 1101 and 1102, capacitor 1104, switch 1103, and amplifier 1105 are connected, is supplied to the integrator internal voltage adjustment circuit 910. The integrator internal voltage adjustment circuit 910 is also supplied with an adjustment signal. As a result, the internal signal at internal node N is adjusted by the integrator internal voltage adjustment circuit 910 to a range near the signal value of the adjustment signal input to the integrator internal voltage adjustment circuit 910 (in other words, within a predetermined range).

[0057] Figure 14 shows an example of a single-phase circuit configuration, but the voltage of the internal nodes can be adjusted using a similar configuration even when the continuous-time integrator 110 and discrete-time integrator 120 are differential circuits. In the case of a differential configuration, the voltage input as the adjustment signal is a common-mode signal, and the internal voltage adjusted by the integrator internal voltage adjustment circuit becomes the common-mode voltage of the continuous-time integrator 110.

[0058] In the configuration example shown in Figure 14, the AD conversion circuit 1 is configured as a second-order hybrid ΔΣ type AD conversion circuit. Also in the configuration example shown in Figure 14, the ΔΣ type AD converter 10 has a 1-bit configuration for both the comparator 180 and the DA converter 190. However, the comparator 180 and DA converter 190 may be configured with multiple bits, and the circuits corresponding to the resistor 1102 of the continuous-time integrator 110 and the switches 1211, 1212, 1214, 1215 and capacitor 1213 of the discrete-time integrator 120 may be increased in proportion to the resolution of the comparator 180 and DA converter 190 and connected in parallel. By configuring the comparator 180 and DA converter 190 with multiple bits, the AD conversion speed of the ΔΣ type AD converter 10 can be increased. Furthermore, by adding one or more discrete-time integrators between the discrete-time integrator 120 and the comparator 180, it may be configured as a third-order or higher hybrid ΔΣ type AD converter. By increasing the number of integrators, the AD conversion speed of the hybrid ΔΣ type AD converter 10 can be increased.

[0059] Figure 15 shows a detailed configuration example of a second-order hybrid ΔΣ type AD converter 10 and voltage adjustment circuit 90 that differs from Figure 14. The ΔΣ type AD converter 10 shown in Figure 15 has a feedforward path, as well as the configuration shown in Figure 4, with the addition of a voltage adjustment circuit 90 (integrator internal voltage adjustment circuit 910) that adjusts the voltage of the internal nodes of the continuous-time integrator 110. R1 ~V R3 V represents a reference voltage, such as ground potential. In Figure 15, each circuit block is configured to supply a different reference voltage, but V R1 ~V R3 The voltages may be the same. The circuit operation of the ΔΣ type AD converter 10 shown in Figure 15 may be similar to the circuit shown in the configuration examples in Figures 1 and 10, for example.

[0060] In the continuous-time integrator 110, the internal signal at internal node N, to which resistors 1101 and 1102, capacitor 1104, switch 1103, and amplifier 1105 are connected, is supplied to the integrator internal voltage adjustment circuit 910. The integrator internal voltage adjustment circuit 910 is also supplied with an adjustment signal. As a result, the internal signal at internal node N is adjusted by the integrator internal voltage adjustment circuit 910 to a range near the signal value of the adjustment signal input to the integrator internal voltage adjustment circuit 910 (in other words, within a predetermined range).

[0061] Figure 15 shows an example of a single-phase circuit configuration, but the voltage of the internal nodes can be adjusted using a similar configuration even when the continuous-time integrator 110 and discrete-time integrator 120 are differential circuits. In the case of a differential configuration, the voltage input as the adjustment signal is a common-mode signal, and the internal voltage adjusted by the integrator internal voltage adjustment circuit becomes the common-mode voltage of the continuous-time integrator 110.

[0062] In the configuration shown in Figure 15, the 4-input comparator 181 receives the output of the discrete-time integrator 130 and a reference signal (reference voltage V R3 In addition to the above, the output of the continuous-time integrator 110 and the analog signal supplied to the continuous-time integrator 110 are supplied. By supplying the signal input to the ΔΣ type AD converter 10 to the comparator 181, the amplitude of the signals output from the continuous-time integrator 110 and the discrete-time integrator 130 can be suppressed, and the effects of the nonlinearity of amplifiers 1105 and 1252 can be suppressed. As a result, the nonlinear distortion characteristics of the ΔΣ type AD converter 10 can be improved.

[0063] In the configuration example shown in Figure 15, the AD conversion circuit 1 is configured as a second-order hybrid ΔΣ type AD conversion circuit. Also in the configuration example shown in Figure 15, the ΔΣ type AD converter 10 has a 1-bit comparator 181 and a DA converter 190. However, the comparator 181 and DA converter 190 may be configured with multiple bits, and the resistor 1102 of the continuous-time integrator 110 may be increased in proportion to the resolution of the comparator 181 and DA converter 190, and connected in parallel. By configuring the comparator 181 and DA converter 190 with multiple bits, the AD conversion speed of the ΔΣ type AD converter 10 can be increased. Furthermore, by adding one or more discrete-time integrators between the discrete-time integrator 120 and the comparator 181, it may be configured as a third-order or higher hybrid ΔΣ type AD converter. By increasing the number of integrators, the AD conversion speed of the hybrid ΔΣ type AD converter 10 can be increased.

[0064] Figure 16 shows a detailed configuration example of the integrator internal voltage adjustment circuit 910. The integrator internal voltage adjustment circuit 910 may include an amplifier 930, a voltage-controlled current source 940, and a current source 950. An adjustment signal is supplied to the non-inverting input terminal of the amplifier 930, and the internal node N of the continuous-time integrator 110 may be connected to the inverting input terminal of the amplifier 930. The output of the amplifier 930 may be connected to the control terminal of the voltage-controlled current source 940. One main terminal of the voltage-controlled current source 940 is connected to the current source 950 and may also be connected to the non-inverting input terminal of the amplifier 930 as the signal to be adjusted. With this configuration, the signal to be adjusted is controlled by the principle of negative feedback so that its voltage is close to the voltage of the adjustment signal. As a result, the voltage of the internal node N of the continuous-time integrator 110 is adjusted within a predetermined range. Here, the voltage-controlled current source 940 can be realized, for example, with a PMOS transistor. Figure 16 shows an example of a circuit that controls the voltage of an internal node being adjusted using the principle of negative feedback. Any circuit that achieves a similar function can be used as the integrator internal voltage adjustment circuit 910.

[0065] Figure 17 shows an example configuration of the AD conversion circuit 1 of the fourth embodiment of this disclosure. The AD conversion circuit 1 is configured as a two-stage ΔΣ type AD conversion circuit. The AD conversion circuit 1 converts an analog signal applied to the input terminal IN into a digital signal and outputs it from the output terminal OUT. The AD conversion circuit 1 may include a ΔΣ type AD converter 10 and a switching circuit 30. In addition, the AD conversion circuit 1 may include a residual voltage holding circuit 20, a digital demodulation circuit 40, a reconstruction circuit 50, and a digital gain adjustment circuit 60.

[0066] During the first period, the switching circuit 30 supplies the analog signal applied to the input terminal IN to the Σ-type AD converter 10. During the second period following the first period, the switching circuit 30 supplies the ΔΣ-type AD converter 10 with a voltage signal corresponding to the voltage output from the integrating circuit of the ΔΣ-type AD converter 10 at the end of the first period. The first period is the period for performing AD conversion to generate the upper bit sequence of the digital signal corresponding to the analog signal applied to the input terminal IN. The second period is the period for performing AD conversion to generate the lower bit sequence of the digital signal corresponding to the analog signal applied to the input terminal IN. The upper bit sequence may consist of multiple bits. The lower bit sequence may also consist of multiple bits.

[0067] The residual voltage holding circuit 20 holds (samples) a voltage signal corresponding to the residual voltage output from the ΔΣ type AD converter 10 at the end of the first period, and supplies that voltage signal to the switching circuit 30 during the second period. The residual voltage holding circuit 20 can be controlled, for example, by a holding circuit reset signal and a sample signal.

[0068] In the first period, the ΔΣ-type AD converter 10 performs AD conversion corresponding to the upper bit sequence, and at the end of the first period, the voltage signal corresponding to the residual voltage held by the residual voltage holding circuit 20 is provided to the ΔΣ-type AD converter 10 by the switching circuit 30. Subsequently, in the second period, the ΔΣ-type AD converter 10 performs AD conversion corresponding to the lower bit sequence. In the first period, the time-series ΔΣ-modulated signal (upper bit sequence) output from the ΔΣ-type AD converter 10 is demodulated into multiple-bit digital signals by the digital demodulation circuit 40. Similarly, in the second period, the time-series ΔΣ-modulated signal (lower bit sequence) output from the ΔΣ-type AD converter 10 is demodulated into multiple-bit digital signals by the digital demodulation circuit 40. The reconstruction circuit 50 generates an output digital signal based on the digital signals of the upper bit sequence and the lower bit sequence demodulated by the digital demodulation circuit 40. The internal signals of the ΔΣ type AD converter 10, the voltage signals held by the residual voltage holding circuit 20, and the internal signals of the digital demodulation circuit 40 are reset according to the reset signal before the start of the first period and before the start of the second period.

[0069] The digital gain adjustment circuit 60 may be positioned between the digital demodulation circuit 40 and the reconstruction circuit 50. The digital gain adjustment circuit 60 can adjust the gain of the digital signal output from the digital demodulation circuit 40 and supply the digital signal with the adjusted gain to the reconstruction circuit 50. The digital gain adjustment circuit 60 may be configured, for example, to adjust the gain of the lower bit sequence of the digital signal output from the digital demodulation circuit 40, but not to adjust the gain of the higher bit sequence of the digital signal output from the digital demodulation circuit 40. The digital gain (correction value) applied by the digital gain adjustment circuit 60 can be acquired prior to the AD conversion of the analog signal that is the target of AD conversion. For example, a reference value analog signal can be input to the AD conversion circuit 1, and a correction value can be generated by comparing the digital signal that should be obtained (expected value) with the digital signal actually output from the AD conversion circuit 1. To further improve the accuracy of the correction, it is preferable to use multiple reference value analog signals with different values ​​to acquire the correction value.

[0070] In the residual voltage holding circuit 20, circuit-specific errors may occur, such as gain errors caused by the finite gain of the amplification circuit. Such gain errors can cause errors between the upper-bit demodulated signal and the lower-bit demodulated signal from the theoretical values ​​shown in equations (2) and (3). This can result in nonlinearity distortion of the A / D converter and degrade its performance. With this configuration, nonlinearity distortion can be improved by digitally correcting the gain error of the residual voltage holding circuit.

[0071] Figure 17 shows a circuit configuration based on the AD conversion circuit 1 of the first embodiment shown in Figure 1. However, it is not limited to this, and a digital gain adjustment circuit 60 may be added to the circuit configurations shown in the second and third embodiments described above.

[0072] The following describes application examples of the AD conversion circuit 1 described above. Figure 18 shows the configuration of a photoelectric converter PEC using the AD conversion circuit 1 of this disclosure. The photoelectric converter PEC can be configured as a solid-state imaging device that captures and outputs an image. Alternatively, the photoelectric converter PEC can be configured as a device that captures an image and outputs a signal obtained from the captured image.

[0073] The photoelectric converter PEC may include, for example, a pixel array (an array composed of multiple photoelectric conversion units) 1000, a vertical drive circuit 1030, a readout circuit (current source, AD conversion circuit) 1010, a control circuit 1050, and a signal processing circuit 1020. The readout circuit 1010 may include multiple current sources connected to multiple vertical lines 1040, and an AD conversion circuit that performs AD conversion on signals output from the pixels of a selected row to the multiple vertical lines 1040. The two-stage ΔΣ type AD conversion circuit (AD conversion circuit 1) described above may be applied to each AD conversion circuit arranged in the readout circuit 1010. This makes it possible to miniaturize the readout circuit 1010.

[0074] The photoelectric conversion device (PEC) may be configured to read a reset level and an optical signal level generated by photoelectric conversion from each pixel of the pixel array 1000 using a readout circuit 1010. The readout circuit 1010 may be configured to output a digital signal of the reset level and a digital signal of the optical signal level. The signal processing circuit 1020 may be configured to perform CDS processing on the digital signal of the reset level and the digital signal of the optical signal level and output the CDS-processed signal. The pixel array 1000, vertical drive circuit 1030, readout circuit 1010, control circuit 1050, and signal processing circuit 1020 may be arranged on a single substrate, distributed across multiple substrates and then stacked, or divided and arranged on multiple chips. The photoelectric conversion device (PEC) may be, for example, a CMOS image sensor. The photoelectric conversion device (PEC) may also be a front-illuminated sensor or a back-illuminated sensor.

[0075] The following describes an example of a photoelectric conversion system using a photoelectric converter (PEC). Figure 19 is a block diagram showing the configuration of a photoelectric conversion system 1400 according to one embodiment. The photoelectric conversion system 1400 of this embodiment includes a photoelectric converter 1415. Here, the photoelectric converter 1415 can be fitted with the above-described photoelectric converter (PEC). The photoelectric conversion system 1400 can be used, for example, as an imaging system. Specific examples of imaging systems include digital still cameras, digital camcorders, and surveillance cameras. Figure 19 shows an example of a digital still camera (imaging device) as the photoelectric conversion system 1400.

[0076] The photoelectric conversion system 1400 shown in Figure 19 includes a photoelectric converter 1415, a lens 1413 that forms an optical image of the subject onto the photoelectric converter 1415, an aperture 1414 for varying the amount of light passing through the lens 1413, and a barrier 1412 for protecting the lens 1413. The lens 1413 and aperture 1414 form an optical system that focuses light onto the photoelectric converter 1415. A photoelectric conversion system used for imaging purposes is also called an imaging system.

[0077] The photoelectric conversion system 1400 has a signal processing unit 1416 that processes the output signal output from the photoelectric conversion device 1415. The signal processing unit 1416 performs signal processing operations that perform various corrections and compressions on the input signal as needed before outputting it. The photoelectric conversion system 1400 further has a buffer memory unit 1406 for temporarily storing image data, and an external interface unit (external I / F unit) 1409 for communicating with an external computer or the like. Furthermore, the photoelectric conversion system 1400 has a recording medium 1411 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 1410 for recording or reading from the recording medium 1411. The recording medium 1411 may be built into the photoelectric conversion system 1400 or it may be detachable. In addition, communication from the recording medium control I / F unit 1410 to the recording medium 1411 and communication from the external I / F unit 1409 may be performed wirelessly.

[0078] Furthermore, the photoelectric conversion system 1400 includes an overall control and calculation unit 1408 that performs various calculations and controls the entire digital still camera, and a timing generation unit 1417 that outputs various timing signals to the photoelectric conversion device 1415 and the signal processing unit 1416. Here, the timing signals and the like may be input from an external source, and the photoelectric conversion system 1400 only needs to include at least the photoelectric conversion device 1415 and the signal processing unit 1416 that processes the output signals output from the photoelectric conversion device 1415. The timing generation unit 1417 may be mounted on the photoelectric conversion device. The overall control and calculation unit 1408 and the timing generation unit 1417 may be configured to perform some or all of the control functions of the photoelectric conversion device 1415.

[0079] The photoelectric converter 1415 outputs an image signal to the signal processing unit 1416. The signal processing unit 1416 performs predetermined signal processing on the image signal output from the photoelectric converter 1415 and outputs image data. The signal processing unit 1416 also generates an image using the image signal. The signal processing unit 1416 may also perform distance measurement calculations on the signal output from the photoelectric converter 1415. The signal processing unit 1416 and the timing generation unit 1417 may be mounted on the photoelectric converter. In other words, the signal processing unit 1416 and the timing generation unit 1417 may be provided on the substrate on which the pixels are arranged, or they may be provided on a separate substrate. By configuring an imaging system using the photoelectric converters of each embodiment described above, an imaging system capable of acquiring higher quality images can be realized.

[0080] Other embodiments of the photoelectric conversion system or mobile device will be described with reference to Figure 20. Figure 20 is a schematic diagram showing an example of the configuration of the photoelectric conversion system or mobile device according to this embodiment. In this embodiment, an example of an in-vehicle camera is shown as the photoelectric conversion system.

[0081] Figure 20 shows an example of a vehicle system and a photoelectric conversion system mounted thereon for imaging. The photoelectric conversion system 1301 includes a photoelectric converter 1302, an image preprocessing unit 1315, an integrated circuit 1303, and an optical system 1314. Here, the photoelectric converter 1302 can be the photoelectric converter PEC described above. The optical system 1314 forms an optical image of the subject on the photoelectric converter 1302. The photoelectric converter 1302 converts the optical image of the subject formed by the optical system 1314 into an electrical signal. The photoelectric converter 1302 can be the photoelectric converter described above. The image preprocessing unit 1315 performs predetermined signal processing on the signal output from the photoelectric converter 1302. The functions of the image preprocessing unit 1315 may be incorporated into the photoelectric converter 1302. The photoelectric conversion system 1301 is provided with at least two sets of optical systems 1314, photoelectric conversion devices 1302, and image preprocessing units 1315, and the output from each set of image preprocessing units 1315 is input to the integrated circuit 1303.

[0082] The integrated circuit 1303 is an integrated circuit for imaging system applications and includes an image processing unit 1304 with memory 1305, an optical distance measuring unit 1306, a distance measurement calculation unit 1307, an object recognition unit 1308, and an anomaly detection unit 1309. The image processing unit 1304 performs image processing such as development and defect correction on the output signal of the image preprocessing unit 1315. The memory 1305 stores the primary storage of the captured image and the location of defects in the captured pixels. The optical distance measuring unit 1306 focuses on the subject and measures the distance. The distance measurement calculation unit 1307 calculates distance measurement information from multiple image data acquired by multiple photoelectric converters 1302. The object recognition unit 1308 recognizes subjects such as cars, roads, signs, and people. When the anomaly detection unit 1309 detects an anomaly in the photoelectric converter 1302, it alerts the main control unit 1313 to the anomaly.

[0083] The integrated circuit 1303 may be implemented by specially designed hardware, by a software module, or by a combination of these. It may also be implemented by a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC), or by a combination of these.

[0084] The main control unit 1313 oversees and controls the operation of the photoelectric conversion system 1301, the vehicle sensor 1310, the control unit 1320, and other components. Alternatively, the system may not have a main control unit 1313, and the photoelectric conversion system 1301, the vehicle sensor 1310, and the control unit 1320 may each have their own communication interfaces, sending and receiving control signals via a communication network (e.g., CAN standard).

[0085] The integrated circuit 1303 has the function of receiving control signals from the main control unit 1313 or transmitting control signals and set values ​​to the photoelectric converter 1302 via its own control unit.

[0086] The photoelectric conversion system 1301 is connected to the vehicle sensor 1310 and can detect the vehicle's driving conditions, such as vehicle speed, yaw rate, and steering angle, as well as the external environment and the state of other vehicles and obstacles. The vehicle sensor 1310 also serves as a distance information acquisition means for acquiring distance information to objects. Furthermore, the photoelectric conversion system 1301 is connected to the driver assistance control unit 1311, which performs various driving assistance functions such as automatic steering, automatic cruising, and collision avoidance. In particular, regarding the collision judgment function, it determines whether a collision with another vehicle or obstacle has occurred and estimates a collision based on the detection results of the photoelectric conversion system 1301 and the vehicle sensor 1310. This enables avoidance control when a collision is estimated and activation of safety devices in the event of a collision.

[0087] Furthermore, the photoelectric conversion system 1301 is also connected to a warning device 1312 that issues a warning to the driver based on the judgment result of the collision judgment unit. For example, if the collision judgment unit determines that there is a high probability of collision, the main control unit 1313 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 1312 warns the user by sounding an alarm, displaying warning information on a display screen such as the car navigation system or instrument panel, or vibrating the seat belt or steering wheel.

[0088] This disclosure includes the following AD conversion circuits, photoelectric converters, imaging devices, moving bodies, and methods for driving AD conversion circuits.

[0089] (Item 1) An AD conversion circuit that converts an analog signal applied to an input terminal into a digital signal, A ΔΣ type AD converter including an integrating circuit for integrating the difference signal, A switching circuit that, in the first period, supplies an analog signal to the input terminal to the ΔΣ type AD converter, and in the second period following the first period, switches the supply of a voltage signal corresponding to the voltage output from the integrating circuit at the end of the first period to the ΔΣ type AD converter, The system includes a holding circuit that holds the voltage signal corresponding to the voltage output from the integrating circuit at the end of the first period, and provides the voltage signal to the ΔΣ type AD converter via the switching circuit during the second period, The aforementioned integrating circuit is characterized by including a continuous-time integrator and a discrete-time integrator connected to the output of the continuous-time integrator.

[0090] (Item 2) The system further includes a comparator connected to the output of the discrete-time integrator and a DA converter connected to the output of the comparator, The AD conversion circuit according to item 1, characterized in that the comparator compares the output of the discrete-time integrator with a reference signal.

[0091] (Item 3) The AD conversion circuit according to item 2, characterized in that the discrete-time integrator includes a first sample circuit connected to the output of the continuous-time integrator and a second sample circuit connected to the output of the DA converter.

[0092] (Item 4) The discrete-time integrator includes a first sample circuit connected to the output of the continuous-time integrator, The AD conversion circuit according to item 2, characterized in that the comparator compares the output of the continuous-time integrator and the analog signal supplied to the continuous-time integrator with the reference signal, in addition to the output of the discrete-time integrator.

[0093] (Item 5) The AD conversion circuit according to item 4, characterized in that the discrete-time integrator further includes a second sample circuit connected to the output of the continuous-time integrator.

[0094] (Item 6) The AD conversion circuit according to item 5, characterized in that the output of the continuous-time integrator is alternately sampled by the first sample circuit and the second sample circuit.

[0095] (Item 7) The AD conversion circuit according to any one of items 1 to 6, characterized in that the continuous-time integrator is a Gm-C type integrator.

[0096] (Item 8) The AD conversion circuit according to any one of items 1 to 7, further comprising a buffer circuit that buffers the output of the switching circuit and supplies it to the ΔΣ type AD converter.

[0097] (Item 9) The buffer circuit includes an amplifier, During the first period, the analog signal supplied to the input terminal is buffered using the amplifier. The AD conversion circuit according to item 8, characterized in that, during the second period, the voltage signal held in the holding circuit is held and buffered using the amplifier.

[0098] (Item 10) The AD conversion circuit according to any one of items 1 to 9, further comprising a voltage adjustment circuit for adjusting the voltage of the internal nodes of the ΔΣ type AD converter within a predetermined range.

[0099] (Item 11) The AD conversion circuit according to item 10, characterized in that the voltage adjustment circuit adjusts the voltage of the internal node of the continuous-time integrator to a predetermined range.

[0100] (Item 12) A digital demodulation circuit that generates a digital signal of the upper bit sequence based on the output of the ΔΣ type AD converter in the first period, and generates a digital signal of the lower bit sequence based on the output of the ΔΣ type AD converter in the second period, A reconfiguration circuit that generates an output digital signal based on the digital signal of the upper bit sequence and the digital signal of the lower bit sequence, An AD conversion circuit according to any one of items 1 to 11, further comprising the above.

[0101] (Item 13) The AD conversion circuit according to item 12, further comprising a gain adjustment circuit disposed between the digital demodulation circuit and the reconstruction circuit.

[0102] (Item 14) The AD conversion circuit according to item 13, characterized in that the gain adjustment circuit performs gain adjustment on the lower bit sequence of the digital signal.

[0103] (Item 15) Photoelectric conversion unit, An AD conversion circuit according to any one of items 1 to 14, configured to convert the analog signal output by the photoelectric conversion unit into a digital signal, A photoelectric conversion device characterized by comprising the following features.

[0104] (Item 16) The photoelectric converter described in item 15, A signal processing unit that processes the signal output from the photoelectric converter, An imaging device characterized by comprising:

[0105] (Item 17) A mobile body characterized by being equipped with the imaging device described in item 16.

[0106] (Item 18) A method for driving an AD conversion circuit that converts an analog signal applied to an input terminal into a digital signal, The AD conversion circuit comprises a ΔΣ type AD converter including an integration circuit for integrating the difference signal, a holding circuit, and a switching circuit for switching the connection between the input terminal and the ΔΣ type AD converter and between the holding circuit and the ΔΣ type AD converter. The aforementioned drive method is The first step is that the switching circuit connects the input terminal and the ΔΣ type AD converter so that the analog signal supplied to the input terminal is supplied to the ΔΣ type AD converter, and the holding circuit holds a voltage signal corresponding to the voltage output from the integrating circuit. The process includes, after the first step, a second step in which the switching circuit connects the holding circuit and the ΔΣ type AD converter so that the voltage signal held by the holding circuit at the end of the first step is supplied to the ΔΣ type AD converter, The driving method is characterized in that the integrating circuit includes a continuous-time integrator and a discrete-time integrator connected to the output of the continuous-time integrator.

[0107] The invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, claims are attached to disclose the scope of the invention. [Explanation of Symbols]

[0108] 1: AD conversion circuit, 10: ΔΣ type AD converter, 20: Holding circuit, 30: Switching circuit, 110: Continuous-time integrator, 120, 130, 131: Discrete-time integrator, IN: Input terminal

Claims

1. An AD conversion circuit that converts an analog signal applied to an input terminal into a digital signal, A ΔΣ type AD converter including an integrating circuit for integrating the difference signal, A switching circuit that, during the first period, supplies an analog signal to the input terminal to the ΔΣ type AD converter, and during the second period following the first period, switches the supply of a voltage signal corresponding to the voltage output from the integration circuit at the end of the first period to the ΔΣ type AD converter, The system includes a holding circuit that holds the voltage signal corresponding to the voltage output from the integrating circuit at the end of the first period, and provides the voltage signal to the ΔΣ type AD converter via the switching circuit during the second period, The AD conversion circuit is characterized by including a continuous-time integrator and a discrete-time integrator connected to the output of the continuous-time integrator.

2. The system further includes a comparator connected to the output of the discrete-time integrator, and a DA converter connected to the output of the comparator, The AD conversion circuit according to claim 1, characterized in that the comparator compares the output of the discrete-time integrator with a reference signal.

3. The AD conversion circuit according to claim 2, characterized in that the discrete-time integrator includes a first sample circuit connected to the output of the continuous-time integrator and a second sample circuit connected to the output of the DA converter.

4. The discrete-time integrator includes a first sample circuit connected to the output of the continuous-time integrator, The AD conversion circuit according to claim 2, characterized in that the comparator compares the output of the continuous-time integrator and the analog signal supplied to the continuous-time integrator with the reference signal, in addition to the output of the discrete-time integrator.

5. The AD conversion circuit according to claim 4, characterized in that the discrete-time integrator further includes a second sample circuit connected to the output of the continuous-time integrator.

6. The AD conversion circuit according to claim 5, characterized in that the output of the continuous-time integrator is alternately sampled by the first sample circuit and the second sample circuit.

7. The AD conversion circuit according to claim 1, characterized in that the continuous-time integrator is a Gm-C type integrator.

8. The AD conversion circuit according to claim 1, further comprising a buffer circuit that buffers the output of the switching circuit and supplies it to the ΔΣ type AD converter.

9. The buffer circuit includes an amplifier, During the first period, the analog signal supplied to the input terminal is buffered using the amplifier. The AD conversion circuit according to claim 8, characterized in that, during the second period, the voltage signal held in the holding circuit is held and buffered using the amplifier.

10. The AD conversion circuit according to claim 1, further comprising a voltage adjustment circuit for adjusting the voltage of the internal nodes of the ΔΣ type AD converter within a predetermined range.

11. The AD conversion circuit according to claim 10, characterized in that the voltage adjustment circuit adjusts the voltage of the internal node of the continuous-time integrator to within a predetermined range.

12. A digital demodulation circuit that generates a digital signal of the upper bit sequence based on the output of the ΔΣ type AD converter in the first period, and generates a digital signal of the lower bit sequence based on the output of the ΔΣ type AD converter in the second period, A reconfiguration circuit that generates an output digital signal based on the digital signal of the upper bit sequence and the digital signal of the lower bit sequence, The AD conversion circuit according to claim 1, further comprising the above.

13. The AD conversion circuit according to claim 12, further comprising a gain adjustment circuit disposed between the digital demodulation circuit and the reconstruction circuit.

14. The AD conversion circuit according to claim 13, characterized in that the gain adjustment circuit performs gain adjustment on the digital signal of the lower bit sequence.

15. Photoelectric conversion unit, An AD conversion circuit according to any one of claims 1 to 14, configured to convert an analog signal output by the photoelectric conversion unit into a digital signal, A photoelectric conversion device characterized by comprising the following features.

16. The photoelectric conversion device according to claim 15, A signal processing unit that processes the signal output from the photoelectric converter, An imaging device characterized by comprising:

17. A mobile body characterized by comprising the imaging device described in claim 16.

18. A method for driving an AD conversion circuit that converts an analog signal applied to an input terminal into a digital signal, The AD conversion circuit comprises a ΔΣ type AD converter including an integration circuit for integrating the difference signal, a holding circuit, and a switching circuit for switching the connection between the input terminal and the ΔΣ type AD converter and between the holding circuit and the ΔΣ type AD converter. The aforementioned drive method is The first step is that the switching circuit connects the input terminal and the ΔΣ type AD converter so that the analog signal supplied to the input terminal is supplied to the ΔΣ type AD converter, and the holding circuit holds a voltage signal corresponding to the voltage output from the integrating circuit. The process includes a second step in which the switching circuit connects the holding circuit and the ΔΣ type AD converter so that the voltage signal held by the holding circuit at the end of the first step is supplied to the ΔΣ type AD converter, The driving method is characterized in that the integrating circuit includes a continuous-time integrator and a discrete-time integrator connected to the output of the continuous-time integrator.

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