Pulse width conversion circuit

Abstract

To provide a pulse width conversion circuit capable of suppressing the usage of a microprocessor.SOLUTION: A pulse width conversion circuit 1 includes: an A / D converter 30 which converts an analog input signal AS3 into a digital input signal DS and transmits the digital input signal DS by SPI communication; a digital potentiometer 50 which receives the digital input signal DS by the SPI communication and generates resistance including a resistance value based on a value of the digital input signal DS; and a multi-vibrator component 60 which includes a circuit constituting a multi-vibrator together with the resistance included in the digital potentiometer 50 and which outputs a pulse signal PS having a pulse width based on the resistance value. Each of the A / D converter 30, the digital potentiometer 50, and the multi-vibrator component 60 is constituted from a component with an independent package.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a pulse width conversion circuit.

Background Art

[0002] Patent Document 1 discloses a pulse width modulation A / D converter. In this A / D converter, an analog input signal to be converted is input to an integrator, and a pulse width modulation signal based on the analog input signal to be converted is output from the integrator. By counting the pulse width of the pulse width modulation signal, the pulse width modulation signal is converted into a digital signal. This A / D converter has a charge transfer element that performs charge transfer instead of a resistor generally used for an integrator. The charge transfer element consists of a switching means and a capacitor.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] As a circuit for converting a pulse width, there is one that uses a microprocessor. The microprocessor generates a pulse signal having a pulse width corresponding to the digital signal based on the digital signal input from the outside. However, in a circuit using a microprocessor, a program of the microprocessor is required, which is troublesome in manufacturing. In addition to the microprocessor, peripheral circuits such as a clock generator are required, and the circuit becomes complicated.

[0005] The present disclosure has been made in view of such problems, and an object thereof is to provide a pulse width conversion circuit capable of suppressing the use of a microprocessor.

Means for Solving the Problems

[0006] [1] A pulse width conversion circuit according to one embodiment of the present disclosure comprises an analog input unit, an A / D converter, a digital potentiometer, a clock generation unit, a chip select generation unit, and a multivibrator component. The analog input unit receives an analog input signal having an analog voltage value. The A / D converter is electrically connected to the analog input unit. The A / D converter includes a circuit that converts the analog input signal into a digital input signal having a digital value, and transmits the digital input signal via SPI communication. The digital potentiometer receives the digital input signal transmitted from the A / D converter via SPI communication and generates a resistor including a resistance value based on the value of the digital input signal. The clock generation unit generates a clock signal for SPI communication. The chip select generation unit generates a chip select signal for SPI communication. The multivibrator component is electrically connected to the digital potentiometer. The multivibrator component includes a circuit that constitutes a multivibrator together with the resistor included in the digital potentiometer, and outputs a pulse signal having a pulse width based on the resistance value. The A / D converter, digital potentiometer, clock generation unit, chip select generation unit, and multivibrator components are each composed of components in separate packages.

[0007] The pulse width conversion circuit described above can perform pulse width conversion in the same way as when using a microprocessor, by incorporating an A / D converter, a digital potentiometer, a clock generation unit, a chip select generation unit, and components for a multivibrator. Furthermore, since the A / D converter, digital potentiometer, clock generation unit, chip select generation unit, and multivibrator components are each composed of components in independent packages (i.e., discrete components), the pulse width conversion circuit can be constructed while suppressing the use of a microprocessor. Therefore, a microprocessor program is not required, and the manufacturing process is simplified. In addition, the circuit can be simplified compared to cases where a microprocessor and its peripheral circuits are provided, and manufacturing costs can be reduced.

[0008] [2] In the pulse width conversion circuit described in [1] above, the analog input section may include a first input section configured to receive an analog input signal, a second input section configured to receive an analog input signal, and a selector switch electrically connected to the first and second input sections, which selectively outputs either the analog input signal from the first input section or the analog input signal from the second input section to the A / D converter. This makes it possible to switch the input source of the analog input signal. For example, when the pulse width conversion circuit described above is incorporated into a device, it is possible to select either an analog input signal provided by a control unit that controls the device as a whole, or an analog input signal that is input to operate the pulse width conversion circuit independently during inspection of the device, etc.

[0009] [3] The pulse width conversion circuit described in [1] or [2] above may further include an amplification circuit. The amplification circuit is electrically connected between the analog input section and the A / D converter, amplifies the analog input signal from the analog input section, and outputs the amplified analog input signal to the A / D converter. By amplifying the analog input signal with the amplification circuit, the A / D converter can convert the analog input signal into a digital input signal with greater accuracy. [Effects of the Invention]

[0010] According to this disclosure, a pulse width conversion circuit can be provided that can reduce the use of a microprocessor. [Brief explanation of the drawing]

[0011] [Figure 1] This is a circuit diagram showing a part of the configuration of a pulse width conversion circuit 1 according to one embodiment. [Figure 2] This is a circuit diagram showing the remaining configuration of the pulse width conversion circuit 1 according to one embodiment. [Modes for carrying out the invention]

[0012] Hereinafter, embodiments of the pulse width conversion circuit according to this disclosure will be described in detail with reference to the attached drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant explanations are omitted.

[0013] Figure 1 is a circuit diagram showing a part of the configuration of the pulse width conversion circuit 1 according to this embodiment. Figure 2 is a circuit diagram showing the configuration of the remaining part of the pulse width conversion circuit 1 according to this embodiment. This pulse width conversion circuit 1 outputs a pulse signal PS having a pulse width corresponding to the voltage value of an analog input signal AS1 (or AS2) input from an external source. As shown in Figures 1 and 2, the pulse width conversion circuit 1 comprises an analog input unit 10, an amplification circuit 20, an A / D converter 30, a clock generation unit 40A, a chip select generation unit 40B, a digital potentiometer 50, and a multivibrator component 60. The analog input unit 10, the amplification circuit 20, the A / D converter 30, the clock generation unit 40A, the chip select generation unit 40B, the digital potentiometer 50, and the multivibrator component 60 are mounted on a common wiring board.

[0014] The analog input unit 10 receives an analog input signal AS1 or AS2 having an analog voltage value from outside the pulse width conversion circuit 1. The analog input unit 10 of this embodiment includes a first input unit 11, a second input unit 12, and a changeover switch 13. The first input unit 11 receives the analog input signal AS1. The second input unit 12 receives the analog input signal AS2, which has a different input path from the analog input signal AS1. The analog input signal AS1 is, for example, an analog input signal provided by a control unit (not shown) that controls a device (such as a vacuum device) when the pulse width conversion circuit 1 is incorporated into the device. The analog input signal AS2 is, for example, an analog input signal that is input to operate the pulse width conversion circuit 1 independently during inspection of the device when the pulse width conversion circuit 1 is incorporated into the device.

[0015] As an example, the first input section 11 and the second input section 12 include a connector 14, a resistor 15, and a bypass capacitor 16. The connector 14 includes multiple (four in the illustrated example) terminals. One terminal of the connector 14 is electrically connected to a power supply potential line 81 inside the pulse width conversion circuit 1, supplying a reference voltage (e.g., +5V) to the wiring connected to the connector 14. Another terminal of the connector 14 is electrically connected to a reference potential line (GND line) 82 inside the pulse width conversion circuit 1, providing a reference potential to the wiring connected to the connector 14. Yet another terminal of the connector 14 (signal input terminal) is electrically connected to a changeover switch 13 via a resistor 15. An analog input signal AS1 is input to the signal input terminal of the first input section 11 from outside the pulse width conversion circuit 1. An analog input signal AS2 is input to the signal input terminal of the second input section 12 from outside the pulse width conversion circuit 1. One end of the bypass capacitor 16 is electrically connected to the node between the resistor 15 and the changeover switch 13, and the other end of the bypass capacitor 16 is electrically connected to the reference potential line 82. The resistor 15 and the bypass capacitor 16 function as filters to reduce noise contained in the analog input signals AS1 and AS2.

[0016] The selector switch 13 is electrically connected to the first input section 11 and the second input section 12, and selectively outputs either the analog input signal AS1 from the first input section 11 or the analog input signal AS2 from the second input section 12 to the A / D converter 30 (to the amplification circuit 20 in this embodiment). The selector switch 13 in the illustrated example includes two input terminals and one output terminal. One input terminal is electrically connected to the signal input terminal of the connector 14 of the first input section 11 via the resistor 15 of the first input section 11. The other input terminal is electrically connected to the signal input terminal of the connector 14 of the second input section 12 via the resistor 15 of the second input section 12. The output terminal is electrically connected to the A / D converter 30 via the amplification circuit 20. The connection of the output terminal is selectively switched to one of the two input terminals. A bypass capacitor 17 for stabilizing the output potential is electrically connected between the output terminal and the reference potential line 82. The changeover switch 13 may be a mechanical switch such as an electromagnetic relay or a toggle switch, or it may be composed of a semiconductor switch such as a transistor.

[0017] Although the analog input unit 10 shown as an example has two input units (first input unit 11 and second input unit 12), the analog input unit 10 may have only one input unit (only the first input unit 11), or it may have three or more input units that can be switched using a changeover switch.

[0018] The amplification circuit 20 is electrically connected between the analog input section 10 and the A / D converter 30. The amplification circuit 20 amplifies the analog input signal AS1 (or AS2) from the analog input section 10 and outputs the amplified analog input signal AS3 to the A / D converter 30. The amplification circuit 20 in the illustrated example includes an operational amplifier 21 and a resistor 22. The operational amplifier 21 is composed of components with independent packages (discrete components). The operational amplifier 21 has an inverting input terminal, a non-inverting input terminal, an output terminal, a positive power supply terminal, and a negative power supply terminal. One end of the resistor 22 is electrically connected to the output terminal of the operational amplifier 21. The other end of the resistor 22 is electrically connected to node N1, which is the output point of the amplification circuit 20. The inverting input terminal of the operational amplifier 21 is electrically connected to node N1 for feedback. The non-inverting input terminal of the operational amplifier 21 is electrically connected to the analog input section 10 (more specifically, the output terminal of the selector switch 13). A positive first power supply voltage (e.g., +15V) is input to the positive power supply terminal of the operational amplifier 21 from the power supply potential line 83. A negative second power supply voltage (e.g., -15V) is input to the negative power supply terminal of the operational amplifier 21 from the power supply potential line 84. Bypass capacitors 23 for noise reduction are connected to both the positive and negative power supply terminals of the operational amplifier 21. The amplification circuit 20 can be omitted if it is not needed.

[0019] The A / D converter 30 is electrically connected to the analog input section 10 via the amplification circuit 20. The A / D converter 30 includes a circuit that converts the analog input signal AS3 into a digital input signal DS having a digital value. The A / D converter 30 also transmits the digital input signal DS via SPI communication. The A / D converter 30 is composed of components (discrete components) in separate packages.

[0020] The A / D converter 30 in the figure example includes a positive input terminal (denoted as Vin+ in the figure), a negative input terminal (denoted as Vin- in the figure), a GND terminal, a power supply terminal (denoted as Vcc in the figure), and a reference voltage terminal (denoted as Vref in the figure). The positive input terminal is electrically connected to node N1 via resistor 31, and an amplified analog input signal AS3 is input to the positive input terminal. A bypass capacitor 32 for stabilizing the potential is connected to the node between the positive input terminal and resistor 31. The negative input terminal is electrically connected to the reference potential line 82, and a reference potential (GND potential) is input to the negative input terminal. The A / D converter 30 converts the potential difference between the positive input terminal and the negative input terminal into a digital input signal DS. The GND terminal is connected to the reference potential line 82. The power supply terminal and the reference voltage terminal are connected to the power supply potential line 81, and a positive third power supply voltage (for example, +5V) is supplied to the power supply terminal and the reference voltage terminal. A bypass capacitor 33 for noise reduction is connected to the power supply terminal and the reference voltage terminal.

[0021] The A / D converter 30 further includes a chip select terminal (denoted as CS in the figure), a clock terminal (denoted as CLK in the figure), and a data terminal (denoted as Da in the figure) for SPI communication. These terminals for SPI communication are respectively connected to the chip select wiring 91, the clock wiring 92, and the data wiring 93 included in the SPI communication wiring group 90. The digital input signal DS generated by the A / D converter 30 is output as a serial signal from the data terminal of the A / D converter 30 to the data wiring 93 of the SPI communication wiring group 90.

[0022] The clock generation unit 40A generates a clock signal SCLK for SPI communication. The frequency of the clock signal SCLK is, for example, 180 kHz. The chip select generation unit 40B generates a chip select signal SCS for SPI communication. The frequency of the chip select signal SCS is, for example, 1 / 20 (9 kHz) of the frequency of the clock signal SCLK. The clock generation unit 40A and the chip select generation unit 40B are each composed of components (discrete components) having independent packages. In the illustrated example, the components constituting the chip select generation unit 40B are the same as the components constituting the clock generation unit 40A.

[0023] In the illustrated example, the clock generation unit 40A and the chip select generation unit 40B have an OUTPUT terminal, a TRIGGER terminal, a THRESHOLD terminal, and a power supply terminal (V in the figure). +and a display), a GND terminal, a DISCHARGE terminal, and a RESET terminal. The OUTPUT terminal is electrically connected to the THRESHOLD terminal via a variable resistor 41 and a fixed resistor 42 connected in series to each other. The resistance value between the OUTPUT terminal and the THRESHOLD terminal, and the capacitor 52 connected between the THRESHOLD terminal and the reference potential line 82 determine the frequencies of the clock signal SCLK and the chip select signal SCS. The TRIGGER terminal is short-circuited to the THRESHOLD terminal. The power supply terminal is electrically connected to the power supply potential line 83, and a positive first power supply voltage (e.g., +15V) is input to the power supply terminal from the power supply potential line 83. A bypass capacitor 43 is connected to the power supply terminal for noise reduction. The GND terminal is connected to the reference potential line 82. The DISCHARGE terminal is connected to the power supply potential line 83 via a pull-up resistor 44. The DISCHARGE terminal of the clock generation unit 40A is electrically connected to the clock wiring 92 and outputs the clock signal SCLK to the clock wiring 92. The DISCHARGE terminal of the chip select generation unit 40B outputs the chip select signal SCS. The RESET terminal of the clock generation unit 40A is connected to the DISCHARGE terminal of the chip select generation unit 40B. Thereby, the clock signal SCLK is synchronized with the chip select signal SCS.

[0024] The pulse width conversion circuit 1 of this embodiment further includes a common-source circuit 45 for inverting the logic of the chip select signal SCS and supplying it to the chip select wiring 91. The common-source circuit 45 is interposed between the chip select generation unit 40B and the chip select wiring 91. The chip select generation unit 40B provides the chip select signal SCS to the chip select wiring 91 via the common-source circuit 45. Specifically, the common-source circuit 45 includes an FET 46 and a resistor 47. The gate terminal of the FET 46 is electrically connected to the DISCHARGE terminal of the chip select generation unit 40B and receives the chip select signal SCS. The drain terminal of the FET 46 is connected to the power supply potential line 81 via the resistor 47. A bypass capacitor 48 and a resistor 49 for stabilizing the chip select signal SCS are connected between the gate terminal of the FET 46 and the reference potential line 82.

[0025] The digital potentiometer 50 receives the digital input signal DS transmitted from the A / D converter 30 via SPI communication and generates a resistor including a resistance value based on the value of the digital input signal DS. The digital potentiometer 50 is also composed of components (discrete components) in separate packages.

[0026] Specifically, the digital potentiometer 50 includes a chip select terminal (indicated as CS in the figure), a clock terminal (indicated as CLK in the figure), and a data terminal (indicated as SD1 in the figure) for SPI communication. These terminals for SPI communication are connected to the chip select wiring 91, clock wiring 92, and data wiring 93, respectively, which are included in the SPI communication wiring group 90. The digital input signal DS generated by the A / D converter 30 is input to the data terminal of the digital potentiometer 50 via the data wiring 93 of the SPI communication wiring group 90.

[0027] The digital potentiometer 50 further includes a first power supply terminal (indicated as Vdd in the figure), a second power supply terminal (indicated as Vss in the figure), a GND terminal, an RS terminal, and an SHDN terminal. The first power supply terminal is connected to a power supply potential line 83, from which a positive first power supply voltage (e.g., +15V) is input to the first power supply terminal. The second power supply terminal is connected to a power supply potential line 84, from which a negative second power supply voltage (e.g., -15V) is input to the first power supply terminal. Bypass capacitors 51 are connected to each of the first and second power supply terminals. The GND terminal is connected to a reference potential line 82. The RS terminal and the SHDN terminal are connected to the power supply potential line 81.

[0028] The digital potentiometer 50 further includes terminals A, B, and W. A fixed resistor is built in between terminals A and B, and this fixed resistor is divided by terminal W. The division point is determined according to the digital input signal DS. That is, the resistance value between terminal W and terminal A, and the resistance value between terminal W and terminal B are determined according to the digital input signal DS. This generates a resistor between terminal W and both terminals A and B, with a resistance value based on the value of the digital input signal DS. In the illustrated example, terminal B is electrically connected to the power supply potential line 83, and terminal W is electrically connected to the multivibrator component 60.

[0029] The multivibrator component 60 is electrically connected to the digital potentiometer 50. The multivibrator component 60 includes a circuit that constitutes a multivibrator together with the resistor included in the digital potentiometer 50, and outputs a pulse signal PS. The multivibrator in this embodiment is a monostable multivibrator. The multivibrator component 60 is also composed of components having independent packages (discrete components).

[0030] The time width of the pulse signal PS is based on the resistance value of the resistor between the W terminal and the B terminal included in the digital potentiometer 50. More specifically, the time width of the pulse signal PS is based on the resistance value determined by the resistor included in the digital potentiometer 50 and the series connection of the fixed resistor 61 and variable resistor 62 provided outside the multivibrator component 60, and the capacitance value of the capacitor 63 provided outside the multivibrator component 60. The resistance value of the variable resistor 62 is pre-adjusted.

[0031] Specifically, the multivibrator component 60 includes terminals T1, T2, A, B, Q, and CD. One end of capacitor 63 is connected to terminal T1, and the other end of capacitor 63 is connected to terminal T2. Terminal T2 is also connected to terminal W of the digital potentiometer 50 via a fixed resistor 61 and a variable resistor 62. A pulse signal PS with a time width corresponding to the capacitance value of capacitor 63 connected to terminals T1 and T2, as well as the resistance values ​​of the digital potentiometer 50, fixed resistor 61, and variable resistor 62, is output from terminal Q. The output timing of the pulse signal PS is determined by a trigger signal TS input to terminal A or B. In the illustrated example, terminal A is short-circuited to terminal Q. As a result, while the pulse signal PS is output from terminal Q due to the input of trigger signal TS, the input of trigger signal TS is disabled. In other words, the circuit that shorts terminal A and terminal Q functions as a malfunction prevention circuit for the multivibrator component 60 during the output of the pulse signal PS. A reset signal RS, which forcibly terminates the pulse signal PS, is input to terminals CD from outside the pulse width conversion circuit 1.

[0032] The pulse width conversion circuit 1 of this embodiment further comprises a trigger signal generation unit 70. The trigger signal generation unit 70 provides a trigger signal TS to the multivibrator component 60. The trigger signal generation unit 70 has a comparator 71. An analog signal, the signal to be measured MS, is input to the first input terminal of the comparator 71. A reference voltage SV is input to the second input terminal of the comparator 71. The comparator 71 outputs a trigger signal TS when the voltage value of the signal to be measured MS exceeds the reference voltage SV. Therefore, the pulse width conversion circuit 1 of this embodiment outputs a pulse signal PS having a time width determined by the analog input signal AS1 (or AS2) to the outside when the voltage value of the signal to be measured MS exceeds the reference voltage SV. The signal to be measured MS varies depending on the device in which the pulse width conversion circuit 1 is incorporated. For example, if the pulse width conversion circuit 1 is incorporated into a vacuum device, the signal to be measured MS may be a signal indicating the degree of vacuum in the device. The significance of the trigger signal TS is not limited to this, and other trigger signals TS with different significances may be provided to the multivibrator component 60.

[0033] The effects obtained by the pulse width conversion circuit 1 of this embodiment, as described above, will now be explained. According to the pulse width conversion circuit 1 of this embodiment, by providing an A / D converter 30, a clock generation unit 40A, a chip select generation unit 40B, a digital potentiometer 50, and a multivibrator component 60, pulse width conversion can be performed in the same way as when a microprocessor is used. Furthermore, the A / D converter 30, clock generation unit 40A, chip select generation unit 40B, digital potentiometer 50, and multivibrator component 60 are each composed of components with independent packages (i.e., discrete components). This makes it possible to construct the pulse width conversion circuit 1 while suppressing the use of a microprocessor. Therefore, a microprocessor program is not required, and the manufacturing process of the pulse width conversion circuit 1 is simplified. In addition, compared to the case in which a microprocessor and its peripheral circuits are provided, the circuit can be simplified and manufacturing costs can be reduced.

[0034] As in this embodiment, the analog input unit 10 may include a first input unit 11 configured to receive an analog input signal AS1, a second input unit 12 configured to receive an analog input signal AS2, and a selector switch 13 electrically connected to the first input unit 11 and the second input unit 12, which selectively outputs either the analog input signal AS1 from the first input unit 11 or the analog input signal AS2 from the second input unit 12 to the A / D converter 30. This makes it possible to switch the input source of the analog input signal. For example, when the pulse width conversion circuit 1 is incorporated into a certain device, it is possible to select either the analog input signal AS1 provided by a control unit that controls the device as a whole, or the analog input signal AS2 that is input to operate the pulse width conversion circuit 1 independently during inspection of the device, etc.

[0035] As in this embodiment, the pulse width conversion circuit 1 may also include an amplification circuit 20. The amplification circuit 20 is electrically connected between the analog input unit 10 and the A / D converter 30, and amplifies the analog input signal AS1 or AS2 from the analog input unit 10, outputting the amplified analog input signal AS3 to the A / D converter 30. By amplifying the analog input signals AS1 and AS2 with the amplification circuit 20, the A / D converter 30 can convert the analog input signal AS3 into a digital input signal DS with greater accuracy. [Explanation of Symbols]

[0036] 1...Pulse width conversion circuit, 10...Analog input section, 11...First input section, 12...Second input section, 13...Selector switch, 14...Connector, 15,22,31...Resistors, 16,17,23,32,33...Bypass capacitors, 20...Amplification circuit, 21...Operational amplifier, 30...A / D converter, 40A...Clock generation section, 40B...Chip select generation section, 41...Variable resistor, 42...Fixed resistor, 43...Bypass capacitor, 44...Pull-up resistor, 45...Common source circuit, 46...FET, 47,49...Resistors, 48,51...Bypass capacitors, 50...Digital potentiometer Data, 52...Capacitor, 60...Component for multivibrator, 61...Fixed resistor, 62...Variable resistor, 63...Capacitor, 70...Trigger signal generation unit, 71...Comparator, 81, 83, 84...Power supply potential line, 82...Reference potential line, 90...SPI communication wiring group, 91...Chip select wiring, 92...Clock wiring, 93...Data wiring, AS1, AS2, AS3...Analog input signal, DS...Digital input signal, MS...Measurement target signal, N1...Node, PS...Pulse signal, SCLK...Clock signal, SCS...Chip select signal, SV...Reference voltage, TS...Trigger signal.

Claims

1. An analog input section that receives an analog input signal having an analog voltage value, An A / D converter is electrically connected to the analog input section and includes a circuit that converts the analog input signal into a digital input signal having a digital value, and transmits the digital input signal via SPI communication. A digital potentiometer that receives the digital input signal transmitted from the A / D converter via SPI communication and generates a resistor including a resistance value based on the value of the digital input signal, A clock generation unit that generates the clock signal for the SPI communication, A chip select generation unit that generates the chip select signal for the SPI communication, A multivibrator component that includes a circuit electrically connected to the digital potentiometer and constituting a multivibrator together with the resistor included in the digital potentiometer, and which outputs a pulse signal having a pulse width based on the resistance value, Equipped with, A pulse width conversion circuit comprising the A / D converter, the digital potentiometer, the clock generation unit, the chip select generation unit, and the multivibrator component, each having an independent package.

2. The aforementioned analog input section is A first input unit configured to receive the aforementioned analog input signal, A second input unit configured to receive the aforementioned analog input signal, A selector switch is electrically connected to the first input unit and the second input unit, and selectively outputs either the analog input signal from the first input unit or the analog input signal from the second input unit to the A / D converter. A pulse width conversion circuit according to claim 1, comprising:

3. The pulse width conversion circuit according to claim 1 or 2, further comprising an amplification circuit electrically connected between the analog input section and the A / D converter, which amplifies the analog input signal from the analog input section and outputs the amplified analog input signal to the A / D converter.

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