Analog-to-digital converter (ADC) sampling system

Abstract

Image sensor, which includes the following: a pixel array including multiple pixels configured and functional to detect light from a scene, wherein the scene includes an object to be detected and a background image, wherein each pixel of the multiple pixels is configured to generate a new voltage signal in response to the intensity of light received by the pixel; a memory for storing digital values ​​corresponding to a predetermined voltage bandwidth around a prior voltage signal R of at least some of the multiple pixels corresponding to the light detected from the background image, wherein the voltage bandwidth defines a positive delta voltage +Δ and a negative delta voltage -Δ relative to the background voltage signal R; a sample-and-hold or track-and-hold module capable of sampling the new voltage signal corresponding to one of the several pixels selected; a digital-to-analog converter that generates a reference voltage R+Δ or R-Δ from the digital values ​​stored in the memory; a comparator that receives the new voltage signal sample value from the hold module and receives one of the reference voltages R+Δ or R-Δ for the selected pixel to compare it with the voltage signal sample value, wherein the comparator is configured to produce a high-voltage output signal if the voltage signal sample value is greater than the reference voltages R+Δ or R-Δ, and to produce a low- or zero-voltage output if the voltage signal sample value is less than the reference voltages R+Δ or R-Δ; a two-bit register containing a most significant bit (MSB) and a least significant bit (LSB), wherein the two-bit register provides a two-bit output signal; and a logic module that receives the voltage output from the comparator, wherein the logic module is configured and functional as follows: Selecting the reference voltage R+Δ to be supplied to the comparator, and setting the MSB to a logic "0" in response to a low-voltage output signal from the comparator or to a logic "1" in response to a high-voltage output signal from the comparator; and then Selecting the reference voltage R-Δ to be supplied to the comparator and setting the LSB to a logic "0" in response to a low-voltage output signal from the comparator or to a logic "1" in response to a high-voltage output signal from the comparator; a background subtraction module configured and functional to receive the two-bit output signal from the two-bit register for the selected pixel and, based on the two-bit output signal, to identify the selected pixel as detecting light from a scene that is different from the light detected by the same pixel in the background image; and a processing module for generating an output image that includes the selected pixel identified by the background subtraction module.

Description

AREA

[0001] This disclosure relates generally to an analog-to-digital converter (ADC) sampling system and method for a device for responding to external stimuli. BACKGROUND

[0002] Computer vision (CV) algorithms are used in a wide variety of applications, such as surveillance, smart homes, and autonomous driving, to name just a few. Many CV algorithms rely on background subtraction to identify moving objects. These algorithms first create a background model, which is then used to identify objects. Because the background model changes due to variations in lighting, the movement of background objects such as chairs, etc., it must be constantly updated.

[0003] Publication WO 2005 / 006397 A2 describes a system and method for load detection using the piezoelectric effect.

[0004] Document US 2010 / 0277607 A1 describes an image sensor with high dynamic range and integrated motion detection.

[0005] Other sensors employ similar algorithms to subtract captured background information, although the range of background model changes for non-optical sensors is generally more limited than in CV applications. Regardless of whether the sensors or detectors are configured to detect light, sound, or heat, many such detectors rely on comparing the light, sound, or heat of a new object to the ambient or background conditions, or to some other reference value. Many such sensors or detectors depend on converting an analog signal from the sensor into a digital signal, and it is this digital signal that is compared between newly captured conditions and background information. The number and density of sensors can mean that the amount of data transmitted and compared can be very large.Performing background comparisons on such large datasets can be cumbersome, slow, and in the worst case, even unacceptable. Therefore, there is a need for a system that attempts to reduce both the data rate and power consumption. SUMMARY

[0006] A brief description of certain embodiments disclosed herein is set forth below. It should be understood that these aspects are presented merely to give the reader a brief overview of these certain embodiments and that these aspects are not intended to limit the scope of protection of this disclosure. In fact, this disclosure may include a multitude of aspects that may not be set forth below.

[0007] Embodiments of the disclosure relate to an analog-to-digital converter (ADC) scanning system and a method for a device for responding to external stimuli. In one embodiment, the device is an optical sensing / detection device comprising a digital or computer processor located near a pixel array, which is configured to control the pixel array. The processor is capable of executing a set of instructions defining a processing algorithm, which are either stored on the processor or on a computer-implemented module. The set of instructions instructs the processor to detect an object, whether moving or stationary, to select one or more pixels required in the next frame, and then to control the pixel array.In another embodiment, the processor is configured to detect the object based on sound, motion, or temperature induced by the object. In yet another embodiment, the "pixel array" for the detection device comprises an array of sensors configured to detect a measurable parameter, such as sound, motion, or temperature. Further embodiments are provided in which the "array" is a single sensor configured to detect whether a measurable parameter is within a threshold of a reference value. For example, a single temperature sensor may be capable of determining whether the ambient temperature is within a predetermined temperature range of a reference temperature. The reference temperature may be a predetermined temperature or a temperature detected at an earlier time—that is, a background temperature.

[0008] In embodiments incorporating optical sensors / detectors, the processor includes a subtraction module capable of subtracting background pixels from an image, leaving a foreground image for further processing. According to another aspect of the disclosure, the subtraction module incorporates a logic-based analog-to-digital converter (ADC) that performs a pixel-by-pixel comparison to determine foreground pixels. In one aspect, the logic ADC generates only one of three binary values ​​indicating whether the image pixel is below a threshold around a background pixel intensity, above the threshold, or within the threshold. In a further adaptation, the logic ADC can be capable of generating a fourth binary value indicating that a particular pixel was not evaluated.The logic ADC can work with other sensors that provide an analog signal and require comparison with an ambient or background signal.

[0009] In one aspect, the logic ADC of this disclosure follows the architecture of a SAR (Successive Approximation Register) ADC. While the conventional SAR ADC has no prior knowledge of what information is being sought, the logic ADC of this disclosure knows that it is "searching" for a new signal that is supposed to lie within or outside a known threshold band. The logic ADC of this disclosure includes a sample-and-hold or track-and-hold component to receive the incoming analog signal from the sensor. This input voltage is fed to an input of a comparator. The other input to the comparator is a reference voltage corresponding to an upper limit of a band centered on a background or ambient signal corresponding to the same sensor or pixel.Based on the result of the comparator, a logic module within the logic ADC sets a most significant bit (MSB) to a corresponding binary value - either a binary "0" if the input voltage exceeds the reference voltage, or a binary "1" if the input voltage is lower than the reference voltage.

[0010] The logic module then increases the reference voltage to a second voltage corresponding to the lower limit of the band centered on the background signal. This new reference signal is compared to the input voltage, and based on the comparator's result, the logic module sets a least significant bit (LSB) to a corresponding binary value—either a binary "0" if the input voltage is lower than the reference voltage, or a binary "1" if the input voltage exceeds the reference voltage. The two bits—MSB and LSB—therefore provide a digital output indicating whether the new input signal lies within a predetermined threshold around a background signal and whether the new signal is merely part of the background or part of a new object.

[0011] It is understood that the same logic module architecture, as explained above, can be used for other sensors / detectors. For example, if a previous temperature sensor might require ten bits of information to determine whether a detected temperature is within a temperature range, the SAR-based architecture of the logic module of the present disclosure allows two data bits to indicate whether the temperature is within the predetermined range. Accordingly, in one embodiment, a sensor capable of detecting a measurable parameter comprises at least one sensor element configured and capable of detecting the measurable parameter and generating a new voltage signal in response to the intensity of the measurable parameter detected by the sensor element.A memory is provided for storing digital values ​​corresponding to a predetermined voltage bandwidth around a reference voltage signal R, where the reference voltage signal R corresponds to a reference value for the measurable parameter at one of the at least one sensor element selected. The voltage bandwidth defines a positive delta voltage +Δ and a negative delta voltage -Δ relative to the reference voltage signal R, corresponding to a threshold around the reference value for the measurable parameter.

[0012] The sensor further includes a sample-and-hold or track-and-hold module capable of sampling the new voltage signal corresponding to the selected one of the at least one sensor element, a digital-to-analog converter generating a reference voltage R+Δ or R-Δ from the digital values ​​stored in the memory, and a comparator receiving the new voltage signal sample value from the hold module and receiving one of the reference voltages R+Δ or R-Δ for the selected pixel in order to compare it with the voltage signal sample value, the comparator being configured to generate a high-voltage output signal if the voltage signal sample value is greater than the reference voltages R+Δ or R-Δ, and to generate a low-voltage or zero-voltage output if the voltage signal sample value is less than the reference voltages R+Δ or R-Δ.A two-bit register is provided, containing a most significant bit (MSB) and a least significant bit (LSB), with the two-bit register providing a two-bit output signal.

[0013] A logic module receives the voltage output from the comparator and is configured and functional to: a) select the reference voltage R+Δ to be supplied to the comparator and set the MSB to a logic "0" in response to a low-voltage output signal from the comparator or to a logic "1" in response to a high-voltage output signal from the comparator, and then b) select the reference voltage R-Δ to be supplied to the comparator and set the LSB to a logic "0" in response to a low-voltage output signal from the comparator or to a logic "1" in response to a high-voltage output signal from the comparator.A background subtraction module is configured and functional to receive the two-bit output signal from the two-bit register for the selected of the at least one sensor element and, based on the two-bit output signal, to identify whether the measurable parameter detected by the selected of the at least one sensor element is within or outside the threshold around the reference value for the measurable parameter. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] These and other features, aspects and advantages of this revelation will be better understood when the following detailed description of certain embodiments is read with reference to the accompanying drawings, in which the same symbols throughout the drawings represent the same techniques, wherein: Fig. Figure 1 is a simplified block diagram of an example of an imaging sensor system according to a described embodiment of the disclosure. Fig. Figure 2 is a diagram of a conventional algorithm for detecting and subtracting background images from a digitized image. Fig. Figure 3 is a diagram of a conventional approach to performing the pixel-wise comparison of the in Fig. 2 shown algorithm. Fig. Figure 4 is a diagram of a new approach according to the revelation for performing the pixel-by-pixel comparison of the digitized images, which is described in Fig. 2 is shown. Fig. 5 is a diagram of the architecture of a logical ADC for use in the in Fig. 4 approaches shown. Fig. Figure 6 is a block diagram of a pixel array representing the logical ADC. Fig. 5 incorporates, according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] The following description is presented to enable a person skilled in the field to manufacture and use the described embodiments and is provided in the context of a specific application and its requirements. Various modifications to the described embodiments will be readily apparent to a person skilled in the art, and the general principles defined here can be applied to other embodiments and applications without altering the nature and scope of protection of the described embodiments. Accordingly, the described embodiments are not limited to those shown but are intended to have the broadest scope consistent with the principles and features disclosed herein.

[0016] Various operations can be described as several discrete actions or operations performed sequentially in a manner most helpful for understanding the claimed subject matter. However, the order of description should not be interpreted in such a way that these operations are necessarily dependent on the order in which they are presented. In particular, these operations may not be performed in the order in which they are presented. Described operations may be performed in a different order than in the described embodiment. Various additional operations may be performed, and / or described operations may be omitted in additional embodiments.

[0017] Fig. Figure 1 illustrates a simplified block diagram of an example imaging sensor system 100 according to an embodiment described in this disclosure. The imaging sensor system 100 comprises a pixel array 102, a readout circuit or analog-to-digital converter (ADC) 104, and an image processing unit 106. Although an imaging sensor system 100 is illustrated with an ADC 104 configured to read light intensity, other non-imaging systems can be provided that are configured to read other forms of signals, such as temperature signals, acoustic signals, optical signals, etc. The pixel array 102 can be a large-area array with multiple tiles or superpixels, each superpixel comprising multiple pixels.As discussed above, the “pixel array” is also intended to include an array of sensors other than optical sensors, or in certain embodiments even a single sensor, such embodiments incorporating a temperature sensor. In an example related to optical imaging, the pixel array 102 can comprise 16×16 tiles or superpixels, and each tile or superpixel can comprise 8×8 pixels. The imaging sensor system 100 detects and records the intensity of light rays incident on each superpixel and / or pixel of the pixel array 102 and, in particular, assigns a value specific to each superpixel and / or pixel that indicates this intensity. In a conventional pixel array, the voltage response of the pixel increases with increasing intensity of the light received by that pixel.

[0018] The readout circuit or ADC 104, coupled to the pixel array 102, reads pixel values ​​or voltages corresponding to the intensity of light rays and then converts these voltages into digital values. In the conventional image sensor architecture, the intensity values ​​correspond to grayscale image values, where the range of light intensity is represented by 10 bits of digital data. However, it is understood that in other applications, the intensity values ​​may correspond to the intensity of a specific wavelength, such as red, green, or blue. Once the pixel values ​​are converted into digital data, the digital data is transferred to the image processing unit 106, which is coupled to the readout circuit / ADC 104. The image processing unit 106 is configured to use the digital data corresponding to the intensity of light to detect the movement of an object (or objects) across the pixel array 102.The image processing unit 106 comprises a computer-readable medium, such as an SRAM 108, and a background (BG) subtraction module 110. A set of instructions is stored or programmed in the background subtraction module 110, which is capable of instructing the image processing unit 106 to detect the movement of an object (or objects) across the pixel array 102 based on the digital data corresponding to the light intensity detected by pixels or superpixels within the array. In particular, the background subtraction module subtracts pixels from the view, wherein the digital data corresponding to the light intensity at that pixel corresponds to the digital data for a portion of the background image detected by that particular pixel.In some embodiments, a set of instructions corresponding to a background subtraction procedure implemented by the module 110 is stored or programmed directly in the image processing unit 106, wherein the instructions are functional to instruct the image processing unit 106 to detect the appearance and movement of an object (or objects) over the pixel array 102 relative to the background.

[0019] An optional learning module 115, coupled with the background subtraction module 110, can be configured to learn on the fly, specifically to learn about the background scene, a moving object, a stationary object, etc., during operation or in real time. For example, the learning module can be configured to learn that a specific moving object is a pet, such as a dog. Information corresponding to the image of the dog, as detected by the pixel array, is stored in the SRAM 108. Over time, the learned information is stored in the SRAM 108, and the image processing unit 106 updates the previously stored learned information in the SRAM 108 with newly learned information.For example, if the initially learned information is a dog, a new moving object is detected, and the learning module learns that the new moving object is a cat, the image processing unit 106 then updates the previously learned information with the newly learned information, e.g., the cat. In other embodiments, the learning module can learn from detected information over time and store the learned information in the SRAM 108 for use in the next event. This stored information provides a database of known objects against which the processing unit 106 can compare a new image to determine, for example, whether the "new" image is indeed the same pet.

[0020] The imaging sensor system 100 further comprises a digital control unit 112, which is coupled to the pixel array 102, the readout circuit / ADC 104, and / or the image processing unit 106. The digital control unit 102 can control and / or synchronize any suitable number of the units 102, 104, and 106. In one embodiment, the digital control unit 102 selects certain pixels and / or superpixels of the pixel array 102 to be read out and digitized by the readout circuit / ADC 104. In another embodiment, the digital control unit 102 can control various parameters, such as the frame rate, integration time, bit depth, etc. If no object is detected via a superpixel of the pixel array 102, the digital control unit 112 can be configured to set the superpixel of the pixel array 102 to a low-resolution mode.This results in significantly less data being read and digitized by the readout circuit / ADC 104, leading to a reduction in the power consumption of the imaging sensor system 100. However, since an object can still appear within the visual range of the special superpixel, the superpixel continues to be monitored, albeit at a lower resolution. Once an object (or objects) has been detected, the digital control unit 112 then sets the superpixel of the pixel array 102 to high-resolution mode, so that the image of the object is fully captured.

[0021] The background subtraction unit 110 of the image processing unit 106 can be configured and enabled to update background information or a background model in the SRAM 108 when changing lighting conditions or a moving object in the background (for example, a chair) is detected by the superpixel of the pixel array 102. The background model is the same size as a single image. However, the background model for each superpixel is updated independently. If a change occurs, the superpixel of the pixel array 102 detects the change, and the digital control unit 112 switches the superpixel of the pixel array 102 to a high-resolution mode.In some embodiments, the image processing module 106 detects that the background model needs to be updated, and the background model is updated and stored in the SRAM 110 while the superpixel of the pixel array 102 is in high resolution mode.

[0022] As previously described, the image processing unit 106 is capable of executing a set of program commands that control the exposure time of the imaging sensor system 100. In one embodiment, the image processing unit 106 controls the exposure time when the lighting conditions change, thus avoiding the need to relearn the background. A change in the lighting conditions can be detected when all pixels in the single image change by approximately the same percentage. In another embodiment, the image processing unit 106 can detect the change in lighting conditions using a separate light sensor device. The digital control unit 112 can then adjust the exposure time accordingly to counteract the effect of the lighting change.As the ambient light decreases or increases, the pixel's exposure time can be adjusted accordingly to effectively maintain a consistent light intensity and, therefore, pixel intensity. This adjustment of the exposure time will result in less frequent background refreshes, leading to performance savings.

[0023] The digital control unit 112 comprises a computer-readable medium, e.g., an SRAM 114 similar to the SRAM 108 of the image processing unit 106. Information regarding the superpixel configurations for low-resolution and high-resolution modes can be stored in the SRAM 114 of the digital control unit 102. The image processing unit 106, coupled to the digital control unit 112, receives a request command from the digital control unit 102 specifying which part of the pixel array's single image should be read in high-resolution or low-resolution mode. The pixel array's single image can be a series.

[0024] Algorithms, such as computer vision (CV) algorithms, are used in a wide variety of applications, including surveillance, smart homes, and autonomous driving. In many of these applications, the algorithms are designed to distinguish between a background model (consisting of, for example, trees, buildings, and roads) and a foreground object (e.g., pedestrians and cars). Fig. Figure 2 is a diagram of a common procedure for detecting foreground objects. First, a background model is generated using a computer vision algorithm. This background model represents how the image would appear if there were no foreground objects in the scene. Therefore, the background model is preferably generated before using the computer vision algorithm to detect objects in a scene. This background model includes light intensity data for each pixel within the pixel array, corresponding to the light intensity of the area of ​​the background image captured by that particular pixel. This background model is stored in memory for future processing. When a new image is captured by the image sensor, the new image data for each pixel within the array is digitized (usually 8-12 bits per pixel), and this new data is also stored in memory.The new image is then compared pixel by pixel with the background model, and the results of the comparison are passed on for further processing. In the case of a superpixel, the pixel-by-pixel comparison is still performed within the superpixel, and the number of pixels that differ from their background counterpart is determined. The result of the comparison can be a single bit, where a binary "0" represents no match between the background and the new data, and a binary "1" represents a match. In the case of a superpixel, a binary "0," representing no match between the background and the new data, is generated based on the number of distinct pixels found within the superpixel. In most cases, the comparison yields a 2-bit binary number for each pixel (or superpixel).In another embodiment, the algorithms can be used to compare a signal from a different sensor type with a reference value. The sensing element can be a temperature sensor, a motion sensor, an acoustic sensor, an imaging sensor, an optical sensor, or any suitable sensing element.

[0025] Fig. Figure 3 schematically illustrates how pixel-wise comparison is implemented in a conventional approach. First, the pixel intensity is digitized by the ADC. As mentioned above, this pixel voltage is digitized to an 8-10 bit value, and most typically to a 10-bit signal. This 10-bit intensity signal I is approximated by the next step S on a 10-bit intensity scale line G. The digital value corresponding to this step S on the scale line G is stored in memory, as shown in Figure 3. Fig. 2 shown, saved. This process is applied to the background pixel to find the background intensity gradation R. The background intensity R is used to find the gradations corresponding to the threshold ±Δ centered on the background pixel intensity. Then, each pixel value of the new image is compared to the intensity of the corresponding background pixel and, in particular, to the threshold values ​​±Δ. If the pixel value lies within a threshold ±Δ of the background intensity value R, as shown in Fig. If the pixel in the new image is similar to the corresponding pixel in the background image, it is assumed that the pixel is similar to the corresponding pixel in the background image. Conversely, if the pixel's intensity is outside the threshold ±Δ, it is assumed to belong to a foreground object rather than the background. With this conventional approach, the end result of the pixel-wise comparison is simply the identification of a region into which a new image pixel intensity value falls—that is, above the threshold, within the threshold, or below the threshold. Thus, the results of this comparison can be summarized using two bits, as in Fig. Figure 3 shows a binary "01" for a pixel intensity below the ±Δ threshold around the background pixel, a binary "10" for a pixel intensity within this threshold, and a binary "11" for a pixel intensity above the background pixel threshold. Following this pixel-by-pixel comparison, further processing takes place to ultimately determine all pixels corresponding to the foreground object(s). Each pixel of the new image will then have a corresponding 2-bit value as a result of the comparison with the background pixels, with all pixels with a binary "10" being identified as corresponding to the background, and all pixels with a binary "11" or "01" being identified as corresponding to the new object(s) passing through the field of view.This information is processed within image processing module 106 to identify the new object(s) in the current scene and generate an output in response to the object(s) identification. This further processing may include providing a display of the object(s), identifying the presence of the object(s), and / or identifying the nature of the object(s) within the field of view.

[0026] The present disclosure provides a method that reduces the performance requirements for comparing pixels between a new image and a stored background image, by performing only two comparison operations instead of the fine quantization required in the conventional method. Instead of processing a 10-bit digital signal indicating pixel intensity, the present disclosure requires only a 2-bit signal. In particular, the present method is based on the recognition that the actual intensity of the light detected by a specific pixel is irrelevant to whether the intensity of the pixel in a new image lies within a threshold of the intensity of the same pixel in a background image.

[0027] This method is achieved through modifications to the analog-to-digital converter (ADC). The modified ADC can be integrated into devices or systems such as imaging devices, optical devices, temperature devices, acoustic devices, and any other suitable devices. The ADC requires only information about the pixel, including the background intensity value R and the predetermined threshold (Δ), to perform just two comparisons, as shown in the diagram from Fig. Figure 4 illustrates this. In a particular embodiment, the ADC can be modified by incorporating aspects of a Successive Approximation Register (SAR) ADC. The SAR ADC utilizes a capacitive digital-to-analog converter (DAC), which simplifies having two comparisons for each pixel based on its background value and the threshold (Δ). An architecture of a modified ADC suitable for the present disclosure is shown in Figure 4. Fig. Figure 5 shows that the modified ADC can have a sampling rate of 5 Msps and a resolution of 8-16 bits. In another embodiment, the ADC can have a sampling rate equal to and not greater than 10 Gsps.

[0028] The “Analog-In” signal 10 in the modified ADC architecture from Fig. 5 corresponds to the voltage of the pixel for the new image, which is to be compared with the voltage of the same pixel for the background image. The pixel voltage is fed to a track-and-hold component 12, which samples the "analog-in" signal 10 on the falling edge of a sampling clock (not shown). In track-and-hold mode, module 12 continues to track the "analog-in" or pixel voltage. Alternatively, the "analog-in" signal can be supplied to a sample-and-hold module. The hold module 12 supplies an input voltage to a comparator 14. The other input to the comparator 14 is a voltage V. DAC, which is the voltage of the sampled pixel in the background image or, in particular, one of the threshold voltages R±Δ around the background pixel voltage ( Fig. 4) corresponds. Thus, the input V corresponds REF The logic element 18 of the modified ADC controls the selection of the voltage supplied to the N-bit (or in this case 2-bit) digital-to-analog converter 16 (DAC). REF -voltage and the selection of the two bits in the n-bit register 20. The N-bit register 20 in the present modified ADC is a 2-bit register in which both output bits 22 are initially set to a logic "1". If the V INIf the new pixel voltage is less than the low-range voltage R-Δ of the background pixel, the comparator output is a low or zero voltage output, which logic element 18 interprets as requiring a logical "0" for the specific bit. The logic element thus changes the most significant bit (MSB) to a logical "0". If the new pixel voltage is greater than the low-range voltage -Δ, the comparator output would be a high voltage, which logic element 18 would interpret as a logical "1", and the logic element would have left the MSB at its initial value of "1".

[0029] The logic element then proceeds to the least significant bit (LSB). The same input voltage “Analog-In” 10, which is sampled by the sample-and-hold circuit 12, is compared with the high-range voltage and, if it corresponds to the new pixel voltage V, INIf the voltage is less than the high-level voltage of the background pixel, the comparator generates a low or zero-voltage output and the logic element clears the least significant bit (LSB) to a logical "0"; otherwise, the LSB remains at a logical "1". If the pixel value is not read in a new image, V IN then be zero and will always be smaller than the reference voltage and its high and low range voltages R±Δ, in which case both bits in the register are cleared to logic “0”.

[0030] It is planned that the SAR logic 18 or the digital control 112 ( Fig. 1) sequentially samples all the pixels in the pixel array and delivers the pixel-specific voltage to the modified ADC for processing as described above. The output 22 of the modified ADC of this disclosure for each pixel of the pixel array is: "00": if the new pixel value was not read "01": if the new pixel value is below the background value range R-Δ “10”: if the new pixel value is within the threshold R±Δ of the background value “11”: if the new pixel value is above the background value range R+Δ.

[0031] This information can then be provided for subsequent processing of the image data, as discussed above. It is understood that the voltage signals from all of the pixels in the pixel array 102, or any desired subset of these pixels, pass through the modified ADC of this disclosure, such that each pixel has a corresponding two-bit output 22. As discussed above, the image processor 106, which receives this output, can be used to identify a new object (or objects) in the current scene and to generate an output in response to the identification of the object (or objects), wherein the output can be a display of the object (or objects) and / or an identification of the presence of the object (or objects) and / or an identification of the type of object (or objects) within the field of view.It is intended that pixels with a register value of "01" or "11" will be displayed in a new image, since the light detected by this pixel differs from the light detected in the background image.

[0032] It goes without saying that the modified ADC disclosed here can be used to compare a new sensor value with previous or background sensor data. The “Analog-In” signal 10 in Fig. 5 would correspond to the new or current version of the sensor and V REF would correspond to a previous or background sensor value, or more specifically, a threshold ±Δ around that background sensor value (i.e., R±Δ).

[0033] The logical ADC is integrated into an example pixel array, as shown in Fig. Figure 6 is shown. In particular, the pixel array 25 can be a QVGA-sized array of 320×240 pixels. The array can be subdivided into 20x15 superpixels, each consisting of 16x16 pixels. It is intended that the controller, such as the controller 112 ( Fig. 1) Each superpixel can operate independently in a low-resolution mode, in which only selected pixels of the superpixel are read at less than the maximum refresh rate, or in a high-resolution mode, in which all pixels are read at the maximum refresh rate. In one embodiment, the controller operates the superpixels in the high-resolution mode to "learn" the scene to be detected and imaged. After this initial step, the controller operates the superpixels in the low-resolution mode, except and until the controller detects a change in a superpixel, at which point the specific superpixel(s) is / are operated in the high-resolution mode. The pixel array can be provided with a register corresponding to each superpixel, which stores the operating mode state of the superpixels.

[0034] As in Fig. As shown in Figure 6, the pixel array comprises standard 4T pixels with a 4 µm pitch and is driven by three signals: Reset (RST), Row Select (RS), and Charge Transfer (TX). Each row is reset (regardless of the superpixel state) to prevent blooming. Correlated Double Sampling (CDS) is used in the readout circuit to cancel charge noise at the floating diffusion node and also the flicker noise of the source-follower transistor in the pixel. First, before charge transfer, the reset voltages of the floating diffusion (VFD) nodes in a row are copied into CRST capacitors (during TRST), and then, after charge transfer, the light intensity signals are copied into CSIG capacitors (during TSIG).When a superpixel is in low-resolution mode, the column readout circuit samples the reset and signal values ​​(for CRST and CSIG) only for the active pixels. This ensures that the data rate in the pixel array is reduced. Due to the small number of pixels in the array and the low refresh rate (10 fps), a single analog-to-digital converter (ADC) with a conversion time of 1.2 µs can be used to digitize all pixel values. The ADC driver can be a switched-capacitor amplifier with an auto-zeroing phase (TAZ).

[0035] The output of the ADC driver is the analog voltage supplied to the modified SAR-ADC 30, which, as in Fig. 5 is constructed. Thus, the output of the ADC driver can be converted into an analog voltage, which is fed to the comparator 14 ( Fig. 5) is supplied for comparison with the background voltage R±Δ. The SAR logic 18 ( Fig.5) selects the voltage comparison points based on the pixel read by the ADC in the pixel array 25. The modified SAR-ADC 30 of the present disclosure simplifies the comparison process because a full binary search is no longer required, as with previous devices, and instead the comparison points between pixels can vary depending on the background. It is provided that the same SAR-ADC 30 can be functional to perform the binary search in an operating mode in which the pixel values ​​are digitized to ten bits. However, in the second operating mode, which can be called a differential sampling mode, the SAR-ADC only compares the pixel value with two references, so that only two bits are necessary to determine whether the current pixel value is similar to, brighter than, or darker than the background value for that pixel (or whether the pixel was inactive).

[0036] Embodiments within the scope of protection of the disclosure may also include non-volatile computer-readable storage media or machine-readable media for carrying or receiving computer-executable instructions or data structures stored thereon. Such non-volatile computer-readable storage media or machine-readable media may be any available media accessible by a general-purpose or specialized computer. For example, and without limitation, such non-volatile computer-readable storage media or machine-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code resources in the form of computer-executable instructions or data structures.Combinations of the above should also be included within the scope of protection of non-volatile computer-readable storage media or machine-readable media.

[0037] Implementations can also be carried out in distributed computing environments where tasks are performed by local and remote processing devices linked by a communication network (either by hardwired links, wireless links or a combination thereof).

[0038] Computer-executable instructions can include, for example, commands and data that cause a general-purpose computer, a specialized computer, or a specialized processing device to perform a certain function or group of functions. Computer-executable instructions also include program modules that are executed by computers in standalone or networked environments. In general, program modules include routines, programs, objects, components, and data structures, etc., that perform specific tasks or implement specific abstract data types. Computer-executable instructions, associated data structures, and program modules represent examples of the program code means for performing steps of the procedures disclosed herein. The specific sequence of such executable instructions or associated data structures represents examples of corresponding actions for implementing the functions described in such steps.

[0039] Although the invention has been described with reference to various embodiments, it is understood that these embodiments are illustrative and that the scope of protection of the disclosure is not limited to them. Many variations, modifications, additions, and improvements are possible. More generally, embodiments according to the invention have been described in context or in specific embodiments. The functionality may be separated differently in various embodiments of the disclosure, combined in blocks, or described using different terminology. These and other variations, modifications, additions, and improvements may fall within the scope of protection of the disclosure as defined in the following claims.

Claims

[1] Image sensor comprising the following: a pixel array including multiple pixels configured and functional to detect light from a scene, wherein the scene includes an object to be detected and a background image, wherein each pixel of the multiple pixels is configured to generate a new voltage signal in response to the intensity of light received by the pixel; a memory for storing digital values ​​corresponding to a predetermined voltage bandwidth around a prior voltage signal R of at least some of the multiple pixels corresponding to the light detected from the background image, wherein the voltage bandwidth defines a positive delta voltage +Δ and a negative delta voltage -Δ relative to the background voltage signal R; a sample-and-hold or track-and-hold module capable of sampling the new voltage signal corresponding to one of the several pixels selected; a digital-to-analog converter that generates a reference voltage R+Δ or R-Δ from the digital values ​​stored in the memory; a comparator that receives the new voltage signal sample value from the hold module and receives one of the reference voltages R+Δ or R-Δ for the selected pixel to compare it with the voltage signal sample value, wherein the comparator is configured to produce a high-voltage output signal if the voltage signal sample value is greater than the reference voltages R+Δ or R-Δ, and to produce a low- or zero-voltage output if the voltage signal sample value is less than the reference voltages R+Δ or R-Δ; a two-bit register containing a most significant bit (MSB) and a least significant bit (LSB), wherein the two-bit register provides a two-bit output signal; and a logic module that receives the voltage output from the comparator, wherein the logic module is configured and functional as follows: Selecting the reference voltage R+Δ to be supplied to the comparator, and setting the MSB to a logic "0" in response to a low-voltage output signal from the comparator or to a logic "1" in response to a high-voltage output signal from the comparator; and then Selecting the reference voltage R-Δ to be supplied to the comparator and setting the LSB to a logic "0" in response to a low-voltage output signal from the comparator or to a logic "1" in response to a high-voltage output signal from the comparator; a background subtraction module configured and functional to receive the two-bit output signal from the two-bit register for the selected pixel and, based on the two-bit output signal, to identify the selected pixel as detecting light from a scene that is different from the light detected by the same pixel in the background image; and a processing module for generating an output image that includes the selected pixel identified by the background subtraction module. [2] Image sensor according to claim 1, further comprising a controller capable of selecting pixels in the pixel array to supply the new voltage signal to the holding module. [3] Image sensor according to one of the preceding claims, wherein the background subtraction module identifies the selected pixel only if the value of the two-bit register is a binary “01” or a binary “11”. [4] Method for determining the display of an image of a scene including a detectable object and a background image, comprising the following steps: Scanning the scene with a pixel array including multiple pixels configured and functional to detect light from the scene, each pixel of the multiple pixels being configured to generate a new voltage signal in response to the intensity of light received by the pixel; a memory for storing digital values ​​corresponding to a predetermined voltage bandwidth around a prior voltage signal R of selected one of the multiple pixels corresponding to the light detected from the background image, wherein the voltage bandwidth defines a positive delta voltage +Δ and a negative delta voltage -Δ relative to the background voltage signal R; for each of the selected pixels: Sampling the new voltage signal that corresponds to the selected pixel; Generating a reference voltage R+Δ or R-Δ from the digital values ​​stored in the memory for the selected pixel; Comparing the new voltage signal sample value with one of the reference voltages R+Δ or R-Δ for the selected pixel and generating a high-voltage output signal if the voltage signal sample value is greater than the reference voltages R+Δ or R-Δ, and generating a low- or zero-voltage output if the voltage signal sample value is less than the reference voltages R+Δ or R-Δ; Selecting the reference voltage R+Δ to be supplied to the comparator, and setting a most significant bit (MSB) of a two-bit register to a logical "0" in response to a low-voltage output signal from the comparator, or to a logical "1" in response to a high-voltage output signal from the comparator; and then Selecting the reference voltage R-Δ to be supplied to the comparator and setting the least significant bit (LSB) of the two-bit register to a logical "0" in response to a low-voltage output signal from the comparator or to a logical "1" in response to a high-voltage output signal from the comparator; Identifying the selected pixel as detecting light from a scene that differs from the light captured by the same pixel in the background image, based on the value of the two-bit register; and a processing module for generating an output image that includes the selected pixel only if it was identified in the previous step. [5] Method according to claim 4, wherein the identification step identifies the selected pixel only if the value of the two-bit register is a binary “01” or a binary “11”. [6] Sensor capable of detecting a measurable parameter and comprising the following: at least one sensor element configured and functional to detect the measurable parameter and to generate a new voltage signal in response to the intensity of the measurable parameter detected by the sensor element; a memory for storing digital values ​​corresponding to a predetermined voltage bandwidth around a reference voltage signal R, wherein the reference voltage signal R corresponds to a reference value for the measurable parameter at a selected one of the at least one sensor element, wherein the voltage bandwidth defines a positive delta voltage +Δ and a negative delta voltage -Δ relative to the reference voltage signal R, corresponding to a threshold around the reference value for the measurable parameter; a sample-and-hold or track-and-hold module capable of sampling the new voltage signal corresponding to the selected signal of the at least one sensor element; a digital-to-analog converter that generates a reference voltage R+Δ or R-Δ from the digital values ​​stored in the memory; a comparator that receives the new voltage signal sample value from the hold module and receives one of the reference voltages R+Δ or R-Δ for the selected pixel to compare it with the voltage signal sample value, wherein the comparator is configured to produce a high-voltage output signal if the voltage signal sample value is greater than the reference voltages R+Δ or R-Δ, and to produce a low- or zero-voltage output if the voltage signal sample value is less than the reference voltages R+Δ or R-Δ; a two-bit register containing a most significant bit (MSB) and a least significant bit (LSB), wherein the two-bit register provides a two-bit output signal; and a logic module that receives the voltage output from the comparator, wherein the logic module is configured and functional as follows: Selecting the reference voltage R+Δ to be supplied to the comparator, and setting the MSB to a logic "0" in response to a low-voltage output signal from the comparator or to a logic "1" in response to a high-voltage output signal from the comparator; and then Selecting the reference voltage R-Δ to be supplied to the comparator, and setting the LSB to a logic "0" in response to a low-voltage output signal from the comparator or to a logic "1" in response to a high-voltage output signal from the comparator; and a background subtraction module configured and functional to receive the two-bit output signal from the two-bit register for the selected of the at least one sensor element and, based on the two-bit output signal, to identify whether the measurable parameter detected by the selected of the at least one sensor element is within or outside the threshold around the reference value for the measurable parameter. [7] Sensor according to claim 6, wherein the measurable parameter is a temperature, the at least one sensor element is a temperature sensor, the reference value is a temperature at an earlier time and the threshold is a temperature range around the predetermined temperature. [8] Sensor according to claim 7, wherein the background subtraction module is configured to identify the selected one of the at least one sensor element only when it detects a temperature that differs from the temperature at an earlier time, based on the value of the two-bit register; and a processing module for generating an output that includes the selected sensor element only if it is identified by the background subtraction module.

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