Solid-state imaging device

Abstract

Reduces variations in output levels. [Solution] The solid-state imaging device 100 comprises a photodetector P, a transfer transistor TRG, a first transistor RST, and a voltage holding circuit 102. The first end of the transfer transistor TRG is connected to the output terminal of the photodetector P, and it transfers the signal output by the photodetector P to its second end at the timing when an ON signal is applied to the drive terminal. The first transistor RST has its first end connected to the power line VDDR, and its second end connected to the first end or the second end of the transfer transistor TRG. The voltage holding circuit 102 is connected between the drive terminal and the second end of the first transistor RST.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device.

Background Art

[0002] In many cases, it is desired to widen the dynamic range of a solid-state imaging device. As a means of realizing a wide dynamic range with single-shot light, there is a technique called the charge storage capacity modulation method. This technique is realized by controlling the overflow level of a reset transistor (or an overflow gate transistor) connected to a photodiode. Specifically, the accumulation time is divided into a plurality of regions, the overflow level is changed for each region to change the charge storage capacity in each region, and the charge exceeding the charge storage capacity is discharged to compress the amount of accumulated charge of a high-luminance signal so that it does not saturate up to a higher limit.

[0003] However, since the control of the overflow level is executed by controlling the gate voltage of the reset transistor, the overflow level after control is affected by the gate-source voltage of the reset transistor. Since the gate-source voltage of the reset transistor has variations (individual differences) for each pixel, the overflow level is different for each pixel even when the same reset gate voltage is input. As a result, the output levels for each pixel are different for the same high-luminance signal, and there is a high probability of increasing fixed pattern noise.

Prior Art Documents

Non-Patent Documents

[0004]

Non-Patent Document 1

[0005] Therefore, one of the non-limiting problems that embodiments of this disclosure aim to solve is reducing variability in output levels. Further examples of problems that embodiments of this disclosure aim to solve may include problems corresponding to the effects described in the embodiments. That is, any problem corresponding to at least one of the effects described in the description of embodiments of this disclosure may be a problem that the disclosure aims to solve. [Means for solving the problem]

[0006] According to one embodiment, the solid-state imaging device comprises a photodetector, a transfer transistor, a first transistor, and a voltage holding circuit. The transfer transistor has its first terminal connected to the output terminal of the photodetector, and transfers the signal output by the photodetector to its second terminal at the timing when an ON signal is applied to the drive terminal. The first transistor has its first end connected to a power line and its second end connected to the first end or the second end of the transfer transistor. The voltage holding circuit is connected between the drive terminal of the first transistor and the second terminal of the first transistor.

[0007] The voltage holding circuit may include a capacitor connected between the drive terminal of the first transistor and the second terminal of the first transistor.

[0008] The voltage holding circuit may also include a second transistor, the first terminal of which is connected to a signal line and the second terminal of which is connected to one terminal of the capacitor and the drive terminal of the first transistor; a third transistor, the first terminal of which is connected to the other terminal of the capacitor and the second terminal of which is connected to the second terminal of the first transistor; and a fourth transistor, the first terminal of which is connected to the first terminal of the second transistor and the second terminal of which is connected to the first terminal of the third transistor, and the other terminal of the capacitor may be connected to the second terminal of the first transistor via the third transistor.

[0009] At the initialization timing, the second and third transistors may be controlled so that they do not turn on at the same time as the fourth transistor.

[0010] The first transistor may be a reset transistor, the second terminal of which is connected to a floating diffusion region, and which initializes the floating diffusion region.

[0011] The first transistor may be a transistor that forms an overflow gate, with its second terminal connected to the output terminal of the photodetector.

[0012] The solid-state imaging device may be formed from stacked semiconductor layers, and the photodetector, the transfer transistor, the first transistor, and the voltage holding circuit may be formed on the same semiconductor layer.

[0013] The solid-state imaging device may be formed from stacked semiconductor layers, and the photodetector and the transfer transistor, and the first transistor and the voltage holding circuit may be formed on separate semiconductor layers. [Brief explanation of the drawing]

[0014] [Figure 1] A schematic block diagram showing an example of a solid-state imaging device according to one embodiment. [Figure 2] A circuit diagram showing an example of a pixel according to one embodiment. [Figure 3]Circuit diagram showing an example of a pixel according to an embodiment. [Figure 4] Timing chart showing an example of the transition of a pixel circuit according to an embodiment. [Figure 5] Schematic diagram showing the timing of correction according to an embodiment. [Figure 6] Schematic diagram showing the timing of correction according to an embodiment. [Figure 7] Circuit diagram showing an example of a pixel according to an embodiment. [Figure 8] Circuit diagram showing an example of a pixel according to an embodiment. [Figure 9] Circuit diagram showing an example of a pixel according to an embodiment. [Figure 10] Timing chart showing an example of the transition of a pixel circuit according to an embodiment. [Figure 11] Circuit diagram showing an example of a pixel according to an embodiment. [Figure 12] Diagram showing an example of a stacked semiconductor layer according to an embodiment. [Figure 13] Diagram showing an example of a stacked semiconductor layer according to an embodiment. [Figure 14] Block diagram showing an example of a schematic configuration of a vehicle control system. [Figure 15] Explanatory diagram showing an example of the installation positions of an external information detection unit and an imaging unit.

Mode for Carrying Out the Invention

[0015] Hereinafter, embodiments in the present disclosure will be described with reference to the drawings. The drawings are used for explanation, and it is not necessary that the shapes, sizes of each part in the actual device, or the size ratios with other configurations are as shown in the drawings. Also, since the drawings are simplified, it is assumed that appropriate configurations necessary for implementation are provided in addition to those shown in the drawings.

[0016] In the present disclosure, each configuration will be described in the following order. 1. Configuration of a solid-state imaging device 2. Configuration of a pixel 3. Examples of stacked implementations 4. Application Examples

[0017] <1. Configuration of the Solid State Imaging System>

[0018] Figure 1 is a schematic block diagram showing an example of a solid-state imaging device according to one embodiment. It should be noted that the features of this disclosure lie in the pixel structure, and therefore, the invention is not limited to this figure and can be applied to general pixels.

[0019] The solid-state imaging device 1 includes, for example, a pixel array 10, a control circuit 12, a first scanning circuit 14, and second scanning circuits 16 and 18. The solid-state imaging device 1 is a device capable of outputting data with a wide dynamic range for the captured data.

[0020] The pixel array 10 is arranged in a two-dimensional array along a first direction (e.g., line direction) and a second direction intersecting the first direction (e.g., column direction). Each pixel is equipped with a photodetector having a photoelectric conversion unit, and outputs a signal corresponding to the intensity of the light received by this photodetector. The signal output from the photodetector is converted into an appropriate analog signal by a pixel circuit provided in the pixel and output to the signal processing circuit 18 via the signal line 180.

[0021] The control circuit 12 is a circuit that controls imaging in the pixel array 10. The control circuit 12 may also control other processes in the solid-state imaging device 1. For example, the control circuit 12 transmits control signals to the first scanning circuit 14 and the second scanning circuit 16 for controlling imaging in the pixel array 10. The control circuit 12 may also transmit control signals to the signal processing circuit 18 for processing the signals output from the pixel array 10. If necessary, the signal processing circuit 18 may also receive information from at least one of the first scanning circuit 14, the second scanning circuit 16, and the signal processing circuit 18 for generating signals to be used for control.

[0022] The first scanning circuit 14 selects pixels belonging to the same line along a first direction in the pixel array 10 and outputs a signal to switch the drive state for each line. The first scanning circuit 14 outputs a line selection signal to each pixel in the pixel array 10 via the signal line 140. Based on the signal output from the first scanning circuit 14, the pixels belonging to the selected line switch between a driveable state and a non-driveable state.

[0023] The second scanning circuit 16 outputs a signal to pixels belonging to the same column along the second direction in the pixel array 10, so that the output from pixels belonging to the line selected by the first scanning circuit 14 is properly executed. The second scanning circuit 16 outputs a signal to pixels belonging to a column in the pixel array 10 via the signal line 160. That is, each pixel is made drivable on the line selected by the first scanning circuit 14, and the pixels on this line are driven based on the signal from the second scanning circuit 16 and output a signal.

[0024] The signal processing circuit 18 is a circuit that appropriately processes the signals output from pixels arranged in the pixel array 10 and converts them into signals suitable for, for example, image signals, video signals, etc., and outputs them. The signal processing circuit 18 may, for example, include an Analog to Digital Converter (ADC) in part to convert analog signals output from pixels into digital signals. The signal processing circuit 18 receives signals from pixels arranged in the pixel array 10 via signal lines 180.

[0025] In this disclosure, the solid-state imaging device 1 formed by these configurations may acquire information using either a rolling shutter or a global shutter imaging mode. That is, the solid-state imaging device 1 may include any pixel circuit, as long as it is not inconsistent with the features of this disclosure.

[0026] <2. Pixel Configuration>

[0027] The basic pixel configuration in this disclosure is described below. Each pixel in the pixel array 10 is equipped with a photodetector and outputs an analog signal based on the intensity of light photoelectrically converted by the photodetector. In this disclosure, one embodiment widens the dynamic range by controlling the lower limit voltage in the output terminal of the photodetector or in the floating diffusion region where the charge temporarily output from the photodetector is accumulated in the pixel circuit.

[0028] (First Embodiment)

[0029] Figure 2 is a circuit diagram showing an example of a pixel according to one embodiment. Pixel 100 includes a pixel circuit that stores a signal corresponding to the intensity of light received by photoelectric conversion in the photodetector P at an appropriate timing, and outputs it at an appropriate timing.

[0030] The semiconductor type and terminal connection direction shown below are examples for each transistor, but are not limited to these. For example, even when indicated as n-type, it is possible to replace it with p-type by appropriately changing the on / off signal applied to the gate. Also, although we have used the terms drain and source for convenience, the connection direction is arbitrary as long as the current flows properly.

[0031] A transfer gate TRG is a transistor whose first end is connected to the output terminal of a photodetector P, and whose second end is connected to a floating diffusion region FD. A transfer gate TRG is, for example, an n-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). When an ON voltage is applied to the gate, the transfer gate TRG transfers the charge (signal) accumulated at the output terminal of the photodetector P to the floating diffusion region FD.

[0032] The floating diffusion region FD is a layer that converts the charge transferred from the output terminal of the photodetector P via the transfer gate TRG into a voltage. The floating diffusion region FD applies the converted voltage to the gate of the amplification transistor AMP. Although not shown in the diagram, a capacitor may be provided between the floating diffusion region FD and ground potential to stabilize the potential of the floating diffusion region FD.

[0033] The amplification transistor AMP is a transistor that flows a drain current in accordance with the magnitude of the voltage applied by the floating diffusion region FD. The amplification transistor AMP may be, for example, an n-type MOSFET. The gate of the amplification transistor AMP is connected to the floating diffusion region FD, the first end is connected to the power line VDDH, and the second end is connected to the selection transistor SEL.

[0034] The selection transistor SEL is a transistor that outputs a current corresponding to the drain current output from the amplification transistor AMP to the signal line 180 based on a drive signal from the first scanning circuit 14 input via the signal line 140. The selection transistor SEL may be, for example, an n-type MOSFET. The gate of the selection transistor SEL is connected to the signal line 140, the first end is connected to the second end of the amplification transistor AMP, and the second end is connected to the signal line 180.

[0035] The reset transistor RST is a transistor used to initialize the charge accumulated in the floating diffusion region FD. The reset transistor RST may be, for example, an n-type MOSFET. The first end of the reset transistor RST is connected to the power line VDDR, and the second end is connected to the floating diffusion region FD.

[0036] The voltage holding circuit 102 is a circuit connected between the gate and the second terminal of the reset transistor RST. As an example, the voltage holding circuit 102 is a circuit that holds the potential difference between the gate and source of the reset transistor RST. By holding the potential difference between the gate and source of the reset transistor RST at a predetermined timing, the lower limit voltage, which is proportional to the storage capacitance of the stray diffusion region FD, can be made independent of the gate-source voltage of the reset transistor RST. This voltage holding circuit 102 will be described in detail.

[0037] Figure 3 is a circuit diagram showing the voltage holding circuit 102 in more detail. The voltage holding circuit 102 includes, for example, a capacitor C for maintaining the gate-source potential difference between the gate (drive terminal) and source (second terminal) of the reset transistor RST, and transistors M2, M3, and M4 that store energy in the capacitor C at appropriate timings to control the gate-source potential difference of the reset transistor RST.

[0038] Capacitor C is provided between the gate and source of the reset transistor RST. One end of capacitor C is connected to the second end of transistor M2 and the gate of reset transistor RST. The other end of capacitor C is connected to the first end of transistor M3, and through transistor M3, it is connected to the source of reset transistor RST.

[0039] Transistor M2 has its first end connected to a signal line that applies a voltage Vrst that defines the gate voltage of reset transistor RST, and its second end connected to one end of capacitor C and the gate of reset transistor RST.

[0040] Transistor M3 has its first terminal connected to the other terminal of capacitor C, and its second terminal connected to the source of reset transistor RST.

[0041] When transistors M2 and M3 are turned on, a capacitor C is connected between the gate and source of the reset transistor RST, and the potential difference between this gate and source can be controlled by the amount of charge stored in capacitor C.

[0042] Transistor M4 has its first terminal connected to the first terminal of transistor M2, and its second terminal connected to the first terminal of transistor M3. When transistors M2 and M3 are off and transistor M4 is turned on, the reference potential of the voltage due to the charge held by capacitor C can be controlled according to the voltage Vrst.

[0043] In summary, the voltage holding circuit 102 comprises transistor M2, transistor M3, transistor M4, and capacitor C. Transistor M2 is connected between the signal line and one end of capacitor C. Transistor M3 is connected between capacitor C and the second end of reset transistor RST. Transistor M4 is connected between the first end of transistor M2 and the first end of transistor M3. Transistors M2, M3, and M4 may be controlled so that they are not turned on at the same time during the initialization period of the floating diffusion region FD and the exposure period of the photodetector P.

[0044] Figure 4 is a timing chart showing the transition between the voltage applied to the gate of each transistor according to one embodiment and the potential that represents the lower limit of the floating diffusion region FD. From top to bottom, the chart shows, in order, the voltage Vrst input to the voltage holding circuit 102, the voltage Vddr applied to the first end of the reset transistor RST, the voltages Vr1 and Vr2 input to the voltage holding circuit 102, and the lower limit voltage of the floating diffusion region FD due to the above voltage transitions.

[0045] As an example, the initial state of the lower limit voltage of the floating diffusion region FD shows a high impedance potential, but during continuous exposure such as during imaging, it may be the potential at the frame switching timing. Furthermore, these voltage transitions may be executed by the first scanning circuit 14 or the second scanning circuit 16 under control from the control circuit 12.

[0046] At the timing before exposure of pixel 100 begins, the pixel circuit related to pixel 100, in particular, the floating diffusion region FD, is initialized. During initialization, voltage Vr1 is set to an ON potential and voltage Vr2 to an OFF potential, and transistors M2 and M3 are controlled to be ON and transistor M4 to be OFF.

[0047] From this state, the voltage applied to the first terminal of the reset transistor RST is transitioned from voltage Vddr to ground potential GND. This transition resets the lower limit voltage of the floating diffusion region FD from the high impedance potential HiZ to ground potential GNP.

[0048] After sufficient time has elapsed for the lower limit voltage of the floating diffusion region FD to be controlled to ground potential, the voltage applied to the first terminal of the reset transistor RST transitions to voltage Vddr. Consequently, the lower limit voltage of the floating diffusion region FD becomes the voltage at the second terminal of the reset transistor RST. This voltage at the second terminal is the gate voltage of the reset transistor RST minus the gate-source voltage of the reset transistor RST. The gate voltage of the reset transistor RST is voltage Vrst1 because transistor M2 is ON. That is, in this state, the lower limit voltage of the floating diffusion region FD is Vrst1 - Vgs, where Vgs is the gate-source voltage of the reset transistor RST.

[0049] At this point, both transistors M2 and M3 are turned on, and transistor M4 is turned off, so the value Vrst1 - (Vrst1 - Vgs) = Vgs is stored in capacitor C.

[0050] When transistors M2 and M3 are turned off while transistor M4 is off, this Vgs value is retained in capacitor C.

[0051] In this state, when transistor M4 is turned on, Vrst1 + Vgs is applied to the gate of reset transistor RST. As a result, the potential of the source of reset transistor RST becomes (Vrst1 + Vgs) - Vgs = Vrst1, and the lower limit voltage of the floating diffusion region FD becomes Vrst1. In other words, the lower limit voltage of the floating diffusion region FD can be controlled without being affected by the Vgs inherent to reset transistor RST.

[0052] At a later timing, by setting the voltage applied to the first terminal of transistor M4 to Vrst2, which is smaller than Vrst1, it becomes possible to fix the lower limit voltage of the floating diffusion region FD to Vrst2, which is unaffected by the gate-source voltage of the reset transistor RST. By starting the exposure after this timing, it is possible to suppress the influence of the transistors constituting the reset transistor RST on the voltage accumulated in the floating diffusion region FD.

[0053] For example, when a high-brightness subject or high-brightness imaging area exists, increasing the voltage applied to the gate of the reset transistor RST can improve the compression ratio of the signal value in the high-brightness area. However, it is possible to transition the voltage applied to the gate of the reset transistor RST at each pixel 100 so that the signal value in this high-brightness area does not include individual differences in the reset transistor RST. As a result, it is possible to acquire high dynamic range image data across the pixel array 10 that is not affected by individual differences in the reset transistor RST, particularly the Vgs of the reset transistor RST. As a result, it is possible to reduce the variation in the output level of the data output as an image signal.

[0054] By suppressing the effect of Vgs on the reset transistor RST, it is possible to reduce pixel-specific fixed pattern noise, even when expanding the dynamic range in high-brightness image regions.

[0055] Figure 5 is a schematic diagram showing the timing of the correction of the lower limit voltage of the floating diffusion region FD according to one embodiment. The above correction may be performed at the same timing as the initialization of the floating diffusion region FD (including other initialization timings of the pixels).

[0056] As shown in the figure, after correction, exposure and charge accumulation in the floating diffusion region FD occur. Subsequently, the first scanning circuit 14 and the second scanning circuit 16 perform processing to read out signals corresponding to the intensity of the received light for each of the 100 pixels.

[0057] The above correction can be performed in a few microseconds to tens of microseconds, which is a very short time compared to exposure and readout. Therefore, it can be performed as an in-frame process, every frame, and even in this case, the impact on the frame rate is small.

[0058] Figure 6 is a schematic diagram illustrating the timing of correction in another example. For example, when the frame time is very short, the correction may be performed every n frames (where n is any integer greater than or equal to 2). The voltage held in capacitor C does not need to be reset every frame; the correction can be performed every n frames.

[0059] In this configuration, it is preferable to define n appropriately so that correction can be made before the effect of discharge from capacitor C becomes significant.

[0060] The embodiments described in this disclosure are described as having one floating diffusion region FD for each pixel 100, but are not limited thereto. The floating diffusion region FD may be provided as one for multiple pixels 100. Thus, the embodiments of this disclosure can also be applied when multiple pixels 100 share a floating diffusion region FD. In this case, both the area in which the floating diffusion region FD is formed and the area in which the voltage holding circuit 102 is formed can be reduced.

[0061] Several embodiments that modify the first embodiment described above are described below.

[0062] (Second Embodiment)

[0063] In the first embodiment described above, the configuration included one transfer gate, but it is not limited to this. Even when there are multiple transfer gates, a voltage holding circuit that performs correction processing can be provided in the same way.

[0064] Figure 7 is a circuit diagram showing an example of a pixel 100 according to one embodiment. As shown in this figure, the pixel 100 may include a transfer gate TRG and a transfer gate TRX as transfer gates that time the transfer of the signal output from the photodetector P. A memory area MEM is formed between the transfer gate TRG and the transfer gate TRX.

[0065] The memory region MEM receives the charge output from the photodetector P via the transfer gate TRG at the appropriate timing. The presence of the memory region MEM makes it possible to overlap the light-receiving period of the photodetector P with the charge transfer period of the transfer gate TRX, enabling global shutter operation. The voltage holding circuit 102 in this disclosure can also be applied to cases where such a memory region MEM is present, i.e., when there are multiple transfer gates, and enables the generation of high dynamic range images with minimal influence of fixed pattern noise in global shutter operation.

[0066] (Third embodiment)

[0067] In the embodiments described above, a mode for controlling the lower limit voltage of the floating diffusion region FD was explained. However, the mode in this disclosure for suppressing the influence of the Vgs of the transistor used for initialization by holding the voltage can also be applied to an overflow gate OFG that controls the overflow of the region connected to the cathode of the photodetector P.

[0068] Figure 8 is a circuit diagram showing an example of a pixel 100 according to one embodiment. The pixel 100 includes an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, a transfer gate TRG, an overflow gate OFG connected to the cathode region PD_C which is the output node of the photodetector P, and a voltage holding circuit 102. The voltage holding circuit 102 may be placed between the gate (drive end) and the source (second end) of the overflow gate OFG.

[0069] The overflow gate OFG is a transistor that, when the output from the photodetector PD becomes saturated, appropriately flows a charge exceeding the saturation charge to the overflow drain. This overflow gate OFG can be used to reset the cathode potential of the photodetector PD. At the timing of this reset, by controlling the voltage holding circuit 102, it is possible to acquire an image signal while suppressing the influence of Vgs of the transistor forming the overflow gate OFG, as described above.

[0070] Figure 9 is a circuit diagram showing an example of a pixel 100 according to one embodiment. The voltage holding circuit 102 can have the same configuration as in each of the embodiments described above, and comprises a transistor M2, a transistor M3, a transistor M4, and a capacitor C. By holding the Vgs of the overflow gate OFG in the capacitor C with this voltage holding circuit 102, a signal with the influence of the Vgs of the overflow gate OFG suppressed can be accumulated in the cathode region PD_C even when the overflow gate OFG is turned on / off.

[0071] Figure 10 is a timing chart showing the transition between the voltage applied to the gate of each transistor according to one embodiment and the potential that represents the lower limit of the floating diffusion region FD. The voltage related to the reset transistor RST in the explanation of Figure 4 is changed to the voltage related to the overflow gate OFG, and it is controlled with the same timing as in the first embodiment described above.

[0072] Vofg is the voltage applied to the first terminal of transistor M2 and the first terminal of transistor M4. Vddo is the voltage applied to the power line VDDO. Vo1 is the voltage applied to the gate of transistor M2 and the gate of transistor M3. Vo2 is the voltage applied to the gate of transistor M4.

[0073] The detailed control timing of the voltage holding circuit 102 itself is the same as that of the first embodiment described above, so a detailed explanation will be omitted.

[0074] Thus, it is possible to provide a voltage holding circuit 102 between the gate and source of the overflow gate OFG. In this case, when charge accumulates in the cathode region PD_C, the voltage applied to the gate of the overflow gate OFG is increased when the brightness is high, thereby enabling compression of the dynamic range in the high-brightness region. At the same time, it becomes possible to acquire an image signal that is less affected by individual differences in the overflow gate OFG, particularly the unique Vgs of each overflow gate OFG.

[0075] (Fourth Embodiment)

[0076] Figure 11 is a circuit diagram showing an example of a pixel 100 according to one embodiment. As shown in this figure, even when the voltage holding circuit 102 is placed relative to the overflow gate OFG shown in the third embodiment, it is also possible to have a configuration with two transfer gates, transfer gate TRG and transfer gate TRX.

[0077] <3. Examples of stacked mounting>

[0078] Figure 12 shows an example of the formation of a semiconductor layer including pixels 100 in a solid-state imaging device 1 according to one embodiment. The semiconductor layer 2 may comprise a first layer 20, a second layer 22, and a third layer 24. The semiconductor layer 2 is formed by stacking the first layer 20, the second layer 22, and the third layer 24. Each layer is joined by an appropriate bonding method. Furthermore, each layer has an electrical connection path made of a metal such as Cu, Au, or Ag, and electrical signals can be exchanged between each layer via this connection path.

[0079] The first layer 20 is primarily provided with a diffusion layer for forming a photodetector P and a floating diffusion region FD (including a memory region MEM). These diffusion regions in the first layer 20 are appropriately connected by predetermined transistors. Wiring for inputting and outputting these signals is arranged in the wiring layer of the first layer 20.

[0080] In addition, the first layer 20 has a transfer gate TRG, a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, a transfer gate TRX, and the like formed therein.

[0081] The second layer 22 forms the elements that constitute the voltage holding circuit 102. The capacitor C may be, for example, a MIM (Metal-Insulator-Metal) capacitor, in which case the capacitor C may be formed in the wiring layer of the second layer 22. Since the capacitor C may hold a relatively large voltage and therefore needs to have a large capacitance, it is desirable to form it in the wiring layer of this second layer 22.

[0082] In addition, transistors M2, M3, M4, etc. are formed in the second layer 22.

[0083] Figure 12 shows the layer configuration in the third or fourth embodiment. In the layer configuration of the first or second embodiment, the layers on which the reset transistor RST and the overflow gate OFG are formed can be reversed. That is, the reset transistor RST is formed on the second layer 22, and the overflow gate OFG is formed on the first layer 20. In other words, the second layer 22 has a transistor related to the voltage Vgs held by the voltage holding circuit 102 (the reset transistor RST in the first or second embodiment, or the overflow gate OFG in the third or fourth embodiment).

[0084] Figure 13 shows an example of the formation of a semiconductor layer including pixels 100 in a solid-state imaging device 1 according to one embodiment. As shown in this figure, the semiconductor layer 2 may be formed by stacking two semiconductor layers, a first layer 20 and a second layer 22.

[0085] In this case, as shown in the figure, the pixels 100 (including the voltage holding circuit 102) in each of the embodiments described above may be formed on the first layer 20, and other logic circuits may be formed on the second layer 22. In embodiments where sufficient capacitance and area for forming the voltage holding circuit 102 can be secured in the first layer 20, such a two-layer structure is also possible.

[0086] However, the invention is not limited to these configurations. For example, elements of the pixel 100 other than the voltage holding circuit 102 and the transistor related to the voltage Vgs held by the voltage holding circuit 102 may be formed on the first layer 20, while the voltage holding circuit 102, the transistor related to the voltage Vgs held by the voltage holding circuit 102, and other logic circuits may be formed on the second layer 22.

[0087] <4. Application Examples>

[0088] The technology disclosed herein can be applied to a variety of products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile vehicle, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, robots, construction machinery, or agricultural machinery (tractors).

[0089] Figure 14 is a block diagram showing a schematic configuration example of a vehicle control system 7000, which is an example of a mobile control system to which the technology described herein may be applied. The vehicle control system 7000 comprises a plurality of electronic control units connected via a communication network 7010. In the example shown in Figure 14, the vehicle control system 7000 comprises a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, an external information detection unit 7400, an internal information detection unit 7500, and an integrated control unit 7600. The communication network 7010 connecting these plurality of control units may be an in-vehicle communication network compliant with any standard such as CAN (Controller Area Network), LIN (Local Interconnect Network), LAN (Local Area Network), or FlexRay (registered trademark).

[0090] Each control unit comprises a microcomputer that performs calculations according to various programs, a storage unit that stores programs executed by the microcomputer or parameters used in various calculations, and a drive circuit that drives various controlled devices. Each control unit is equipped with a network interface for communication with other control units via the communication network 7010, and a communication interface for communication with devices or sensors inside or outside the vehicle via wired or wireless communication. Figure 14 illustrates the functional configuration of the integrated control unit 7600, which includes a microcomputer 7610, a general-purpose communication interface 7620, a dedicated communication interface 7630, a positioning unit 7640, a beacon receiver 7650, an in-vehicle equipment interface 7660, an audio / image output unit 7670, an in-vehicle network interface 7680, and a storage unit 7690. Other control units similarly include a microcomputer, a communication interface, and a storage unit.

[0091] The drivetrain control unit 7100 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 7100 functions as a control device for generating driving force for the vehicle, such as an internal combustion engine or drive motor; a driving force transmission mechanism for transmitting driving force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating braking force for the vehicle. The drivetrain control unit 7100 may also function as a control device such as ABS (Antilock Brake System) or ESC (Electronic Stability Control).

[0092] A vehicle state detection unit 7110 is connected to the drivetrain control unit 7100. The vehicle state detection unit 7110 includes, for example, a gyro sensor for detecting the angular velocity of the vehicle's axial rotational motion, an acceleration sensor for detecting the vehicle's acceleration, or at least one of the sensors for detecting the amount of accelerator pedal operation, brake pedal operation, steering wheel steering angle, engine speed, or wheel rotation speed. The drivetrain control unit 7100 performs calculations using signals input from the vehicle state detection unit 7110 to control the internal combustion engine, drive motor, electric power steering system, brake system, etc.

[0093] The body system control unit 7200 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 7200 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 7200 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 7200 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0094] The battery control unit 7300 controls the secondary battery 7310, which is the power source for the drive motor, according to various programs. For example, the battery control unit 7300 receives information such as battery temperature, battery output voltage, or remaining battery capacity from the battery device equipped with the secondary battery 7310. The battery control unit 7300 uses these signals to perform calculations and controls the temperature of the secondary battery 7310 or the cooling device provided in the battery device.

[0095] The external information detection unit 7400 detects information from outside the vehicle equipped with the vehicle control system 7000. For example, the external information detection unit 7400 is connected to at least one of the imaging unit 7410 and the external information detection unit 7420. The imaging unit 7410 includes at least one of the following: a Time of Flight (ToF) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras. The external information detection unit 7420 includes at least one of the following: an environmental sensor for detecting the current weather or climate, or an ambient information detection sensor for detecting other vehicles, obstacles, or pedestrians around the vehicle equipped with the vehicle control system 7000.

[0096] The environmental sensor may be at least one of the following: a raindrop sensor for detecting rain, a fog sensor for detecting fog, a sunshine sensor for detecting the degree of sunlight, and a snow sensor for detecting snowfall. The ambient information detection sensor may be at least one of the following: an ultrasonic sensor, a radar device, and a LIDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging) device. These imaging unit 7410 and external information detection unit 7420 may be provided as independent sensors or devices, or as a device in which multiple sensors or devices are integrated.

[0097] Here, Figure 15 shows examples of the installation locations of the imaging unit 7410 and the external information detection unit 7420. The imaging units 7910, 7912, 7914, 7916, and 7918 are installed, for example, at least one of the following locations on the vehicle 7900: the front nose, side mirrors, rear bumper, tailgate, and the upper part of the windshield inside the passenger compartment. The imaging unit 7910 installed on the front nose and the imaging unit 7918 installed on the upper part of the windshield inside the passenger compartment mainly acquire images of the front of the vehicle 7900. The imaging units 7912 and 7914 installed on the side mirrors mainly acquire images of the sides of the vehicle 7900. The imaging unit 7916 installed on the rear bumper or tailgate mainly acquires images of the rear of the vehicle 7900. The imaging unit 7918, located at the top of the windshield inside the vehicle, is primarily used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0098] Figure 15 shows an example of the imaging range of each imaging unit 7910, 7912, 7914, and 7916. Imaging range a shows the imaging range of imaging unit 7910 located on the front nose, imaging ranges b and c show the imaging ranges of imaging units 7912 and 7914 located on the side mirrors, respectively, and imaging range d shows the imaging range of imaging unit 7916 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 7910, 7912, 7914, and 7916, an overhead view image of vehicle 7900 can be obtained.

[0099] The external information detection units 7920, 7922, 7924, 7926, 7928, and 7930, which are installed on the front, rear, sides, corners, and the upper part of the windshield inside the vehicle 7900, may be, for example, ultrasonic sensors or radar devices. The external information detection units 7920, 7926, and 7930, which are installed on the front nose, rear bumper, back door, and the upper part of the windshield inside the vehicle 7900, may be, for example, LIDAR devices. These external information detection units 7920 to 7930 are mainly used to detect preceding vehicles, pedestrians, or obstacles.

[0100] Returning to Figure 14, the explanation continues. The external information detection unit 7400 causes the imaging unit 7410 to capture images of the area outside the vehicle and receives the captured image data. The external information detection unit 7400 also receives detection information from the connected external information detection unit 7420. If the external information detection unit 7420 is an ultrasonic sensor, radar device, or LIDAR device, the external information detection unit 7400 emits ultrasonic waves or electromagnetic waves and receives information on the received reflected waves. Based on the received information, the external information detection unit 7400 may perform object detection processing such as detecting people, vehicles, obstacles, signs, or characters on the road surface, or distance detection processing. Based on the received information, the external information detection unit 7400 may perform environmental recognition processing to recognize rainfall, fog, or road surface conditions. Based on the received information, the external information detection unit 7400 may calculate the distance to an object outside the vehicle.

[0101] Furthermore, the external information detection unit 7400 may perform image recognition processing or distance detection processing to recognize people, vehicles, obstacles, signs, or characters on the road surface based on the received image data. The external information detection unit 7400 may perform distortion correction or alignment processing on the received image data, and may also synthesize image data captured by different imaging units 7410 to generate an overhead view image or a panoramic image. The external information detection unit 7400 may also perform viewpoint transformation processing using image data captured by different imaging units 7410.

[0102] The in-vehicle information detection unit 7500 detects information inside the vehicle. The in-vehicle information detection unit 7500 is connected to, for example, a driver status detection unit 7510 that detects the driver's state. The driver status detection unit 7510 may include a camera that images the driver, a biosensor that detects the driver's biometric information, or a microphone that collects sounds inside the vehicle. The biosensor is installed, for example, on the seat or steering wheel and detects the biometric information of a passenger sitting in the seat or a driver holding the steering wheel. Based on the detection information input from the driver status detection unit 7510, the in-vehicle information detection unit 7500 may calculate the driver's level of fatigue or concentration, or determine whether the driver is dozing off. The in-vehicle information detection unit 7500 may perform processing such as noise cancellation on the collected audio signals.

[0103] The integrated control unit 7600 controls the overall operation of the vehicle control system 7000 according to various programs. An input unit 7800 is connected to the integrated control unit 7600. The input unit 7800 is implemented by a device that can be operated by the occupant, such as a touch panel, buttons, a microphone, a switch, or a lever. The integrated control unit 7600 may also receive data obtained by voice recognition of audio input via the microphone. The input unit 7800 may be, for example, a remote control device using infrared or other radio waves, or an external device such as a mobile phone or PDA (Personal Digital Assistant) that supports the operation of the vehicle control system 7000. The input unit 7800 may also be, for example, a camera, in which case the occupant can input information through gestures. Alternatively, data obtained by detecting the movement of a wearable device worn by the occupant may be input. Furthermore, the input unit 7800 may include, for example, an input control circuit that generates an input signal based on information input by a passenger or the like using the input unit 7800 and outputs it to the integrated control unit 7600. By operating this input unit 7800, passengers or the like can input various data to the vehicle control system 7000 or instruct it to perform processing operations.

[0104] The memory unit 7690 may include a ROM (Read Only Memory) for storing various programs executed by a microcomputer, and a RAM (Random Access Memory) for storing various parameters, calculation results, or sensor values. The memory unit 7690 may also be implemented using magnetic storage devices such as an HDD (Hard Disk Drive), semiconductor storage devices, optical storage devices, or magneto-optical storage devices.

[0105] The general-purpose communication interface 7620 is a general-purpose communication interface that mediates communication between various devices present in the external environment 7750. The general-purpose communication interface 7620 may implement cellular communication protocols such as GSM (Global System of Mobile communications), WiMAX (registered trademark), LTE (Registered trademark) (Long Term Evolution), or LTE-A (LTE-Advanced), or other wireless communication protocols such as wireless LAN (also known as Wi-Fi (registered trademark)) or Bluetooth (registered trademark). The general-purpose communication interface 7620 may connect, for example, to devices (e.g., application servers or control servers) located on an external network (e.g., the Internet, a cloud network, or a carrier-specific network) via a base station or access point. Furthermore, the general-purpose communication interface 7620 may connect to terminals located near the vehicle (for example, terminals belonging to the driver, pedestrians, or shops, or MTC (Machine Type Communication) terminals) using, for example, P2P (Peer To Peer) technology.

[0106] The Dedicated Communication Interface 7630 is a communication interface that supports communication protocols developed for use in vehicles. The Dedicated Communication Interface 7630 may implement standard protocols such as WAVE (Wireless Access in Vehicle Environment), DSRC (Dedicated Short Range Communications), or cellular communication protocols, which are combinations of lower-layer IEEE 802.11p and upper-layer IEEE 1609. The Dedicated Communication Interface 7630 typically performs V2X communication, a concept that includes one or more of the following: vehicle-to-vehicle communication, vehicle-to-infrastructure communication, vehicle-to-home communication, and vehicle-to-pedestrian communication.

[0107] The positioning unit 7640 performs positioning by receiving GNSS signals from GNSS (Global Navigation Satellite System) satellites (for example, GPS signals from GPS (Global Positioning System) satellites) and generates location information including the vehicle's latitude, longitude, and altitude. The positioning unit 7640 may also determine its current location by exchanging signals with a wireless access point, or it may acquire location information from a terminal such as a mobile phone, PHS, or smartphone that has positioning capabilities.

[0108] The beacon receiver 7650 receives radio waves or electromagnetic waves transmitted from, for example, a radio station installed on a road, and obtains information such as the current location, traffic congestion, road closures, or travel time. The functions of the beacon receiver 7650 may also be included in the dedicated communication interface 7630 described above.

[0109] The in-vehicle equipment interface 7660 is a communication interface that mediates connections between the microcomputer 7610 and various in-vehicle equipment 7760 located inside the vehicle. The in-vehicle equipment interface 7660 may establish a wireless connection using wireless communication protocols such as Wi-Fi, Bluetooth (registered trademark), NFC (Near Field Communication), or WUSB (Wireless USB). Furthermore, the in-vehicle equipment interface 7660 may establish wired connections such as USB (Universal Serial Bus), HDMI (Registered Trademark) (High-Definition Multimedia Interface), or MHL (Mobile High-Definition Link) via connection terminals (and cables if necessary) not shown. The in-vehicle equipment 7760 may include, for example, at least one of the following: a mobile device or wearable device owned by a passenger, or an information device brought into or installed in the vehicle. The in-vehicle equipment 7760 may also include a navigation device that performs route searching to any destination. The in-vehicle equipment interface 7660 exchanges control signals or data signals with these in-vehicle equipment 7760s.

[0110] The in-vehicle network interface 7680 is an interface that mediates communication between the microcomputer 7610 and the communication network 7010. The in-vehicle network interface 7680 transmits and receives signals and other data in accordance with a predetermined protocol supported by the communication network 7010.

[0111] The microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 according to various programs based on information acquired via at least one of the following: general-purpose communication I / F 7620, dedicated communication I / F 7630, positioning unit 7640, beacon receiver 7650, in-vehicle equipment I / F 7660, and in-vehicle network I / F 7680. For example, the microcomputer 7610 may calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on acquired in-vehicle and external information, and output control commands to the drivetrain control unit 7100. For example, the microcomputer 7610 may perform coordinated control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following based on distance between vehicles, maintaining vehicle speed, collision warning, or lane departure warning. Furthermore, the microcomputer 7610 may perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on the acquired information about the vehicle's surroundings.

[0112] The microcomputer 7610 may generate three-dimensional distance information between the vehicle and surrounding structures, people, and other objects based on information acquired via at least one of the general-purpose communication I / F 7620, dedicated communication I / F 7630, positioning unit 7640, beacon receiver 7650, in-vehicle equipment I / F 7660, and in-vehicle network I / F 7680, and create local map information including surrounding information of the vehicle's current location. Furthermore, the microcomputer 7610 may predict dangers such as vehicle collision, proximity of pedestrians, or entry into a closed road based on the acquired information, and generate warning signals. These warning signals may, for example, be signals to generate a warning sound or illuminate a warning lamp.

[0113] The audio-image output unit 7670 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example in Figure 14, the output devices are exemplified as an audio speaker 7710, a display unit 7720, and an instrument panel 7730. The display unit 7720 may include, for example, at least one of an onboard display and a head-up display. The display unit 7720 may have an AR (Augmented Reality) display function. The output devices may be other devices other than these, such as headphones, wearable devices such as glasses-type displays worn by occupants, projectors, or lamps. If the output device is a display device, the display device visually displays the results obtained from various processes performed by the microcomputer 7610 or information received from other control units in various formats such as text, images, tables, graphs, etc. Furthermore, if the output device is an audio output device, the audio output device converts the audio signal, consisting of the reproduced audio data or sound data, into an analog signal and outputs it audibly.

[0114] In the example shown in Figure 14, at least two control units connected via the communication network 7010 may be integrated into a single control unit. Alternatively, individual control units may be composed of multiple control units. Furthermore, the vehicle control system 7000 may include other control units not shown. Also, in the above description, some or all of the functions performed by one control unit may be assigned to other control units. In other words, as long as information is transmitted and received via the communication network 7010, predetermined calculation processing may be performed by any of the control units. Similarly, a sensor or device connected to one control unit may be connected to another control unit, and multiple control units may transmit and receive detection information to each other via the communication network 7010.

[0115] Furthermore, the computer programs for realizing each function of the solid-state imaging device 1 according to this embodiment, as described with reference to Figures 1 to 13, can be implemented in any of the control units or the like. A computer-readable recording medium containing such a computer program can also be provided. Examples of recording media include magnetic disks, optical disks, magneto-optical disks, and flash memory. Alternatively, the computer programs may be distributed without using a recording medium, for example, via a network.

[0116] In the vehicle control system 7000 described above, the solid-state imaging device 1 according to this embodiment, as described using Figures 1 to 13, can be applied to the imaging unit 7410 and the driver state detection unit 7510 in the application example shown in Figure 14.

[0117] Furthermore, at least some of the components of the solid-state imaging device 1 described using Figures 1 to 13 may be implemented in a module for the integrated control unit 7600 shown in Figure 14 (for example, an integrated circuit module consisting of a single die). Alternatively, the solid-state imaging device 1 described using Figures 1 to 13 may be implemented by multiple control units of the vehicle control system 7000 shown in Figure 14.

[0118] The embodiments described above may also take the following forms.

[0119] (1) A light-receiving element, A transfer transistor, the first terminal of which is connected to the output terminal of the light-receiving element, transfers the signal output by the light-receiving element to the second terminal at the timing when an ON signal is applied to the drive terminal, A first transistor, the first terminal of which is connected to a power line and the second terminal of which is connected to the first terminal or the second terminal of the transfer transistor, A voltage holding circuit is connected between the drive terminal of the first transistor and the second terminal of the first transistor, A solid-state imaging device equipped with the following features.

[0120] (2) The voltage holding circuit is A capacitor is connected between the drive terminal of the first transistor and the second terminal of the first transistor. Equipped with, (1) The solid-state imaging device described above.

[0121] (3) The voltage holding circuit is A second transistor, the first terminal of which is connected to a signal line and the second terminal of which is connected to one end of the capacitor and the drive terminal of the first transistor, A third transistor, the first terminal of which is connected to the other terminal of the capacitor and the second terminal of which is connected to the second terminal of the first transistor, A fourth transistor, the first terminal of which is connected to the first terminal of the second transistor, and the second terminal of which is connected to the first terminal of the third transistor, Equipped with, The other end of the capacitor is connected to the second end of the first transistor via the third transistor. (2) The solid-state imaging device described above.

[0122] (4) During initialization, the second and third transistors are controlled so that they do not turn on at the same time as the fourth transistor. (3) The solid-state imaging device described above.

[0123] (5) The first transistor is a reset transistor whose second terminal is connected to a floating diffusion region and which initializes the floating diffusion region. A solid-state imaging device as described in any of (1) to (4).

[0124] (6) The first transistor is a transistor that forms an overflow gate, with its second terminal connected to the output terminal of the light-receiving element. A solid-state imaging device as described in any of (1) to (4).

[0125] (7) Formed by stacked semiconductor layers, The light-receiving element, the transfer transistor, the first transistor, and the voltage holding circuit are formed on the same semiconductor layer. A solid-state imaging device as described in any of (1) to (6).

[0126] (8) Formed by stacked semiconductor layers, The light-receiving element and the transfer transistor, The first transistor and the voltage holding circuit, This is formed on another semiconductor layer. A solid-state imaging device as described in any of (1) to (6).

[0127] (9) A light-receiving element, A transfer transistor, the first terminal of which is connected to the output terminal of the light-receiving element, transfers the signal output by the light-receiving element to the second terminal at the timing when an ON signal is applied to the drive terminal, A first transistor, the first terminal of which is connected to a power line and the second terminal of which is connected to the first terminal or the second terminal of the transfer transistor, A voltage holding circuit is connected between the drive terminal of the first transistor and the second terminal of the first transistor, An electronic device having a solid-state imaging unit.

[0128] (10) The solid-state imaging unit has the characteristics of a solid-state imaging device as described in any of (2) to (8). (9) Electronic equipment as described above.

[0129] The aspects of this disclosure are not limited to the embodiments described above, but include various conceivable variations, and the effects of this disclosure are not limited to those described above. The components in each embodiment may be appropriately combined and applied. That is, various additions, modifications, and partial deletions are possible, as long as they do not deviate from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents. [Explanation of Symbols]

[0130] 1: Solid-state imaging device, 10: Pixel array, 100: Pixels, P: Light-receiving element, TRG: Transfer Gate, TRX: Transfer gate, RST: Reset transistor, AMP: Amplifying transistor, SEL: Selector transistor, OFG: Overflow Gate FD: Floating Diffusion Region, MEM: Memory area, PD_C: Cathode region, VDDH: Power line, VDDR: Power line, VDDO: Power line, 102: Voltage holding circuit, C: Capacitor, M2, M3, M4: Transistors, 12: Control circuits, 14: First scanning circuit, 140: Signal line, 16: Second scanning circuit, 160: Signal line, 18: Signal processing circuit, 180: Signal line, 2: Semiconductor layer, 20: 1st layer, 22: 2nd layer, 24: 3rd layer

Claims

1. A light-receiving element, A transfer transistor, the first terminal of which is connected to the output terminal of the light-receiving element, transfers the signal output by the light-receiving element to the second terminal at the timing when an ON signal is applied to the drive terminal, A first transistor, the first terminal of which is connected to a power line and the second terminal of which is connected to the first terminal or the second terminal of the transfer transistor, A voltage holding circuit is connected between the drive terminal of the first transistor and the second terminal of the first transistor, A solid-state imaging device equipped with the following features.

2. The voltage holding circuit is A capacitor is connected between the drive terminal of the first transistor and the second terminal of the first transistor. Equipped with, The solid-state imaging apparatus according to claim 1.

3. The voltage holding circuit is A second transistor, the first terminal of which is connected to a signal line and the second terminal of which is connected to one end of the capacitor and the drive terminal of the first transistor, A third transistor, the first terminal of which is connected to the other terminal of the capacitor and the second terminal of which is connected to the second terminal of the first transistor, A fourth transistor, the first terminal of which is connected to the first terminal of the second transistor, and the second terminal of which is connected to the first terminal of the third transistor, Equipped with, The other end of the capacitor is connected to the second end of the first transistor via the third transistor. The solid-state imaging apparatus according to claim 2.

4. During initialization, the second and third transistors are controlled so that they do not turn on at the same time as the fourth transistor. The solid-state imaging apparatus according to claim 3.

5. The first transistor is a reset transistor whose second terminal is connected to a floating diffusion region and which initializes the floating diffusion region. The solid-state imaging apparatus according to claim 1.

6. The first transistor is a transistor that forms an overflow gate, with its second terminal connected to the output terminal of the light-receiving element. The solid-state imaging apparatus according to claim 1.

7. Formed by stacked semiconductor layers, The light-receiving element, the transfer transistor, the first transistor, and the voltage holding circuit are formed on the same semiconductor layer. The solid-state imaging apparatus according to claim 1.

8. Formed by stacked semiconductor layers, The light-receiving element and the transfer transistor, The first transistor and the voltage holding circuit, This is formed on another semiconductor layer. The solid-state imaging apparatus according to claim 1.

Images