Semiconductor equipment

Abstract

To provide a semiconductor device with improved electrical characteristics and reliability. [Solution] The semiconductor device of the present invention comprises a first channel pattern and a second channel pattern superimposed on each other, a first gate pattern disposed between the first channel pattern and the second channel pattern and superimposed on the first channel pattern and the second channel pattern, a first connecting conductive pattern and a second connecting conductive pattern separated from each other in a first direction via the first channel pattern, the second channel pattern, and the first gate pattern, and a first source / drain pattern connected to the first channel pattern and the second channel pattern, wherein the first connecting conductive pattern and the second connecting conductive pattern are electrically connected to the first gate pattern.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a channel pattern.

Background Art

[0002] A semiconductor device includes an integrated circuit composed of MOS (Metal Oxide Semiconductor) field effect transistors (MOSFETs). As the size and design rules of semiconductor devices are gradually reduced, the scaling down of the size of MOS field effect transistors is also accelerating. The operating characteristics of semiconductor devices deteriorate as the size of MOS field effect transistors is reduced. Therefore, various methods for forming semiconductor devices with better performance while overcoming the limitations corresponding to the high integration of semiconductor devices are being studied.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the above prior art, and an object of the present invention b is to provide a semiconductor device with improved electrical characteristics and reliability.

Means for Solving the Problems

[0005] A semiconductor device according to one aspect of the present invention, made to achieve the above objective, comprises: a first channel pattern and a second channel pattern superimposed on each other; a first gate pattern disposed between the first channel pattern and the second channel pattern and superimposed on the first channel pattern and the second channel pattern; a first connecting conductive pattern and a second connecting conductive pattern separated from each other in a first direction via the first channel pattern, the second channel pattern, and the first gate pattern; and a first source / drain pattern connected to the first channel pattern and the second channel pattern, wherein the first connecting conductive pattern and the second connecting conductive pattern are electrically connected to the first gate pattern.

[0006] A semiconductor device according to another aspect of the present invention made to achieve the above objectives comprises: a first channel pattern and a second channel pattern superimposed on each other; a first gate pattern disposed between the first channel pattern and the second channel pattern and superimposed on the first channel pattern and the second channel pattern; a first connecting conductive pattern separated from the first channel pattern and the second channel pattern and electrically connected to the first gate pattern; and a source / drain pattern connected to the first channel pattern and the second channel pattern, wherein the first channel pattern, the second channel pattern, and the first gate pattern are disposed between the upper and lower surfaces of the first connecting conductive pattern.

[0007] A semiconductor device according to one embodiment includes a first channel pattern and a second channel pattern superimposed on each other, a first gate pattern disposed between the first channel pattern and the second channel pattern and superimposed on the first channel pattern and the second channel pattern, a first connecting conductive pattern and a second connecting conductive pattern separated from each other in a first direction via the first channel pattern, the second channel pattern, and the first gate pattern, a first source / drain pattern connected to the first channel pattern and the second channel pattern, a third channel pattern separated from the first channel pattern in a first direction, a fourth channel pattern separated from the second channel pattern in a first direction and superimposed on the third channel pattern, and a first gate pattern disposed between the third channel pattern and the fourth channel pattern and superimposed on the third channel pattern and the fourth channel pattern. The device comprises a second gate pattern separated from the pattern in the first direction, a third connected conductive pattern and a fourth connected conductive pattern separated from each other in the first direction via the third channel pattern and the fourth channel pattern, a second source / drain pattern connected to the third channel pattern and the fourth channel pattern, a first spacer superimposed on the first source / drain pattern and the second source / drain pattern, a first mask pattern superimposed on the first channel pattern, the second channel pattern and the first gate pattern, a second mask pattern superimposed on the third channel pattern, the fourth channel pattern and the second gate pattern, a second spacer on the first mask pattern, the second mask pattern and the first spacer, and a cover insulating film on the first mask pattern, the second mask pattern and the first to fourth connected conductive patterns. [Effects of the Invention]

[0008] According to the semiconductor device of the present invention, by including a linked conductive pattern, the uniformity of the critical voltage of the cell transistor can be improved, and the size of the semiconductor device can be minimized. [Brief explanation of the drawing]

[0009] [Figure 1A] This is a plan view of a semiconductor device according to one embodiment. [Figure 1B] This is a cross-sectional view along the line A-A' in Figure 1A. [Figure 1C] This is a cross-sectional view along the line B-B' in Figure 1A. [Figure 1D] This is a cross-sectional view along the line C-C' in Figure 1A. [Figure 1E] This is a cross-sectional view along the line D-D' in Figure 1A. [Figure 1F] This is an enlarged view of the Q1 region in Figure 1A. [Figure 1G] This is an enlarged view of area Q2 in Figure 1B. [Figure 1H] This is an enlarged view of area Q3 in Figure 1C. [Figure 2] Figures 1A to 1H illustrate the manufacturing method of a semiconductor device. [Figure 3A] Figures 1A to 1H illustrate the manufacturing method of a semiconductor device. [Figure 3B] Figures 1A to 1H illustrate the manufacturing method of a semiconductor device. [Figure 4A] Figures 1A to 1H illustrate the manufacturing method of a semiconductor device. [Figure 4B] Figures 1A to 1H illustrate the manufacturing method of a semiconductor device. [Figure 5] Figures 1A to 1H illustrate the manufacturing method of a semiconductor device. [Figure 6A] Figures 1A to 1H illustrate the manufacturing method of a semiconductor device. [Figure 6B] Figures 1A to 1H illustrate the manufacturing method of a semiconductor device. [Figure 6C]These are diagrams for explaining the method of manufacturing a semiconductor device according to FIGS. 1A to 1H. [Figure 7A] These are diagrams for explaining the method of manufacturing a semiconductor device according to FIGS. 1A to 1H. [Figure 7B] These are diagrams for explaining the method of manufacturing a semiconductor device according to FIGS. 1A to 1H. [Figure 7C] These are diagrams for explaining the method of manufacturing a semiconductor device according to FIGS. 1A to 1H. [Figure 7D] These are diagrams for explaining the method of manufacturing a semiconductor device according to FIGS. 1A to 1H. [Figure 8A] These are diagrams for explaining the method of manufacturing a semiconductor device according to FIGS. 1A to 1H. [Figure 8B] These are diagrams for explaining the method of manufacturing a semiconductor device according to FIGS. 1A to 1H. [Figure 8C] These are diagrams for explaining the method of manufacturing a semiconductor device according to FIGS. 1A to 1H. [Figure 9A] These are diagrams for explaining the method of manufacturing a semiconductor device according to FIGS. 1A to 1H. [Figure 9B] These are diagrams for explaining the method of manufacturing a semiconductor device according to FIGS. 1A to 1H. [Figure 9C] These are diagrams for explaining the method of manufacturing a semiconductor device according to FIGS. 1A to 1H. [Figure 10A] These are diagrams for explaining the method of manufacturing a semiconductor device according to FIGS. 1A to 1H. [Figure 10B] These are diagrams for explaining the method of manufacturing a semiconductor device according to FIGS. 1A to 1H. [Figure 10C] These are diagrams for explaining the method of manufacturing a semiconductor device according to FIGS. 1A to 1H. [Figure 11A] These are diagrams for explaining the method of manufacturing a semiconductor device according to FIGS. 1A to 1H. [Figure 11B] These are diagrams for explaining the method of manufacturing a semiconductor device according to FIGS. 1A to 1H. [Figure 12A] These are diagrams for explaining the method of manufacturing a semiconductor device according to FIGS. 1A to 1H. [Figure 12B]Figures 1A to 1H illustrate the manufacturing method of a semiconductor device. [Figure 12C] Figures 1A to 1H illustrate the manufacturing method of a semiconductor device. [Figure 13A] Figures 1A to 1H illustrate the manufacturing method of a semiconductor device. [Figure 13B] Figures 1A to 1H illustrate the manufacturing method of a semiconductor device. [Figure 13C] Figures 1A to 1H illustrate the manufacturing method of a semiconductor device. [Figure 14A] Figures 1A to 1H illustrate the manufacturing method of a semiconductor device. [Figure 14B] Figures 1A to 1H illustrate the manufacturing method of a semiconductor device. [Figure 14C] Figures 1A to 1H illustrate the manufacturing method of a semiconductor device. [Figure 14D] Figures 1A to 1H illustrate the manufacturing method of a semiconductor device. [Figure 15A] This is a cross-sectional view of a semiconductor device according to one embodiment. [Figure 15B] This is a cross-sectional view of a semiconductor device according to one embodiment. [Figure 15C] This is a cross-sectional view of a semiconductor device according to one embodiment. [Figure 16A] This is an enlarged cross-sectional view of a semiconductor device according to one embodiment. [Figure 16B] This is an enlarged cross-sectional view of a semiconductor device according to one embodiment. [Figure 17] This is a cross-sectional view of a semiconductor device according to one embodiment. [Modes for carrying out the invention]

[0010] Hereinafter, specific examples of embodiments for carrying out the present invention will be described in detail with reference to the drawings.

[0011] Figure 1A is a plan view of a semiconductor device according to one embodiment. Figure 1B is a cross-sectional view along the line A-A' in Figure 1A. Figure 1C is a cross-sectional view along the line B-B' in Figure 1A. Figure 1D is a cross-sectional view along the line C-C' in Figure 1A. Figure 1E is a cross-sectional view along the line D-D' in Figure 1A. Figure 1F is an enlarged view of the Q1 region in Figure 1A. Figure 1G is an enlarged view of the Q2 region in Figure 1B. Figure 1H is an enlarged view of the Q3 region in Figure 1C.

[0012] Referring to Figures 1A, 1B, 1C, 1D, and 1E, the semiconductor device includes a substrate 10. Logic cells are arranged on the substrate 10. In this invention, a logic cell means a logic element that performs a specific function (e.g., AND, OR, XOR, XNOR, inverter, etc.). The logic cell includes transistors for constituting the logic element.

[0013] The substrate 10 is a semiconductor substrate, an insulating substrate, or a semiconductor on-insulator (SOI) substrate. The semiconductor substrate includes, for example, silicon, germanium, silicon-germanium, GaP, or GaAs. The substrate 10 has the shape of a plate that extends along a plane that extends in a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 intersect each other. For example, the first direction D1 and the second direction D2 are mutually orthogonal horizontal directions.

[0014] In one embodiment, the semiconductor device does not need to include the substrate 10.

[0015] An insulating pattern 11 is provided on the substrate 10. The insulating pattern 11 includes insulating patterns 11 arranged in a first direction. The insulating pattern 11 includes insulating patterns 11 arranged in a second direction D2. The insulating pattern 11 contains an insulating material. As an example, the insulating pattern 11 contains an oxide.

[0016] In one embodiment, the semiconductor device may not include an insulating pattern 11 and may include an active pattern that protrudes in a third direction D3 from the substrate 10. The active pattern is positioned where the insulating pattern 11 would normally be located. The third direction D3 intersects the first direction D1 and the second direction D2. For example, the third direction D3 is perpendicular to the first direction D1 and the second direction D2.

[0017] An intervening pattern 12 is provided on the substrate 10. The intervening pattern 12 includes intervening patterns 12 arranged in a first direction. The intervening pattern 12 includes intervening patterns 12 arranged in a second direction D2. The intervening pattern 12 contains an insulating material.

[0018] A channel pattern 31 is provided. The channel pattern 31 is superimposed on the insulating pattern 11 in a third direction D3. One insulating pattern 11 and multiple channel patterns 31 are superimposed in the third direction D3.

[0019] The channel pattern 31 includes a semiconductor material. For example, the channel pattern 31 includes a two-dimensional semiconductor material (e.g., WSe2, MoS2, BP (Black phosphorus)). In one embodiment, the channel pattern 31 may be a single-atom layer film.

[0020] The number of channel patterns 31 superimposed on the third direction D3 is not limited to those shown in the illustration. In one embodiment, the number of channel patterns 31 superimposed on the third direction D3 may be two or fewer, or four or more.

[0021] A source / drain pattern SD is provided. The source / drain pattern SD is positioned between channel patterns 31 that are separated in a second direction D2. The source / drain pattern SD is connected to a channel pattern 31 that is superimposed in a third direction D3. The channel pattern 31 superimposed in the third direction D3 is positioned between source / drain pattern SDs that are separated in a second direction D2. The source / drain pattern SD is positioned between intervening patterns 12 that are adjacent to each other in a first direction D1.

[0022] The source / drain pattern SD is an epitaxial pattern formed by a selective epitaxial growth (SEG) process. The source / drain pattern SD contains silicon or silicon germanium. The source / drain pattern SD is doped with impurities.

[0023] A gate pattern GE1 is provided. The gate pattern GE1 is superimposed on the insulating pattern 11 and the channel pattern 31 in a third direction D3. One insulating pattern 11, multiple gate patterns GE1, and multiple channel patterns 31 are superimposed in a third direction D3. The channel patterns 31 are placed between the gate patterns GE1. The channel patterns 31 and the gate patterns GE1 are separated.

[0024] The gate pattern GE1 contains a conductive material. For example, the gate pattern GE1 contains TiAlC or TiN.

[0025] An upper channel pattern 32 is provided. The upper channel pattern 32 is superimposed in a third direction D3 on the insulating pattern 11, the channel pattern 31, and the gate pattern GE1. One insulating pattern 11, multiple channel patterns 31, multiple gate patterns GE1, and multiple upper channel patterns 32 are superimposed in a third direction D3. The upper channel pattern 32 is positioned at a higher level than the channel pattern 31 and the gate pattern GE1.

[0026] The upper channel pattern 32 contains a semiconductor material. For example, the upper channel pattern 32 contains a two-dimensional semiconductor material (e.g., WSe2, MoS2, BP (Black phosphorus)). The upper channel pattern 32 and the channel pattern 31 may contain the same material or different materials. In one embodiment, the upper channel pattern 32 may be a single-atom layer film.

[0027] The number of upper channel patterns 32 superimposed on the third direction D3 is not limited to those shown in the illustration. In one embodiment, the number of upper channel patterns 32 superimposed on the third direction D3 may be two or fewer, or four or more.

[0028] An upper source / drain pattern USD is provided. The upper source / drain pattern USD is positioned between upper channel patterns 32 separated in the second direction D2. The upper source / drain pattern USD is connected to an upper channel pattern 32 superimposed in the third direction D3. The upper channel pattern 32 superimposed in the third direction D3 is positioned between upper source / drain patterns USD separated in the second direction D2. The upper source / drain pattern USD is positioned at a higher level than the source / drain pattern SD.

[0029] The upper source / drain pattern USD is an epitaxial pattern formed by a selective epitaxial growth (SEG) process. The upper source / drain pattern USD contains silicon or silicon germanium. The upper source / drain pattern USD is doped with impurities. The source / drain pattern SD and the upper source / drain pattern USD have different conductivity types. For example, the source / drain pattern SD has an N-type conductivity, and the upper source / drain pattern USD has a P-type conductivity.

[0030] An upper gate pattern GE2 is provided. The upper gate pattern GE2 is superimposed in a third direction D3 on the insulating pattern 11, channel pattern 31, gate pattern GE1, and upper channel pattern 32. One insulating pattern 11, multiple gate patterns GE1, multiple channel patterns 31, multiple upper channel patterns 32, and multiple upper gate patterns GE2 are superimposed in a third direction D3. The upper channel pattern 32 is positioned between the upper gate patterns GE2. The upper channel pattern 32 and the upper gate pattern GE2 are separated. The upper gate pattern GE2 is positioned at a higher level than the channel pattern 31 and gate pattern GE1.

[0031] The upper gate pattern GE2 contains a conductive material. For example, the upper gate pattern GE2 contains TiAlC or TiN. The gate pattern GE1 and the upper gate pattern GE2 may contain the same material or different materials.

[0032] A gate insulating film GI is provided. The gate insulating film GI is in contact with the gate pattern GE1 and the channel pattern 31, or with the upper gate pattern GE2 and the upper channel pattern 32. The gate insulating film GI separates the channel pattern 31 from the gate pattern GE1. The gate insulating film GI separates the upper channel pattern 32 from the upper gate pattern GE2. The gate insulating film GI contains an insulating material. As an example, the gate insulating film GI contains an oxide.

[0033] The upper source / drain pattern USD is positioned at a higher level than the source / drain pattern SD. The inner spacer IS is positioned between the source / drain pattern SD and the gate pattern GE1 or between the upper source / drain pattern USD and the upper gate pattern GE2. The inner spacer IS and the gate pattern GE1 or the upper gate pattern GE2 are separated by a gate insulating film GI. An upper channel pattern 32 is provided between the inner spacer IS separated in a third direction D3. A channel pattern 31 is provided between the inner spacer IS separated in a third direction D3. The inner spacer IS contains an insulating material.

[0034] A first interlayer insulation pattern 43 is provided. The first interlayer insulation pattern 43 is superimposed in a third direction D3 on the insulation pattern 11, channel pattern 31, gate pattern GE1, upper channel pattern 32, and upper gate pattern GE2. The first interlayer insulation pattern 43 is positioned between channel pattern 31 and upper channel pattern 32, and between gate pattern GE1 and upper gate pattern GE2. The first interlayer insulation pattern 43 contains an insulating material.

[0035] A second interlayer insulation pattern 44 is provided. The second interlayer insulation pattern 44 is superimposed in a third direction D3 on the source / drain pattern SD and the upper source / drain pattern USD. The second interlayer insulation pattern 44 is located between the source / drain pattern SD and the upper source / drain pattern USD. The second interlayer insulation pattern 44 contains insulating material.

[0036] The first interlayer insulation pattern 43 and the second interlayer insulation pattern 44 are arranged alternately with respect to each other in the second direction D2.

[0037] A mask pattern MP is provided. The mask pattern MP is superimposed in a third direction D3 on the insulating pattern 11, channel pattern 31, gate pattern GE1, upper channel pattern 32, and upper gate pattern GE2. One mask pattern MP, one insulating pattern 11, multiple gate patterns GE1, multiple channel patterns 31, multiple upper channel patterns 32, and multiple upper gate patterns GE2 are superimposed in a third direction D3.

[0038] The mask pattern MP is positioned at a higher level than the upper channel pattern 32 and the upper gate pattern GE2. The mask pattern MP is provided on the gate insulating film GI. The lower surface of the mask pattern MP is in contact with the gate insulating film GI. The mask pattern MP contains an insulating material. As an example, the mask pattern MP contains a nitride.

[0039] A linked conductive pattern 21 is provided. Between two linked conductive patterns 21 separated from each other in a first direction D1, a mask pattern MP, an insulating pattern 11, a channel pattern 31, an upper channel pattern 32, a gate pattern GE1, an upper gate pattern GE2, and a gate insulating film GI are provided superimposed in a third direction D3. The linked conductive pattern 21 is electrically connected to the gate pattern GE1 and the upper gate pattern GE2. The linked conductive pattern 21 is in contact with the gate pattern GE1 and the upper gate pattern GE2. The linked conductive pattern 21 is in contact with the mask pattern MP and the gate insulating film GI. The channel pattern 31 and the upper channel pattern 32 are separated from the linked conductive pattern 21 by the gate insulating film GI.

[0040] The lower surface 21_L of the connecting conductive pattern 21 is in contact with the substrate 10. The lower surface 21_L of the connecting conductive pattern 21 is coplane with the lower surface of the insulating pattern 11. The upper surface 21_U of the connecting conductive pattern 21 is coplane with the upper surface of the mask pattern MP. The upper surface 21_U of the connecting conductive pattern 21 is in contact with the cover insulating film 40, which will be described later. Between the lower surface 21_L and the upper surface 21_U of the connecting conductive pattern 21, the mask pattern MP, insulating pattern 11, channel pattern 31, upper channel pattern 32, gate pattern GE1, upper gate pattern GE2, and gate insulating film GI are provided. The upper surface 21_U of the connecting conductive pattern 21 is the uppermost part of the connecting conductive pattern 21. The lower surface 21_L of the connecting conductive pattern 21 is the lowermost part of the connecting conductive pattern 21.

[0041] The linked conductive pattern 21 contains a conductive material different from the gate pattern GE1 and the upper gate pattern GE2. For example, the linked conductive pattern 21 contains a two-dimensional conductive material (e.g., graphene or a transition metal chalcogenide). In one embodiment, the linked conductive pattern 21 may be a single-atom layer film.

[0042] A cover insulating film 40 is provided on the connected conductive pattern 21 and the mask pattern MP. The cover insulating film 40 includes an intervening portion 42 and an upper portion 41 connecting the intervening portions 42. The intervening portion 42 of the cover insulating film 40 is positioned at a lower level than the upper portion 41 of the cover insulating film 40. The intervening portion 42 is provided between the connected conductive patterns 21 that are adjacent to each other in a first direction D1. The intervening portion 42 is in contact with the two connected conductive patterns 21. The upper portion 41 of the cover insulating film 40 is in contact with the upper surface of the mask pattern MP. The cover insulating film 40 contains an insulating material. As an example, the cover insulating film 40 contains a nitride.

[0043] A first spacer 22 is provided. The first spacer 22 is provided on the upper source / drain pattern USD and the source / drain pattern SD. The first spacer 22 is superimposed on the upper source / drain pattern USD and the source / drain pattern SD in a third direction D3.

[0044] The first spacer 22 includes a first portion 22a, a second portion 22b on the first portion 22a, and a third portion 22c on the second portion 22b. The first portion 22a of the first spacer 22 is provided between adjacent source / drain patterns SD in a first direction D1 and between adjacent upper source / drain patterns USD in a first direction D1. The first portion 22a of the first spacer 22 is in contact with the adjacent source / drain patterns SD and the adjacent upper source / drain patterns USD in a first direction D1. The width of the first portion 22a of the first spacer 22 in a first direction D1 is the same as the distance in a first direction D1 between adjacent source / drain patterns SD and the distance in a first direction D1 between adjacent upper source / drain patterns USD in a first direction D1. The first portion 22a of the first spacer 22 is provided on the intervening pattern 12.

[0045] The third portion 22c of the first spacer 22 is separated from each other in the second direction D2. The first spacer 22 contains an insulating material.

[0046] A second spacer 23 is provided. The second spacer 23 is provided on the first spacer 22 and the mask pattern MP. The second spacer 23 extends in the first direction D1. A third portion 22c of the first spacer 22 is provided between adjacent second spacers 23 in the second direction D2. The second spacer 23 contains an insulating material.

[0047] A filling insulating film 53 is provided. The filling insulating film 53 is provided on the first spacer 22. The filling insulating film 53 is provided between the third portion 22c of the first spacer 22. The filling insulating film 53 contains an insulating material.

[0048] A first isolation insulating film 51 and a second isolation insulating film 52 are provided. The first isolation insulating film 51 penetrates the second portion 22b of the first spacer 22 in a third direction D3. The lower part of the first isolation insulating film 51 is provided within the first portion 22a of the first spacer 22. The first isolation insulating film 51 is superimposed on the first portion 22a of the first spacer 22 in a third direction D3. The second isolation insulating film 52 penetrates the second portion 22b of the first spacer 22 in a third direction D3. The lower part of the second isolation insulating film 52 is provided within the first portion 22a of the first spacer 22. The second isolation insulating film 52 is superimposed on the first portion 22a of the first spacer 22 in a third direction D3. The length of the first isolation insulating film 51 in the third direction D3 is less than the length of the second isolation insulating film 52 in the third direction D3. The first and second isolation insulating films (51, 52) contain an insulating material.

[0049] Active contacts (AC1, AC2) are provided. The active contacts (AC1, AC2) include a first active contact AC1 and a second active contact AC2. The first active contact AC1 penetrates the filling insulating film 53 and the second portion 22b of the first spacer 22 in a third direction D3. The first active contact AC1 is in contact with the upper source / drain pattern USD. The second active contact AC2 penetrates the filling insulating film 53, the second portion 22b of the first spacer 22, the upper source / drain pattern USD, and the second interlayer insulation pattern 44 in a third direction D3. The second active contact AC2 is in contact with the upper source / drain pattern USD and the source / drain pattern SD. The active contacts (AC1, AC2) contain a conductive material.

[0050] A gate contact GC is provided. The gate contact GC penetrates the upper part 41 of the cover insulating film 40, the mask pattern MP, and the gate insulating film GI in a third direction D3. The gate contact GC is in contact with the upper gate pattern GE2. The gate contact GC contains a conductive material.

[0051] A lower active contact LAC is provided. The lower active contact LAC is superimposed on the first active contact AC1 in a third direction D3. The lower active contact LAC is in contact with the source / drain pattern SD. The lower active contact LAC penetrates the substrate 10 in the third direction D3. The lower active contact LAC contains a conductive material.

[0052] The channel pattern 31 includes a first channel pattern 31_1, a second channel pattern 31_2, a third channel pattern 31_3, and a fourth channel pattern 31_4, all of which are superimposed on each other in the third direction D3.

[0053] The third channel pattern 31_3 is positioned at the same level as the first channel pattern 31_1 and is separated from the first channel pattern 31_1 in the first direction D1. The fourth channel pattern 31_4 is positioned at the same level as the second channel pattern 31_2 and is separated from the second channel pattern 31_2 in the first direction D1.

[0054] Gate pattern GE1 includes a first gate pattern GE1_1 positioned between the first channel pattern 31_1 and the second channel pattern 31_2, and a second gate pattern GE1_2 positioned between the third channel pattern 31_3 and the fourth channel pattern 31_4. The second gate pattern GE1_2 is positioned at the same level as the first gate pattern GE1_1 and is separated from the first gate pattern GE1_1 in the first direction D1. The first gate pattern GE1_1 is superimposed on the first and second channel patterns (31_1, 31_2) in the third direction D3. The second gate pattern GE1_2 is superimposed on the third and fourth channel patterns (31_3, 31_4) in the third direction D3.

[0055] The linked conductive pattern 21 includes first and second channel patterns (31_1, 31_2) and first linked conductive patterns 21_1 and 21_2 which are separated from each other in the first direction D1 via the first gate pattern GE1_1. The linked conductive pattern 21 also includes third and fourth channel patterns (31_3, 31_4) and third linked conductive patterns 21_3 and 41_4 which are separated from each other in the first direction D1 via the second gate pattern GE1_2.

[0056] The first connected conductive pattern 21_1 and the second connected conductive pattern 21_2 are electrically connected to the first gate pattern GE1_1. The first connected conductive pattern 21_1 and the second connected conductive pattern 21_2 are in contact with the first gate pattern GE1_1. The third connected conductive pattern 21_3 and the fourth connected conductive pattern 21_4 are electrically connected to the second gate pattern GE1_2. The third connected conductive pattern 21_3 and the fourth connected conductive pattern 21_4 are in contact with the second gate pattern GE1_2. The first connected conductive pattern 21_1 and the second connected conductive pattern 21_2 are separated from the first and second channel patterns (31_1, 31_2). The third connected conductive pattern 21_3 and the fourth connected conductive pattern 21_4 are separated from the third and fourth channel patterns (31_3, 31_4). The first and second channel patterns (31_1, 31_2) and the first gate pattern GE1_1 are positioned between the upper surface 21_U and the lower surface 21_L of the first and second connected conductive patterns (21_1, 21_2), respectively.

[0057] The source / drain pattern SD includes a first source / drain pattern SD1 connected to the first and second channel patterns (31_1, 31_2) and a second source / drain pattern SD2 connected to the third and fourth channel patterns (31_3, 31_4).

[0058] The mask pattern MP includes a first mask pattern MP1 superimposed in the third direction D3 on the first and second channel patterns (31_1, 31_2) and the first gate pattern GE1_1, and a second mask pattern MP2 superimposed in the third direction D3 on the third and fourth channel patterns (31_3, 31_4) and the second gate pattern GE1_2.

[0059] Referring to Figures 1F, 1G, and 1H, the connecting conductive pattern 21 includes a lower section 21a and an upper section 21b. The lower section 21a of the connecting conductive pattern 21 includes a first sidewall section 21a1 and a second sidewall section 21a2. The second sidewall section 21a2 is connected to the first sidewall section 21a1. The second sidewall sections 21a2 are separated from each other in the second direction D2.

[0060] The first side wall 21a1_S1 of the first side wall portion 21a1 is in contact with the side wall GE1_S of the gate pattern GE1, the side wall GE2_S of the upper gate pattern GE2, and the side wall GI_S of the gate insulating film GI. The first side wall 21a2_S1 of the second side wall portion 21a2 is in contact with the first side wall 23_S1 of the second spacer 23. The second side wall 23_S2 of the second spacer 23 is in contact with the first side wall 22_S1 of the first spacer 22. The second side wall 22_S2 of the first spacer 22 is in contact with the filling insulating film 53. The first side wall 23_S1 and the second side wall 23_S2 of the second spacer 23 are opposite to each other. The first side wall 22_S1 and the second side wall 22_S2 of the first spacer 22 are opposite to each other.

[0061] The intervening portion 42 of the cover insulating film 40 includes a first portion 42a and a second portion 42b. The first portion 42a of the intervening portion 42 is in contact with the first side wall portion 21a1 and the second side wall portion 21a2. The first portion 42a of the intervening portion 42 is positioned between the second portion 42b of the intervening portion 42. The second portion 42b of the intervening portion 42 is in contact with the second side wall portion 21a2. The width of the first portion 42a of the intervening portion 42 in the first direction D1 is greater than the width of the second portion 42b of the intervening portion 42 in the first direction D1.

[0062] The first portion 42a of the intervening portion 42 includes a first side wall 42a_S1 that contacts the second side wall 21a2_S2 of the second side wall portion 21a2, and a second side wall 42a_S2 that contacts the second side wall 21a1_S2 of the first side wall portion 21a1. The second portion 42b of the intervening portion 42 includes a first side wall 42b_S1 that contacts the first side wall 23_S1 of the second spacer 23, and a second side wall 42b_S2 that contacts the third side wall 21a2_S3 of the second side wall portion 21a2. The third side wall 21a1_S3 of the first side wall portion 21a1 contacts the first side wall 23_S1 of the second spacer 23.

[0063] The upper part 21b of the connected conductive pattern 21 includes a first side wall 21b_S1 that contacts the first portion 42a of the intervening portion 42 and a second side wall 21b_S2 that contacts the side wall MP_S of the mask pattern MP.

[0064] The second side wall 21b_S2 of the upper part 21b of the connected conductive pattern 21 and the first side wall 21a1_S1 of the first side wall portion 21a1 of the connected conductive pattern 21 are connected to each other and intersect each other. The angle between the second side wall 21b_S2 of the upper part 21b of the connected conductive pattern 21 and the upper surface of the substrate 10 is different from the angle between the first side wall 21a1_S1 of the first side wall portion 21a1 of the connected conductive pattern 21 and the upper surface of the substrate 10.

[0065] The first side wall 21b_S1 of the upper part 21b of the connected conductive pattern 21 and the second side wall 21a1_S2 of the first side wall portion 21a1 of the connected conductive pattern 21 are connected to each other and intersect each other. The angle between the first side wall 21b_S1 of the upper part 21b of the connected conductive pattern 21 and the upper surface of the substrate 10 is different from the angle between the second side wall 21a1_S2 of the first side wall portion 21a1 of the connected conductive pattern 21 and the upper surface of the substrate 10.

[0066] The side walls 31_S, part of the bottom surface 31_L, and part of the top surface 31_U of the channel pattern 31 are in contact with the source / drain pattern SD. The side walls 32_S, part of the bottom surface 32_L, and part of the top surface 32_U of the upper channel pattern 32 are in contact with the upper source / drain pattern USD.

[0067] In this embodiment, the semiconductor device includes a connecting conductive pattern 21, which ensures that the portion electrically connecting the gate patterns (GE1, GE2) has a relatively constant width. Therefore, the uniformity of the critical voltage of the cell transistor can be improved.

[0068] In this embodiment, the semiconductor device includes a connected conductive pattern 21, resulting in a relatively small distance in the first direction D1 between the channel pattern 31 and the intervening portion 42 of the cover insulating film 40. For example, the distance in the first direction D1 between the channel pattern 31 and the intervening portion 42 of the cover insulating film 40 is 5.5 nm or less. Therefore, the size of the semiconductor device can be minimized.

[0069] Figures 2, 3A, 3B, 4A, 4B, 5, 6A, 6B, 6C, 7A, 7B, 7C, 7D, 8A, 8B, 8C, 9A, 9B, 9C, 10A, 10B, 10C, 11A, 11B, 12A, 12B, 12C, 13A, 13B, 13C, 14A, 14B, 14C, and 14D are diagrams illustrating the method for manufacturing a semiconductor device according to Figures 1A to 1H.

[0070] Referring to Figure 2, a substrate 10 is provided. An insulating film 111 is provided on the substrate 10. The insulating film 111 contains an insulating material.

[0071] A preliminary channel film 131 and a sacrificial film 161 are formed on the insulating film 111. The preliminary channel film 131 and the sacrificial film 161 are stacked alternately on each other in a third direction D3. The preliminary channel film 131 contains a semiconductor material. For example, the preliminary channel film 131 contains a two-dimensional semiconductor material. The sacrificial film 161 contains an insulating material. For example, the first sacrificial film 161 contains an oxide.

[0072] In one embodiment, the preliminary channel film 131 is deposited on a sacrificial film 161. In one embodiment, the preliminary channel film 131 is deposited on a deposition substrate and transferred onto the sacrificial film 161 on the deposition substrate. In one embodiment, the preliminary channel film 131 can be grown on the sacrificial film 161.

[0073] An interlayer insulating film 143 is formed on the sacrificial film 161. The interlayer insulating film 143 contains an insulating material.

[0074] A preliminary upper channel film 132 and a sacrificial film 161 are formed on the interlayer insulating film 143. The preliminary upper channel film 132 and the sacrificial film 161 are stacked alternately on each other in the third direction D3. The preliminary upper channel film 132 contains a semiconductor material. As an example, the preliminary upper channel film 132 contains a two-dimensional semiconductor material.

[0075] In one embodiment, the preliminary upper channel film 132 is deposited on the sacrificial film 161. In one embodiment, the preliminary upper channel film 132 is deposited on a deposition substrate and transferred to the sacrificial film 161 on the deposition substrate. In one embodiment, the preliminary upper channel film 132 can be grown on the sacrificial film 161.

[0076] A mask film ML (referred to as MP: mask pattern in Figure 6 and later) is formed on the sacrificial film 161. The mask film ML contains an insulating material.

[0077] Referring to Figures 3A and 3B, the mask film ML, sacrificial film 161, preliminary upper channel film 132, interlayer insulating film 143, preliminary channel film 131, and insulating film 111 are patterned. Each of the mask film ML, sacrificial film 161, preliminary upper channel film 132, interlayer insulating film 143, preliminary channel film 131, and insulating film 111 is separated into multiple parts by patterning.

[0078] A liner 162 is formed. Forming the liner 162 includes forming the liner 162 on the mask film ML, sacrificial film 161, preliminary upper channel film 132, interlayer insulating film 143, preliminary channel film 131, and insulating film 111, and removing the upper part of the liner 162 to separate the liner 162 into multiple liners 162. The liner 162 contains an insulating material.

[0079] Referring to Figures 4A and 4B, a gate sacrificial film 163 is formed on the liner 162 and the mask film ML. A gate mask film 164 is formed on the gate sacrificial film 163. The gate sacrificial film 163 contains, for example, polysilicon. The gate mask film 164 contains an insulating material.

[0080] Referring to Figure 5, the gate sacrificial film 163 and the gate mask film 164 are patterned. The gate sacrificial film 163 is patterned and separated into multiple gate sacrificial patterns 165. The gate mask film 164 is patterned and separated into multiple gate mask patterns 166.

[0081] A preliminary spacer film 123 is formed on the mask film ML, the gate sacrificial pattern 165, and the gate mask pattern 166. The preliminary spacer film 123 contains an insulating material.

[0082] Referring to Figures 6A, 6B, and 6C, the mask film ML, sacrificial film 161, preliminary upper channel film 132, interlayer insulating film 143, preliminary channel film 131, and insulating film 111 are patterned. Patterning the mask film ML, sacrificial film 161, preliminary upper channel film 132, interlayer insulating film 143, preliminary channel film 131, and insulating film 111 includes performing an etching process using the gate mask pattern 166 and preliminary spacer film 123 as etching masks. In the etching process using the gate mask pattern 166 and preliminary spacer film 123 as etching masks, the preliminary spacer film 123 is separated into a plurality of second spacers 23.

[0083] The mask film ML is patterned and separated into multiple mask patterns MP. The sacrificial film 161 is patterned and separated into multiple sacrificial patterns 171. The preliminary upper channel film 132 is patterned and separated into multiple upper channel patterns 32. The interlayer insulating film 143 is patterned and separated into multiple first interlayer insulating patterns 43. The preliminary channel film 131 is patterned and separated into multiple channel patterns 31. The insulating film 111 is patterned and separated into multiple insulating patterns 11.

[0084] The sacrificial pattern 171 is selectively etched through its sidewalls. The sacrificial pattern 171 is selectively etched so that its width in the second direction D2 becomes smaller than the width of the channel pattern 31 in the second direction D2 and the width of the upper channel pattern 32 in the second direction D2.

[0085] An inner spacer IS is formed. The inner spacer IS is formed on the sacrificial pattern 171.

[0086] A source / drain pattern SD is formed. In one embodiment, the source / drain pattern SD is formed through an epitaxial growth process using a channel pattern 31 as a seed.

[0087] A second interlayer insulation pattern 44 is formed. The second interlayer insulation pattern 44 is formed on the source / drain pattern SD.

[0088] An upper source / drain pattern USD is formed. In one embodiment, the upper source / drain pattern USD is formed through an epitaxial growth process using the upper channel pattern 32 as a seed.

[0089] A first spacer 22 is formed. The first spacer 22 is formed on the source / drain pattern SD and the upper source / drain pattern USD.

[0090] A filling insulating film 53 is formed on the first spacer 22.

[0091] Referring to Figures 7A, 7B, 7C, and 7D, the gate mask pattern 166 is removed. With the gate mask pattern 166 removed, the gate sacrificial pattern 165 is exposed. A capping film 172 is formed on the filling insulating film 53. The capping film 172 contains an insulating material.

[0092] Referring to Figures 8A, 8B, and 8C, the gate sacrificial pattern 165 is removed. The sacrificial pattern 171 is removed. In the process of removing the sacrificial pattern 171, the liner 162 is etched to form the intervening pattern 12.

[0093] Referring to Figures 9A, 9B, and 9C, a preliminary gate insulating film pGI is formed. The preliminary gate insulating film pGI contains an insulating material.

[0094] A preliminary gate film pGE1 and a preliminary upper gate film pGE2 are formed. The preliminary gate film pGE1 and the preliminary upper gate film pGE2 contain a conductive material.

[0095] The preliminary gate insulating film pGI, preliminary gate film pGE1, and preliminary upper gate film pGE2 fill the empty space formed by the removal of the sacrificial pattern 171.

[0096] Referring to Figures 10A, 10B, and 10C, the preliminary upper gate film pGE2 is etched. The preliminary upper gate film pGE2 is etched, exposing the preliminary gate insulating film pGI located at the top of the preliminary gate insulating film pGI.

[0097] Referring to Figures 11A and 11B, the mask pattern MP is used as an etching mask to etch the preliminary upper gate film pGE2 and the preliminary gate film pGE1. The preliminary upper gate film pGE2 is etched and separated into the upper gate pattern GE2. The preliminary gate film pGE1 is etched and separated into the gate pattern GE1.

[0098] The shape of the mask pattern MP changes during the etching process of the preliminary upper gate film pGE2 and preliminary gate film pGE1.

[0099] Referring to Figures 12A and 12B, a pre-connecting conductive film 121 is formed. The pre-connecting conductive film 121 is formed on the gate pattern GE1, the upper gate pattern GE2, the mask pattern MP, and the second spacer 23. The pre-connecting conductive film 121 is in contact with the side walls of the gate pattern GE1, the upper gate pattern GE2, the mask pattern MP, and the second spacer 23, as well as the upper surface of the mask pattern MP.

[0100] The pre-linking conductive film 121 is formed, for example, through a vapor deposition process. The pre-linking conductive film 121 contains a conductive material. As an example, the pre-linking conductive film 121 contains a two-dimensional conductive material.

[0101] Referring to Figures 13A and 13B, a linked conductive pattern 21 is formed. In one embodiment, forming the linked conductive pattern 21 includes performing a first etching step to etch the portion of the pre-linked conductive film 121 that is in contact with the upper surface of the mask pattern MP and the portion that is in contact with the upper surface of the substrate 10, and performing a second etching step to etch the portion of the pre-linked conductive film 121 that is in contact with the side wall of the second spacer 23.

[0102] The first etching step forms a single connecting conductive pattern 21 between two channel patterns 31 adjacent to each other in the first direction D1. The second etching step separates the single connecting conductive pattern 21 between the two channel patterns 31 adjacent to each other in the first direction D1 into two connecting conductive patterns 21. The second etching step forms the second sidewall portion 21a2 (see Figure 1F) of the connecting conductive pattern 21.

[0103] Referring to Figures 14A, 14B, 14C, and 14D, a cover insulating film 40 is formed. The intervening portion 42 of the cover insulating film 40 is formed between the connecting conductive patterns 21. The upper part 41 of the cover insulating film 40 is formed on the upper surface of the mask pattern MP.

[0104] After forming the cover insulating film 40, a step is performed to flatten the cover insulating film 40. For example, the cover insulating film 40 is flattened by a chemical mechanical polishing step. The flattening step of the cover insulating film 40 removes the upper part of the filling insulating film 53, the upper part of the third portion 22c of the first spacer 22, and the upper part of the second spacer 23.

[0105] Referring to Figures 1A to 1E, the active contacts (AC1, AC2), gate contact GC, and lower active contact LAC are formed.

[0106] The semiconductor device manufacturing method according to this embodiment simplifies the semiconductor device manufacturing method by using a self-alignment etching process that utilizes a mask pattern MP to etch the preliminary gate film pGE1 and the preliminary upper gate film pGE2, thereby eliminating the step of cutting the preliminary gate film pGE1 and the preliminary upper gate film pGE2.

[0107] Figures 15A, 15B, and 15C are cross-sectional views of a semiconductor device according to one embodiment. The semiconductor device shown in Figures 15A, 15B, and 15C is similar to the semiconductor device shown in Figures 1A to 1H, except as described below.

[0108] Referring to Figures 15A, 15B, and 15C, the semiconductor device includes a gate pattern GEa superimposed in a third direction D3 on the insulating pattern 11, a gate insulating film GIa, a channel pattern 231, and a mask pattern MPa.

[0109] An insulating pattern 11 superimposed in a third direction D3, a gate pattern GEa, a gate insulating film GIa, a channel pattern 231, and connected conductive patterns 221 separated from each other in a first direction D1 via a mask pattern MPa are provided.

[0110] A cover insulating film 240 is provided on the connecting conductive pattern 221 and the mask pattern MP. A first spacer 222 is provided on the source / drain pattern SD and a second spacer 223 is provided on the mask pattern MP. The active contact ACa is in contact with the source / drain pattern SD. A filling insulating film 253 is provided on the first spacer 222.

[0111] A first separation insulating film 251 and a second separation insulating film 252 are provided. The active contact ACa is positioned between the first separation insulating films 251 or between the first separation insulating film 251 and the second separation insulating film 252.

[0112] Figures 16A and 16B are enlarged cross-sectional views of a semiconductor device according to one embodiment. The semiconductor device shown in Figures 16A and 16B is similar to the semiconductor device shown in Figures 1A to 1H, except as described below.

[0113] Referring to Figures 16A and 16B, the gate insulating film GIb includes a first film 311 and a second film 312. The first film 311 is in contact with the gate pattern GE1b or the upper gate pattern GE2b. The second film 312 is in contact with the channel pattern 31 or the upper channel pattern 32. The second film 312 and the first film 311 contain different insulating materials. The first film 311 is a high-dielectric film with a higher dielectric constant than the second film 312.

[0114] The gate pattern GE1b includes a first conductive film 321 and a second conductive film 322 surrounding the first conductive film 321. The first conductive film 321 and the second conductive film 322 have different work functions.

[0115] The upper gate pattern GE2b includes a third conductive film 331 and a fourth conductive film 332 surrounding the third conductive film 331. The third conductive film 331 and the fourth conductive film 332 have different work functions.

[0116] Figure 17 is an enlarged cross-sectional view of a semiconductor device according to one embodiment. The semiconductor device shown in Figure 17 is similar to the semiconductor devices shown in Figures 1A to 1H, except as described below.

[0117] Referring to Figure 17, the first spacer 422 on the source / drain pattern SDc, the upper source / drain pattern USDc, and the second interlayer insulation pattern 444 includes a first portion 422b provided between two source / drain patterns SDc adjacent to each other in the first direction D1 and between two upper source / drain patterns USDc adjacent to each other in the first direction D1.

[0118] The first portion 422b of the first spacer 422 includes a first side portion P1, a second side portion P2, and a connecting portion P3. The first side portion P1 and the second side portion P2 are separated from each other in a first direction D1. The first side portion P1 and the second side portion P2 are connected by the connecting portion P3. Each of the first side portion P1 and the second side portion P2 is in contact with the source / drain pattern SDc and the upper source / drain pattern USDc.

[0119] A portion of the filling insulating film 453 is provided on the connecting portion P3 between the first side portion P1 and the second side portion P2. The first separating insulating film 451 is provided on the filling insulating film 453 between the first side portion P1 and the second side portion P2. The second separating insulating film 452 is provided between the first side portion P1 and the second side portion P2.

[0120] Although embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the embodiments described above, and can be modified and implemented in various ways without departing from the technical spirit of the present invention. [Explanation of Symbols]

[0121] 10 circuit boards 11 Insulation Patterns 12 Intervention Patterns 21, 221 Linked conductive patterns 21_1, 21_2, 21_3, 21_4 First to fourth linked conductive patterns 21_L, 31_L, 32_L bottom surface 21_U, 31_U, 32_U Top surface 21a Lower part 21b, 41 top 21a1, 21a2 1st and 2nd side wall parts 21a1_S1, 21a2_S1, 21b_S1, 22_S1, 23_S1, 42a_S1, 42b_S1 1st side wall 21a1_S2, 21a2_S2, 21b_S2, 22_S2, 23_S2, 42a_S2, 42b_S2 2nd side wall 21a1_S3, 21a2_S3 3rd side wall 22, 222, 422 First Spacer 23, 223 Second Spacer 22a, 42a, 422b Part 1 22b, 42b 2nd part 22c Part 3 31, 231 Channel Pattern 31_1, 31_2, 31_3, 31_4 Channel 1-4 Patterns 31_S, 32_S side wall 32 Upper channel pattern 40, 240 Cover insulating film 42 Interposition part 43. First layer insulation pattern 44, 444 Second layer insulation pattern 51, 251, 451 First Separation Insulating Film 52, 252, 452 Second Separation Insulating Film 53, 253, 453 Filling Insulating Film 111 Insulating Film 121 Pre-connecting conductive film 123 Spare spacer membrane 131 Spare channel membrane 132 Spare upper channel membrane 143 Interlayer insulating film 161 Sacrificial membrane 162 Liner 163 Gate sacrificial film 164 Gate mask film 165 Gate Sacrifice Pattern 166 Gate Mask Patterns 171 Sacrifice Patterns 172 Capping film 311, 312 1st, 2nd membrane 321, 322, 331, 332 Conductive films 1st to 4th AC1, AC2 First and Second Active Contacts A Ca Activated Contact Lenses GC gate contact GE1, GE1b, GEa gate patterns GE1_1, GE1_2 First and Second Gate Patterns GE1_S, GE2_S, GI_S, MP_S side wall GE2, GE2b Upper Gate Pattern GI, GIa, GIb gates of an waveguide. IS Inner Spacer LAC Lower Active Contact ML mask film (MP: Mask pattern) MP, MPa mask pattern MP1, MP2 First and Second Mask Patterns P1, P2 First and second side sections P3 connection part pGI Pre-gate Insulator pGE1 Pre-gate film pGE2 Pre-emptive Upper Gate Membrane SD, SDc Source / Drain Pattern SD1, SD2 First and Second Source / Drain Patterns USD, USDc Top Source / Drain Pattern

Claims

1. The first channel pattern and the second channel pattern superimposed on each other, A first gate pattern is positioned between the first channel pattern and the second channel pattern and superimposed on the first channel pattern and the second channel pattern, A first connected conductive pattern and a second connected conductive pattern that are separated from each other in a first direction via the first channel pattern, the second channel pattern, and the first gate pattern, The system comprises a first channel pattern and a first source / drain pattern connected to the second channel pattern, A semiconductor device characterized in that the first connected conductive pattern and the second connected conductive pattern are electrically connected to the first gate pattern.

2. The semiconductor device according to claim 1, characterized in that the first connected conductive pattern and the second connected conductive pattern include a two-dimensional conductive material.

3. The semiconductor device according to claim 1, characterized in that the first channel pattern and the second channel pattern include a two-dimensional semiconductor material.

4. A third channel pattern separated from the first channel pattern in the first direction, A fourth channel pattern separated from the second channel pattern in the first direction, A second gate pattern is positioned between the third channel pattern and the fourth channel pattern and is separated from the first gate pattern in a first direction, A third channel pattern, a fourth channel pattern, and a third and fourth connected conductive patterns separated from each other in a first direction via the second gate pattern, The system further includes a second source / drain pattern connected to the third channel pattern and the fourth channel pattern, The semiconductor device according to claim 1, characterized in that the third connected conductive pattern and the fourth connected conductive pattern are electrically connected to the second gate pattern.

5. The first to fourth connected conductive patterns further include a cover insulating film on the first connected conductive pattern to the fourth connected conductive pattern, The semiconductor device according to claim 4, characterized in that the cover insulating film includes an intervening portion between the second connecting conductive pattern and the third connecting conductive pattern.

6. The second connected conductive pattern is The first side wall portion in contact with the first gate pattern, Including a second side wall portion connected to the first side wall portion, The semiconductor device according to claim 5, characterized in that the second sidewalls are spaced apart from each other in a second direction intersecting the first direction.

7. The intervening portion is, The first portion of the first side wall and the first side wall of the second side wall, The second portion of the second side wall, each in contact with the second side wall, The first portion of the intervening part is positioned between the second portion of the intervening part. The semiconductor device according to claim 6, characterized in that the width of the first portion of the intervening portion in the first direction is greater than the width of each of the second portions of the intervening portion in the first direction.

8. The first source / drain pattern and the second source / drain pattern are superimposed on a first spacer, The first spacer is, The first portion between the first source / drain pattern and the second source / drain pattern, The second part of the first part mentioned above, A third portion that intersects the first direction on the second portion and is separated from each other in a second direction, The semiconductor device according to claim 4, characterized in that the width of the first portion of the first spacer in the first direction is the same as the distance in the first direction between the first source / drain pattern and the second source / drain pattern.

9. The first channel pattern and the second channel pattern superimposed on each other, A first gate pattern is positioned between the first channel pattern and the second channel pattern and superimposed on the first channel pattern and the second channel pattern, A first connecting conductive pattern, which is separated from the first channel pattern and the second channel pattern and electrically connected to the first gate pattern, The system comprises a source / drain pattern connected to the first channel pattern and the second channel pattern, A semiconductor device characterized in that the first channel pattern, the second channel pattern, and the first gate pattern are arranged between the upper and lower surfaces of the first connected conductive pattern.

10. The semiconductor device according to claim 9, characterized in that the first connected conductive pattern contains a conductive material different from the first gate pattern.

Images