Semiconductor equipment

Abstract

The present invention provides a semiconductor device that includes a high-electron-mobility transistor with improved reliability. [Solution] The semiconductor device includes a channel layer 132, a barrier layer 136, a gate electrode layer 155, a gate semiconductor layer 152 located between the barrier layer and the gate electrode layer, a source electrode 173 and a drain electrode 175 located away from the gate electrode layer in the D2 direction, a field dispersion layer 177 located on the gate electrode layer, connected to the source electrode, and overlapping the gate electrode layer in the D3 direction, and a source wiring layer 178TM located on the field dispersion layer, connected to the source electrode, and overlapping the gate electrode layer in the D3 direction, wherein the length from any one point in the source wiring layer overlapping the gate electrode in the D3 direction to one end of the source wiring layer in the D2 direction away from the source electrode is smaller than the length from any one point in the field dispersion layer overlapping the gate electrode in the third direction to one end of the field dispersion layer in the D2 direction away from the source electrode.

Description

[Technical Field]

[0001] This invention relates to a semiconductor device. [Background technology]

[0002] In modern society, semiconductor devices are closely related to daily life. In particular, the importance of power semiconductor devices, used in various fields such as transportation (electric vehicles, railways, electric trams), renewable energy systems (solar and wind power), and mobile devices, is steadily increasing. Power semiconductor devices are semiconductor devices used to handle high voltages and high currents, performing functions such as power conversion and control in large power systems and high-power electronic devices. Power semiconductor devices possess the ability and durability to handle high power, can handle large amounts of current, and can withstand high voltages. For example, power semiconductor devices can handle voltages from several hundred to several thousand volts and currents from tens to several thousand amperes. Power semiconductor devices can minimize power loss and improve the efficiency of electrical energy. Furthermore, power semiconductor devices can operate stably even in environments with high temperatures.

[0003] Such power semiconductor devices can be classified by material, for example, into SiC power semiconductor devices and GaN power semiconductor devices. By using SiC or GaN instead of existing silicon (Si) to manufacture power semiconductor devices, the disadvantages of silicon, which has unstable properties at high temperatures, can be overcome. SiC power semiconductor devices are resistant to high temperatures and have low power loss, making them suitable for electric vehicles and renewable energy systems. GaN power semiconductor devices require a higher cost but are efficient in terms of speed, making them suitable for high-speed charging of mobile devices, etc. [Overview of the project] [Problems that the invention aims to solve]

[0004] The present invention has been made in view of the above-mentioned prior art, and the object of the present invention is to provide a semiconductor device that can reduce the electric field peak of the channel layer, efficiently disperse the electric field of the channel layer to flatten the profile, and prevent voltage drop due to wiring resistance by increasing the area of ​​the semiconductor device. [Means for solving the problem]

[0005] A semiconductor device according to one aspect of the present invention, made to achieve the above objective, includes a channel layer, a barrier layer located on the channel layer and containing a material having a different energy band gap from the channel layer, a gate electrode layer located on the barrier layer and extending in a first direction, a gate semiconductor layer located between the barrier layer and the gate electrode layer, a source electrode and a drain electrode connected to the channel layer and located away from the gate electrode layer in a second direction different from the first direction, a field dispersion layer located on the gate electrode layer and connected to the source electrode and overlapping the gate electrode layer in a third direction different from the first and second directions, and a source wiring layer located on the field dispersion layer and connected to the source electrode and overlapping the gate electrode layer in a third direction, wherein the length from any one point in the gate electrode layer and the source wiring layer overlapping in the third direction to one end of the source wiring layer in a second direction away from the source electrode is smaller than the length from any one point in the gate electrode layer and the field dispersion layer overlapping in the third direction to one end of the field dispersion layer in a second direction away from the source electrode.

[0006] A semiconductor device according to another aspect of the present invention made to achieve the above objectives includes a channel layer, a barrier layer located on the channel layer and containing a material having a different energy band gap from the channel layer, a gate electrode layer located on the barrier layer and extending in a first direction, a gate semiconductor layer located between the barrier layer and the gate electrode layer, a source electrode and a drain electrode connected to the channel layer and located away from the gate electrode layer in a second direction different from the first direction, a field dispersion layer located on the gate electrode layer and connected to the source electrode and overlapping the gate electrode layer in a third direction different from the first and second directions, and a source wiring layer located on the gate electrode layer and connected to the source electrode and overlapping the field dispersion layer in a third direction, wherein the length from any one point in the gate electrode layer and the source wiring layer overlapping in the third direction to one end of the source wiring layer in a second direction away from the source electrode is smaller than the length from any one point in the gate electrode layer and the field dispersion layer overlapping in the third direction to one end of the field dispersion layer in a second direction away from the source electrode, and the thickness of the source wiring layer in the third direction is greater than the thickness of the field dispersion layer in the third direction.

[0007] A semiconductor device according to yet another aspect of the present invention, made to achieve the above objective, includes a channel layer; a barrier layer located on the channel layer and containing a material having a different energy band gap from the channel layer; a gate electrode layer located on the barrier layer and extending in a first direction; a gate semiconductor layer located between the barrier layer and the gate electrode layer; a source electrode and a drain electrode connected to the channel layer and located away from the gate electrode layer in a second direction different from the first direction; a field dispersion layer located on the gate electrode layer and connected to the source electrode, overlapping the gate electrode layer in a third direction different from the first and second directions; and a source wiring layer located on the field dispersion layer and connected to the source electrode, overlapping the gate electrode layer in a third direction, wherein one end of the source wiring layer in the second direction away from the source electrode overlaps with the field dispersion layer in the third direction, and the field dispersion layer is located between one end of the source wiring layer and the barrier layer in the third direction. [Effects of the Invention]

[0008] The semiconductor device according to the present invention reduces the electric field peak of the channel layer and efficiently disperses the electric field of the channel layer to flatten the profile, while also preventing voltage drop due to wiring resistance as the area of ​​the semiconductor device increases. [Brief explanation of the drawing]

[0009] [Figure 1] This is a plan view showing a semiconductor device according to one embodiment. [Figure 2] This is a plan view showing a semiconductor device according to one embodiment. [Figure 3] This is a plan view showing a semiconductor device according to one embodiment. [Figure 4] This is a plan view showing a semiconductor device according to one embodiment. [Figure 5] This is a cross-sectional view taken along the line A-A' in Figure 4. [Figure 6] This is a cross-sectional view taken along the line B-B' in Figure 4. [Figure 7] Figure 5 corresponds to a cross-sectional view illustrating another embodiment. [Figure 8] Figure 5 corresponds to a cross-sectional view illustrating another embodiment. [Figure 9] Figure 8 corresponds to a cross-sectional view illustrating another embodiment. [Figure 10] This is a plan view showing a semiconductor device according to one embodiment. [Figure 11] This is a cross-sectional view taken along the line A-A' in Figure 10. [Modes for carrying out the invention]

[0010] Hereinafter, various embodiments of the present invention will be described in detail with reference to the drawings, so that those with ordinary skill in the art to which the present invention pertains can easily implement them. The present invention can be implemented in a variety of different forms and is not limited to the embodiments described herein.

[0011] To clearly explain the present invention, parts not related to the explanation are omitted, and the same reference numerals are used for the same or similar components throughout the specification.

[0012] In addition, the sizes and thicknesses of the respective components shown in the drawings are arbitrarily shown for convenience of explanation, and the present invention is not necessarily limited to what is shown in the drawings. In the drawings, the thickness is enlarged to clearly represent various layers and regions. And, in the drawings, for convenience of explanation, the thicknesses of some layers and regions are exaggeratedly shown.

[0013] Also, when a part such as a layer, film, region, plate, etc. is “on” another part, this includes not only the case where it is “directly on” the other part, but also the case where there are other parts in between. Conversely, when a part is “directly on” another part, it means that there are no other parts in between. Also, “on” a reference part means that it is located above or below the reference part, and does not necessarily mean that it is located “upward” in the direction opposite to gravity.

[0014] Also, throughout the specification, when a part “includes” a certain component, this means that, unless otherwise stated to the contrary, it does not exclude other components, but may further include other components.

[0015] Also, throughout the specification, when it is said “on a plane”, this means the case when the target part is viewed from above, and when it is said “in a cross-section”, this means the case when the cross-section obtained by vertically cutting the target part is viewed from the side.

[0016] Also, throughout the specification, two directions parallel to the upper surface of the substrate and intersecting each other are defined as the first direction D1 and the second direction D2, respectively, and the direction perpendicular to the upper surface of the substrate is described as the third direction D3. As an example, the first direction D1 and the second direction D2 are perpendicular to each other.

[0017] Figures 1 to 4 are plan views showing a semiconductor device according to one embodiment. Figure 5 is a cross-sectional view taken along the line A-A' in Figure 4. Figure 6 is a cross-sectional view taken along the line B-B' in Figure 4.

[0018] For clear understanding and simplified illustration, Figure 1 primarily shows the barrier layer 136, gate electrode layer 155, first source electrode 173M0, first drain electrode 175M0, and first field dispersion layer 177M0, as well as the gate connection portion 155c and gate contact hole CH1.

[0019] Figure 2 shows the barrier layer 136, gate electrode layer 155, first source electrode 173M0, first drain electrode 175M0, second drain electrode 175M1, first field dispersion layer 177M0, and second field dispersion layer 177M1, as well as the gate connection portion 155c, gate contact hole CH1, first via 179V0, gate via 179VG, gate lead line 193M1, and gate signal line 194M1.

[0020] Figure 3 shows the barrier layer 136, gate electrode layer 155, first source electrode 173M0, first drain electrode 175M0, third drain electrode 175M2, first field dispersion layer 177M0, and third field dispersion layer 177M2. It also shows the gate connection portion 155c, gate contact hole CH1, second via 179V1, and source signal line 191M2. The second drain electrode 175M1 and second field dispersion layer 177M1 are not shown.

[0021] Figure 4 shows the barrier layer 136, gate electrode layer 155, first source electrode 173M0, fourth source electrode 173TM, first drain electrode 175M0, third drain electrode 175M2, fourth drain electrode 175TM, first field dispersion layer 177M0, third field dispersion layer 177M2, and source wiring layer 178TM. It also shows the gate connection portion 155c, gate contact hole CH1, third via 179V2, gate signal line 194M1, source pad 191TM, drain pad 192TM, and gate pad 194TM. The second drain electrode 175M1 and second field dispersion layer 177M1 are not shown.

[0022] Referring to Figures 1 to 6, the semiconductor device includes a channel layer 132, a barrier layer 136 located on the channel layer 132, a gate electrode layer 155 located on the barrier layer 136, a gate semiconductor layer 152 located between the barrier layer 136 and the gate electrode layer 155, and a source electrode 173 and a drain electrode 175 located on both sides of the gate electrode layer 155 and connected to the channel layer 132.

[0023] The channel layer 132 is a layer that forms a channel between the source electrode 173 and the drain electrode 175, and a two-dimensional electron gas (2DEG) 134 is located inside the channel layer 132. The two-dimensional electron gas 134 is a charge transport model used in solid-state physics, and it refers to a group of electrons that can move freely in two dimensions (e.g., in the xy-plane direction) but cannot move in other one dimensions (e.g., in the z-direction), and are rigidly constrained within two dimensions. In other words, the two-dimensional electron gas 134 exists in a form like a two-dimensional piece of paper in three-dimensional space. Such a two-dimensional electron gas 134 mainly appears in semiconductor heterogeneous junction structures, and in a semiconductor device according to one embodiment, it is generated at the interface between the channel layer 132 and the barrier layer 136. For example, the two-dimensional electron gas 134 is generated in the part of the channel layer 132 that is closest to the barrier layer 136.

[0024] The channel layer 132 contains a nitride comprising a group III-V material, such as Al, Ga, In, B, or a combination thereof. The channel layer 132 consists of a single layer or multiple layers. As an example, the channel layer 132 may be Al x In y Ga 1-x-y The channel layer 132 includes N(0≦x≦1, 0≦y≦1, x+y≦1), and for example, the channel layer 132 includes AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or a combination thereof. The channel layer 132 is either a doped layer or an undoped layer. The thickness of the channel layer 132 is approximately several hundred nm or less.

[0025] The channel layer 132 is located on the substrate 110, and a seed layer 115 or a buffer layer 120 is located between the substrate 110 and the channel layer 132. The substrate 110, seed layer 115, or buffer layer 120 are necessary layers for forming the channel layer 132, and may be omitted in some cases. For example, when using a GaN substrate as the channel layer 132, at least one of the substrate 110, seed layer 115, or buffer layer 120 is omitted. Considering that GaN substrates are relatively expensive, a Si substrate 110 is used to grow the GaN-containing channel layer 132. In this case, since the lattice structure of Si and the lattice structure of GaN are different, it is not easy to grow the channel layer 132 directly on the substrate 110. For this reason, the seed layer 115 and buffer layer 120 are grown on the substrate 110 first, and then the channel layer 132 is grown on the buffer layer 120. Furthermore, at least one of the substrate 110, seed layer 115, or buffer layer 120 may be removed in the final structure of the semiconductor device after being used in the manufacturing process.

[0026] The substrate 110 contains a semiconductor material. For example, the substrate 110 may contain sapphire, Si, SiC, AlN, GaN, or a combination thereof. The substrate 110 may be an SOI (Silicon on Insulator) substrate. However, the material of the substrate 110 is not limited to this, and all commonly used substrates may be applied. In some cases, the substrate 110 may contain an insulating material. For example, various layers, including a channel layer 132, may be formed on a semiconductor substrate first, and then the semiconductor substrate may be removed and replaced with an insulating substrate.

[0027] The seed layer 115 is located on the substrate 110. The seed layer 115 is located directly on the substrate 110. However, it is not limited to this, and other predetermined layers may be located between the substrate 110 and the seed layer 115. The seed layer 115 is a layer that serves as a seed for growing the buffer layer 120, and consists of a crystal lattice structure that serves as a seed for the buffer layer 120. For example, the seed layer 115 contains AlN, but is not limited to this.

[0028] The buffer layer 120 is located on the seed layer 115. The buffer layer 120 is located directly on the seed layer 115. However, it is not limited to this, and a predetermined other layer may be located between the seed layer 115 and the buffer layer 120. The buffer layer 120 is located between the seed layer 115 and the channel layer 132. The buffer layer 120 contains a group III-V material, for example, a nitride containing Al, Ga, In, B, or a combination thereof. The buffer layer 120 contains Al x In y Ga 1-x-y N includes (0≦x≦1, 0≦y≦1, x+y≦1), and for example, the buffer layer 120 includes AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or a combination thereof. The buffer layer 120 consists of a single layer or multiple layers. For example, the buffer layer 120 includes a superlattice layer and a high-resistance layer.

[0029] The superlattice layer is for relaxing the difference in lattice constant and thermal expansion coefficient between the substrate 110 and the channel layer 132, thereby relaxing the tensile stress and compressive stress generated between the substrate 110 and the channel layer 132.

[0030] The high-resistance layer is located on the superlattice layer. For example, the high-resistance layer is directly located on the superlattice layer. However, it is not limited thereto, and other layers can also be further located between the superlattice layer and the high-resistance layer. The high-resistance layer is located between the superlattice layer and the channel layer 132. The high-resistance layer prevents the semiconductor element from deteriorating by preventing leakage current from flowing through the channel layer 132. The high-resistance layer is made of a material with low conductivity so that the space between the substrate 110 and the channel layer 132 is electrically insulated.

[0031] As an example, the high-resistance layer has a resistance value of 1.0X10 6 Ω·cm or more. For example, the resistance value of the high-resistance layer is 1.0X10 10 Ω·cm or more. As another example, the resistance value of the high-resistance layer is 1.0X10 12 Ω·cm or more. The resistance value can be measured by forming a measurement electrode in the high-resistance layer and flowing a current.

[0032] The high-resistance layer contains III-V group materials, for example, nitrides containing Al, Ga, In, B, or combinations thereof. The high-resistance layer 126 contains Al x In y Ga 1-x-y N (0≦x≦1, 0≦y≦1, x + y≦1), and for example, contains AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof. The high-resistance layer consists of a single layer or multiple layers.

[0033] The barrier layer 136 is located on the channel layer 132. The barrier layer 136 is located directly on the channel layer 132. However, it is not limited to this, and other predetermined layers may be located between the channel layer 132 and the barrier layer 136. The region of the channel layer 132 that overlaps with the barrier layer 136 becomes the drift region DTR. The drift region DTR is located between the source electrode 173 and the drain electrode 175. When a potential difference occurs between the source electrode 173 and the drain electrode 175, carriers move in the drift region DTR. The semiconductor device is turned on / off depending on whether a voltage is applied to the gate electrode layer 155 and the magnitude of the voltage applied to the gate electrode layer 155. When a voltage greater than or equal to the threshold voltage is applied to the gate electrode layer 155 and the semiconductor device is turned on, a channel is created in the depletion region DPR. This causes carrier movement in the drift region DTR. If a voltage lower than the threshold voltage is applied to the gate electrode layer 155, or if no voltage is applied, the channel path is blocked in the depletion region DPR, and carrier movement does not occur.

[0034] The barrier layer 136 contains a group III-V material, for example, a nitride containing Al, Ga, In, B, or a combination thereof. x In y Ga 1-x-y N(0≦x≦1, 0≦y≦1, x+y≦1) is included, and for example, the barrier layer 136 includes GaN, InN, AlGaN, AlInN, InGaN, AlN, AlInGaN, or a combination thereof. The energy band gap of the barrier layer 136 is adjusted by the composition ratio of Al or In.

[0035] The barrier layer 136 contains a semiconductor material having different properties from the channel layer 132. The barrier layer 136 differs from the channel layer 132 in at least one of the following: polarization characteristics, energy band gap, and lattice constant. For example, the barrier layer 136 contains a material having a different energy band gap than the channel layer 132. In this case, the barrier layer 136 has a higher energy band gap and a higher electrical polarizability than the channel layer 132. Such a barrier layer 136 induces a two-dimensional electron gas 134 in the channel layer 132, which has a relatively lower electrical polarizability. In this respect, the barrier layer 136 is called a channel supply layer or a two-dimensional electron gas supply layer. The two-dimensional electron gas 134 is formed in a portion of the channel layer 132 located below the interface between the channel layer 132 and the barrier layer 136. The two-dimensional electron gas 134 has very high electron mobility.

[0036] The gate electrode layer 155 is located on the barrier layer 136. The gate electrode layer 155 overlaps with a portion of the barrier layer 136 in the third direction D3. The gate electrode layer 155 overlaps with a portion of the drift region DTR of the channel layer 132 in the third direction D3. In the second direction D2, the gate electrode layer 155 is located between the source electrode 173 and the drain electrode 175. In the second direction D2, the gate electrode layer 155 is separated from the source electrode 173 and the drain electrode 175. The gate electrode layer 155 extends along the first direction D1 in a plane. That is, the gate electrode layer 155 has the shape of a bar that extends long along the first direction D1 in a plane.

[0037] The gate electrode layer 155 contains a conductive material. For example, the gate electrode layer 155 contains metals, metal alloys, conductive metal nitrides, metal silicides, doped semiconductor materials, conductive metal oxides, or conductive metal nitrogen oxides. For example, the gate electrode layer 155 contains titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbide nitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbide nitride ( The gate electrode layer 155 may, but is not limited to, a single layer or multiple layers, contain TaCN, tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof.

[0038] Although not shown in the figures, some embodiments further include a hard mask layer located on the gate electrode layer 155. The hard mask layer is a hard mask used when patterning the gate electrode material layer or gate semiconductor layer during the process of forming the gate electrode layer 155. However, the hard mask layer is removed by the etching conditions during etching of the gate electrode material layer or by the cleaning conditions after etching. As an example, the hard mask layer includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0039] The gate semiconductor layer 152 is located between the barrier layer 136 and the gate electrode layer 155. That is, the gate semiconductor layer 152 is located on the barrier layer 136, and the gate electrode layer 155 is located on the gate semiconductor layer 152. The gate electrode layer 155 makes Schottky contact with the gate semiconductor layer 152. However, it is not limited to this, and in some cases, the gate electrode layer 155 makes ohmic contact with the gate semiconductor layer 152. The gate semiconductor layer 152 overlaps with the gate electrode layer 155 in the third direction D3. The upper surface of the gate semiconductor layer 152 is entirely covered by the gate electrode layer 155.

[0040] The gate semiconductor layer 152 is located between the source electrode 173 and the drain electrode 175 in the second direction D2. The gate semiconductor layer 152 is separated from both the source electrode 173 and the drain electrode 175 in the second direction D2. The gate semiconductor layer 152 is located closer to the source electrode 173 than to the drain electrode 175. That is, the separation distance between the gate semiconductor layer 152 and the source electrode 173 is smaller than the separation distance between the gate semiconductor layer 152 and the drain electrode 175.

[0041] The gate semiconductor layer 152 comprises a nitride containing a group III-V material, such as Al, Ga, In, B, or a combination thereof. x In y Ga 1-x-yThe range N includes (0≦x≦1, 0≦y≦1, x+y≦1). For example, the gate semiconductor layer 152 includes AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or a combination thereof. The gate semiconductor layer 152 includes a material having a different energy band gap than the barrier layer 136. For example, the gate semiconductor layer 152 includes GaN, and the barrier layer 136 includes AlGaN. The gate semiconductor layer 152 is doped with a predetermined impurity. In this case, the impurity doped into the gate semiconductor layer 152 is a p-type dopant that provides holes. For example, the gate semiconductor layer 152 includes GaN doped with a p-type impurity. That is, the gate semiconductor layer 152 consists of a p-GaN layer. However, it is not limited to this, and the gate semiconductor layer 152 may be a p-AlGaN layer. The impurity doped into the gate semiconductor layer 152 may be magnesium (Mg). The gate semiconductor layer 152 consists of a single layer or multiple layers.

[0042] The gate semiconductor layer 152 forms a depletion region (DPR) within the channel layer 132. The depletion region (DPR) is located within the drift region (DTR) and has a narrower width than the drift region (DTR). Because the gate semiconductor layer 152, which has a different energy band gap than the barrier layer 136, is located on the barrier layer 136, the energy band levels in the portion of the barrier layer 136 that overlaps with the gate semiconductor layer 152 become higher. As a result, a depletion region (DPR) is formed in the region of the channel layer 132 that overlaps with the gate semiconductor layer 152. The depletion region (DPR) is a region in the channel path of the channel layer 132 where the two-dimensional electron gas 134 is not formed or has a lower electron concentration than the remaining region. In other words, the depletion region (DPR) means a region within the drift region (DTR) where the flow of the two-dimensional electron gas 134 is interrupted. When a depletion region (DPR) occurs, no current flows between the source electrode 173 and the drain electrode 175, and the channel path is blocked. As a result, the semiconductor device has normally-off characteristics.

[0043] In other words, the semiconductor device is a normally-off semiconductor device (HEMT, High Electron Mobility Transistor). In the normal state, when no voltage is applied to the gate electrode layer 155, a depletion region DPR exists, and the semiconductor device is in the off state. Although not shown in the diagram, when a voltage above the threshold voltage is applied to the gate electrode layer 155, the depletion region DPR disappears, and the two-dimensional electron gas 134 in the drift region DTR is continuously connected. That is, the two-dimensional electron gas 134 is formed throughout the entire channel path between the source electrode 173 and the drain electrode 175, and the semiconductor device becomes on. In summary, the semiconductor device includes semiconductor layers with different electrical polarization characteristics, and semiconductor layers with relatively high polarizability induce the formation of a two-dimensional electron gas 134 in other semiconductor layers joined to them. Such a two-dimensional electron gas 134 is used as a channel between the source electrode 173 and the drain electrode 175, and the continuation or interruption of the flow of such two-dimensional electron gas 134 is controlled by a bias voltage applied to the gate electrode layer 155. In the gate-off state, the flow of the two-dimensional electron gas 134 is interrupted, and no current flows between the source electrode 173 and the drain electrode 175. In the gate-on state, the flow of the two-dimensional electron gas 134 continues, causing current to flow between the source electrode 173 and the drain electrode 175.

[0044] The semiconductor device described above is a normally-off high electron mobility transistor, but is not limited to this. For example, the semiconductor device may be a normally-on high electron mobility transistor. In the case of a normally-on high electron mobility transistor, the gate semiconductor layer 152 is omitted, and as a result, the gate electrode layer 155 is located directly on the barrier layer 136. That is, the gate electrode layer 155 is in contact with the barrier layer 136. However, it is not limited to this, and a gate dielectric layer may be interposed between the gate electrode layer 155 and the barrier layer 136. In such a structure, the two-dimensional electron gas 134 when no voltage is applied to the gate electrode layer 155 is used as a channel, and a current flows between the source electrode 173 and the drain electrode 175. Also, when a negative voltage is applied to the gate electrode layer 155, a depletion region (DPR) occurs where the flow of the two-dimensional electron gas 134 below the gate electrode layer 155 is interrupted.

[0045] The buffer layer 120, channel layer 132, barrier layer 136, and gate semiconductor layer 152 described above are sequentially stacked on the substrate 110. In a semiconductor device, at least one of the buffer layer 120, channel layer 132, barrier layer 136, and gate semiconductor layer 152 may be omitted. Such buffer layer 120, channel layer 132, barrier layer 136, and gate semiconductor layer 152 are made of the same semiconductor material, but the material composition ratio of each layer differs considering the role of each layer and the performance required of the semiconductor device.

[0046] The semiconductor device further includes a first protective layer 156, a second protective layer 140, a third protective layer 150, a fourth protective layer 160, or a combination thereof, located on a barrier layer 136 and a gate electrode layer 155. As an example, the semiconductor device includes a first protective layer 156, a second protective layer 140 located on the first protective layer 156, a third protective layer 150 located on the second protective layer 140, and a fourth protective layer 160 located on the third protective layer 150.

[0047] The first protective layer 156 covers the upper surfaces of the barrier layer 136 and the gate electrode layer 155, and covers the side surfaces of the gate electrode layer 155 and the gate semiconductor layer 152. The lower surface of the first protective layer 156 is in contact with the barrier layer 136, the gate electrode layer 155, and the gate semiconductor layer 152. The upper surface of the first protective layer 156 is in contact with the second protective layer 140. The second to fourth protective layers 140, 150, and 160 are separated from the barrier layer 136, the gate electrode layer 155, and the gate semiconductor layer 152 by the first protective layer 156. Therefore, the second to fourth protective layers 140, 150, and 160 do not come into contact with the barrier layer 136, the gate electrode layer 155, and the gate semiconductor layer 152.

[0048] The barrier layer 136 or gate electrode layer 155, etc., are protected and isolated from other components by the first to fourth protective layers 156, 140, 150, and 160. The first to fourth protective layers 156, 140, 150, and 160 contain insulating materials. For example, the first to fourth protective layers 156, 140, 150, and 160 contain oxides such as SiO2 or Al2O3. As another example, the first to fourth protective layers 156, 140, 150, and 160 contain nitrides such as SiN or oxynitrides such as SiON. The first to fourth protective layers 156, 140, 150, and 160 may contain the same material or different materials. If the first to fourth protective layers 156, 140, 150, and 160 consist of the same material, the boundaries between the first to fourth protective layers 156, 140, 150, and 160 may not be visible. The first to fourth protective layers 156, 140, 150, and 160 each consist of a single layer or multiple layers.

[0049] The thickness T_140 of the second protective layer 140 in the third direction D3 is less than or equal to the thickness T_156 of the first protective layer 156 in the third direction D3. The thickness T_150 of the third protective layer 150 in the third direction D3 may be greater than the thickness T_156 of the first protective layer 156 in the third direction D3. The thickness T_160 of the fourth protective layer 160 in the third direction D3 may be greater than the thickness T_150 of the third protective layer 150 in the third direction D3.

[0050] Here, the thicknesses T_156, T_140, T_150, and T_160 of the first to fourth protective layers 156, 140, 150, and 160 in the third direction D3 are defined as the shortest length in the third direction D3 at a position that does not overlap with the first to third field dispersion layers 177M0, 177M1, and 177M2 in the third direction D3, while being located on the drift region DTR between the gate electrode layer 155 and the drain electrode 175.

[0051] The source electrode 173 and drain electrode 175 are located on the channel layer 132. The source electrode 173 and drain electrode 175 are separated from each other in a second direction D2, and the gate electrode layer 155 and gate semiconductor layer 152 are located between the source electrode 173 and drain electrode 175. The gate electrode layer 155 and gate semiconductor layer 152 are separated from the source electrode 173 and drain electrode 175 in a second direction D2. The source electrode 173 is electrically connected to the channel layer 132 on one side of the gate electrode layer 155. The drain electrode 175 is electrically connected to the channel layer 132 on the other side of the gate electrode layer 155. The source electrode 173 and drain electrode 175 are located outside the drift region DTR of the channel layer 132. The interface between the source electrode 173 and the channel layer 132 is one edge of the drift region DTR. Similarly, the interface between the drain electrode 175 and the channel layer 132 is the other edge of the drift region DTR. However, it is not limited to this, and the source electrode 173 and drain electrode 175 may not be located outside the drift region DTR of the channel layer 132. In this case, the channel layer 132 is not recessed, and the source electrode 173 and drain electrode 175 are located on the upper surface of the channel layer 132. The bottom surfaces of the source electrode 173 and drain electrode 175 are in contact with the upper surface of the channel layer 132. Also, the barrier layer 136 is not recessed, and the source electrode 173 and drain electrode 175 are located on the upper surface of the barrier layer 136. In other words, the bottom surfaces of the source electrode 173 and drain electrode 175 are in contact with the upper surface of the barrier layer 136. The portion of the channel layer 132 in contact with the source electrode 173 and drain electrode 175 is highly doped. In this process, carriers that have passed through the two-dimensional electron gas 134 are transferred to the source electrode 173 and drain electrode 175 by passing through the highly doped portion of the channel layer 132, i.e., the upper part of the two-dimensional electron gas 134. The source electrode 173 and drain electrode 175 do not directly contact the two-dimensional electron gas 134 in the horizontal direction. The horizontal direction refers to the direction parallel to the upper surface of the channel layer 132 or the barrier layer 136.

[0052] The source electrode 173 and the drain electrode 175 extend along a first direction D1 in a plane. That is, the source electrode 173 and the drain electrode 175 have the shape of long rods that extend along the first direction D1 in a plane. The source electrode 173 and the drain electrode 175 extend in directions parallel to each other. The source electrode 173 and the drain electrode 175 extend in a direction parallel to the gate electrode layer 155.

[0053] The source electrode 173 and drain electrode 175 contain a conductive material. For example, the source electrode 173 and drain electrode 175 contain metals, metal alloys, conductive metal nitrides, metal silicides, doped semiconductor materials, conductive metal oxides, or conductive metal nitrogen oxides. For example, the source electrode 173 and drain electrode 175 contain titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbide nitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbide nitride This may include, but is not limited to, alloys (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof. The source electrode 173 and drain electrode 175 consist of a single layer or multiple layers. The source electrode 173 and drain electrode 175 are in ohmic contact with the channel layer 132. The regions within the channel layer 132 that are in contact with the source electrode 173 and the drain electrode 175 are doped at a relatively higher concentration compared to other regions.

[0054] The source electrode 173 includes a first source electrode 173M0, a second source electrode (173M1 in Figure 8), a third source electrode (173M2 in Figure 8), a fourth source electrode (173TM in Figure 8), or a combination thereof. The second source electrode 173M1 is located on the first source electrode 173M0. The third source electrode 173M2 is located on the second source electrode 173M1. The fourth source electrode 173TM is located on the third source electrode 173M2. At least some of the first source electrode 173M0, the second source electrode 173M1, the third source electrode 173M2, or the fourth source electrode 173TM may be omitted. For example, in Figure 8, the source electrode 173 includes a first source electrode 173M0 and a fourth source electrode 173TM, the fourth source electrode 173TM is located on the first source electrode 173M0, and the second source electrode 173M1 and the third source electrode 173M2 are omitted.

[0055] The first source electrode 173M0 is in direct contact with the channel layer 132 and is electrically connected to the channel layer 132. The second source electrode 173M1, the third source electrode 173M2, and the fourth source electrode 173TM do not come into direct contact with the channel layer 132, but are electrically connected to the channel layer 132 via the first source electrode 173M0.

[0056] The drain electrode 175 includes a first drain electrode 175M0, a second drain electrode 175M1, a third drain electrode 175M2, and a fourth drain electrode 175TM. The second drain electrode 175M1 is located on the first drain electrode 175M0. The third drain electrode 175M2 is located on the second drain electrode 175M1. The fourth drain electrode 175TM is located on the third drain electrode 175M2. For example, in Figure 5, the first drain electrode 175M0, the second drain electrode 175M1, the third drain electrode 175M2, and the fourth drain electrode 175TM are sequentially stacked in the third direction D3. However, it is not limited to this, and at least some of the first drain electrode 175M0, the second drain electrode 175M1, the third drain electrode 175M2, or the fourth drain electrode 175TM may be omitted.

[0057] The first drain electrode 175M0 is in direct contact with the channel layer 132 and is electrically connected to the channel layer 132. The second drain electrode 175M1, the third drain electrode 175M2, and the fourth drain electrode 175TM do not come into direct contact with the channel layer 132, but are electrically connected to the channel layer 132 via the first drain electrode 175M0.

[0058] The upper surfaces of the first source electrode 173M0 and the first drain electrode 175M0 are located on the first protective layer 156. The upper surfaces of the first source electrode 173M0 and the first drain electrode 175M0 are located between the first protective layer 156 and the second protective layer 140. The first source electrode 173M0 and the first drain electrode 175M0 are positioned on both sides of the gate electrode layer 155, spaced apart from each other, with trenches penetrating the first protective layer 156 and the barrier layer 136 and recessing the upper surface of the channel layer 132. The first source electrode 173M0 and the first drain electrode 175M0 are located within the trenches located on both sides of the gate electrode layer 155, respectively. The first source electrode 173M0 and the first drain electrode 175M0 are formed to fill the trenches. Within the trenches, the first source electrode 173M0 and the first drain electrode 175M0 are in contact with the channel layer 132 and the barrier layer 136. The channel layer 132 forms the bottom and side walls of the trench, and the barrier layer 136 forms the side walls of the trench. Therefore, the first source electrode 173M0 and the first drain electrode 175M0 are in contact with the top and side surfaces of the channel layer 132. Also, the first source electrode 173M0 and the first drain electrode 175M0 are in contact with the side surfaces of the barrier layer 136. That is, the first source electrode 173M0 and the first drain electrode 175M0 cover the side surfaces of the channel layer 132 and the barrier layer 136. The top surfaces of the first source electrode 173M0 and the first drain electrode 175M0 protrude beyond the top surface of the first protective layer 156. Also, at least one of the first source electrode 173M0 and the first drain electrode 175M0 covers at least a portion of the top surface of the first protective layer 156. The second protective layer 140 is located on the first source electrode 173M0 and the first drain electrode 175M0. At least a portion of the first source electrode 173M0 and the first drain electrode 175M0 is covered by the second protective layer 140.

[0059] The semiconductor device further includes a first field dispersion layer 177M0 located on a first protective layer 156. The first field dispersion layer 177M0 is located between the source electrode 173 and the drain electrode 175. The gate electrode layer 155 is covered by the first field dispersion layer 177M0. The first field dispersion layer 177M0 is electrically coupled to the source electrode 173. For example, on any one cross-section cut perpendicular to a first direction D1 (e.g., Figure 5), the first field dispersion layer 177M0 is coupled to the first source electrode 173M0. Thus, the first field dispersion layer 177M0 is not coupled to the source electrode 173 and is not a floating field dispersion layer separated from the source electrode 173 in a second direction D2. However, on other cross-sections cut perpendicular to the first direction D1 (for example, Figure 9), there are portions where the first field dispersion layer 177M0 is not connected to the source electrode 173, and the first field dispersion layer 177M0 is separated from the first source electrode 173M0 in the second direction D2. However, even in this case, the first field dispersion layer 177M0 on other cross-sections cut perpendicular to the first direction D1 is connected to the source electrode 173.

[0060] The first field dispersion layer 177M0 contains the same material as the first source electrode 173M0 and is located in the same layer as the first source electrode 173M0. For example, the first field dispersion layer 177M0 is formed simultaneously with the first source electrode 173M0 using the same process. In this case, the boundary between the first field dispersion layer 177M0 and the first source electrode 173M0 is not clear, and the first field dispersion layer 177M0 is formed integrally with the first source electrode 173M0. However, it is not limited to this, and the first field dispersion layer 177M0 may be a separate component separated from the first source electrode 173M0. Also, the first field dispersion layer 177M0 may be located in a different layer from the first source electrode 173M0 and may be formed using a different process.

[0061] In some embodiments, the first field dispersion layer 177M0 is electrically connected to the gate electrode layer 155. For example, an opening is formed in the first protective layer 156 that overlaps with the gate electrode layer 155, and the first field dispersion layer 177M0 is connected to the gate electrode layer 155 through the opening. In this case, the first field dispersion layer 177M0 is not connected to the source electrode 173.

[0062] The semiconductor device further includes a second field dispersion layer 177M1 located on the second protective layer 140. The second field dispersion layer 177M1, together with the first field dispersion layer 177M0, constitutes a field dispersion layer. The second field dispersion layer 177M1 is located between the source electrode 173 and the drain electrode 175. The second field dispersion layer 177M1 overlaps the gate electrode layer 155 in the third direction D3. The second field dispersion layer 177M1 overlaps the first field dispersion layer 177M0 in the third direction D3. The gate electrode layer 155 and the first field dispersion layer 177M0 are covered by the second field dispersion layer 177M1. The second field dispersion layer 177M1 is wider than the width of the first field dispersion layer 177M0. The second field dispersion layer 177M1 completely covers the first field dispersion layer 177M0. However, this is not limited to the above, and the width, positional relationship, etc., of the first field dispersion layer 177M0 and the second field dispersion layer 177M1 can be changed in various ways.

[0063] The second field dispersion layer 177M1 is electrically connected to the source electrode 173. In some embodiments, the second field dispersion layer 177M1 on any one cross-section perpendicular to the first direction D1 (e.g., Figure 11) is connected to the second source electrode 173M1.

[0064] Alternatively, on another cross-section perpendicular to the first direction D1 (for example, Figure 5), the second field dispersion layer 177M1 is not connected to the second source electrode 173M1 and is separated from the source electrode 173 in the second direction D2. In this case, the second field dispersion layer 177M1 is connected to the first field dispersion layer 177M0 via the first via 179V0 and indirectly connected to the source electrode 173 via the first field dispersion layer 177M0. The first via 179V0 penetrates the second protective layer 140 and is located between the second field dispersion layer 177M1 and the first field dispersion layer 177M0 in the third direction D3. The first via 179V0 penetrates the second protective layer 140 and electrically connects the second field dispersion layer 177M1 and the first field dispersion layer 177M0.

[0065] Therefore, the second field dispersion layer 177M1 is not a floating field dispersion layer that is not connected to the source electrode 173 and is separated from the source electrode 173 in the second direction D2. However, on any one cross-section cut perpendicular to the first direction D1 (for example, Figure 9), there is a portion of the second field dispersion layer 177M1 that is not connected to the source electrode 173. However, even in this case, the second field dispersion layer 177M1 on the other cross-section cut perpendicular to the first direction D1 is connected to the source electrode 173.

[0066] The second field dispersion layer 177M1 contains the same material as the second source electrode 173M1 and is located in the same layer as the second source electrode 173M1. For example, the second field dispersion layer 177M1 is formed simultaneously with the second source electrode 173M1 using the same process. In this case, the boundary between the second field dispersion layer 177M1 and the second source electrode 173M1 is not clear, and the second field dispersion layer 177M1 is formed integrally with the second source electrode 173M1. However, it is not limited to this, and the second field dispersion layer 177M1 may be a separate component separated from the second source electrode 173M1. Also, the second field dispersion layer 177M1 may be located in a different layer from the second source electrode 173M1 and may be formed using a different process.

[0067] The semiconductor device further includes a third field dispersion layer 177M2 located on a third protective layer 150. The third field dispersion layer 177M2, together with the first field dispersion layer 177M0 and the second field dispersion layer 177M1, constitutes a field dispersion layer. The third field dispersion layer 177M2 is located between the source electrode 173 and the drain electrode 175. The third field dispersion layer 177M2 overlaps with the gate electrode layer 155 in a third direction D3. The third field dispersion layer 177M2 overlaps with the first field dispersion layer 177M0 and the second field dispersion layer 177M1 in a third direction D3. The gate electrode layer 155, the first field dispersion layer 177M0, and the second field dispersion layer 177M1 are covered by the third field dispersion layer 177M2. The third field dispersion layer 177M2 has a greater width than the second field dispersion layer 177M1. The third field dispersion layer 177M2 completely covers the second field dispersion layer 177M1. However, it is not limited to this, and the widths, positional relationships, etc., of the first field dispersion layer 177M0, the second field dispersion layer 177M1, and the third field dispersion layer 177M2 can be changed in various ways.

[0068] The third field dispersion layer 177M2 is electrically connected to the source electrode 173. In some embodiments, the third field dispersion layer 177M2 on any one cross section cut perpendicular to the first direction D1 (e.g., Figure 11) is connected to the third source electrode 173M2.

[0069] Alternatively, on any one cross-section perpendicular to the first direction D1 (for example, Figure 5), the third field dispersion layer 177M2 is not connected to the third source electrode 173M2 and is separated from the source electrode 173 in the second direction D2. In this case, the third field dispersion layer 177M2 is connected to the second field dispersion layer 177M1 via the second via 179V1, connected to the first field dispersion layer 177M0 via the second field dispersion layer 177M1, and indirectly connected to the source electrode 173 via the first field dispersion layer 177M0. The second via 179V1 penetrates the third protective layer 150 and is located between the third field dispersion layer 177M2 and the second field dispersion layer 177M1 in the third direction D3. The second via 179V1 penetrates the third protective layer 150 and electrically connects the third field dispersion layer 177M2 and the second field dispersion layer 177M1.

[0070] Therefore, the third field dispersion layer 177M2 is not connected to the source electrode 173 and is not a floating field dispersion layer separated from the source electrode 173 in the second direction D2. However, on one of the cross-sections cut perpendicular to the first direction D1 (for example, Figure 9), there is a portion of the third field dispersion layer 177M2 that is not connected to the source electrode 173. However, even in this case, the third field dispersion layer 177M2 on the other cross-sections cut perpendicular to the first direction D1 is connected to the source electrode 173.

[0071] The third field dispersion layer 177M2 contains the same material as the third source electrode 173M2 and is located in the same layer as the third source electrode 173M2. The third field dispersion layer 177M2 is formed simultaneously with the third source electrode 173M2 using the same process. The boundary between the third field dispersion layer 177M2 and the third source electrode 173M2 is not clearly defined, and the third field dispersion layer 177M2 is formed integrally with the third source electrode 173M2. However, this is not limited to the third field dispersion layer 177M2 being a separate component separated from the third source electrode 173M2. Alternatively, the third field dispersion layer 177M2 may be located in a different layer than the third source electrode 173M2 and formed using a different process.

[0072] In some embodiments, at least one of the first field dispersion layer 177M0, the second field dispersion layer 177M1, or the third field dispersion layer 177M2 may be omitted. For example, the semiconductor device may include the first field dispersion layer 177M0 but not the second field dispersion layer 177M1 or the third field dispersion layer 177M2. Or, the semiconductor device may include the second field dispersion layer 177M1 but not the first field dispersion layer 177M0 or the third field dispersion layer 177M2. Or, the semiconductor device may include the third field dispersion layer 177M2 but not the first field dispersion layer 177M0 or the second field dispersion layer 177M1.

[0073] The semiconductor device includes a source wiring layer 178TM located on a fourth protective layer 160. The source wiring layer 178TM is located between the source electrode 173 and the drain electrode 175.

[0074] The source wiring layer 178TM overlaps with the gate electrode layer 155 in the third direction D3. At least a portion of the source wiring layer 178TM overlaps with the first field dispersion layer 177M0, the second field dispersion layer 177M1, and the third field dispersion layer 177M2 in the third direction D3.

[0075] For example, the source wiring layer 178TM is located on the uppermost field dispersion layer 177 in the third direction D3. The source wiring layer 178TM is located on the gate electrode layer 155, the first field dispersion layer 177M0, the second field dispersion layer 177M1, and the third field dispersion layer 177M2. In other words, the source wiring layer 178TM is the uppermost metal layer in the third direction D3 among the metal layers connected to the source electrode 173.

[0076] At least portions of the gate electrode layer 155, the first field dispersion layer 177M0, the second field dispersion layer 177M1, and the third field dispersion layer 177M2 are covered by the source wiring layer 178TM. As will be described later, the source wiring layer 178TM has a narrower width than the third field dispersion layer 177M2. The source wiring layer 178TM covers only a portion of the third field dispersion layer 177M2. As a result, the source wiring layer 178TM does not function as a field dispersion layer 177.

[0077] The source wiring layer 178TM is electrically connected to the source electrode 173. In some embodiments, the source wiring layer 178TM on any one cross section cut perpendicular to the first direction D1 (e.g., Figure 11) is connected to the fourth source electrode 173TM.

[0078] Alternatively, on any one cross-section perpendicular to the first direction D1 (for example, Figure 5), the source wiring layer 178TM is not connected to the first source electrode 173M0 and is separated from the source electrode 173 in the second direction D2. In this case, the source wiring layer 178TM is connected to the third field dispersion layer 177M2 via the third via 179V2, to the second field dispersion layer 177M1 via the third field dispersion layer 177M2, to the first field dispersion layer 177M0 via the second field dispersion layer 177M1, and indirectly connected to the source electrode 173 via the first field dispersion layer 177M0. The third via 179V2 penetrates the fourth protective layer 160 and is located between the source wiring layer 178TM and the third field dispersion layer 177M2 in the third direction D3. The third via 179V2 penetrates the fourth protective layer 160 and electrically connects the source wiring layer 178TM and the third field dispersion layer 177M2.

[0079] Therefore, the source wiring layer 178TM is not connected to the source electrode 173 and is not a floating electrode separated from the source electrode 173 in the second direction D2. However, even in this case, the source wiring layer 178TM on other cross-sections cut perpendicular to the first direction D1 is connected to the source electrode 173.

[0080] The source wiring layer 178TM contains the same material as the fourth source electrode 173TM in Figure 8, for example, and is located in the same layer as the fourth source electrode 173TM. The source wiring layer 178TM is formed simultaneously with the fourth source electrode 173TM in the same process. The boundary between the source wiring layer 178TM and the fourth source electrode 173TM is not clear, and the source wiring layer 178TM is formed integrally with the fourth source electrode 173TM. However, it is not limited to this, and the source wiring layer 178TM is a separate component separated from the fourth source electrode 173TM. Alternatively, the source wiring layer 178TM may be located in a different layer from the fourth source electrode 173TM and formed in a different process.

[0081] On the other hand, the first drain electrode 175M0 has a first projection 175M0_p that protrudes in a second direction D2. The first projection 175M0_p protrudes from the upper part of the first drain electrode 175M0 in the second direction D2. Here, the upper surface of the first projection 175M0_p is located at a higher level than the upper surface of the first drain electrode 175M0. However, it is not limited to this, and the upper surface of the first projection 175M0_p and the upper surface of the first drain electrode 175M0 are located at substantially the same level.

[0082] As described above, the first drain electrode 175M0 is formed to penetrate the first protective layer 156 and the barrier layer 136, filling a trench that recesses the upper surface of the channel layer 132, and the first projection 175M0_p protrudes in the second direction D2 toward the second protective layer 140 and is located on the first protective layer 156. Therefore, at least a portion of the first projection 175M0_p overlaps with the drift region DTR in the third direction D3.

[0083] The second drain electrode 175M1 has a second projection 175M1_p that protrudes in a second direction D2. The second projection 175M1_p protrudes from the upper part of the second drain electrode 175M1 in the second direction D2. Here, the upper surface of the second projection 175M1_p is located at a higher level than the upper surface of the second drain electrode 175M1. However, it is not limited to this, and the upper surface of the second projection 175M1_p and the upper surface of the second drain electrode 175M1 are located at substantially the same level.

[0084] The second drain electrode 175M1 penetrates the second protective layer 140 and is formed to fill a trench that exposes the upper surface of the first drain electrode 175M0. The second projection 175M1_p protrudes in the second direction D2 toward the third protective layer 150 and is located on the second protective layer 140. Therefore, at least a portion of the second projection 175M1_p overlaps with the drift region DTR in the third direction D3.

[0085] The third drain electrode 175M2 has a third projection 175M2_p that protrudes in a second direction D2. The third projection 175M2_p protrudes from the upper part of the third drain electrode 175M2 in the second direction D2. Here, the upper surface of the third projection 175M2_p is located at a higher level than the upper surface of the third drain electrode 175M2. However, it is not limited to this, and the upper surface of the third projection 175M2_p and the upper surface of the third drain electrode 175M2 are located at substantially the same level.

[0086] The third drain electrode 175M2 is formed to penetrate the third protective layer 150 and fill a trench that exposes the upper surface of the second drain electrode 175M1, and the third projection 175M2_p protrudes in the second direction D2 toward the fourth protective layer 160 and is located on the third protective layer 150. Therefore, at least a portion of the third projection 175M2_p overlaps with the drift region DTR in the third direction D3.

[0087] The fourth drain electrode 175TM has a fourth projection 175TM_p that protrudes in a second direction D2. The fourth projection 175TM_p protrudes from the upper part of the fourth drain electrode 175TM in the second direction D2. Here, the upper surface of the fourth projection 175TM_p is located at a higher level than the upper surface of the fourth drain electrode 175TM. However, it is not limited to this, and the upper surface of the fourth projection 175TM_p and the upper surface of the fourth drain electrode 175TM are located at substantially the same level.

[0088] The fourth drain electrode 175TM penetrates the fourth protective layer 160 and is formed to fill a trench that exposes the upper surface of the third drain electrode 175M2, and the fourth projection 175TM_p protrudes in the second direction D2 toward the source wiring layer 178TM and is located on the fourth protective layer 160. Thus, at least a portion of the fourth projection 175TM_p overlaps with the drift region DTR in the third direction D3.

[0089] The first to fourth protrusions 175M0_p, 175M1_p, 175M2_p, and 175TM_p each contain the same material as the first to fourth drain electrodes 175M0, 175M1, 175M2, and 175TM, and are located in the same layer as the first to fourth drain electrodes 175M0, 175M1, 175M2, and 175TM. For example, the first to fourth protrusions 175M0_p, 175M1_p, 175M2_p, and 175TM_p are each formed simultaneously in the same process as the first to fourth drain electrodes 175M0, 175M1, 175M2, and 175TM. In this case, the boundary between each of the first to fourth protrusions 175M0_p, 175M1_p, 175M2_p, and 175TM_p and the first to fourth drain electrodes 175M0, 175M1, 175M2, and 175TM is not clear, and each of the first to fourth protrusions 175M0_p, 175M1_p, 175M2_p, and 175TM_p is formed integrally with the first to fourth drain electrodes 175M0, 175M1, 175M2, and 175TM. However, it is not limited to this, and each of the first to fourth protrusions 175M0_p, 175M1_p, 175M2_p, and 175TM_p may be a separate component separated from the first to fourth drain electrodes 175M0, 175M1, 175M2, and 175TM. Furthermore, each of the first to fourth protrusions 175M0_p, 175M1_p, 175M2_p, and 175TM_p can be formed by a different process than the first to fourth drain electrodes 175M0, 175M1, 175M2, and 175TM.

[0090] In some embodiments, at least one of the first to fourth protrusions 175M0_p, 175M1_p, 175M2_p, and 175TM_p may be omitted. For example, the semiconductor device may include the first protrusion 175M0_p but not the second to fourth protrusions 175M1_p, 175M2_p, and 175TM_p. Or, the semiconductor device may include the second protrusion 175M1_p but not the first, third, and fourth protrusions 175M0_p, 175M2_p, and 175TM_p. Or, the semiconductor device may include the third protrusion 175M2_p but not the first, second, and fourth protrusions 175M0_p, 175M1_p, and 175TM_p. Alternatively, the semiconductor device includes a fourth protrusion 175TM_p but does not include the first to third protrusions 175M0_p, 175M1_p, and 175M2_p.

[0091] For example, the extension length L_178TM of the source wiring layer 178TM in the second direction D2 is smaller than the extension length L_178TM of the field distribution layer 177 in the second direction D2. For example, the extension length L_178TM of the source wiring layer 178TM in the second direction D2 is smaller than the extension length L_177M2 of the third field distribution layer 177M2 in the second direction D2. The extension length L_178TM of the source wiring layer 178TM in the second direction D2 is smaller than the extension length L_177M1 of the second field distribution layer 177M1 in the second direction D2. The extension length L_178TM of the source wiring layer 178TM in the second direction D2 is smaller than the extension length L_177M0 of the first field distribution layer 177M0 in the second direction D2.

[0092] Here, the extension length L_178TM of the source wiring layer 178TM in the second direction D2 is defined as the length from any one point in the source wiring layer 178TM that overlaps with the gate electrode layer 155 and the third direction D3 to one end of the source wiring layer 178TM in the second direction D2 away from the source electrode 173. In other words, the extension length L_178TM of the source wiring layer 178TM in the second direction D2 is the length that overlaps with the drift region DTR located between the gate electrode layer 155 and the drain electrode 175 and the third direction D3. Furthermore, the extension length L_178TM of the source wiring layer 178TM in the second direction D2 is the shortest length in the second direction D2 among the lengths that satisfy the above conditions.

[0093] Furthermore, the extension lengths L_177M0, L_177M1, and L_177M2 of the first to third field dispersion layers 177M0, 177M1, and 177M2 in the second direction D2 are defined as the length from any one point in each of the first to third field dispersion layers 177M0, 177M1, and 177M2 that overlaps with the gate electrode layer 155 in the third direction D3, to one end of each of the first to third field dispersion layers 177M0, 177M1, and 177M2 in the second direction D2 away from the source electrode 173. In other words, the extension lengths L_177M0, L_177M1, and L_177M2 of the first to third field dispersion layers 177M0, 177M1, and 177M2 in the second direction D2 are the lengths that overlap with the drift region DTR located between the gate electrode layer 155 and the drain electrode 175 in the third direction D3. Furthermore, the extension lengths L_177M0, L_177M1, and L_177M2 of the first to third field dispersion layers 177M0, 177M1, and 177M2 in the second direction D2 are the shortest lengths in the second direction D2 that satisfy the above conditions.

[0094] Furthermore, the extension length L_177M0 of the first field dispersion layer 177M0 in the second direction D2 is smaller than the extension length L_177M1 of the second field dispersion layer 177M1 in the second direction D2. The extension length L_177M1 of the second field dispersion layer 177M1 in the second direction D2 is smaller than the extension length L_177M2 of the third field dispersion layer 177M2 in the second direction D2.

[0095] As a result, at least portions of the first to third field dispersion layers 177M0, 177M1, and 177M2 do not overlap with the other field dispersion layers 177 in the third direction D2, in other words, they are not obstructed by the other field dispersion layers 177, and directly overlap with the drift region DTR located between the gate electrode layer 155 and the drain electrode 175 in the third direction D3. Therefore, the first to third field dispersion layers 177M0, 177M1, and 177M2 function as field dispersion layers 177.

[0096] On the other hand, the entire source wiring layer 178TM in the drift region DTR located between the gate electrode layer 155 and the drain electrode 175 overlaps with at least one of the first to third field dispersion layers 177M0, 177M1, and 177M2 in the third direction D2. In other words, one end of the source wiring layer 178TM in the second direction D2 away from the source electrode 173 overlaps with the field dispersion layer 177 in the third direction D3. For example, the field dispersion layer 177 is located between one end of the source wiring layer 178TM and the barrier layer 136 in the third direction D3. Thus, the source wiring layer 178TM is blocked in the third direction D3 by at least one of the first to third field dispersion layers 177M0, 177M1, and 177M2, and therefore does not directly overlap the drift region DTR located between the gate electrode layer 155 and the drain electrode 175 in the third direction D3. Therefore, the source wiring layer 178TM does not function as the field distribution layer 177.

[0097] On the other hand, the length L_175M0_p of the first protrusion 175M0_p in the drain electrode 175 in the second direction D2 is smaller than the length L_175M1_p of the second protrusion 175M1_p in the second direction D2. The length L_175M1_p of the second protrusion 175M1_p in the second direction D2 is smaller than the length L_175M2_p of the third protrusion 175M2_p in the second direction D2. The length L_175M2_p of the third protrusion 175M2_p in the second direction D2 is smaller than the length L_175TM_p of the fourth protrusion 175TM_p in the second direction D2. The length L_175TM_p of the fourth projection 175TM_p in the second direction D2 is greater than the lengths L_175M0_p, L_175M1_p, and L_175M2_p of the first to third projections 175M0_p, 175M1_p, and 175M2_p in the second direction D2.

[0098] Here, the lengths L_175M0_p, L_175M1_p, L_175M2_p, and L_175TM_p of the first to fourth protrusions 175M0_p, 175M1_p, 175M2_p, and 175TM_p in the second direction D2 are defined, for example, as the length from the point where the first to fourth protrusions 175M0_p, 175M1_p, 175M2_p, and 175TM_p intersect with the first to fourth drain electrodes 175M0, 175M1, 175M2, and 175TM, respectively, to one end in the second direction D2 away from the first to fourth drain electrodes 175M0, 175M1, 175M2, and 175TM. In other words, the lengths L_175M0_p, L_175M1_p, L_175M2_p, and L_175TM_p of the first to fourth protrusions 175M0_p, 175M1_p, 175M2_p, and L_175TM_p in the second direction D2 are the lengths that overlap the drift region DTR located between the gate electrode layer 155 and the drain electrode 175 with the third direction D3. Also, the lengths L_175M0_p, L_175M1_p, L_175M2_p, and L_175TM_p of the first to fourth protrusions 175M0_p, 175M1_p, 175M2_p, and L_175TM_p in the second direction D2 are the shortest lengths in the second direction D2 that satisfy the above conditions.

[0099] As the area of ​​a semiconductor device increases, the voltage drop due to wiring resistance increases, and in the case of low-voltage, large-area devices, the effect of wiring resistance becomes even greater. To improve this, it is necessary to increase the width of the wiring. In a structure in which a field dispersion layer 177 connected to the source electrode 173 is applied to efficiently disperse the E-Field, for example, referring to Figure 4, if there is no source wiring layer 178TM and a fourth drain electrode 175TM, the voltage drop due to wiring resistance is not large on the source electrode 173 side because the width of the third field dispersion layer 177M2 is wide, but on the drain electrode 175 side, the voltage drop due to wiring resistance is relatively large because the third drain electrode 175M2 does not extend very far in the second direction D2. As a result, the width of the fourth drain electrode 175TM, which corresponds to the drain wiring layer on the drain electrode 175 side, can be widened to improve the wiring resistance of the device.

[0100] As mentioned above, for example, the extension lengths L_177M0, L_177M1, and L_177M2 of the first to third field distribution layers 177M0, 177M1, and 177M2 to the second direction D2 become longer the higher they are located in the third direction D3. However, the extension length L_178TM of the source wiring layer 178TM located on the third field distribution layer 177M2, which is the highest of the field distribution layers 177 in the third direction D3, to the second direction D2 is shorter than the extension length L_177M2 of the third field distribution layer 177M2 to the second direction D2.

[0101] Since the source wiring layer 178TM of the source electrode 173 does not serve as a field dispersion layer, the extension length L_178TM in the second direction D2 decreases, which further increases the length L_175TM_p of the fourth protrusion 175TM_p in the second direction D2 of the drain electrode 175. For example, the first to fourth drain electrodes 175M0, 175M1, 175M2, and 175TM each have first to fourth protrusions 175M0_p, 175M1_p, 175M2_p, and 175TM_p, respectively, and the further the first to fourth protrusions 175M0_p, 175M1_p, 175M2_p, and 175TM_p are positioned higher in the third direction D3, the longer their lengths L_175M0_p, L_175M1_p, L_175M2_p, and L_175TM_p are in the second direction D2 extending towards the drift region.

[0102] This allows the field dispersion layer 177 to reduce the electric field peak of the channel layer 132, efficiently disperse the electric field of the channel layer 132 to flatten the profile, and reduce the extension length L_178TM of the source wiring layer 178TM located on the field dispersion layer 177 in the second direction D2, while increasing the length L_175TM_p of the fourth protrusion 175TM_p on the drain electrode 175 side in the second direction D2, thereby reducing the wiring resistance on the drain electrode 175 side.

[0103] For example, if the length L_175TM_p of the fourth protrusion 175TM_p of the drain electrode 175 in the second direction D2 is 2 μm, increasing the length of the gate electrode layer 155 in the first direction D1 from 0.5 mm to 1.3 mm results in an 8% increase in resistance. In contrast, if the length L_175TM_p of the fourth protrusion 175TM_p of the drain electrode 175 in the second direction D2 is 6 μm, increasing the length of the gate electrode layer 155 in the first direction D1 from 0.5 mm to 1.3 mm results in a 4% increase in resistance, thus improving the wiring resistance.

[0104] On the other hand, the thickness T_177M0 of the first field dispersion layer 177M0 in the third direction D3 is smaller than the thickness T_177M1 of the second field dispersion layer 177M1 in the third direction D3. The thickness T_177M1 of the second field dispersion layer 177M1 in the third direction D3 is smaller than the thickness T_177M2 of the third field dispersion layer 177M2 in the third direction D3. The thickness T_177M2 of the third field dispersion layer 177M2 in the third direction D3 is smaller than the thickness T_178TM of the source wiring layer 178TM in the third direction D3. The thickness T_178TM of the source wiring layer 178TM in the third direction D3 is larger than the thicknesses T_177M0, T_177M1, and T_177M2 of the first to third field dispersion layers 177M0, 177M1, and 177M2 in the third direction D3.

[0105] Here, the thicknesses T_177M0, T_177M1, and T_177M2 of the first to third field dispersion layers 177M0, 177M1, and 177M2 in the third direction D3 are defined as the shortest length from one end of the first to third field dispersion layers 177M0, 177M1, and 177M2 in the second direction D2 away from the source electrode 173 to the third direction D3. Similarly, the thickness T_178TM of the source wiring layer 178TM in the third direction D3 is defined as the shortest length from one end of the source wiring layer 178TM in the second direction D2 away from the source electrode 173 to the third direction D3.

[0106] The thickness T_175M0_p of the first protrusion 175M0_p in the third direction D3 is smaller than the thickness T_175M1_p of the second protrusion 175M1_p in the third direction D3. The thickness T_175M1_p of the second protrusion 175M1_p in the third direction D3 is smaller than the thickness T_175M2_p of the third protrusion 175M2_p in the third direction D3. The thickness T_175M2_p of the third protrusion 175M2_p in the third direction D3 is smaller than the thickness T_175TM_p of the fourth protrusion 175TM_p in the third direction D3. The thickness T_175TM_p of the fourth projection 175TM_p in the third direction D3 is greater than the thicknesses T_175M0_p, T_175M1_p, and T_175M2_p of the first to third projections 175M0_p, 175M1_p, and 175M2_p in the third direction D3.

[0107] Here, the thicknesses T_175M0_p, T_175M1_p, T_175M2_p, and T_175TM_p of the first to fourth protrusions 175M0_p, 175M1_p, 175M2_p, and 175TM_p in the third direction D3 are defined as the shortest length from one end of the first to fourth protrusions 175M0_p, 175M1_p, 175M2_p, and 175TM_p in the third direction D3 in the second direction D2 away from the drain electrode 175.

[0108] On the other hand, the length L_179V0 of the first via 179V0 in the second direction D2 is smaller than the length L_179V1 of the second via 179V1 in the second direction D2. The length L_179V1 of the second via 179V1 in the second direction D2 is smaller than the length L_179V2 of the third via 179V2 in the second direction D2.

[0109] Furthermore, the first angle formed by the side wall of the first via 179V0 in the second direction D2 and the lower surface of the second protective layer 140 is greater than the second angle formed by the side wall of the second via 179V1 in the second direction D2 and the lower surface of the third protective layer 150. The second angle formed by the side wall of the second via 179V1 in the second direction D2 and the lower surface of the third protective layer 150 is greater than or equal to the third angle formed by the side wall of the third via 179V2 in the second direction D2 and the lower surface of the fourth protective layer 160.

[0110] This reduces the occurrence of voids due to profile defects, even when the thicknesses T_156, T_140, T_150, and T_160 of the first to fourth protective layers 156, 140, 150, and 160 in the third direction D3 increase as they are positioned higher in the third direction D3.

[0111] As an example, the semiconductor device includes a plurality of gate electrode layers 155, a plurality of source electrodes 173, and a plurality of drain electrodes 175.

[0112] The gate electrode layer 155, source electrode 173, and drain electrode 175 have a bar shape that extends along a first direction D1 in a plane, and the gate electrode layer 155 is arranged alternately with the source electrode 173 and drain electrode 175 along a second direction D2. For example, along the second direction D2, they may be arranged in the order of gate electrode layer 155, source electrode 173, gate electrode layer 155, drain electrode 175, gate electrode layer 155, source electrode 173, gate electrode layer 155, drain electrode 175.

[0113] Gate connecting portions 155c are located between a plurality of gate electrode layers 155 that are spaced apart in the second direction D2. The gate connecting portions 155c extend in the second direction D2 and connect the gate electrode layers 155. A plurality of gate connecting portions 155c are located between any one gate electrode layer 155 and another gate electrode layer 155 that is spaced apart in the second direction D2, and the plurality of gate connecting portions 155c are arranged at a certain distance apart in the first direction D1 between the gate electrode layers 155. In addition, the gate semiconductor layer 152 is also located between the barrier layer 136 and the gate connecting portions 155c. The first protective layer 156 covers the upper surface and side surface of the gate connecting portions 155c.

[0114] As the source electrode 173 extends in the first direction D1 between gate electrode layers 155 separated in the second direction D2, the source electrode 173 passes over the gate coupling portion 155c. At this time, the first protective layer 156 is located between the source electrode 173 and the gate coupling portion 155c. The source electrode 173 and the gate coupling portion 155c are not connected. The source electrode 173 also has a gate contact hole CH1 that exposes the gate coupling portion 155c in the third direction D3. For example, the first source electrode 173M0 has a gate contact hole CH1, the gate contact hole CH1 penetrates the first source electrode 173M0, and the first protective layer 156 and the second protective layer 140 are laminated inside the gate contact hole CH1.

[0115] The semiconductor device further includes a gate lead line 193M1 connected to a gate coupling portion 155c. The gate lead line 193M1 extends in a first direction D1 between one gate electrode layer 155 and another gate electrode layer 155 spaced apart from it in a second direction D2. As a result, the gate lead line 193M1 passes over and connects with a plurality of gate coupling portions 155c that are spaced apart at regular intervals in the first direction D1.

[0116] The gate pull-out line 193M1 is located on the second protective layer 140. The gate pull-out line 193M1 is also covered by the third protective layer 150, the fourth protective layer 160, or both of them.

[0117] As described above, the source electrode 173, for example, the first source electrode 173M0, is also separated in the first direction D1 between the gate electrode layer 155 separated in the second direction D2, so that the gate lead line 193M1 is located on the first source electrode 173M0, and the gate lead line 193M1 and the first source electrode 173M0 overlap in the third direction D3. The second protective layer 140 is located between the gate lead line 193M1 and the first source electrode 173M0. The gate lead line 193M1 and the first source electrode 173M0 are not connected.

[0118] For example, the gate lead line 193M1 contains the same material as the second source electrode 173M1 or the second field dispersion layer 177M1 and is located in the same layer as the second source electrode 173M1 or the second field dispersion layer 177M1. For example, the gate lead line 193M1 is formed simultaneously in the same process as the second source electrode 173M1 or the second field dispersion layer 177M1. In this case, the boundary between the gate lead line 193M1 and the second source electrode 173M1 or the second field dispersion layer 177M1 is not clear, and the gate lead line 193M1 is formed integrally with the second source electrode 173M1 or the second field dispersion layer 177M1. However, without limiting this, the gate lead line 193M1 may be a separate component separated from the second source electrode 173M1 or the second field dispersion layer 177M1. Furthermore, the gate lead line 193M1 is located in a different layer from the second source electrode 173M1 or the second field dispersion layer 177M1 and may be formed by a different process.

[0119] As an example, the gate lead line 193M1 is connected to the gate connector 155c via the gate via 179VG. The gate via 179VG is located between the gate lead line 193M1 and the gate connector 155c in a third direction D3. The gate via 179VG is located within the gate contact hole CH1. The gate via 179VG extends in the third direction D3, passing through the first protective layer 156 and the second protective layer 140 laminated within the gate contact hole CH1. The gate via 179VG electrically connects the gate lead line 193M1 and the gate connector 155c.

[0120] The gate lead line 193M1 extends in a first direction D1 until it intersects with the gate signal line 194M1. For example, the gate signal line 194M1 extends in a second direction D2 on one side and connects to the gate pad 194TM.

[0121] The gate pad 194TM is located on at least a portion of the gate signal line 194M1. For example, the gate pad 194TM is located on the fourth protective layer 160, with the third protective layer 150 and the fourth protective layer 160 interposed between the gate pad 194TM and the gate signal line 194M1. The gate pad 194TM and the gate signal line 194M1 are electrically connected by vias or the like that passing through the third protective layer 150 and the fourth protective layer 160.

[0122] The source signal line 191M2 is located above at least a portion of the gate signal line 194M1. The source signal line 191M2 is located on the third protective layer 150, and the third protective layer 150 is interposed between the source signal line 191M2 and the gate signal line 194M1. Therefore, the source signal line 191M2 and the gate signal line 194M1 are not electrically connected.

[0123] The source signal line 191M2 extends in the second direction D2 and connects to the source pad 191TM. The source signal line 191M2 extends in the second direction D2 on one side to which the gate signal line 194M1 extends and in the second direction D2 on the other side and connects to the source pad 191TM.

[0124] The source pad 191TM is located on at least a portion of the source signal line 191M2. The source pad 191TM is located on the fourth protective layer 160, which is interposed between the source pad 191TM and the source signal line 191M2. The source pad 191TM and the source signal line 191M2 are electrically connected by vias or the like that that penetrate the fourth protective layer 160. Alternatively, the source wiring layer 178TM extends in the first direction D1 and is connected to the source pad 191TM.

[0125] Furthermore, the fourth drain electrode 175TM, which corresponds to the drain wiring layer, extends in the first direction D1 until it contacts the drain pad 192TM. The fourth drain electrode 175TM and the drain pad 192TM are electrically connected. For example, the source pad 191TM and the drain pad 192TM are spaced apart in the first direction D1, with the gate electrode layer 155, source electrode 173, and drain electrode 175 in between, and extend in the second direction D2. Therefore, the source wiring layer 178TM extends in one first direction D1 until it intersects with the source pad 191TM, and the fourth drain electrode 175TM extends in the other first direction D1 until it intersects with the drain pad 192TM.

[0126] The gate pad 194TM, source pad 191TM, and drain pad 192TM each contain the same material as the source wiring layer 178TM and the fourth drain electrode 175TM, and are located in the same layer as the source wiring layer 178TM and the fourth drain electrode 175TM. For example, the gate pad 194TM, source pad 191TM, and drain pad 192TM are each formed simultaneously in the same process as the source wiring layer 178TM and the fourth drain electrode 175TM. In this case, the boundaries between the source pad 191TM and drain pad 192TM and the source wiring layer 178TM and the fourth drain electrode 175TM are not clear, and the source pad 191TM and drain pad 192TM are each formed integrally with the source wiring layer 178TM and the fourth drain electrode 175TM. However, without limiting this, the source pad 191TM and drain pad 192TM may each be separate components separated from the source wiring layer 178TM and the fourth drain electrode 175TM. Furthermore, the gate pad 194™, source pad 191™, and drain pad 192™ are located in different layers from the source wiring layer 178™ and the fourth drain electrode 175™, and may be formed by different processes.

[0127] Figure 7 is a cross-sectional view showing another embodiment, corresponding to Figure 5.

[0128] The embodiment shown in Figure 7 corresponds to the same parts as the embodiment shown in Figure 5, so its explanation will be omitted, and the focus will be on the differences. Also, the same reference numerals will be used for the same components as in the previous embodiment.

[0129] Referring to Figure 7, at least one of the first to fourth source electrodes 173M0, 173M1, 173M2, and 173TM is omitted, at least one of the first to fourth drain electrodes 175M0, 175M1, 175M2, and 175TM is omitted, at least one of the first to third field dispersion layers 177M0, 177M1, and 177M2 is omitted, and at least one of the first to fourth protective layers 156, 140, 150, and 160 is omitted.

[0130] As an example, Figure 7 shows the case where the second source electrode 173M1, the third source electrode 173M2, the fourth source electrode 173TM, the second drain electrode 175M1, the second field dispersion layer 177M1, and the second protective layer 140 are omitted.

[0131] For example, the source electrode 173 includes a first source electrode 173M0. A third protective layer 150 and a fourth protective layer 160 are sequentially laminated between the first source electrode 173M0 and the source wiring layer 178TM. The drain electrode 175 includes a first drain electrode 175M0, a third drain electrode 175M2, and a fourth drain electrode 175TM, which are sequentially laminated in a third direction D3.

[0132] The field distribution layer 177 includes a first field distribution layer 177M0 and a third field distribution layer 177M2. The first field distribution layer 177M0 is connected to the third field distribution layer 177M2 via a second via 179V1, and the third field distribution layer 177M2 is connected to the source wiring layer 178TM via a third via 179V2.

[0133] In this case, a first protective layer 156 is located between the gate electrode layer 155 and the first field dispersion layer 177M0, a third protective layer 150 is located between the first field dispersion layer 177M0 and the third field dispersion layer 177M2, and a fourth protective layer 160 is located between the third field dispersion layer 177M2 and the source wiring layer 178TM.

[0134] Figure 8 is a cross-sectional view showing another embodiment, corresponding to Figure 5.

[0135] The embodiment shown in Figure 8 corresponds to the same parts as the embodiment shown in Figure 5, so its explanation will be omitted, and the focus will be on the differences. Also, the same reference numerals will be used for the same components as in the previous embodiment.

[0136] Referring to Figure 8, the source electrode 173 includes the first to fourth source electrodes 173M0, 173M1, 173M2, and 173TM. The first to fourth source electrodes 173M0, 173M1, 173M2, and 173TM are sequentially connected in the third direction D3. The first to fourth source electrodes 173M0, 173M1, 173M2, and 173TM are electrically connected.

[0137] On the other hand, the first to third field dispersion layers 177M0, 177M1, and 177M2 are either connected to the first to third source electrodes 173M0, 173M1, and 173M2, respectively, or separated in the second direction D2 without being connected. In addition, the source wiring layer 178TM is either connected to the fourth source electrode 173TM, or separated in the second direction D2 without being connected.

[0138] In Figure 8, the first field dispersion layer 177M0 is connected to the first source electrode 173M0, and the source wiring layer 178TM is connected to the fourth source electrode 173TM, but the second and third field dispersion layers 177M1 and 177M2 are separated in the second direction D2 without being connected to the second and third source electrodes 173M1 and 173M2, respectively.

[0139] Furthermore, Figure 8 does not show the first via 179V0 connecting the second field dispersion layer 177M1 and the first field dispersion layer 177M0, the second via 179V1 connecting the third field dispersion layer 177M2 and the second field dispersion layer 177M1, or the third via 179V2 connecting the source wiring layer 178TM and the third field dispersion layer 177M2.

[0140] However, even in this case, the second and third field dispersion layers 177M1 and 177M2 are not floating field dispersion layers that are separated from the source electrode 173 in the second direction D2 without being connected to the source electrode 173. Rather, in other cross-sections cut perpendicular to the first direction D1, there are portions in which the second and third field dispersion layers 177M1 and 177M2 are connected to the source electrode 173.

[0141] Figure 9 is a cross-sectional view showing another embodiment, corresponding to Figure 8.

[0142] The embodiment shown in Figure 9 corresponds to the same parts as the embodiment shown in Figure 8, so its explanation will be omitted, and the focus will be on the differences. Also, the same reference numerals will be used for the same components as in the previous embodiment.

[0143] Figure 8 shows the case where the first field dispersion layer 177M0 is connected to the first source electrode 173M0.

[0144] Referring to Figure 9, the first field dispersion layer 177M0 is not connected to the first source electrode 173M0 and is separated in the second direction D2. However, even in this case, the first field dispersion layer 177M0 is not connected to the source electrode 173 and is not a floating field dispersion layer separated from the source electrode 173 in the second direction D2. On other cross-sections cut perpendicular to the first direction D1, there is a portion where the first field dispersion layer 177M0 is connected to the source electrode 173.

[0145] Figure 10 is a plan view showing a semiconductor device according to one embodiment. Figure 11 is a cross-sectional view taken along the line A-A' in Figure 10.

[0146] The embodiments shown in Figures 10 and 11 correspond to the same parts as the embodiments shown in Figures 4 and 5, so their explanation will be omitted, and the focus will be on the differences. Also, the same reference numerals will be used for the same components as in the previous embodiments.

[0147] For clear understanding and simplified illustration, Figure 10 shows the barrier layer 136, gate electrode layer 155, first source electrode 173M0, first drain electrode 175M0, first protrusion 175M0_p, third drain electrode 175M2, fourth drain electrode 175TM, first field dispersion layer 177M0, third field dispersion layer 177M2, and source wiring layer 178TM, while omitting the illustration of the second source electrode 173M1, third source electrode 173M2, fourth source electrode 173TM, second drain electrode 175M1, and second field dispersion layer 177M1.

[0148] Referring to Figures 10 and 11, the source electrode 173 includes a first source electrode 173M0, a second source electrode 173M1, a third source electrode 173M2, and a fourth source electrode 173TM. The first source electrode 173M0, the second source electrode 173M1, the third source electrode 173M2, and the fourth source electrode 173TM are sequentially stacked in the third direction D3. Furthermore, the first source electrode 173M0, the second source electrode 173M1, the third source electrode 173M2, and the fourth source electrode 173TM are electrically connected.

[0149] The drain electrode 175 includes a first drain electrode 175M0, a second drain electrode 175M1, a third drain electrode 175M2, and a fourth drain electrode 175TM, which are sequentially stacked in a third direction D3. Furthermore, the first drain electrode 175M0, the second drain electrode 175M1, the third drain electrode 175M2, and the fourth drain electrode 175TM are electrically connected.

[0150] The field dispersion layer 177 includes a first field dispersion layer 177M0, a second field dispersion layer 177M1, and a third field dispersion layer 177M2. A first protective layer 156 is located between the gate electrode layer 155 and the first field dispersion layer 177M0, a second protective layer 140 is located between the first field dispersion layer 177M0 and the second field dispersion layer 177M1, a third protective layer 150 is located between the second field dispersion layer 177M1 and the third field dispersion layer 177M2, and a fourth protective layer 160 is located between the third field dispersion layer 177M2 and the source wiring layer 178TM.

[0151] The first field dispersion layer 177M0 is connected to the first source electrode 173M0, the second field dispersion layer 177M1 is connected to the second source electrode 173M1, the third field dispersion layer 177M2 is connected to the third source electrode 173M2, and the source wiring layer 178TM is connected to the fourth source electrode 173TM.

[0152] Although embodiments of the present invention have been described in detail above, the technical scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concepts of the present invention also fall within the technical scope of the present invention. [Explanation of Symbols]

[0153] 110: Circuit board 115: Seed layer 120: Buffer layer 132: Channel Layer 136: Barrier layer 152: Gate semiconductor layer 155: Gate Shutdown 155c: Gate connection section 173: Source electrode 173M0, 173M1, 173M2, 173TM: 1st to 4th source electrodes 175: Drain electrode 175M0, 175M1, 175M2, 175TM: 1st to 4th drain electrodes 175M0_p, 175M1_p, 175M2_p, 175TM_p: 1st to 4th protrusion 177: Field Dispersion Layer 177M0, 177M1, 177M2: 1st to 3rd field dispersion layers 178TM: Upper wiring layer 156, 140, 150, 160: 1st to 4th protective layer

Claims

1. Channel layer and A barrier layer located on the channel layer and containing a material having a different energy band gap from the channel layer, A gate electrode layer located on the barrier layer and extending in a first direction, A gate semiconductor layer located between the barrier layer and the gate electrode layer, A source electrode and a drain electrode are connected to the channel layer and are located away from the gate electrode layer in a second direction different from the first direction, A field dispersion layer located on the gate electrode layer, connected to the source electrode, and overlapping the gate electrode layer in a third direction different from the first and second directions, It includes a source wiring layer located on the field dispersion layer, connected to the source electrode, and overlapping the gate electrode layer in the third direction, A semiconductor device characterized in that the length from any one point in the gate electrode layer and the source wiring layer overlapping in the third direction to one end of the source wiring layer in the second direction away from the source electrode is smaller than the length from any one point in the gate electrode layer and the field dispersion layer overlapping in the third direction to one end of the field dispersion layer in the second direction away from the source electrode.

2. The semiconductor device includes a plurality of field dispersion layers, The semiconductor device according to claim 1, characterized in that the source wiring layer is located on the uppermost field dispersion layer in the third direction among the field dispersion layers.

3. The aforementioned field dispersion layer is A first field dispersion layer located on the gate electrode, A second field dispersion layer located on the first field dispersion layer, The system further includes a third field dispersion layer located on the second field dispersion layer, or a combination thereof. The semiconductor device according to claim 2, characterized in that the source wiring layer is located on the field dispersion layer that is the uppermost of the first to third field dispersion layers in the third direction.

4. The length from any one point in the gate electrode layer and the first field dispersion layer overlapping in the third direction to one end of the first field dispersion layer in the second direction away from the source electrode is smaller than the length from any one point in the gate electrode layer and the second field dispersion layer overlapping in the third direction to one end of the second field dispersion layer in the second direction away from the source electrode. The length from any one point in the gate electrode layer and the second field dispersion layer overlapping in the third direction to one end of the second field dispersion layer in the second direction away from the source electrode is smaller than the length from any one point in the gate electrode layer and the third field dispersion layer overlapping in the third direction to one end of the third field dispersion layer in the second direction away from the source electrode. The semiconductor device according to claim 3, characterized in that the length from any one point in the source wiring layer overlapping the gate electrode layer in the third direction to one end of the source wiring layer in the second direction away from the source electrode is smaller than the length from any one point in the third field dispersion layer overlapping the gate electrode layer in the third direction to one end of the third field dispersion layer in the second direction away from the source electrode.

5. The thickness of the first field dispersion layer in the third direction is smaller than the thickness of the second field dispersion layer in the third direction. The thickness of the second field dispersion layer in the third direction is smaller than the thickness of the third field dispersion layer in the third direction. The thickness of the third field dispersion layer in the third direction is smaller than the thickness of the source wiring layer in the third direction. The semiconductor device according to claim 3, characterized in that the thickness of the source wiring layer in the third direction is greater than the thickness of the first to third field dispersion layers in the third direction.

6. The aforementioned semiconductor device is A first protective layer covering the terminal terminal and located below the first field dispersion layer, A second protective layer located on the first protective layer and between the first field dispersion layer and the second field dispersion layer, A third protective layer located on the second protective layer and between the second field dispersion layer and the third field dispersion layer, The semiconductor device according to claim 3, further comprising a fourth protective layer located on the third protective layer and between the third field dispersion layer and the source wiring layer, or a combination thereof.

7. The thickness of the second protective layer in the third direction is less than or equal to the thickness of the first protective layer in the third direction. The thickness of the third protective layer in the third direction is greater than the thickness of the first protective layer in the third direction. The semiconductor device according to claim 6, characterized in that the thickness of the fourth protective layer in the third direction is greater than or equal to the thickness of the third protective layer in the third direction.

8. The source electrode is The first source electrode located on the channel layer, A second source electrode located on the first source electrode, A third source electrode located on the second source electrode, The semiconductor device according to claim 6, further comprising a fourth source electrode located on the third source electrode, or a combination thereof.

9. The first source electrode is connected to the channel layer by penetrating the first protective layer. The second source electrode is located on the first source electrode and is connected to the first source electrode by penetrating the second protective layer. The third source electrode is located on the second source electrode and is connected to the second source electrode by penetrating the third protective layer. The semiconductor device according to claim 8, characterized in that the fourth source electrode is located on the third source electrode and is connected to the third source electrode through the fourth protective layer.

10. The first source electrode is connected to the first field dispersion layer, The second source electrode is connected to the second field dispersion layer, The third source electrode is connected to the third field dispersion layer, The semiconductor device according to claim 9, characterized in that the fourth source electrode is connected to the source wiring layer.

11. The fourth source electrode is positioned apart from the first source electrode in the third direction. The semiconductor device according to claim 9, characterized in that the second protective layer, the third protective layer, the fourth protective layer, or a combination thereof is located between the fourth source electrode and the first source electrode.

12. On any one cross-section perpendicular to the first direction, The first field dispersion layer is connected to the source electrode, the second field dispersion layer is located at a distance from the source electrode in the second direction, and the third field dispersion layer is located at a distance from the source electrode in the second direction, or The semiconductor device according to claim 8, characterized in that the first field dispersion layer is located at a distance from the source electrode in the second direction, the second field dispersion layer is located at a distance from the source electrode in the second direction, and the third field dispersion layer is located at a distance from the source electrode in the second direction.

13. The aforementioned semiconductor device is A first via that penetrates the second protective layer and connects the first field dispersion layer and the second field dispersion layer, A second via that penetrates the third protective layer and connects the second field dispersion layer and the third field dispersion layer, The semiconductor device according to claim 12, characterized in that it includes a third via that penetrates the fourth protective layer and connects the third field dispersion layer and the source wiring layer, or a combination thereof.

14. The length of the first via in the second direction is less than the length of the second via in the second direction, and the length of the second via in the second direction is less than the length of the third via in the second direction. The semiconductor device according to claim 13, characterized in that the first angle formed by the side wall of the first via in the second direction and the lower surface of the second protective layer is greater than the second angle formed by the side wall of the second via in the second direction and the lower surface of the third protective layer, and the second angle formed by the side wall of the second via in the second direction and the lower surface of the third protective layer is greater than or equal to the third angle formed by the side wall of the third via in the second direction and the lower surface of the fourth protective layer.

15. The drain electrode is A first drain electrode located on the channel layer, A second drain electrode located on the first drain electrode, A third drain electrode located on the second drain electrode, A fourth drain electrode located on the third drain electrode, or a combination thereof, The first drain electrode has a first projection that protrudes toward the second protective layer in the second direction and is located on the first protective layer, The second drain electrode has a second projection that protrudes toward the third protective layer in the second direction and is located on the second protective layer, The third drain electrode has a third projection that protrudes toward the fourth protective layer in the second direction and is located on the third protective layer, The semiconductor device according to claim 8, characterized in that the fourth drain electrode has a fourth projection that protrudes toward the source wiring layer in the second direction and is located on the third protective layer.

16. The length of the first projection in the second direction is smaller than the length of the second projection in the second direction. The length of the second projection in the second direction is smaller than the length of the third projection in the second direction. The length of the third projection in the second direction is smaller than the length of the fourth projection in the second direction. The semiconductor device according to claim 15, characterized in that the length of the fourth projection in the second direction is greater than the length of the first to third projections in the second direction.

17. The thickness of the first protrusion in the third direction is smaller than the thickness of the second protrusion in the third direction. The thickness of the second protrusion in the third direction is smaller than the thickness of the third protrusion in the third direction. The thickness of the third projection in the third direction is smaller than the thickness of the fourth projection in the third direction. The semiconductor device according to claim 15, characterized in that the thickness of the fourth projection in the third direction is greater than the thickness of the first to third projections in the third direction.

18. The aforementioned semiconductor device is The gate electrode layer comprises a plurality of such layers, The present invention further includes gate connecting portions that extend in the second direction between the plurality of gate electrode layers and connect the gate electrode layers, The first source electrode has a gate contact hole that passes over the gate connecting portion with the first protective layer in between, and exposes the gate connecting portion. It further includes a gate pull-out line located on the gate connecting portion and extending in the first direction, The semiconductor device according to claim 8, further comprising a gate via connecting the gate connecting portion and the gate lead line via the gate contact hole.

19. Channel layer and A barrier layer located on the channel layer and containing a material having a different energy band gap from the channel layer, A gate electrode layer located on the barrier layer and extending in a first direction, A gate semiconductor layer located between the barrier layer and the gate electrode layer, A source electrode and a drain electrode are connected to the channel layer and are located away from the gate electrode layer in a second direction different from the first direction, A field dispersion layer located on the gate electrode layer, connected to the source electrode, and overlapping the gate electrode layer in a third direction different from the first and second directions, It includes a source wiring layer located on the gate electrode layer, connected to the source electrode, and overlapping the field dispersion layer in the third direction, The length from any one point in the gate electrode layer and the source wiring layer overlapping in the third direction to one end of the source wiring layer in the second direction away from the source electrode is smaller than the length from any one point in the gate electrode layer and the field dispersion layer overlapping in the third direction to one end of the field dispersion layer in the second direction away from the source electrode. A semiconductor device characterized in that the thickness of the source wiring layer in the third direction is greater than the thickness of the field dispersion layer in the third direction.

20. Channel layer and A barrier layer located on the channel layer and containing a material having a different energy band gap from the channel layer, A gate electrode layer located on the barrier layer and extending in a first direction, A gate semiconductor layer located between the barrier layer and the gate electrode layer, A source electrode and a drain electrode are connected to the channel layer and are located away from the gate electrode layer in a second direction different from the first direction, A field dispersion layer located on the gate electrode layer, connected to the source electrode, and overlapping the gate electrode layer in a third direction different from the first and second directions, It includes a source wiring layer located on the field dispersion layer, connected to the source electrode, and overlapping the gate electrode layer in the third direction, One end of the source wiring layer in the second direction away from the source electrode overlaps with the field dispersion layer in the third direction, A semiconductor device characterized in that, in the third direction, the field dispersion layer is located between one end of the source wiring layer and the barrier layer.

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