Semiconductor equipment

Abstract

The present invention provides a semiconductor device that can suppress the decrease in the breakdown strength of a diode. [Solution] The semiconductor device comprises a semiconductor substrate 20, a transistor 100 provided on the semiconductor substrate and having a gate electrode 12, a source region 6a of a first conductivity type provided on one side of the gate electrode, and a base contact region 7 of a second conductivity type provided on the other side of the gate electrode, a diode 200 provided on the semiconductor substrate and adjacent to the transistor on one side of the gate electrode, and a field relaxation region 8b of a second conductivity type provided between the transistor and the diode on the semiconductor substrate and having its side surface in contact with the main electrode region, wherein the portion of the field relaxation region facing the base contact region protrudes toward the gate electrode in a plan view.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 describes that a trench-type SBD for a silicon carbide semiconductor device is composed of Schottky trenches between adjacent gate trenches and a conductive film that fills the Schottky trenches.

[0003] Patent Document 2 describes a MOS-type semiconductor device that incorporates SBDs on the same semiconductor substrate. In the MOS-type semiconductor device, first trenches that constitute a trench gate structure and second trenches that constitute trench sidewall SBDs are arranged alternately in a repeating manner. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2023-110951 [Patent Document 2] Japanese Patent Publication No. 2020-113633 [Overview of the project] [Problems that the invention aims to solve]

[0005] In a MOSFET semiconductor device incorporating an SBD, a pn junction is formed at the connection point between the SBD and the MOSFET. In some cases, an electric field may concentrate near this pn junction, potentially leading to a decrease in reliability.

[0006] The present disclosure aims to provide a semiconductor device that can suppress the decrease in the breakdown strength of a diode. [Means for solving the problem]

[0007] To achieve the above objective, one aspect of the present disclosure is a semiconductor device comprising: (a) a semiconductor substrate; (b) a transistor provided on the semiconductor substrate and having a gate electrode, a main electrode region of a first conductivity type provided on one side of the gate electrode, and a base contact region of a second conductivity type provided on the other side of the gate electrode; (c) a diode provided on the semiconductor substrate and adjacent to the transistor on one side of the gate electrode; and (d) a field relaxation region of a second conductivity type provided between the transistor and the diode on the semiconductor substrate, with its side surface in contact with the main electrode region; and (e) the portion of the field relaxation region facing the base contact region protruding toward the gate electrode in a plan view. [Effects of the Invention]

[0008] According to this disclosure, it is possible to provide a semiconductor device that can suppress the decrease in the breakdown strength of a diode. [Brief explanation of the drawing]

[0009] [Figure 1] This is an explanatory diagram showing an example of the planar shape of the source region, base contact region, and field relaxation region of a semiconductor device according to the first embodiment. [Figure 2] This is a cross-sectional view showing the longitudinal cross-sectional configuration of the semiconductor device as seen from direction AA in Figure 1. [Figure 3] Figure 1 is a cross-sectional view showing the longitudinal cross-sectional configuration of the semiconductor device as seen from the BB direction. [Figure 4] Figure 1 is a cross-sectional view showing the longitudinal cross-sectional configuration of the semiconductor device as seen from the CC direction. [Figure 5] This is an explanatory diagram showing an example of the planar shape of the source region, base contact region, and field relaxation region of a semiconductor device according to the first embodiment. [Figure 6] This is a longitudinal cross-sectional view along the X direction of the portion of the semiconductor device according to the first modification of the first embodiment in which a protrusion of the electric field relaxation region is provided. [Figure 7] This is a longitudinal cross-sectional view along the X direction of a portion of a semiconductor device according to the first modification of the first embodiment in which a protrusion in the field relaxation region is not provided. [Figure 8] This is a longitudinal cross-sectional view along the X direction of the portion of the semiconductor device according to the first modification of the first embodiment in which a p-type semiconductor region is provided. [Figure 9] This is an explanatory diagram showing an example of the arrangement positions of the gate electrode and Schottky conductor layer in a semiconductor device according to a second modification of the first embodiment. [Figure 10] This is an explanatory diagram showing an example of the planar shape of the source region, base contact region, and electric field relaxation region of a semiconductor device relating to a comparative example. [Modes for carrying out the invention]

[0010] Embodiments of this disclosure will be described below with reference to the drawings. In the drawings, identical or similar parts are denoted by the same or similar reference numerals, and redundant explanations are omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from the actual ones. Furthermore, there may be parts where the dimensional relationships and ratios differ between drawings. In addition, the embodiments shown below are illustrative examples of devices and methods for realizing the technical concept of this disclosure, and the technical concept of this disclosure does not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0011] As used herein, the "first main electrode region" means a semiconductor region that becomes either the source region or the drain region in a field-effect transistor (FET) or a static induction transistor (SIT). In an insulated gate bipolar transistor (IGBT), the "first main electrode region" means a semiconductor region that becomes either the source region or the collector region. Also, in a static induction thyristor (SI thyristor) or a gate turn-off thyristor (GTO), the "first main electrode region" means a semiconductor region that becomes either the anode region or the cathode region. The "second main electrode region" means a semiconductor region that becomes the other of the source region and the drain region in an FET or a SIT. In an IGBT, the "second main electrode region" means the region that becomes the other of the source region and the collector region. In an SI thyristor or a GTO, the "second main electrode region" means a semiconductor region that becomes the other of the anode region and the cathode region. Thus, if the "first main electrode region" is the source region, the "second main electrode region" means the drain region. If the "first main electrode region" is the source region, the "second main electrode region" means the collector region. If the "first main electrode region" is the anode region, the "second main electrode region" means the cathode region. If the bias relationship is exchanged, in an FET or the like, the functions of the "first main electrode region" and the "second main electrode region" can be exchanged. Further, when simply described as the "main electrode region" in this specification, it comprehensively means either the first main electrode region or the second main electrode region. <> <>

[0012] <> Also, the definitions of directions such as up and down in the following description are merely for convenience of explanation and do not limit the technical idea of the present disclosure. For example, if the object is rotated by 90° and observed, up and down are read as left and right, and if it is rotated by 180° and observed, up and down are read in reverse. Also, the "upper surface" may be read as the "front surface", and the "lower surface" may be read as the "back surface". <> <>

[0013] <> In the following description, the case where the first conductivity type is n-type and the second conductivity type is p-type will be exemplarily described. However, the conductivity types may be selected in the reverse relationship, i.e., the first conductivity type may be p-type and the second conductivity type may be n-type. Also, the “+” and “-” attached to “n” and “p” respectively mean semiconductor regions with relatively higher or lower impurity densities compared to the semiconductor regions without the attached “+” and “-”. However, even for semiconductor regions with the same “n” attached, it does not mean that the impurity densities of the respective semiconductor regions are exactly the same. Furthermore, in the following description, members and regions with the limitation of “the first conductivity type” and “the second conductivity type” added thereto mean members and regions made of semiconductor materials even without specific explicit limitation, which is obvious technically and logically.

[0014] [First Embodiment] ​Power semiconductor devices incorporating transistors such as MOSFETs and freewheeling diodes are subjected to voltages of several hundred volts. When current flows through the transistor in such a power semiconductor device, the depletion layer that forms between the n-type source region and the p-type field relaxation region of the transistor moves towards the diode side. For example, consider the case shown in the comparative example in Figure 10, where, in a plan view, the source region 6a of transistor 100x and the field relaxation region 8b adjacent to the freewheeling diode 200x are in contact by a linear boundary L1. Although not shown in the figure, the depletion layer forms along boundary L1. When current flows through the transistor from this state, boundary L1 moves towards the freewheeling diode 200x side, to the position indicated by the symbol L2. The depletion layer also moves to the position indicated by the symbol L2. When the depletion layer moves towards the freewheeling diode 200x side, the width of the field relaxation region 8b decreases, which may reduce the breakdown strength of the freewheeling diode 200x. Thus, even if the source region 6a is designed to have the same width as the field relaxation region 8b, when current flows through the transistor, the width of the field relaxation region 8b decreases, which may reduce the breakdown strength of the freewheeling diode 200x. Also, if the boundary L1 is linear, the structure of the transistor 100x becomes asymmetrical. This may cause the threshold voltage Vth to decrease, and variations in contact may lead to localized current concentration and a high electric field. Furthermore, variations in the characteristics of the transistor 100x may occur, which may affect reliability.

[0015] ≪Structure of Semiconductor Devices≫ As an example of a semiconductor device (semiconductor chip) according to the first embodiment, a trench-gate type MOSFET (metal-oxide-semiconductor field-effect transistor) will be described. As shown in Figures 1 to 4, the semiconductor device according to the first embodiment includes a transistor 100 as an active element and a diode 200 as a freewheeling diode (FWD). The freewheeling diode is provided, for example, to dissipate surge current generated when the transistor 100 is turned on or off. The transistor 100 is, for example, a MOSFET. The diode 200 is, for example, a Schottky barrier diode (SBD), but may also be a PiN diode. Figure 2 shows a vertical cross-section viewed from the AA direction in Figure 1. Figure 3 shows a vertical cross-section viewed from the BB direction in Figure 1. Figure 4 shows a vertical cross-section viewed from the CC direction in Figure 1. In addition, in Figure 1, the planar positions of the gate electrode 12 embedded in the gate trench 9 and the Schottky conductor layer 13 provided along the sides and bottom of the diode trench 10 are also shown to make the positional relationship easier to understand. The same applies to Figures 5 and 9.

[0016] As shown in Figure 1, the semiconductor device according to the first embodiment includes a transistor 100 and a diode 200 adjacent to the transistor 100 along the X direction in a plan view. Multiple transistors 100 are arranged adjacent to each other along the X direction (two or more rows) to form a set 100A. Multiple sets 100A are provided, and one diode 200 is provided between adjacent sets 100A. Then, sets 100A and diodes 200 are arranged alternately multiple times along the X direction, such as set 100A, diode 200, set 100A, diode 200. In addition, electric field relaxation regions 8a and 8b are provided in the semiconductor region between the transistor 100 and the diode 200. The semiconductor device according to the first embodiment can be made into a power semiconductor device (power device) that can carry a large current by arranging multiple transistors 100 to form a multi-channel structure. The transistor 100 arranged adjacent to the left side of the diode 200 in the plane of the paper is called transistor 101 to distinguish it from the other transistors. Transistor 100, located adjacent to diode 200 on the right side of the page, is called transistor 102 to distinguish it from other transistors. When transistors 101 and 102 are not distinguished from other transistors, they are simply called transistor 100. Transistor 101 is the rightmost (rightmost end) transistor along the X direction among multiple transistors belonging to a set 100A, and is adjacent to the left side of diode 200. Transistor 102 is the leftmost (leftmost end) transistor along the X direction among multiple transistors belonging to a set 100A, and is adjacent to the right side of diode 200. Transistor 102 is a mirror image of transistor 101 with respect to diode 200. Therefore, in this embodiment, the configuration of this technology will be explained using transistor 101 as an example.

[0017] As shown in Figure 2, the insulated gate semiconductor device according to the first embodiment includes a semiconductor substrate 20. The semiconductor substrate 20 is composed of a SiC semiconductor substrate containing silicon carbide (SiC). When the semiconductor substrate 20 is composed of a SiC semiconductor substrate, the insulated gate semiconductor device according to the first embodiment is a SiC semiconductor device. The semiconductor substrate 20 is not limited to a SiC substrate, and may be a semiconductor substrate made of a wide-bandgap semiconductor such as gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), or aluminum nitride (AlN), or it may be a silicon (Si) semiconductor substrate.

[0018] The semiconductor substrate 20 is a first conductivity type (n - It comprises a drift layer 2 of type n. A current diffusion layer (CSL) 3 of type n with a higher impurity concentration than the drift layer 2 is selectively provided on the upper surface of the drift layer 2. The lower surface of the current diffusion layer 3 is in contact with the upper surface of the drift layer 2. Note that the current diffusion layer 3 is not necessarily required, and if the current diffusion layer 3 is not provided, the drift layer 2 may be extended to the region of the current diffusion layer 3. On the upper surface of the current diffusion layer 3, a second conductivity type n is provided. - A base region 5 of type 3 is provided. The lower surface of the base region 5 is in contact with the upper surface of the current diffusion layer 3. If the current diffusion layer 3 is not provided, the lower surface of the base region 5 is in contact with the upper surface of the drift layer 2.

[0019] The upper surface of the base region 5 is provided with the first main electrode region (source region) 6a, 6b and the base contact region 7 of the transistor 101. The source regions 6a, 6b have a first conductivity type (n) with a higher impurity concentration than the drift layer 2. + This is a semiconductor region of type (p). The base contact region 7 has a higher impurity concentration than the base region 5, and is of type 2 conductivity (p). + This is a semiconductor region of type (p). The lower surfaces of source regions 6a and 6b and the lower surface of base contact region 7 are in contact with the upper surface of base region 5. Field relaxation regions 8a and 8b are provided on the upper side of base region 5. Field relaxation regions 8a and 8b have a higher impurity concentration than base region 5, and are of type 2 conductivity (p). +This is a semiconductor region of type 8a, and is a breakdown structure such as a guard ring (Field Limiting Ring). The lower surfaces of the field relaxation regions 8a and 8b are in contact with the upper surface of the base region 5.

[0020] A trench (gate trench) 9 for the transistor 101 is provided on the upper surface of the semiconductor substrate 20. The gate trench 9 penetrates the source regions 6a and 6b and the base region 5 from the upper surface of the source regions 6a and 6b in the direction normal to the upper surface of the source regions 6a and 6b (depth direction). The source region 6a is located to the right of the gate trench 9, and the source region 6b and the base contact region 7 are located to the left. In this embodiment, the direction connecting the right and left sides of the gate trench 9 is defined as the X direction. The source region 6b is interposed between the base contact region 7 and the gate trench 9, and the side surface of the source region 6b is in contact with the side surface of the base contact region 7. The source region 6a, the base region 5, and the current diffusion layer 3 are in contact with the right side surface of the gate trench 9. The source region 6b, the base region 5, and the current diffusion layer 3 are in contact with the left side surface of the gate trench 9. A gate bottom protection region 4a is provided at the bottom of the gate trench 9. The gate bottom protection region 4a has a higher impurity concentration than the base region 5, and is of the second conductivity type (p + This is a semiconductor region of type 3, and is provided inside the current diffusion layer 3. The gate bottom protection region 4a has a planar pattern that extends in a stripe shape in the depth direction and the front direction of the plane of the paper in Figure 2. If the current diffusion layer 3 is not provided, the side surface of the gate trench 9 may be in contact with the drift layer 2 instead of the current diffusion layer 3. The gate bottom protection region 4a may also be provided inside the drift layer 2. Furthermore, the gate trench 9 is not limited to the planar pattern that extends in a stripe shape as shown in Figure 1, and may have a dot-shaped planar pattern, although this is not shown.

[0021] As shown in Figure 2, a gate insulating film 11 is provided so as to cover the bottom (lower surface) and sides of the gate trench 9. As the gate insulating film 11, a single layer film of any one of the following can be used: silicon dioxide film (SiO2 film), silicon oxynitride (SiON) film, strontium oxide (SrO) film, silicon nitride (Si3N4) film, aluminum oxide (Al2O3) film, magnesium oxide (MgO) film, yttrium oxide (Y2O3) film, hafnium oxide (HfO2) film, zirconium oxide (ZrO2) film, tantalum oxide (Ta2O5) film, or bismuth oxide (Bi2O3) film, or a multilayer film made by stacking multiple of these.

[0022] Inside the gate trench 9, a gate electrode 12 is embedded with a gate insulating film 11 in between. The gate insulating film 11 and the gate electrode 12 constitute an insulated gate electrode structure (11,12). In other words, transistor 100 is a trench-type transistor. The set 100A shown in Figure 1 is also a set of multiple gate electrodes 12 arranged adjacent to each other along the X direction. Among the multiple gate electrodes 12 included in one set 100A, the gate electrode 12 adjacent to the diode 200, that is, the gate electrode 12 located furthest out along the X direction, is called gate electrode 12a to distinguish it from the other gate electrodes 12. Gate electrode 12a is the first gate electrode. When gate electrode 12a is not distinguished from the other gate electrodes 12, it is simply called gate electrode 12. As the material for the gate electrode 12, for example, a polysilicon film (doped polysilicon film) with high impurity concentrations of impurities such as phosphorus (P) or boron (B) can be used.

[0023] As shown in Figure 2, an interlayer insulating film 15 is selectively provided on the upper surface of the insulated gate electrode structure (11,12). The interlayer insulating film 15 is composed of single-layer films such as silicon oxide films doped with boron (B) and phosphorus (P) (BPSG films), silicon oxide films doped with phosphorus (P) (PSG films), undoped silicon oxide films that do not contain phosphorus (P) or boron (B) and are called "NSG", silicon oxide films doped with boron (B) (BSG films), silicon nitride films (Si3N4 films), or laminated films made by stacking multiple such films.

[0024] On the upper surface of the semiconductor substrate 20, a diode trench (diode trench) 10 is provided, spaced apart from the gate trench 9 of the transistor 101. As shown in Figure 1, the diode 200 is provided parallel to the gate trench 9. As shown in Figure 2, the diode trench 10 penetrates the electric field relaxation regions 8a and 8b and the base region 5 from the upper surface of the electric field relaxation regions 8a and 8b in the direction normal to the upper surface of the electric field relaxation regions 8a and 8b (depth direction). The electric field relaxation region 8a is located to the right of the diode trench 10, and the electric field relaxation region 8b is located to the left. As shown in Figure 1, the right side surface of the electric field relaxation region 8a is in contact with the left side surface of the source region 6b. The left side surface of the electric field relaxation region 8b is in contact with the right side surface of the source region 6a. The electric field relaxation regions 8a and 8b are provided to maintain the dielectric strength of the diode 200 against electric fields. As shown in Figure 2, the electric field relaxation region 8a, the base region 5, and the current diffusion layer 3 are in contact with the right side of the diode trench 10. The electric field relaxation region 8b, the base region 5, and the current diffusion layer 3 are in contact with the left side of the diode trench 10. A trench bottom protection region 4b is provided at the bottom of the diode trench 10. The trench bottom protection region 4b has a higher impurity concentration than the base region 5, and is composed of a second conductivity type (p + This is a semiconductor region of type 3, located inside the current diffusion layer 3. The trench bottom protection region 4b has a planar pattern that extends in a stripe shape in the depth direction and forward direction of the plane of the paper in Figure 2. If the current diffusion layer 3 is not provided, the side surface of the diode trench 10 may be in contact with the drift layer 2 instead of the current diffusion layer 3. Also, the trench bottom protection region 4b may be located inside the drift layer 2.

[0025] A Schottky conductor layer 13 is provided to cover the bottom (lower surface) and sides of the diode trench 10. The Schottky conductor layer 13 is made of, or contains, any of, titanium (Ti), molybdenum (Mo), tungsten (W), and nickel (Ni). The Schottky conductor layer 13 may be a single layer of any of the above materials, or a multilayer film of multiple materials. An electrode 14 is embedded inside the diode trench 10 with the Schottky conductor layer 13 interposed therebetween. The electrode 14 is made of, for example, a metallic material. The electrode 14 is made of, or mainly contains, either tungsten (W) and aluminum (Al). The Schottky conductor layer 13 is Schottky junctioned to the current diffusion layer 3. If the current diffusion layer 3 is not provided, the Schottky conductor layer 13 is Schottky junctioned to the drift layer 2. Thus, the diode 200 is a trench-type Schottky barrier diode.

[0026] The semiconductor device according to the first embodiment has a semiconductor region 19 in the planar position shown in Figure 1. As shown in Figure 4, the semiconductor region 19 is a second-conductivity type (p-type) semiconductor region with a higher impurity concentration than the base region 5, located below the base region 5. As shown in Figure 1, the longitudinal direction of the semiconductor region 19 in plan view extends along the X direction. More specifically, the longitudinal direction of the semiconductor region 19 in plan view extends over a plurality of transistors 100 and a plurality of diodes 200. The dimension of the semiconductor region 19 in the short direction in plan view is smaller than, for example, the spacing between the protrusions 81 described later. Therefore, it does not fill all of the Schottky region of the diode 200. Note that the longitudinal direction of the semiconductor region 19 in plan view may extend only over the transistors 100. As shown in Figure 4, the upper surface of the semiconductor region 19 is in contact with the lower surface of the base region 5. The lower side of the semiconductor region 19 is in contact with the gate bottom protection region 4a and the trench bottom protection region 4b. The semiconductor region 19 has the function of connecting the gate bottom protection region 4a and the trench bottom protection region 4b to the base region 5. The lower surface of the semiconductor region 19 is located shallower than the lower surfaces of the gate bottom protection region 4a and the trench bottom protection region 4b. By providing the semiconductor region 19, the breakdown withstand capability of the transistor 100 can be improved. In addition, by providing the semiconductor region 19, it becomes easier to fabricate the transistor 101 by matching (connecting) a diode to the structure of the transistor 101.

[0027] As shown in FIG. 2, a first main electrode (source electrode) 17 is provided so as to cover the source regions 6a and 6b, the electric field relaxation regions 8b and 8b, and the upper surface of the electrode 14. The lower surface of the source electrode 17 is in contact with the source regions 6a and 6b, the base contact region 7, the electric field relaxation regions 8b and 8b, and the upper surface of the electrode 14 and is electrically conductive. The source electrode 17 is provided separately from a gate wiring electrode (not shown) that is electrically connected to the gate electrode 12. The source electrode 17 has a barrier metal layer 16 on the lower surface side. The barrier metal layer 16 contacts the upper surface of the semiconductor substrate 20. The barrier metal layer 16 is selectively provided, for example, at positions overlapping the source regions 6a and 6b and the electric field relaxation regions 8b and 8b. The barrier metal layer 16 is made of a metal such as titanium nitride (TiN), titanium (Ti), or a stacked structure of TiN / Ti with Ti as the lower layer. The source electrode 17 other than the barrier metal layer 16 is made of a metal such as aluminum (Al), aluminum-silicon (Al-Si), aluminum-copper (Al-Cu), or copper (Cu). The above-described electrode 14 and the source electrode 17 may be integrally formed of the same material.

[0028] On the lower surface side of the drift layer 2, a second main electrode region (drain region) 1 of the first conductivity type (n + type) having a higher impurity concentration than the drift layer 2 is provided. The drain region 1 is composed of a semiconductor substrate (Si substrate) made of Si. A dislocation conversion layer or a recombination promotion layer, which is an n-type buffer layer having a higher impurity concentration than the drift layer 2 and a lower impurity concentration than the drain region 1, may be provided between the drift layer 2 and the drain region 1.

[0029] On the lower surface side of the drain region 1, a second main electrode (drain electrode) 18 is provided. As the drain electrode 18, for example, a single-layer film made of gold (Au) or a metal film laminated in the order of titanium (Ti), nickel (Ni), and Au from the drain region 1 side can be used, and a metal film such as molybdenum (Mo) or tungsten (W) may be laminated on the lowermost layer thereof. Also, nickel silicide (NiSi xA drain contact layer such as a film may be provided. When simply referred to as "main electrode," it comprehensively means either the first main electrode (source electrode) 17 or the second main electrode (drain electrode) 18.

[0030] The configurations of the source regions 6a and 6b, the base contact region 7, and the field relaxation regions 8b and 8b will be described in detail below with reference to Figure 5. In plan view, the field relaxation region 8a is a mirror image of the field relaxation region 8b with respect to the diode trench 10. Therefore, in this embodiment, only the configuration of the field relaxation region 8b will be described.

[0031] The approximate boundary D between transistors 100 belonging to group 100A is indicated by a dashed line. Boundary D is not actually visible to the naked eye. Also, the transistor 100 positioned adjacent to the left of transistor 101 is called transistor 103 to distinguish it from the other transistors. If transistor 103 is not distinguished from the other transistors, it is simply called transistor 100. Also, the gate electrode 12 of transistor 103 positioned adjacent to the left of gate electrode 12a is called gate electrode 12b to distinguish it from the other gate electrode 12. If gate electrode 12b is not distinguished from the other gate electrode 12, it is simply called gate electrode 12. The source region 6b on the left side of gate electrode 12a is provided as a continuous and integrated entity with the source region 6a on the right side of gate electrode 12b at boundary D. Between gate electrode 12a and gate electrode 12b, multiple island-shaped base contact regions 7 are provided arranged in a row along the Y direction. The base contact regions 7 are located equidistant from gate electrode 12a and 12b and are shared by transistors 101 and 103. Similarly, a base contact region 7 is provided between adjacent gate electrodes 12.

[0032] The electric field relaxation region 8b has a portion facing the base contact region 7 along the Y direction and a portion not facing it. Among the portions of the electric field relaxation region 8b facing the base contact region 7, the portion facing the base contact region 7 protrudes toward the gate electrode 12a in a plan view more than the non-facing portion. This protruding portion is called a convex portion 81. The dimension of the convex portion 81 along the Y direction is provided to be approximately the same as the dimension of the base contact region 7 along the Y direction. The distance between adjacent convex portions 81 along the Y direction is provided to be approximately the same as the distance between adjacent base contact regions 7 along the Y direction. Further, FIG. 5 shows a boundary L in a plan view between the source region 6a on the right side of the gate electrode 12a and the electric field relaxation region 8b. The boundary L is non-linear and bent in a rectangular wave shape along the convex portion 81. Although not shown, a depletion layer occurs along the boundary L. When the distance between the portion of the electric field relaxation region 8b where the convex portion 81 is provided and the gate electrode 12a is d1, and the distance between the portion of the electric field relaxation region 8b where the convex portion 81 is not provided and the gate electrode 12a is d3, d1 is smaller than d3 (d1 < d3). By providing the convex portion 81, the distance between the electric field relaxation region 8b and the gate electrode 12a can be partially reduced. Thereby, the depletion layer generated along the boundary L can be partially brought closer to the transistor 101 and partially moved away from the diode 200. Thereby, even when a current is passed through the transistor 100, it is possible to suppress the depletion layer from approaching the diode 200 too much and suppress a decrease in the breakdown voltage of the diode 200.

[0033] Hereinafter, the reason why the boundary between the source region 6a on the right side of the gate electrode 12a and the electric field relaxation region 8b is not uniformly brought closer to the gate electrode 12a will be described. When the distance between the base contact region 7 and the gate electrode 12a is d2 and the distance between adjacent gate electrodes 12 is d4, the above-mentioned d1 satisfies the following formula (1), and the above-mentioned d3 satisfies the following formula (2). d2×0.9≦d1≦d2×1.1 …(1) (d4 / 2)×0.9≦d3≦(d4 / 2)×1.1 …(2)

[0034] By setting d1 and d3 to the sizes described above, as shown in Figures 2, 3, and 5, the source region 6a on the right side of the gate electrode 12a becomes a mirror image of the source region 6b on the left side of the gate electrode 12a. The source region 6a on the right side of the gate electrode 12a has the same or similar shape as the source region 6a on the right side of the gate electrode 12b. By providing the source region 6a on the right side of the gate electrode 12a in the shape described above, the operation of the transistor becomes equal on both the right and left sides of the gate electrode 12a, allowing for balanced operation. Furthermore, by providing the source regions 6a and 6b as evenly as possible on the right and left sides of the gate electrode 12a, it is possible to prevent the electric field from concentrating at the boundary L between the source region 6a and the electric field relaxation region 8b. This further suppresses the decrease in the breakdown strength of the diode 200. It also suppresses the decrease in the breakdown strength of the transistor 101. Note that d1, d2, d3, and d4 described above are dimensions when no bias voltage is applied and no current is flowing through the transistor 100.

[0035] <<Main effects of the first embodiment>> In the semiconductor device according to the first embodiment, the portion of the electric field relaxation region 8b facing the base contact region 7 protrudes toward the gate electrode 12a in a plan view. More specifically, the portion of the electric field relaxation region 8b facing the base contact region 7 protrudes toward the gate electrode 12a in a plan view more than the portion not facing the base contact region 7. The voltage is higher at the pn junction directly below the depletion layer. With the configuration of the electric field relaxation region 8b described above, the region where the voltage is high can be shifted toward the transistor 101. This reduces the voltage load on the diode 200 and suppresses a decrease in the breakdown withstand capability of the diode 200. By optimizing the structure of the connection portion between the electric field relaxation region 8b and the source region 6a, a highly reliable device can be obtained while maintaining high breakdown voltage.

[0036] Furthermore, according to the semiconductor device of the first embodiment, the distances d1 and d3 shown in Figure 5 are set to the sizes defined by equations (1) and (2) above. Instead of uniformly extending the electric field relaxation region 8b toward the gate electrode 12a, a boundary L is provided so that the source region 6a on the right side of the gate electrode 12a and the source region 6b on the left side are mirror images of each other. As a result, the operation of the transistor can be made equal on both sides of the gate electrode 12a, and the tendency for the electric field to concentrate on one side of the gate electrode 12a can be suppressed. This makes it possible to improve the breakdown withstand capability of the diode 200 without significantly changing the breakdown withstand capability of the transistor 101.

[0037] <<First Modification of the First Embodiment>> The semiconductor device according to the first modification of the first embodiment differs from the semiconductor device according to the first embodiment described above in that the diode 200 is a planar Schottky barrier diode, as shown in Figures 6, 7, and 8. The other configurations of the semiconductor device according to the first modification of the first embodiment are the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted. Figure 6 is a longitudinal cross-sectional view along the X direction of the portion of the electric field relaxation region 8b where the protrusion 81 is provided. Figure 7 is a longitudinal cross-sectional view along the X direction of the portion of the electric field relaxation region 8b where the protrusion 81 is not provided. Figure 8 is a longitudinal cross-sectional view along the X direction of the portion where the semiconductor region 19 is provided. Even in this modification, the planar shapes of the source region 6a, the electric field relaxation region 8b, and the base contact region 7 are the same as in Figure 1. As shown in Figures 6, 7, and 8, the semiconductor substrate 20 does not have a diode trench 10. The Schottky conductor layer 13 is flat and its lower surface is Schottky bonded to the current diffusion layer 3. If the current diffusion layer 3 is not provided, the Schottky conductor layer 13 is Schottky bonded to the drift layer 2. Even with the semiconductor device according to this first modification of the first embodiment, the same effects as the semiconductor device according to the first embodiment described above can be obtained.

[0038] ≪Second Modification of the First Embodiment≫ In the semiconductor device according to the first embodiment, as shown in Figure 1, one Schottky conductor layer 13 was provided between pairs 100A, but this technology is not limited to this. In the semiconductor device according to the second modification of the first embodiment, as shown in Figure 9, multiple Schottky conductor layers 13 are provided between pairs 100A. Multiple Schottky conductor layers 13 of the diode 200 are provided in adjacent rows (two or more) along the X direction to form pairs 200A. Then, pairs 100A and pairs 200A are provided alternately multiple times along the X direction, such as pairs 100A, pairs 200A, pairs 100A, pairs 200A. Other configurations of the semiconductor device according to the second modification of the first embodiment are the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0039] To lower the Vf (forward voltage generated between the anode and cathode) of a Schottky barrier diode, multiple diodes 200 (Schottky conductor layers 13) can be arranged in a row along the X direction. To increase the number of Schottky conductor layers 13 included in one set 200A, the arrangement pitch P2 of the Schottky conductor layers 13 may be narrowed. For example, the arrangement pitch P2 of the Schottky conductor layers 13 may be smaller than the arrangement pitch P1 of the gate electrodes 12. Also, the number of Schottky conductor layers 13 arranged between sets 100A may be less than the number of gate electrodes 12 included in one set 100A. Furthermore, an electric field relaxation region 8c is provided between the Schottky conductor layers 13. Note that the diode 200 shown in Figure 9 may be of trench type or planar type. According to the semiconductor device according to the second modification of the first embodiment, since multiple diodes 200 are arranged in a row, the forward voltage of the diodes 200 can be lowered.

[0040] [Other embodiments] Although the first embodiment and its variations have been described above, the discussions and drawings that constitute part of this disclosure should not be understood as limiting this disclosure. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0041] For example, a MOSFET was given as an example of a semiconductor device according to the first embodiment and its modified form, n + Instead of drain region 1 of type p + This method is also applicable to insulated-gate bipolar transistors (IGBTs) with a collector region of a certain type. In addition to IGBTs alone, it is also applicable to reverse-conducting IGBTs (RC-IGBTs) and reverse-blocking insulated-gate bipolar transistors (RB-IGBTs). Furthermore, although transistor 100 was trench-type in the above embodiment, it may also be planar-type.

[0042] Furthermore, the configurations disclosed in the first embodiment and its variations can be combined as appropriate, within the bounds of consistency. Thus, this disclosure naturally includes various embodiments not described herein. Therefore, the technical scope of this disclosure is determined solely by the inventive features relating to the claims that are reasonable given the above description. [Explanation of Symbols]

[0043] 1 Drain area 2 Drift Layers 3 Current Diffusion Layer 4a,4b Gate bottom protection area 5 Base area 6a,6b Source area 7 Base Contact Area 8a,8b Electric field relaxation region 9 Gate Trench 10 Diode Trench 11 Gate insulating film 12,12a,12b gate electrode 13 Schottky conductor layer 14 electrodes 15 Interlayer insulating film 16 Barrier metal layer 17 Source electrodes 18 Drain electrode 19 Semiconductor field 20 Semiconductor substrates 81 Convex part 100, 101, 102, 103, 100x transistors 100A, 200A set 200,200x diodes d1, d2, d3, d4 distance L,L1 boundary P1, P2 placement pitch

Claims

1. Semiconductor substrate and A transistor provided on the semiconductor substrate and having a gate electrode, a first conductivity type main electrode region provided on one side of the gate electrode, and a second conductivity type base contact region provided on the other side of the gate electrode, A diode provided on the semiconductor substrate and adjacent to the transistor on one side of the gate electrode, A second conductivity type field relaxation region is provided between the transistor and the diode of the semiconductor substrate, and its side surface is in contact with the main electrode region, Equipped with, The portion of the electric field relaxation region facing the base contact region protrudes toward the gate electrode in a plan view. Semiconductor equipment.

2. If the direction connecting one side and the other side of the gate electrode is defined as the X direction, and the direction perpendicular to the X direction in a plan view is defined as the Y direction, The base contact regions are arranged in a plurality of island-like configurations along the Y direction. The main electrode region is also provided on the other side of the gate electrode and is in contact with the base contact region. The portion of the electric field relaxation region facing the base contact region protrudes toward the gate electrode in a plan view from the portion not facing the base contact region. The semiconductor device according to claim 1.

3. The device has multiple sets of gate electrodes arranged adjacent to each other along the X direction. The diodes are arranged between adjacent pairs of the aforementioned diodes. When the gate electrode adjacent to the diode among the plurality of gate electrodes included in the set is designated as the first gate electrode, the distance between the first gate electrode and the protruding portion is d1, and the distance between the first gate electrode and the base contact region is d2, then the condition d2 × 0.9 ≤ d1 ≤ d2 × 1.1 is satisfied. Let d3 be the distance between the first gate electrode and the non-protruding portion, and d4 be the distance between adjacent gate electrodes, then (d4 / 2) × 0.9 ≤ d3 ≤ (d4 / 2) × 1.1 satisfies, The semiconductor device according to claim 2.

4. The diode is a Schottky barrier diode having a Schottky conductor layer in contact with the semiconductor substrate. A semiconductor device according to claim 1 or 2.

5. The diode is a planar or trench type Schottky barrier diode. The semiconductor device according to claim 4.

6. The main electrode has contact with the upper surface of the main electrode region and the base contact region, and is electrically connected to the Schottky conductor layer. The semiconductor device according to claim 4.

7. If the direction connecting one side and the other side of the gate electrode is defined as the X direction, and the direction perpendicular to the X direction in a plan view is defined as the Y direction, The device has multiple sets of gate electrodes arranged adjacent to each other along the X direction. Multiple Schottky conductor layers are provided between adjacent pairs of these layers, arranged side by side along the X direction. The semiconductor device according to claim 4.

8. The arrangement pitch of adjacent Schottky conductor layers is smaller than the arrangement pitch of adjacent gate electrodes. The semiconductor device according to claim 7.

9. If the direction connecting one side and the other side of the gate electrode is defined as the X direction, and the direction perpendicular to the X direction in a plan view is defined as the Y direction, The device has multiple sets of gate electrodes arranged adjacent to each other along the X direction. The Schottky conductor layers are provided one at a time or in multiples arranged adjacent to each other along the X direction between adjacent pairs of the aforementioned pairs. The number of Schottky conductor layers arranged between the sets is less than the number of gate electrodes included in the set. The semiconductor device according to claim 4.

10. If the direction connecting one side and the other side of the gate electrode is defined as the X direction, and the direction perpendicular to the X direction in a plan view is defined as the Y direction, A semiconductor region of a second conductivity type is provided in contact with the lower surface of the base region of the transistor and whose longitudinal direction in plan view extends along the X direction, The semiconductor device according to claim 1.

11. The semiconductor substrate is a silicon carbide semiconductor substrate. The semiconductor device according to any one of claims 1 to 3.

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