Thin-film transistor

Abstract

The aim is to provide a thin-film transistor that can maintain its function even if foreign matter remains on the gate electrode. [Solution] The TFT 10 is disposed on the first main surface 21GSA with its lower surface 312 facing the first main surface 21GSA and comprises a gate electrode 31 whose first side surface 313A extends in a first direction, a gate insulating film 34 disposed on the upper side of the gate electrode 31, a semiconductor layer 35 disposed on the upper side of the gate insulating film 34 and including a first portion 351 which is disposed on the first side of the first side surface 313A via the gate insulating film 34 and extends in a first direction, a source electrode 32 disposed in a position that does not overlap with the gate electrode 31 when viewed from above, and a drain electrode 33 disposed in a position that does not overlap with the gate electrode 31 when viewed from above and is aligned with the source electrode 32 in a first direction, and the source electrode 32 and the drain electrode 33 each contact the first portion 351 at different positions in the first direction.

Description

Technical Field

[0001] The present disclosure relates to thin film transistors.

Background Art

[0002] Conventionally, as an example of a thin film transistor (hereinafter also referred to as a TFT), the one described in Patent Document 1 is known. This TFT includes a gate electrode having sidewalls and an upper surface, a gate insulating layer covering the upper surface of the gate electrode, a first source / drain region covering this gate insulating layer, a second source / drain region arranged at a position adjacent to the sidewalls of the gate electrode, a channel region covering the sidewalls of the gate electrode and located between the first source / drain region and the second source / drain region. In this case, the length of the channel region is approximately equal to the thickness of the gate electrode. Accordingly, it is said that a TFT having a channel region shorter than a channel region that can be formed by performing patterning using photolithography can be provided.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the manufacturing process of a bottom-gate TFT, where the gate electrode is located beneath the semiconductor layer, foreign matter may be generated on the gate electrode when it is formed on the substrate. This foreign matter may remain even after cleaning, etching, and resist stripping. If such foreign matter remains on the gate electrode and a gate insulating film covering the gate electrode, and a semiconductor layer covering this gate insulating film, are then provided, the gate insulating film and semiconductor layer may not be formed properly on the foreign matter, leaving it exposed. In such cases, if the source / drain region is formed to cover the gate insulating film and semiconductor layer, the gate electrode and the source / drain region may become electrically connected via the foreign matter, resulting in a problem where a properly functioning TFT cannot be obtained. The TFT described in Patent Document 1 cannot solve this problem because the first source / drain region is positioned to cover the upper surface of the gate electrode.

[0005] This disclosure was completed based on the circumstances described above, and aims to provide a thin-film transistor whose function is easily maintained even if foreign matter remains on the gate electrode. [Means for solving the problem]

[0006] The thin-film transistor of this disclosure has a top surface, a bottom surface and a side surface, and is disposed on the first main surface with the bottom surface facing the first main surface of the substrate, the first side surface of which extends in a first direction, a gate electrode disposed on the upper side of the gate electrode, a semiconductor layer disposed on the upper side of the gate insulating film and including a first portion disposed on the first side surface of the gate electrode via the gate insulating film and extending in a first direction, a source electrode disposed at a position that does not overlap with the gate electrode when viewed from above, and a drain electrode disposed at a position that does not overlap with the gate electrode when viewed from above, and is arranged in a manner parallel to the source electrode in a first direction, wherein the source electrode and the drain electrode are in contact at different positions in the first direction of the first portion. [Effects of the Invention]

[0007] According to this disclosure, it is possible to provide a thin-film transistor whose function is easily maintained even if foreign matter remains on the gate electrode. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a schematic plan view of a liquid crystal panel equipped with a TFT according to an embodiment. [Figure 2] Figure 2 is a schematic cross-sectional view of a liquid crystal panel equipped with a TFT according to an embodiment. [Figure 3] Figure 3 is a schematic plan view showing the pixel arrangement in the display area of ​​the array substrate provided in the liquid crystal panel. [Figure 4] Figure 4 is a perspective view of the TFT according to this embodiment. [Figure 5] Figure 5 is a cross-sectional view of the TFT according to this embodiment. [Figure 6] Figure 6 is a perspective view of the intersection point where gate wiring and source wiring intersect. [Figure 7] Figure 7 is a cross-sectional view of the intersection. [Modes for carrying out the invention]

[0009] First, embodiments of this disclosure will be listed and described. (1) The thin-film transistor of the present disclosure has an upper surface, a lower surface and a side surface, and is disposed on the first main surface with the lower surface facing the first main surface of the substrate, and comprises a gate electrode having the first side surface of the side surface extending in a first direction, a gate insulating film disposed on the upper side of the gate electrode, a semiconductor layer disposed on the upper side of the gate insulating film and including a first portion disposed on the first side surface of the gate electrode via the gate insulating film and extending in a first direction, a source electrode disposed at a position that does not overlap with the gate electrode when viewed from above, and a drain electrode disposed at a position that does not overlap with the gate electrode when viewed from above, and is arranged in a manner parallel to the source electrode in a first direction, wherein the source electrode and the drain electrode are in contact at different positions in the first direction of the first portion.

[0010] In the thin-film transistor according to this disclosure, the source electrode and drain electrode are positioned so as not to overlap with the gate electrode when viewed from above. Furthermore, the source electrode and drain electrode are in contact with a first portion of the semiconductor layer, which is located on the upper side of the first side surface of the gate electrode, via a gate insulating film. Therefore, even if foreign matter remains on the gate electrode during the manufacturing process of the thin-film transistor, electrical connection between the gate electrode and the source electrode, and between the gate electrode and the drain electrode, is suppressed through that foreign matter. Accordingly, this disclosure aims to provide a thin-film transistor whose function is easily maintained even if foreign matter remains on the gate electrode.

[0011] (2) In the thin-film transistor described in (1), the semiconductor layer may include a source contact portion which extends from the lower end of the first portion to the upper side of the first main surface and contacts the source electrode, and a drain contact portion which extends from the lower end of the first portion to the upper side of the first main surface at a position different from the source contact portion and contacts the drain electrode.

[0012] In this case, the source contact portion and drain contact portion of the semiconductor layer are formed extending from the lower end of the first portion to the upper side of the first main surface, and the source electrode and drain electrode are in contact with these source contact portion and drain contact portion. That is, in a thin-film transistor, the source electrode and drain electrode can be positioned spaced apart from the first side surface of the gate electrode when viewed from above. Therefore, even if foreign matter remains on the first side surface of the gate electrode during the manufacturing process of the thin-film transistor, electrical connection between the gate electrode and the source electrode, and between the gate electrode and the drain electrode, is suppressed through that foreign matter.

[0013] (3) In the thin-film transistor described in (2), the gate insulating film is not formed in a position that overlaps with the source contact portion and the drain contact portion, the source electrode may be positioned above the source contact portion, and the drain electrode may be positioned above the drain contact portion.

[0014] In this case, the source contact portion and drain contact portion of the semiconductor layer are placed on the first main surface of the substrate without a gate insulating film in between. The source electrode and drain electrode are then placed above the source contact portion and drain contact portion. Since the gate insulating film is not placed below the source contact portion and drain contact portion, the position of the source electrode and drain electrode is less likely to be higher than that of the gate electrode. Therefore, even if foreign matter remains on the gate electrode, it is more reliably suppressed that the gate electrode and source electrode, and the gate electrode and drain electrode, will be electrically connected through that foreign matter.

[0015] (4) In the thin-film transistor described in any of (1) to (3), the first side surface slopes downward from the top surface to the bottom surface, and the semiconductor layer does not have to be located on the upper side of the second side surface of the gate electrode that is opposite to the first side surface, or on the upper side of the top surface.

[0016] In this case, the semiconductor layer positioned to overlap the gate electrode when viewed from above is only the first portion. Therefore, even if foreign matter remains on the part of the gate electrode other than the first portion during the manufacturing process, defects caused by the foreign matter are less likely to occur in the semiconductor layer. This can improve the yield of thin-film transistors. Furthermore, since the first side surface slopes downward from the top surface to the bottom surface, it becomes easier to make the thickness of the gate insulating film formed on the first side surface thinner than the thickness of the gate insulating film formed on the top surface, improving the design flexibility of thin-film transistors.

[0017] (5) In the thin-film transistor described in any of (1) to (4), a channel region may be formed in the aforementioned first portion.

[0018] In this case, in the semiconductor layer, a channel region is formed in a first portion that does not overlap with the source electrode and the drain electrode when viewed from above. Therefore, even if foreign matter remains on the gate electrode, the gate electrode and the source electrode, and the gate electrode and the drain electrode are prevented from being electrically connected through the foreign matter even during the driving of the thin film transistor.

[0019] <Details of Embodiments of the Present Disclosure> The schematic configuration of an embodiment of the present disclosure will be described with reference to FIGS. 1 to 7. In this specification, the TFT (thin film transistor) 10 provided in the liquid crystal panel 1 is exemplified. <000009​​​​​​Referring to Figure 1, the configuration of the liquid crystal panel 1 will be explained. As shown in Figure 1, the liquid crystal panel 1 has a rectangular shape when viewed in plan view. The central part of the screen of the liquid crystal panel 1 is the display area AA where the image is displayed. The outer edge of the screen of the liquid crystal panel 1, which is frame-like and surrounds the display area AA, is the non-display area NAA where the image is not displayed. In Figure 1, the area enclosed by the dashed line is the display area AA.

[0022] As shown in Figure 1, the liquid crystal panel 1 is formed by bonding together a pair of substrates 20 and 21. Of the pair of substrates 20 and 21, the one placed on the front side is the opposing substrate (CF substrate) 20, and the one placed on the back side is the array substrate (active matrix substrate) 21. Both the opposing substrate 20 and the array substrate 21 are made of glass substrates 20GS and 21GS that are almost transparent and have excellent light transmission, with various films laminated on the inner surface. The substrates 20GS and 21GS mainly contain, for example, alkali-free glass. The array substrate 21 is larger than the opposing substrate 20, and a part of it protrudes laterally from the opposing substrate 20. A driver 13 for driving the display and a flexible substrate 14 are mounted (connected) to the protruding portion 21A of the array substrate 21 via an ACF (Anisotropic Conductive Film). The flexible substrate 14 has a structure in which a large number of wiring patterns are formed on a substrate that has insulating and flexible properties. A control circuit board 15 is connected to the flexible circuit board 14, which supplies various input signals to the driver 13 from an external source.

[0023] A liquid crystal display is constructed by combining a liquid crystal panel 1 with a backlight device (not shown) that illuminates the liquid crystal panel 1 with light. The configuration of the backlight device is as is known, and includes, for example, a light source such as an LED and an optical component that converts the light from the light source into planar light by applying an optical effect. The backlight has its light-emitting surface positioned below the liquid crystal panel 1 and illuminates the liquid crystal panel 1 from below.

[0024] Next, with reference to Figure 2, the cross-sectional configuration of the liquid crystal panel 1 will be outlined. As shown in Figure 2, the pair of substrates 20 and 21 are arranged opposite each other with a gap in the Z-axis direction, which is the normal direction to the main surfaces of the substrates 20 and 21. Between the pair of substrates 20 and 21, at least a liquid crystal layer 22 and a sealing portion 23 that seals the liquid crystal layer 22 are interposed. The liquid crystal layer 22 contains liquid crystal molecules, which are substances whose optical properties change when an electric field is applied. The sealing portion 23 as a whole has a rectangular frame shape when viewed in plan, and surrounds the liquid crystal layer 22 all around in a non-display area (NAA). This sealing portion 23 maintains a gap equal to the thickness of the liquid crystal layer 22. Polarizing plates 24 are attached to the outer surfaces of the pair of substrates 20 and 21.

[0025] Next, with reference to Figure 3, an overview of the pixel arrangement in the display area AA of the array substrate 21 will be described. As shown in Figure 3, multiple gate wirings (scanning wirings) GL and source wirings (pixel wirings) SL are arranged in a grid pattern on the inner surface of the array substrate 21. The inner surface of the array substrate 21 on which these grid-like gate wirings GL and source wirings SL are arranged is the first main surface 21GSA, which faces the front side of the pair of main surfaces of the substrate 21GS that constitutes the array substrate 21. The gate wirings GL extend along the Y-axis direction, traversing the display area AA. Multiple gate wirings GL are arranged side by side with spacing in the X-axis direction. The source wirings SL extend along the X-axis direction, traversing the display area AA, and are almost perpendicular (intersecting) with the gate wirings GL. Multiple source wirings SL are arranged with spacing in the Y-axis direction. The point where the gate wirings GL and source wirings SL intersect is called the intersection point CP.

[0026] A TFT 10 and a pixel electrode PE are provided near the intersection point CP. The TFT 10 and the pixel electrode PE are arranged in a matrix (matrix) with spacing along the X-axis and Y-axis directions. The gate wiring GL, source wiring SL, and pixel electrode PE are connected to the TFT 10. The TFT 10 has at least a gate electrode 31 to which the gate wiring GL is connected, a source electrode 32 to which the source wiring SL is connected, a drain electrode 33 to which the pixel electrode PE is connected, and a semiconductor layer 35 connected to the source electrode 32 and the drain electrode 33. Of the gate wiring GL, the portion that overlaps with the first portion 351, which is part of the semiconductor layer 35, when viewed from above, is the gate electrode 31. In Figure 3, the first portion 351 of the semiconductor layer 35 is shown in a shaded state. Also, of the gate wiring GL, the portion adjacent to the pixel electrode PE is the gate electrode 31. In this specification, the Y-axis direction in which the gate wiring GL and the gate electrode 31 extend is also referred to as the first direction. Of the source wiring SL, the portion adjacent to the intersection point CP has a predetermined width in the X-axis direction and extends in the Y-axis direction, superimposing on the source contact portion 352, which is part of the semiconductor layer 35, when viewed from above. This superimposed portion becomes the source electrode 32. The drain electrode 33 also superimposes on the drain contact portion 353, which is part of the semiconductor layer 35, when viewed from above.

[0027] The TFT10 is an active element that controls the current flowing through the semiconductor layer 35, which is made of semiconductor material, by applying a voltage to the gate electrode 31, and has the function of switching the current between the source electrode 32 and the drain electrode 33. Specifically, the TFT10 is driven based on the scanning signal supplied to the gate electrode 31 by the gate wiring GL. Then, the potential related to the image signal (data signal) supplied to the source electrode 32 by the source wiring SL is supplied to the drain electrode 33 via the semiconductor layer 35. As a result, the pixel electrode PE is charged to the potential related to the image signal. The pixel electrode PE is located in a region surrounded by the gate wiring GL and the source wiring SL, and has a longitudinal shape with the X-axis direction as its longitudinal direction.

[0028] The configuration of the TFT10 will be described in detail with reference to Figures 4 and 5. In addition to the configuration described above, the TFT10 includes a gate insulating film 34. The configuration of the TFT10 will be described below, starting from the bottom layer.

[0029] As shown in Figures 4 and 5, the gate electrode 31 is directly provided on the upper side of the first main surface 21GSA of the substrate 21GS. The gate electrode 31 has a rectangular shape with length in the first direction (Y-axis direction) when viewed from above. The gate electrode 31 has an upper surface 311, a lower surface 312, and a side surface 313. The front surface of the gate electrode 31 is the upper surface 311. The lower surface 312 is the surface opposite to the upper surface 311 in the Z-axis direction, and faces and contacts the first main surface 21GSA of the substrate 21GS. The upper surface 311 and the lower surface 312 are elongated surfaces parallel to the X-axis direction and the Y-axis direction, with the longer side direction coinciding with the Y-axis direction and the shorter side direction coinciding with the X-axis direction. The width dimension of the upper surface 311 in the X-axis direction is smaller than the width dimension of the lower surface 312 in the X-axis direction.

[0030] The side surface 313 is adjacent to the upper surface 311 and the lower surface 312, forming the end faces on both sides of the gate electrode 31 in the X-axis direction. Of the side surfaces 313, the one positioned close to the source electrode 32 and the drain electrode 33 is designated as the first side surface 313A. Of the side surfaces 313, the one positioned on the opposite side from the first side surface 313A in the X-axis direction, and positioned close to the aforementioned pixel electrode PE, is designated as the second side surface 313B. The length direction of the first side surface 313A and the second side surface 313B coincides with the first direction (Y-axis direction). Furthermore, since the width dimension of the upper surface 311 is smaller than the width dimension of the lower surface 312, the first side surface 313A and the second side surface 313B slope downward from the upper surface 311 to the lower surface 312. That is, the cross-section of the gate electrode 31 cut in the XZ plane is trapezoidal (forward tapered) with the width narrowing from the lower surface 312 to the upper surface 311.

[0031] The gate wiring GL and gate electrode 31 consist of multiple laminated metal films made of different types of metal materials, for example, the lower metal film is made of titanium (Ti) and the upper metal film is made of copper (Cu).

[0032] The gate insulating film 34 is arranged in a laminated manner on the first main surface 21GSA of the substrate 21GS and on the upper side of the gate electrode 31. As shown in Figures 4 and 5, the gate insulating film 34 is formed to cover the upper surface 311, the first side surface 313A, and the second side surface 313B of the gate electrode 31. On the other hand, the gate insulating film 34 is not formed on the upper side of the portion of the first main surface 21GSA that extends in the X-axis direction adjacent to the first side surface 313A of the gate electrode 31. Specifically, the gate insulating film 34 is not formed on the upper side of the portion of the first main surface 21GSA that overlaps with the source contact portion 352 and the drain contact portion 353, which will be described later, and on the upper side of the region between the source contact portion 352 and the drain contact portion 353 in the Y-axis direction. The gate insulating film 34 may or may not be formed on the upper side of the other portions of the first main surface 21GSA.

[0033] The gate insulating film 34 is a type of inorganic material (inorganic resin material) such as SiO2 (silicon oxide, silicon oxide) or SiN x It is made of silicon nitride or the like. The gate insulating film 34 is interposed between the gate wiring GL and gate electrode 31 and the semiconductor layer 35 to keep them in an insulating state.

[0034] The semiconductor layer 35 is a layer made of semiconductor material and, as shown in Figures 4 and 5, comprises a first portion 351, a source contact portion 352, and a drain contact portion 353. The first portion 351 is a portion of the semiconductor layer 35 that, when viewed from above, overlaps the first side surface 313A of the gate electrode 31, and is arranged with respect to the first side surface 313A via the gate insulating film 34, extending in a first direction (Y-axis direction). The first portion 351 is arranged to cover from above the portion where the gate insulating film 34 covers the first side surface 313A of the gate electrode 31, and has a rectangular shape with length in the first direction when viewed from above. The first side surface 313A of the gate electrode 31 is sloped downwards, and the portion of the gate insulating film 34 provided on the upper layer of the first side surface 313A is also sloped downwards. Therefore, the first portion 351 as a whole is also sloped downwards. The upper end of the first portion 351 reaches the upper end of the first side surface 313A of the gate electrode 31, but does not reach the upper side of the top surface 311. In other words, when viewed from above, the first portion 351 is positioned to overlap the first side surface 313A of the gate electrode 31, but does not overlap the top surface 311 or the second side surface 313B of the gate electrode 31.

[0035] As mentioned above, the gate insulating film 34 is not formed on the upper side of the portion of the first main surface 21GSA that extends in the X-axis direction adjacent to the first side surface 313A of the gate electrode 31. For this reason, the lower end portion 351U of the first portion 351 is in contact with the first main surface 21GSA of the substrate 21GS. The source contact portion 352 and the drain contact portion 353 of the semiconductor layer 35 are portions that extend from the lower end portion 351U of the first portion 351 to the upper side of the first main surface 21GSA at different positions in the first direction (Y-axis direction).

[0036] The source contact portion 352 is formed by extending with a predetermined width from one end of the first portion 351 in the first direction (Y-axis direction) toward a direction intersecting the first direction (Y-axis direction) and moving away from the gate electrode 31. The one end is the end that is close to the source wiring SL connected to the source electrode 32 of the TFT 10. In this embodiment, the source contact portion 352 is formed by extending with a predetermined width in the first direction (Y-axis direction) toward a direction toward a direction toward a direction toward a gate electrode 31 in the X-axis direction which is perpendicular to the first direction (Y-axis direction). That is, the source contact portion 352 has a rectangular shape with a long side extending in the X-axis direction and a short side extending in the Y-axis direction when viewed from above, and the short side on the side where the gate electrode 31 is located is in contact with the first portion 351.

[0037] The drain contact portion 353 is formed by extending with a predetermined width from the end of the first portion 351 opposite to the one side described above in the first direction (Y-axis direction), toward the direction away from the gate electrode 31 in a direction intersecting the first direction (Y-axis direction). In this embodiment, the drain contact portion 353 is formed by extending with a predetermined width in the first direction (Y-axis direction), toward the direction away from the gate electrode 31 in the X-axis direction which is perpendicular to the first direction (Y-axis direction), similar to the source contact portion 352. That is, the drain contact portion 353 is rectangular in shape, having a long side extending in the X-axis direction and a short side extending in the Y-axis direction when viewed from above, similar to the source contact portion 352, with the short side on the side where the gate electrode 31 is located in contact with the first portion 351. As a result, the semiconductor layer 35 in the region between the source contact portion 352 and the drain contact portion 353 in the first direction (Y-axis direction) appears to be cut out. In other words, the semiconductor layer 35 is not formed in the region between the source contact portion 352 and the drain contact portion 353 in the Y-axis direction. The first portion 351 is interposed between the source contact portion 352 and the drain contact portion 353 and extends in the first direction (Y-axis direction), and is not directly connected to the source contact portion 352 and the drain contact portion 353.

[0038] In this manner, the source contact portion 352 and the drain contact portion 353 are arranged side by side with a gap between them in the first direction (Y-axis direction). Furthermore, the source contact portion 352 and the drain contact portion 353 are positioned so as not to overlap the gate electrode 31 when viewed from above. In addition, the gate insulating film 34 is not formed on the lower side of the source contact portion 352 and the drain contact portion 353, and is provided directly on the upper side of the first main surface 21GSA without the gate insulating film 34 in between.

[0039] The semiconductor material constituting the semiconductor layer 35 according to this embodiment is mainly composed of an oxide semiconductor material. "Main component" refers to the component present in the largest quantity among the constituent components of the semiconductor layer 35. The oxide semiconductor may be amorphous or crystalline, but amorphous oxide semiconductors are preferably used. This is because, when a semiconductor film is made of an oxide semiconductor, the charge mobility is much higher than that of an amorphous silicon semiconductor film, allowing it to be driven at a lower voltage.

[0040] The semiconductor layer 35 according to this embodiment is mainly composed of an In-Ga-Zn oxide semiconductor material (IGZO) containing In (indium), Ga (gallium), and Zn (zinc), which is a type of oxide semiconductor material. The composition ratio of In, Ga, and Zn in the In-Ga-Zn oxide semiconductor material is not particularly limited. The composition ratio of In, Ga, and Zn may be In:Ga:Zn=1:1:1, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:2, etc., and the composition ratio can be appropriately selected. The In-Ga-Zn oxide semiconductor material may be amorphous or crystalline.

[0041] In this embodiment, the semiconductor layer 35 has its source contact portion 352 and drain contact portion 353 subjected to a low-resistance treatment during the manufacturing process, thereby reducing their resistance. In Figures 3 and 4, the first portion 351, which is a non-low-resistance region of the semiconductor layer 35 that has not undergone low-resistance treatment, is shown as a shaded area. As mentioned above, the first portion 351 is the portion of the semiconductor layer 35 that superimposes on the first side surface 313A of the gate electrode 31 when viewed from above. The first portion 351, which is a non-low-resistance region of the semiconductor layer 35, is formed as a channel region having semiconductor properties. That is, charge movement is possible in the first portion 351 only under specific conditions (when a scanning signal is supplied to the gate electrode 31). The low-resistance region of the semiconductor layer 35, which is designed to reduce resistance, has an extremely low resistivity, for example, about 1 / 10000000000 to 1 / 100, compared to the non-low-resistance region, and is always capable of charge transfer, thus functioning as a conductor. Therefore, the source contact portion 352 and the drain contact portion 353, which are designated as the low-resistance region, each possess the properties of a conductor.

[0042] The low-resistance treatment of the semiconductor layer 35 is selectively applied to the source contact portion 352 and the drain contact portion 353 of the semiconductor layer 35, while the first portion 351 is not subjected to the low-resistance treatment. The low-resistance treatment includes, for example, plasma treatment using gases such as NH3, H2, N2, and He, and annealing treatment. Specifically, gate wiring GL, gate electrode 31, and gate insulating film 34 are provided on the first main surface 21GSA of the substrate 21GS, and then the semiconductor layer 35 is provided. After that, the low-resistance treatment is performed from the front side of the substrate 21GS through a predetermined mask having openings in the portions corresponding to the source contact portion 352 and the drain contact portion 353. This selectively applies the low-resistance treatment to the source contact portion 352 and the drain contact portion 353. The low-resistance treatment may also be performed from the back side of the substrate 21GS. Specifically, the gate insulating film 34 may be used as a mask, and the source contact portion 352 and drain contact portion 353 of the semiconductor layer 35 that are not covered by the gate insulating film 34 may be selectively subjected to a low-resistance treatment. On the other hand, the first portion 351 that is covered by the gate insulating film 34 is not subjected to a low-resistance treatment.

[0043] As shown in Figures 4 and 5, the source electrode 32 and drain electrode 33 are positioned on the upper side of the source contact portion 352 and drain contact portion 353, respectively. As shown in Figure 3, the portion of the source wiring SL adjacent to the intersection portion CP has a predetermined width in the X-axis direction and extends in the Y-axis direction toward the source contact portion 352. The source electrode 32 is formed by the tip of this extended portion overlapping the upper side of the source contact portion 352. In other words, a portion of the source wiring SL has a portion that extends with a predetermined width in the X-axis direction, and the portion of that portion that overlaps the source contact portion 352 is the source electrode 32. Since the source contact portion 352 has a rectangular shape with length in the X-axis direction when viewed from above, the shape of the source electrode 32 provided on its upper side is also a rectangular shape with length in the X-axis direction when viewed from above. The end of the source electrode 32 closest to the gate electrode 31 is spaced apart from the portion where the source contact portion 352 contacts the lower end portion 351U of the first portion 351. In other words, the source electrode 32 does not directly contact the first portion 351, but contacts the first portion 351 via the source contact portion 352.

[0044] The drain electrode 33 is formed so as to overlap the drain contact portion 353 in an island-like manner when viewed from above. Like the source electrode 32, the drain electrode 33 has a rectangular shape with length in the X-axis direction when viewed from above. The drain electrode 33 is positioned so as to be aligned with the source electrode 32 in the first direction (Y-axis direction) when viewed from above, in a position that does not overlap the source electrode 32. The end of the drain electrode 33 that is close to the gate electrode 31 is spaced apart from the part of the drain contact portion 353 that contacts the lower end 351U of the first portion 351. The end of the drain electrode 33 that is not close to the gate electrode 31 is connected to the pixel electrode PE.

[0045] Thus, the drain electrode 33 is not in direct contact with the first portion 351, but is in contact with the first portion 351 via the drain contact portion 353. Furthermore, the source electrode 32 and the drain electrode 33 are in contact with the first portion 351 at different positions in the first direction (Y-axis direction) via the source contact portion 352 and the drain contact portion 353, respectively. Here, the source contact portion 352 and the drain contact portion 353 are connected via the first portion 351, and are not directly connected to each other. For this reason, the source electrode 32, which is positioned above the source contact portion 352, and the drain electrode 33, which is positioned above the drain contact portion 353, are electrically connected via the first portion 351. In this way, when no voltage is applied to the gate electrode 31, direct electrical connection between the source electrode 32 and the drain electrode 33 is avoided.

[0046] The source electrode 32, source wiring SL, and drain electrode 33, like the gate wiring GL and gate electrode 31, consist of multiple laminated metal films made of different types of metal materials. For example, the lower metal film is made of titanium (Ti), and the upper metal film is made of copper (Cu).

[0047] The TFT10 according to this embodiment has the structure described above, and its manufacturing method will now be explained. This manufacturing process includes a gate electrode formation step for forming the gate electrode 31, a gate insulating film formation step for forming the gate insulating film 34, a semiconductor layer formation step for forming the semiconductor layer 35, a resistance reduction step for reducing the resistance of the source contact portion 352 and drain contact portion 353 of the semiconductor layer 35, and a source / drain electrode formation step for forming the source electrode 32 and drain electrode 33.

[0048] The gate electrode formation process involves depositing a conductive metal film of a predetermined thickness onto the entire upper surface of the first main surface 21GSA of the substrate 21GS by sputtering, followed by patterning. "Patterning" refers to the processing of a film based on a general photolithography method. Specifically, a photoresist film is deposited on the film to be processed, the photoresist film is exposed using an exposure apparatus through a photomask having a predetermined aperture pattern, the photoresist film is developed, and etching is performed through the developed photoresist film to process the film to be processed, i.e., patterning is achieved. This forms the gate wiring GL and the gate electrode 31. The gate wiring GL and the gate electrode 31 are formed by etching so that the first side surface 313A and the second side surface 313B each slope downward from the upper surface 311 to the lower surface 312. That is, the gate wiring GL and the gate electrode 31 are formed to have a forward taper shape as shown in Figures 4 and 5 when viewed from the first direction in a side view.

[0049] In the gate insulating film formation process, a silicon compound film or the like is deposited and patterned onto the entire upper surface of the first main surface 21GSA, on which the gate wiring GL and gate electrode 31 are formed by plasma CVD (Chemical Vapor Deposition). This forms the gate insulating film 34. At this time, the gate insulating film 34 is not formed on the upper layer side of the portion of the first main surface 21GSA that extends in the X-axis direction adjacent to the first side surface 313A of the gate electrode 31. In other words, the gate insulating film 34 is not formed in the area where the source contact portion 352 and drain contact portion 353 are formed in the subsequent semiconductor layer formation process, and in the region between the source contact portion 352 and drain contact portion 353 in the first direction (Y-axis direction). Furthermore, the gate insulating film 34 is formed in the region corresponding to the intersection portion CP where the gate wiring GL and source wiring SL intersect.

[0050] In the plasma CVD film deposition process, the sample is incident on the first main surface 21GSA of the substrate 21GS at a nearly perpendicular angle. On the other hand, the gate wiring GL and the first side surface 313A and second side surface 313B of the gate electrode 31 are inclined with respect to the first main surface 21GSA, so the angle of incidence of the sample on the first side surface 313A and second side surface 313B is not perpendicular. Therefore, as shown in Figure 5, the film thickness T1 of the gate insulating film 34 formed on the upper side of the upper surface 311 of the gate electrode 31, which is provided nearly parallel to the first main surface 21GSA, is thicker than the film thickness T2 of the gate insulating film 34 formed on the upper side of the first side surface 313A and second side surface 313B. In this way, in the gate insulating film formation process, the gate insulating film 34 formed on the upper side of the first side surface 313A and second side surface 313B is thinner than the gate insulating film 34 formed on the upper side of the upper surface 311. The first side surface 313A is the portion on its upper side where the first portion 351 of the semiconductor layer 35 is arranged via the gate insulating film 34. In this way, during the gate insulating film formation process, the gate insulating film 34 arranged on the lower side of the first portion 351 of the semiconductor layer 35 is thinned.

[0051] The semiconductor layer formation process involves depositing a semiconductor film made of IGZO or the like to the entire upper surface of the first main surface 21GSA of the substrate 21GS to a predetermined thickness using a sputtering method, followed by patterning. This forms a semiconductor layer 35 having a first portion 351, a source contact portion 352, and a drain contact portion 353. During this process, the opening of the photomask, the amount of exposure to the photoresist film, and the amount of etching via the developed photoresist film are controlled. As a result, the first portion 351 is positioned on the upper side of the first side surface 313A of the gate electrode 31, and not on the upper side of the upper surface 311 or the second side surface 313B. Furthermore, the semiconductor layer 35 is not formed in the region corresponding to the intersection CP where the gate wiring GL and source wiring SL intersect. Because the first side surface 313A of the gate electrode 31 is sloped downward, the film thickness of the first portion 351, which is disposed on the upper side of the first side surface 313A via the gate insulating film 34, is thinner than the film thickness of the source contact portion 352 and the drain contact portion 353 formed on the first main surface 21GSA.

[0052] The low-resistance process involves applying a low-resistance treatment to the source contact portion 352 and the drain contact portion 353 of the semiconductor layer 35 formed by the semiconductor layer formation process. This reduces the resistance of the source contact portion 352 and the drain contact portion 353, making them conductive. On the other hand, as mentioned above, the first portion 351 of the semiconductor layer 35 is not subjected to the low-resistance treatment. Therefore, the first portion 351 is formed as a non-low-resistance region, that is, as a channel region with semiconductor properties.

[0053] In the source / drain electrode formation process, the source electrode 32, drain electrode 33, and source wiring SL are patterned simultaneously on the first main surface 21GSA of the substrate 21GS, on which the semiconductor layer 35 has been formed, by a pattern formation process similar to that of the gate electrode formation process. At this time, a gate insulating film 34 is formed in the region corresponding to the intersection CP where the gate wiring GL and source wiring SL intersect, and the source wiring SL is formed on the upper side of the gate insulating film 34.

[0054] In the gate electrode formation process, foreign matter such as dust may adhere to the surface of the metal film during the deposition process, and the gate wiring GL and gate electrode 31 may be formed with the attached foreign matter remaining. Also, in the gate insulating film formation process, foreign matter may adhere to the surface of the gate wiring GL and gate electrode 31, or become mixed into the silicon compound film, during the deposition process. In such cases, the gate insulating film 34 may be formed on the upper side of the gate wiring GL and gate electrode 31 with the foreign matter remaining. In such cases, the gate insulating film 34 and semiconductor layer 35 above the foreign matter may not be formed properly, resulting in defects. Furthermore, if the source electrode 32 and drain electrode 33 are formed on the upper side of such gate insulating film 34 and semiconductor layer 35, the gate electrode 31 and source electrode 32, and the gate electrode 31 and drain electrode 33 may be electrically connected via the foreign matter, resulting in a problem where a properly functioning TFT cannot be obtained.

[0055] In the TFT10 according to this embodiment, the source electrode 32 and drain electrode 33 are not positioned above the gate electrode 31, and the source electrode 32 and drain electrode 33 are positioned so as not to overlap with the gate electrode 31 when viewed from above. Therefore, even if foreign matter remains above the gate electrode 31, electrical connection between the gate electrode 31 and the source electrode 32 and drain electrode 33 via that foreign matter is avoided. In this way, by adopting a configuration in which the source electrode 32 and drain electrode 33 are positioned so as not to overlap with the gate electrode 31 when viewed from above, the TFT10 is more likely to maintain normal function even if foreign matter remains above the gate electrode 31. Consequently, the yield during the manufacturing of the TFT10 is improved, and the TFT10 can be provided at a low cost.

[0056] Furthermore, in the TFT 10, the semiconductor layer 35 is not provided on the upper surface 311 and the second side surface 313B of the gate electrode 31, and the first portion 351 of the semiconductor layer 35 is provided only on the upper side of the first side surface 313A. On the other hand, in conventional TFTs, the semiconductor layer 35 is generally formed to cover the entire upper surface 311, the first side surface 313A, and the second side surface 313B of the gate electrode 31. In other words, in the TFT 10, the area of ​​the semiconductor layer 35 provided on the upper side of the gate electrode 31 is smaller compared to conventional TFTs where the semiconductor layer 35 is formed on the entire upper side of the gate electrode 31. Accordingly, the possibility of defects or other problems occurring in the semiconductor layer 35 due to foreign matter remaining on the gate electrode 31 is reduced. This also contributes to lowering the manufacturing cost of the TFT 10.

[0057] Furthermore, in the TFT 10, the source contact portion 352 and the drain contact portion 353 each extend from the lower end portion 351U of the first portion 351 to the upper side of the first main surface 21GSA at different positions in the first direction (Y-axis direction). The source electrode 32 and the drain electrode 33 are connected to these source contact portion 352 and drain contact portion 353, respectively. Therefore, the TFT 10 can position the source electrode 32 and the drain electrode 33 at a distance from the first side surface 313A of the gate electrode 31 when viewed from above. Consequently, even if foreign matter remains on the first side surface 313A of the gate electrode 31, the TFT 10 can suppress electrical connection between the gate electrode 31 and the source electrode 32, and between the gate electrode 31 and the drain electrode 33, respectively, through that foreign matter.

[0058] Furthermore, in the TFT 10, the gate insulating film 34 is not formed on the lower side of the source contact portion 352 and the drain contact portion 353. That is, the source contact portion 352 and the drain contact portion 353 are arranged side by side with a gap in the first direction (Y-axis direction) and are directly provided on the upper side of the first main surface 21GSA without the gate insulating film 34 in between. The source electrode 32 and the drain electrode 33 are positioned above the source contact portion 352 and the drain contact portion 353, respectively. As a result, the positions of the source electrode 32 and the drain electrode 33 are less likely to be higher than the gate electrode 31 compared to the case where the gate insulating film 34 is formed on the lower side of the source contact portion 352 and the drain contact portion 353. Therefore, even if foreign matter remains above the gate electrode 31, it is more reliably avoided that the gate electrode 31 and the source electrode 32, and the gate electrode 31 and the drain electrode 33, will be electrically connected to the gate electrode 31 via the foreign matter.

[0059] Here, referring to Figures 6 and 7, the configuration of the intersection point CP where the gate wiring GL and source wiring SL intersect will be explained. The intersection point CP is formed simultaneously with the TFT 10 by the manufacturing process of the TFT 10 described above.

[0060] As shown in Figures 6 and 7, the intersection CP comprises, in order from the bottom layer, a gate wiring GL, a gate insulating film 34, and a source wiring SL. The gate wiring GL extends in the first direction (Y-axis direction). The source wiring SL extends in a direction intersecting the first direction. In this embodiment, the source wiring SL is arranged on the upper side of the gate wiring GL via the gate insulating film 34, perpendicular to the gate wiring GL.

[0061] The gate wiring GL, like the gate electrode 31 of the TFT 10, has an upper surface 311, a lower surface 312, and a side surface 313. Therefore, the thickness of the gate insulating film 34 formed on the upper side of the upper surface 311 of the gate wiring GL is the same thickness T1 as that formed on the upper side of the upper surface 311 of the TFT 10. The source wiring SL is mainly located on the upper side of the upper surface 311 of the gate wiring GL. The thickness T1 of the gate insulating film 34 interposed between this upper surface 311 and the source wiring SL located on its upper side is thicker than the thickness T2 of the gate insulating film 34 located on the lower side of the first portion 351 of the semiconductor layer 35 shown in Figure 5. Therefore, the insulation between the gate wiring GL and the source wiring SL is effectively ensured. In this way, the TFT 10 can improve the reliability of its performance by thinning the thickness of the gate insulating film 34 located on the lower side of the first portion 351 of the semiconductor layer 35 while ensuring the insulation between the gate wiring GL and the source wiring SL.

[0062] As described above, the TFT 10 has an upper surface 311, a lower surface 312, and a side surface 313, and is disposed on the first main surface 21GSA with the lower surface 312 facing the first main surface 21GSA of the substrate 21GS, and comprises a gate electrode 31 whose first side surface 313A of the side surface 313 extends in a first direction (Y-axis direction), a gate insulating film 34 disposed on the upper side of the gate electrode 31, a semiconductor layer 35 disposed on the upper side of the gate insulating film 34 and including a first portion 351 which is disposed on the gate insulating film 34 with respect to the first side surface 313A of the gate electrode 31 via the gate insulating film 34 and extends in a first direction, a source electrode 32 disposed in a position that does not overlap with the gate electrode 31 when viewed from above, and a drain electrode 33 disposed in a position that does not overlap with the gate electrode 31 when viewed from above, and is arranged in a position parallel to the source electrode 32 in the first direction. The source electrode 32 and the drain electrode 33 each contact the first portion 351 at different positions in the first direction.

[0063] In the TFT 10, the source electrode 32 and drain electrode 33 are positioned so that they do not overlap with the gate electrode 31 when viewed from above. Furthermore, the source electrode 32 and drain electrode 33 are in contact with a first portion 351 of the semiconductor layer 35, which is located on the upper side of the first side surface 313A of the gate electrode 31 via a gate insulating film 34. Therefore, even if foreign matter remains on the gate electrode 31 during the manufacturing process of the TFT 10, electrical connection between the gate electrode 31 and the source electrode 32, and between the gate electrode 31 and the drain electrode 33, is suppressed through that foreign matter. Consequently, the function of the TFT 10 is more likely to be maintained even if foreign matter remains on the gate electrode 31.

[0064] The semiconductor layer 35 includes a source contact portion 352 which extends from the lower end 351U of the first portion 351 along the upper side of the first main surface 21GSA and contacts the source electrode 32, and a drain contact portion 353 which extends from the lower end 351U of the first portion 351 along the upper side of the first main surface 21GSA at a position different from the source contact portion 352 and contacts the drain electrode 33.

[0065] In this case, the source contact portion 352 and drain contact portion 353 of the semiconductor layer 35 are formed extending from the lower end portion 351U of the first portion 351 along the upper side of the first main surface 21GSA, and the source electrode 32 and drain electrode 33 are in contact with the source contact portion 352 and drain contact portion 353. That is, the TFT 10 can position the source electrode 32 and drain electrode 33 at a distance from the first side surface 313A of the gate electrode 31 when viewed from above. Therefore, even if foreign matter remains on the first side surface 313A of the gate electrode 31 during the manufacturing process of the TFT 10, electrical connection between the gate electrode 31 and the source electrode 32, and between the gate electrode 31 and the drain electrode 33, is suppressed through that foreign matter.

[0066] The gate insulating film 34 is not formed in a position that overlaps with the source contact portion 352 and the drain contact portion 353. The source electrode 32 is positioned above the source contact portion 352, and the drain electrode 33 is positioned above the drain contact portion 353.

[0067] In this case, the source contact portion 352 and drain contact portion 353 of the semiconductor layer 35 are arranged on the first main surface 21GSA of the side surface 313 without interposing the gate insulating film 34. The source electrode 32 and drain electrode 33 are then arranged above the source contact portion 352 and drain contact portion 353. Since the gate insulating film 34 is not arranged below the source contact portion 352 and drain contact portion 353, the positions of the source electrode 32 and drain electrode 33 are less likely to be higher than the gate electrode 31. Therefore, even if foreign matter remains on the gate electrode 31, it is more reliably suppressed that the gate electrode 31 and the source electrode 32, and the gate electrode 31 and the drain electrode 33, respectively, will be electrically connected via that foreign matter.

[0068] The first side surface 313A slopes downward from the top surface 311 to the bottom surface 312, and the semiconductor layer 35 is not located on the upper side of the second side surface 313B, which is opposite to the first side surface 313A, or on the upper side of the top surface 311 of the gate electrode 31.

[0069] In this case, the semiconductor layer 35 positioned to overlap the gate electrode 31 when viewed from above is only the first portion 351. Therefore, even if foreign matter remains on the part of the gate electrode 31 other than the first portion during the manufacturing process, defects caused by the foreign matter are less likely to occur in the semiconductor layer 35. As a result, the yield of the TFT 10 can be improved. In addition, since the first side surface 313A slopes downward from the top surface 311 to the bottom surface 312, it becomes easier to make the thickness of the gate insulating film 34 formed on the first side surface 313A thinner than the thickness of the gate insulating film 34 formed on the top surface 311, thereby improving the design flexibility of the TFT 10.

[0070] A channel region is formed in the first part 351.

[0071] In this case, a channel region is formed in the first portion 351 of the semiconductor layer 35, which is located in a position that does not overlap with the source electrode 32 and the drain electrode 33 when viewed from above. Therefore, even if foreign matter remains on the gate electrode 31, the electrical connection between the gate electrode 31 and the source electrode 32, and between the gate electrode 31 and the drain electrode 33, is suppressed through the foreign matter, even when the TFT 10 is driven.

[0072] <Other Embodiments> This disclosure is not limited to the embodiments described above and in the drawings. For example, the following embodiments are also included in the technical scope of this disclosure, and various modifications can be made without departing from the spirit of the disclosure.

[0073] (1) The angle of inclination of the side surface 313 of the gate electrode 31, which slopes downward from the upper surface 311 to the lower surface 312, may be arbitrarily determined. It is preferable that at least the first side surface 313A of the side surface 313 slopes downward. In this case, the second side surface 313B may be formed to slope downward with respect to the upper surface 311 and the lower surface 312, or it may be formed to extend substantially vertically so as to be perpendicular to the upper surface 311 and the lower surface 312. Alternatively, the first side surface 313A may be formed to extend vertically so as to be perpendicular to the upper surface 311 and the lower surface 312.

[0074] (2) The end of the source electrode 32 that is close to the gate electrode 31 may be positioned to be in contact with the lower end 351U of the first portion 351 of the source contact portion 352 without any gap. Similarly, the end of the drain electrode 33 that is close to the gate electrode 31 may be positioned to be in contact with the lower end 351U of the first portion 351 of the drain contact portion 353 without any gap. In other words, the source electrode 32 and the drain electrode 33 may be positioned to be in direct contact with the first portion 351 at the lower end 351U. Even in this case, the source electrode 32 and the drain electrode 33 are positioned so as not to overlap with the gate electrode 31 when viewed from above. Therefore, even if foreign matter remains on the first side surface 313A of the gate electrode 31, it is unlikely that the gate electrode 31 and the source electrode 32, and the gate electrode 31 and the drain electrode 33 will be electrically connected via the foreign matter.

[0075] (3) The gate wiring GL and gate electrode 31, source wiring SL and source electrode 32, and drain electrode 33 may be single-layer structures or laminated structures of three or more layers made of three or more types of metal materials. In addition, the specific metal materials used for the gate wiring GL and gate electrode 31, source wiring SL and source electrode 32, and drain electrode 33 may be aluminum (Al), molybdenum (Mo), or alloys or compounds thereof, in addition to titanium and copper.

[0076] (4) The gate insulating film 34 may be a single layer or a multilayer structure made of multiple silicon compound films. For example, a two-layer gate insulating film 34 may be constructed by placing a silicon nitride film on the lower layer and a silicon oxide film on the upper layer. The stacking order of these films may also be reversed. Furthermore, the gate insulating film 34 may be a multilayer structure of three or more layers.

[0077] (5) The semiconductor layer 35 may be an amorphous silicon thin film or a polycrystalline silicon thin film.

[0078] (6) A base coat film made of a silicon compound film or the like may be provided on the upper side of the first main surface 21GSA of the substrate 21GS, and the gate electrode 31 may be placed on the upper side of the base coat to form the TFT 10.

[0079] (7) In the embodiments described above, the TFT 10 provided in the liquid crystal panel 1 was used as an example, but the technology of this disclosure can also be applied to TFTs provided in display panels such as organic EL panels. Furthermore, the technology of this disclosure can also be applied to TFTs provided in semiconductor devices other than display panels. [Explanation of Symbols]

[0080] 10: TFT 21GS: Substrate 21GSA: First main surface 31: Gate electrode 32: Source electrode 33: Drain electrode 34: Gate insulating film 35: Semiconductor layer 311: Top surface 312: Bottom surface 313: Side surface 313A: First side surface 313B: Second side surface 351: First portion 351U: Bottom end 352: Source contact portion 352: Drain contact portion GL: Gate wiring SL: Drain wiring

Claims

1. A gate electrode having an upper surface, a lower surface and side surfaces, the lower surface facing the first main surface of the substrate, and the first side surface of the side surfaces extending in a first direction, The gate insulating film is disposed on the upper side of the gate electrode, A semiconductor layer comprising a first portion disposed on the upper side of the gate insulating film, disposed with respect to the first side surface of the gate electrode via the gate insulating film and extending in the first direction, A source electrode positioned so as not to overlap with the gate electrode when viewed from above, A drain electrode is arranged in a position that does not overlap with the gate electrode when viewed from above, and is positioned in the first direction parallel to the source electrode, Equipped with, A thin-film transistor in which the source electrode and the drain electrode are in contact at different positions in the first direction of the first portion.

2. The aforementioned semiconductor layer is A source contact portion is a portion that extends from the lower end of the first portion to the upper side of the first main surface and contacts the source electrode, The lower end of the first portion extends to the upper side of the first main surface at a position different from the source contact portion and is a drain contact portion that contacts the drain electrode, A thin-film transistor according to claim 1, comprising:

3. The gate insulating film is not formed in a position that overlaps with the source contact portion and the drain contact portion. The source electrode is positioned above the source contact portion, The thin-film transistor according to claim 2, wherein the drain electrode is disposed above the drain contact portion.

4. The first side surface slopes downward from the upper surface to the lower surface, The thin-film transistor according to claim 1, wherein the semiconductor layer is not disposed on the upper side of the second side of the gate electrode that is opposite to the first side, and on the upper side of the top surface.

5. The thin-film transistor according to claim 1, wherein a channel region is formed in the first portion.

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