Silicon carbide MOSFET with two-stage oxide trench

Abstract

A semiconductor device and a method for manufacturing a semiconductor device are provided. [Solution] A semiconductor device may include a drift region formed on a silicon carbide substrate. It may also include a trench penetrating the source region and channel layer to reach the drift region. Furthermore, it may include an oxide region covering the inner surface of the trench. The oxide region may include a bottom, lower side, and upper side. The thickness of the bottom and lower side may be greater than the thickness of the upper side. The semiconductor device may also include a gate electrode formed within the trench whose inner surface is covered by the oxide region. Finally, it may include a shield region in contact with the bottom of the trench. The width of this semiconductor region may be less than or equal to the width of the trench.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices in general, and more particularly to silicon carbide (SiC) devices including a two-stage oxide trench. [Background technology]

[0002] Metal-oxide-semiconductor field-effect transistor (MOSFET) cells may be planar MOSFETs or trench MOSFETs. Compared to planar MOSFETs, the trench structure of trench MOSFETs contributes to more efficient control of the depletion layer. By etching trenches perpendicular to the substrate and covering their inner surfaces with a gate oxide film and a conductive material (usually polysilicon), trench MOSFETs can achieve higher integration density and reduced on-resistance compared to planar MOSFETs. Furthermore, the trench structure minimizes parasitic capacitance and contributes to improved thermal management characteristics. In one embodiment, when forming a trench MOSFET using silicon carbide (SiC), the breakdown voltage is improved compared to a silicon (Si) trench MOSFET because SiC has a larger band gap than silicon (Si). [Overview of the Initiative]

[0003] In one embodiment, a semiconductor device is generally provided. The semiconductor device may include a semiconductor substrate of a first conductivity type. The semiconductor substrate may be formed from silicon carbide (SiC). The semiconductor device may further include a drift region of a first conductivity type formed on the semiconductor substrate. The semiconductor device may further include a channel of a second conductivity type opposite to the first conductivity type, formed on the drift region. The semiconductor device may further include a source region of a first conductivity type formed on the channel. The semiconductor device may further include a trench penetrating the source region and the channel layer to reach the drift region. The semiconductor device may further include an oxide region covering the inner surface of the trench. The oxide region may include a bottom, a lower side, and an upper side. The thickness of the bottom may be greater than the thickness of the upper side. The thickness of the lower side may be greater than the thickness of the upper side. A gate electrode may be formed in the trench whose inner surface is covered by the oxide region. The semiconductor device may further include a shield region of a second conductivity type in contact with the bottom of the trench, the width of which the shield region may be less than or equal to the width of the trench.

[0004] In one embodiment, a semiconductor device is generally provided. The semiconductor device may include a semiconductor substrate of a first conductivity type. The semiconductor substrate may be formed from silicon carbide (SiC). The semiconductor device may further include a drift region of a first conductivity type formed on the semiconductor substrate. The semiconductor device may further include a channel of a second conductivity type opposite to the first conductivity type, formed on the drift region. The semiconductor device may further include a source region of a first conductivity type formed on the channel. The semiconductor device may further include a trench penetrating the source region and the channel layer to reach the drift region. The semiconductor device may further include an oxide region covering the inner surface of the trench. The oxide region may include a bottom, a lower side, and an upper side. The thickness of the bottom may be greater than the thickness of the upper side. The thickness of the lower side may be greater than the thickness of the upper side. At least one gate electrode may be formed in the trench whose inner surface is covered with the oxide region. The semiconductor device may further include a shield region of a second conductivity type in contact with the bottom of the trench, the width of which the shield region may be less than or equal to the width of the trench.

[0005] In one embodiment, a method for manufacturing a semiconductor device is provided. The method may include the step of forming a first oxide layer having a first thickness that covers the inner surface of a trench formed in a silicon carbide (SiC) substrate. The method may further include the step of forming a layer of conductive material on the bottom of the trench covered with the first oxide layer. The method may further include the step of forming a nitride layer above the layer of conductive material and along the side walls of the trench. The method may further include the step of etching the conductive material using the nitride layer as a hard mask. The method may include the step of performing a first oxidation process on the remaining portion of the layer of conductive material to form the bottom and lower sides of the oxidation region in the trench. The method may further include the step of removing the nitride layer and cleaning the exposed side walls of the trench. The method may further include the step of performing a second oxidation process on the exposed side walls of the trench to form the upper sides of the oxidation region. The method may further include the step of forming a gate electrode in the trench covered with the oxidation region.

[0006] The above summary is illustrative and not limiting in any sense. Further embodiments, features, and characteristics will become apparent by referring to the accompanying drawings and the following detailed description, in addition to the exemplary aspects, embodiments, and features described above. In the drawings, the same reference numerals indicate identical or functionally similar elements. [Brief explanation of the drawing]

[0007] [Figure 1] This figure shows a partial example of a silicon carbide MOSFET including a two-stage oxide trench in one embodiment. [Figure 2] This figure shows an example of a silicon carbide MOSFET including a two-stage oxide trench in one embodiment. [Figure 3] This figure shows an example of an oxidation region in a silicon carbide MOSFET including a two-stage oxidation trench in one embodiment. [Figure 4A]A diagram showing one step of the manufacturing process of a silicon carbide MOSFET including a two-step oxidation trench in one embodiment. [Figure 4B] A diagram showing another step of the manufacturing process of a silicon carbide MOSFET including a two-step oxidation trench in one embodiment. [Figure 5A] A diagram showing another step of the manufacturing process of a silicon carbide MOSFET including a two-step oxidation trench in one embodiment. [Figure 5B] A diagram showing another step of the manufacturing process of a silicon carbide MOSFET including a two-step oxidation trench in one embodiment. [Figure 6A] A diagram showing another step of the manufacturing process of a silicon carbide MOSFET including a two-step oxidation trench in one embodiment. [[ID=z13]] [Figure 6B] A diagram showing another step of the manufacturing process of a silicon carbide MOSFET including a two-step oxidation trench in one embodiment. [Figure 7A] A diagram showing another step of the manufacturing process of a silicon carbide MOSFET including a two-step oxidation trench in one embodiment. [Figure 7B] A diagram showing another step of the manufacturing process of a silicon carbide MOSFET including a two-step oxidation trench in one embodiment. [Figure 8A] A diagram showing another step of the manufacturing process of a silicon carbide MOSFET including a two-step oxidation trench in one embodiment. [Figure 8B] A diagram showing another step of the manufacturing process of a silicon carbide MOSFET including a two-step oxidation trench in one embodiment. [[ID=z29]] [Figure 8C] A diagram showing another step of the manufacturing process of a silicon carbide MOSFET including a two-step oxidation trench in one embodiment. [[ID=z32]] [Figure 9A] A diagram showing another example of a silicon carbide MOSFET including a two-step oxidation trench in one embodiment. [Figure 9B] It should be noted that there are some repeated tags in the original text, and the translated text tries to maintain the same format as the original while accurately translating the content. Also, the specific meaning of the 7-digit tags - [Figure 9B] is not clear from the given context, so they are left unchanged as required. If there is any additional information about these tags that could help with a more accurate translation or understanding, it would be beneficial.A diagram showing another step of a manufacturing process of a silicon carbide MOSFET including a two-step oxidation trench in one embodiment. [Figure 9C] A diagram showing another step of a manufacturing process of a silicon carbide MOSFET including a two-step oxidation trench in one embodiment. [Figure 9D] A diagram showing another step of a manufacturing process of a silicon carbide MOSFET including a two-step oxidation trench in one embodiment. [Figure 9E] A diagram showing another step of a manufacturing process of a silicon carbide MOSFET including a two-step oxidation trench in one embodiment. [Figure 10] A flowchart showing a process for manufacturing a silicon carbide MOSFET including a two-step oxidation trench in one embodiment. **DETAILED DESCRIPTION OF THE INVENTION**

[0008] In the following description, in order to facilitate understanding of various embodiments of the present application, a number of specific details including specific structures, components, materials, dimensions, processing steps, and technologies are described. However, those skilled in the art will understand that the various embodiments of the present application can be realized without these specific details. In some cases, descriptions of details of known structures or processing steps are omitted so as not to obscure the present application.

[0009] Note that when an element as a layer, region, or substrate is described as being "on" or "above" another element, it may be directly above the other element or there may be another element in between. On the other hand, when an element is described as being "directly on" or "directly above" another element, it means that there is no other element in between. Also, when an element is described as being "under" or "below" another element, it may be directly under the other element or there may be another element in between. On the other hand, when an element is described as being "directly under" or "directly below" another element, it means that there is no other element in between.

[0010] Trench-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) can handle large powers and provide high-power drive capability by conducting current vertically from the top to the bottom of a semiconductor die. A trench-gate MOSFET can include a number of parallel-connected active trench-gate MOSFET cells, each containing a trench formed in the semiconductor die within its active region. Each active trench has a source region around it and a doped body region opposite it, and the trench can be deep enough to penetrate the body region until it reaches a drift region below the top surface of the semiconductor die. Each active trench-gate cell has a gate embedded in the trench, which can include a gate electrode containing doped polysilicon and a gate dielectric. By applying an appropriate bias to these gate electrodes, current conduction in the body region is controlled, and the MOSFET cell is turned on. This causes current to flow from the source at the top to the drain at the bottom.

[0011] Compared to silicon (Si) equipment, silicon carbide (SiC) equipment offers higher voltage resistance and can withstand higher voltages. Therefore, SiC equipment may be more suitable than Si equipment for high-power applications requiring high voltage resistance. Compared to Si equipment, SiC equipment has lower on-resistance (RDSon). A lower RDSon results in less conduction loss and improved efficiency. Furthermore, compared to Si equipment, SiC equipment can operate at higher temperatures and possess desirable switching characteristics (e.g., higher switching frequencies). However, the manufacturing processes for Si equipment cannot be used for SiC equipment. For example, because SiC has a higher hardness than Si, processes typically used for Si equipment may not be applicable to SiC equipment.

[0012] Figure 1 is a side view showing a portion of a silicon carbide MOSFET including a two-stage oxide trench in one embodiment. Figure 1 shows a side view showing a portion of a semiconductor device 100 or apparatus 100. The apparatus 100 may be formed using a substrate 103 which includes a gate region 102 (or gate electrode, hereinafter "gate 102"), a source terminal 104 (hereinafter "source 104"), a drain terminal 106 (hereinafter "drain 106"), a passivation oxide layer 108, a drift region 110, a junction field-effect transistor (JFET) region 112, a first doped region 114, a second doped region 116, a base 118, an oxide region 120, and a shield region 130. The substrate 103 is a semiconductor substrate doped with a first type of impurity, such as an N-type impurity. This makes the substrate 103 a first conductivity type. In this specification, the first conductivity type is either N-type or P-type, and the second conductivity type may have conductivity opposite to that of the first conductivity type. For example, if the first conductivity type is N-type, the second conductivity type is P-type, and vice versa.

[0013] The device 100 can be a SiC trench MOSFET. In one embodiment, the device 100 can be one of several SiC trench MOSFETs in an integrated circuit. The trench MOSFET can be formed by etching a trench 101 vertically (e.g., in the -y direction) within a SiC substrate (e.g., substrate 103) and doping the remaining SiC substrate with different types and / or concentrations of impurities. The walls of the trench 101 are covered with a gate oxide layer (e.g., an oxide region 120 described later), and the inner surface of the covered trench 101 can be filled with a conductive material such as polysilicon to form the gate 102. The source 104 is a region of a first conductivity type, and the drain 106 may be a region of a first conductivity type. The passivation oxide layer 108 may be an oxide layer intentionally formed to act as a barrier protecting the device 100 from environmental factors such as moisture, chemicals, and environmental pollutants that could impair the functionality of the device 100.

[0014] The drift region 110 is located between the base 118 and the substrate 103 and may extend along the wall of the trench 101 where the gate 102 is located. The drift region 110 may be a region in which carriers (e.g., electrons or holes) can drift from the source 104 to the drain 106. When a voltage is applied to the gate 102, an electric field is generated and an inversion layer is formed in the channel region (hereinafter referred to as "channel") 109. In one embodiment, the channel 109 is of a second conductivity type and its doping concentration is about 1 × 10⁻⁶ 15 cm -3 ~1 × 10 18 cm -3 It can vary within this range. In some embodiments, N-type channel depletion-mode MOSFET operation can be achieved by using a first type of impurity to form the channel 109. The electric field can move carriers toward the drain 106. This allows current to flow from the source 104 to the drain 106. The strength and distribution of the electric field in the drift region 110 affect various electrical properties, including on-resistance (RDSon), breakdown voltage, or other characteristics of the device 100.

[0015] The apparatus 100 may further include a JFET region 112 formed within the drift region 110. The JFET region 112 provides a direct junction between the gate 102 and the channel 109. In one embodiment, the JFET region 112 may be located between the upper surface of the drift region 110 adjacent to the trench 101 and the lower surface of the channel 109, the base 118, and the second doped region 116. In some cases, the JFET region 112 may be formed by doping with a high concentration of a first conductivity type donor impurity. The doping concentration may be, for example, 1 × 10⁻⁶. 16 cm -3 ~1 × 10 18 cm -3 It can vary within this range.

[0016] The first doped region 114 can be a region doped with a first type of impurity such as an N-type impurity. The second doped region 116 can be a region doped with a second type of impurity such as a P-type impurity. The first doped region 114 can have a first conductivity type, and the second doped region 116 can have a second conductivity type. The first doped region 114 and the second doped region 116 can be in contact with the source 104. The first doped region 114 can be in contact with the passivation oxide layer 108. When the device 100 is an N-type device, the first doped region 114 can also be referred to as the first doped region, and the second doped region 116 can also be referred to as the second doped region. In some embodiments, the first doped region 114 can also be referred to as a high-concentration doped region. When the first conductivity type is N-type, the first doped region 114 can be formed by ion implanting or diffusing an N-type dopant such as phosphorus (P) or arsenic (As) into a region that will ultimately become the first doped region 114. When the first conductivity type is N-type, the second doped region 116 can be formed by ion implanting or diffusing a P-type dopant such as boron (B), aluminum (Al), or gallium (Ga) into a region that will ultimately become the second doped region 114. The depth and doping concentration of the first doped region 114 and the second doped region 116 can be controlled to define the RDSon and breakdown voltage of the device 100. For example, the doping concentration of the first doped region 114 can be in the range of about 1×10 19 cm -3 ~ about 1×10 21 cm -3 and the doping concentration of the second doped region 116 can be in the range of about 1×10 18 cm -3 ~ about - 1×10 21 cm -3 can be in the range of.

[0017] It should be noted that there seems to be an error in the original text where "約1×10 " in the middle of the description of the doping concentration range of the second doped region 116 has a "-" sign in the translation by mistake. It should be corrected according to the correct original text meaning.Base 118 may be a region doped with a second type of impurity (e.g., the same type as the second doped region 116), such as a P-type impurity. The impurity concentration of the impurity used to dope base 118 can be lower than that of the second doped region 116. By having a lower impurity concentration than the second doped region 116, base 118 can facilitate the passage of majority carriers injected from the emitter (e.g., source 104) through base 118 to the collector (e.g., drain 106). In one embodiment, the doping concentration of base 118 is approximately 1 × 10⁻⁶ 16 cm -3 ~Approx. 1×10 18 cm -3 It can vary within the range of . In some embodiments, base 118 may be doped with a low concentration of a first type of impurity to realize an accumulation-mode MOSFET (ACCUFET). In this case, the doping concentration of base 118 is about 1 × 10⁻⁶. 14 cm -3 ~Approx. 1×10 16 cm -3 It can vary within the range of . In other embodiments, base 118 may be doped with a first type of impurity to realize a depletion-mode MOSFET. In this case, the doping concentration of base 118 is about 1 × 10⁻⁶. 16 cm -3 ~Approx. 1×10 18 cm -3 It can vary within this range.

[0018] In one embodiment, the layer covering the inner surface of the trench 101, i.e., the gate oxide film, may be an insulating material that isolates the gate 102 from the semiconductor channel (e.g., channel 109) and other conductive layers or regions of the apparatus 100. The insulating material covering the inner surface of the trench 101 may be, for example, silicon dioxide (SiO2) or other high dielectric constant dielectrics. The oxide layer also helps to control the current flow between the source 104 and the drain 106 by adjusting the electric field in the drift region 110. A thinner gate oxide film relatively improves the control efficiency of the channel, while a thicker film can prevent dielectric breakdown of the gate oxide film. The threshold voltage of the apparatus 100 can also be controlled by the thickness of the gate oxide film. If the electric field strength in the drift region 110 is excessively high, the gate oxide film may degrade over time, adversely affecting the overall lifespan and reliability of the apparatus 100. Degradation of the oxide film may cause a shift in the threshold voltage. In trench-type MOSFETs, trenches tend to have a shape where the depth (e.g., in the y-axis direction) is relatively greater than the width (e.g., in the x-axis direction). Therefore, the electric field lines tend to concentrate at the bottom of the trench, and the electric field below the trench (e.g., in the -y direction) tends to be higher than in other regions, such as near the side walls of the trench.

[0019] In conventional devices, a P-type shield may be placed below the trench by P-type ion implantation to mitigate the high electric field at the bottom of the trench. However, the addition of a P-type shield can compromise the ideal diffusion resistance. Diffusion resistance is the resistance that occurs when current diffuses from the gate to other areas of the device. Increasing the contact area between the gate and other areas of the device reduces diffusion resistance, leading to a decrease in RDSon and improved device performance. Adding a P-type shield reduces the contact area between the gate and other areas of the device, thus increasing diffusion resistance.

[0020] In conventional equipment, the bottom of the gate oxide film covering the inner surface of the trench can be thickened to reduce the electric field at the bottom of the trench. However, thermally growing a thick oxide film in SiC is difficult. For example, silicon (Si) and carbon (C) have a strong covalent bond, and it is difficult to break this bond. Therefore, it is difficult for oxygen to react with SiC to form a stable oxide film, and more energy is required to break the bond and cause an oxidation reaction. Furthermore, because SiC has thermal stability and does not degrade even at high temperatures, its reactivity with oxygen is low at high temperatures, requiring harsher conditions for oxide layer formation. This makes it difficult to form a thicker and smoother oxide layer.

[0021] Furthermore, conventional techniques for reducing the electric field at the bottom of a trench do not mitigate the high electric fields at the trench corners and the lower part of the trench sidewalls. Some conventional techniques involve extending a P-type shield laterally (e.g., along the x-axis) below the trench to reduce the electric field at the trench corners, but the diffusion resistance increases as the width of the P-type shield extends beyond the gate oxide film. As will be described later, the apparatus 100 may have a gate oxide film labeled as an oxidation region 120 having a bottom and lower side that are thicker than the upper side, and a P-type shield labeled as a shield region 130 that does not extend laterally beyond the gate oxide film (e.g., beyond the trench sidewall). The oxidation region 120 may be fabricated by a multi-stage (e.g., two-stage) process in which the thickness of the bottom, lower side, and upper side of the oxidation region 120 can be independently controlled. Furthermore, by varying these thicknesses, and particularly by forming a thicker lower side of the oxidation region 120, the shield region 130 can be manufactured to have a width that does not extend beyond the gate oxide film.

[0022] Figure 2 shows an example of a silicon carbide MOSFET including a two-stage oxide trench in one embodiment. The description of Figure 2 can be made by referring to the components shown in Figure 1. Figure 2 shows a cross-sectional view of an entire unit, i.e., one cell, of a device 100 for mounting a SiC trench type MOSFET. As shown in Figure 2, the trench 101 is formed by etching between two first doped regions 114a and 114b (e.g., first doped regions), two second doped regions 116a and 116b (e.g., second doped regions), and two base regions 118a and 118b, respectively. As shown in Figure 2, the trench 101 has a U-shape overall, and the shield region 130 can extend over the bottom of the trench 101 without extending beyond the side walls of the trench 101. The oxidation region 120 has a thick bottom, a thick lower side portion located at the bottom of the side of the oxidation region 120, and a thin upper side portion located at the top of the side of the oxidation region 120.

[0023] Figure 3 shows an example of an oxidation region 120 in a silicon carbide MOSFET including a two-stage oxidation trench in one embodiment. The description of Figure 3 can be made by referring to the components shown in Figures 1 and 2. As shown in Figure 3, the oxidation region 120 may include an upper side portion 304, a lower side portion 306, and a bottom portion 308. The thickness of the upper side portion 304 is indicated by the reference numeral V. For example, the thickness V can vary in the range of about 1 nm to about 20 nm. The thickness of the lower side portion 306 is indicated by the reference numeral U. For example, the thickness U can vary in the range of about 1 nm to about 500 nm. The thickness of the bottom portion 308 is indicated by the reference numeral T. For example, the thickness T can vary in the range of about 1 nm to about 500 nm. Thicknesses U and T may be greater than thickness V. Thicknesses U and T may be the same as each other or may be different from each other.

[0024] The bottom portion 308 can contact the shield region 130. The bottom portion 308 and the shield region 130 can contribute to reducing the electric field near the bottom of the trench 101, for example, in the drift region 110 located below the trench 101. The upper side portion 304 can contact at least one of the first doped region 114, the base 118, and the JFET region 112. The lower side portion 306 can contact the JFET region 112 and the drift region 110. The lower side portion 305 can contribute to reducing the electric field in the drift region 110 located near the side wall of the trench 101 and near the corner 302 of the trench 101. By utilizing the lower side portion 306 to reduce the electric field in the drift region 110 near the corner 302, the width W of the bottom portion 308 can be kept less than or equal to the width of the trench 101. In other words, to reduce the electric field near the corner 302, it is not necessary to extend the bottom 308 beyond the side wall of the trench 101. Note that the width W of the bottom 308 can be set so as not to exceed the side wall of the trench 101 and not to overlap with the corner 302.

[0025] Figures 4A to 8C illustrate a series of steps in a silicon carbide MOSFET manufacturing process including a two-stage oxide trench in one embodiment. The explanation of Figures 4A to 8C can be made by referring to the components shown in Figures 1 to 3. In Figure 4A, the shield region 130 may be embedded in a laminated structure comprising a first doped region 114, a second doped region 116, a base 118, and a drift region 110. Various techniques are used to embed the shield region 130, such as using a photomask or implantation mask to selectively block or allow the implantation of a second conductivity type (e.g., aluminum) dopant at the location of the shield region 130 within the drift region 110. For example, ion implantation equipment can be used to introduce ions of the dopant material into the SiC lattice to form the second conductivity type shield region 130. Annealing can be performed to activate the dopant, repair any damage to the substrate caused by ion implantation, and ensure that the dopant is properly integrated into the lattice. In one embodiment, the dopant concentration in the shield region 130 is approximately 1 × 10⁻¹⁶15 cm -3 ~5×10 17 cm -3 The depth of the trench 101 (in the vertical direction) into the drift region 110 (e.g., in the -y direction) is in the range of about 0.5 μm to about 10 μm, preferably in the range of about 0.5 μm to about 2 μm.

[0026] In Figure 4B, after filling the shield region 130, an oxide layer (hereinafter also referred to as "oxide film") 402 having a thickness t1 may be formed covering the wall surface of the trench 101. The oxide film 402 may be formed by thermal oxidation of the oxidizing material. However, in some embodiments, the oxide film 402 may be formed by conformal deposition of the oxidizing material. The oxide film 402 may be a high-quality oxide film having relatively superior properties compared to other oxide films in terms of purity, stability, or specific functional properties. The oxide film 402 may be formed by an oxide film such as silicon dioxide (SiO2). The duration of oxidation for forming the oxide film 402 may be controlled to define the thickness t1. For example, by controlling the oxidation process, an oxide film 402 with a thickness t1 varying in the range of about 1 nm to about 500 nm can be obtained. In some embodiments, a chemomechanical planarization (CMP) process may be performed to remove excess oxidizing material (e.g., oxide film 402) from the top surface of the apparatus 100, forming the smooth top surface shown in Figure 5A.

[0027] In Figure 5A, after the inner surface of the trench 101 is covered with an oxide film 402, a conductive material 502 such as polysilicon can be deposited inside the trench 101 whose inner surface is covered with the oxide film 402. The conductive material 502 substantially fills the bottom of the trench 101. In one embodiment, the thickness h1 of the conductive material 502 deposited inside the trench 101 may be in the range of about 0 μm to about 1 μm. However, the thickness h1 of the conductive material 502 can vary in the range of 0% to 50% of the depth of the trench. The thickness h1 of the conductive material 502 can determine the position of the uppermost part of the lower side 306 of the oxidation region 120, which will be described later.

[0028] In Figure 5B, the nitride layer 512 can be deposited in the trench 101 along the top of the oxide film 402 that is not covered by the conductive material 502. As shown in the figure, the lower surface of the deposited nitride layer 512 can directly contact the upper surface of the conductive material 502. Formation of the nitride layer 512 involves depositing a nitride material (e.g., silicon nitride) using various deposition methods. In exemplary embodiments, the thickness of the nitride layer 512 can vary in the range of about 10 nm to about 500 nm. The nitride layer 512 can function as a hard mask layer during etching of the conductive material 502.

[0029] In Figure 6A, the nitride layer 512 is used as a hard mask to etch the conductive material 502. The conductive material 502 can be etched using various wet etching and dry etching techniques that selectively remove the conductive material 502 without removing the oxide film 402 or the nitride layer 512. After the etching process, a first portion (horizontal portion) a of the conductive material 502 remains at the bottom of the trench 101, which is lined with the conductive material 502, and a second portion (vertical portion) b of the conductive material 502 remains on the opposing sidewalls of the trench 101, which is lined with the oxide film 402. In one embodiment, the thickness of the conductive material 502 remaining in the trench 101 may be determined by the thickness of the nitride layer 512.

[0030] In Figure 6B, following the etching process of the conductive material 502, the apparatus 100 undergoes a first thermal oxidation process. Here, the polysilicon in the conductive material 502 is oxidized, and together with the oxide film 402, oxide layers (hereinafter also referred to as "oxide films") 602 of varying thicknesses are formed, covering the bottom and side walls of the trench 101. The thickness t2 of the oxide film 602 formed on the bottom of the trench 101 can vary in the range of approximately 0 nm to 500 nm. The oxide film 602 may be a high-quality oxide film having relatively superior properties compared to other oxide films in terms of purity, stability, or specific functional characteristics, for example. The oxide film 602 may be formed by an oxide such as SiO2.

[0031] In Figure 7A, the nitride layer 512 can be removed from the apparatus 100 using any suitable technique, including, for example, reactive ion etching (RIE). After the nitride layer 512 is removed, a cleaning process can be performed to clean the upper sidewall of the trench 101. After the cleaning process, the remaining portion 702 of the oxide film 602 remains in the trench 101. In Figure 7B, a second thermal oxidation process can be performed on the apparatus 100 to form an oxidation region 120. During the second thermal oxidation process, an upper side portion 304 can be formed along the exposed upper sidewall of the trench 101 (i.e., the sidewall of the trench 101 not covered by the remaining portion 702 of the oxide film 602). Thus, the oxidation region 120 can be formed by combining the remaining portion 702 of the oxide film 602 with the newly formed upper side portion 304 of the oxidation material extending along the upper sidewall of the trench 101 to the upper surface of the apparatus 100. The duration of the second thermal oxidation process can be controlled so that the thickness V of the upper side portion 304 varies between approximately 1 nm and approximately 20 nm.

[0032] Since the duration defining the thickness t1 of oxide film 402 and the thickness t2 of oxide film 602 in the oxidation process can be controlled independently or in separate steps, the thickness T of the bottom 308 and the thickness U of the lower side 306 can be defined individually to control the reduction in the electric field at the bottom, sides, and corners 302 of the trench 101. As described above, oxidation processes that form relatively thick oxide films on a SiC substrate are difficult. To address this challenge, the process described herein allows oxide films 402 and 602 to be formed in different steps and combined to form a thicker oxide film, such as a thicker portion of the oxidation region 120. In one embodiment, the thickness T of the bottom 308 may be substantially the same as the thickness t2. In another embodiment, the thickness T of the bottom 308 can vary in the range of about 1 nm to 500 nm depending on the duration of the second oxidation process. The thickness U of the lower side 306 can vary in the range of about 1 nm to 500 nm depending on the duration of the second oxidation process.

[0033] In Figure 8A, a conductive material 810, such as polysilicon, can be deposited in the trench 101 on the oxidation region 120. Alternatively, the conductive material 810 can be deposited on a first doped region 114 and a second doped region 116 (not shown). In such cases, as shown in Figure 8A, the conductive material 810 can be etched to remove a portion of the conductive material 810 on the first doped region 114 and the second doped region 116, and the remaining conductive material 810 can be aligned with the tops of the first doped region 114 and the second doped region 116.

[0034] In Figure 8B, an additional oxide layer 802 may be formed on the conductive material 810 by oxidation. The oxide film 802 may be a high-quality oxide that has relatively superior properties compared to other oxides in terms of purity, stability, or specific functional characteristics. The oxide layer 802 may be formed by an oxide such as SiO2. In Figure 8C, the additional oxide layer 802 may be etched to form the passivation oxide layer 108 shown in Figure 1. After etching, a source 104 may be added.

[0035] Figure 9A shows another example of a silicon carbide MOSFET including a two-stage oxide trench in one embodiment. For a description of Figure 9A, refer to the components shown in Figures 1 to 8B. In one embodiment, Figure 9A shows an entire unit, i.e., one cell, of a device 900 for mounting a SiC trench type MOSFET having an oxide region 120 and a shield region 130 as described herein, as well as a split-gate structure. The device 900 may be a split-gate trench type MOSFET including at least two gate electrodes 902 and 904. The oxide region 120 may be located between the gates 902 and 904 and the trench 101. In another embodiment, the device 900 shown in Figure 9A may mount a SiC trench type MOSFET having a shielded-gate structure together with the oxide region 120 and shield region 130 as described herein. This allows the gate electrode 904 to function as a shield and have a different doping concentration than the gate electrode 902. Figures 9B to 9E show a series of steps in the manufacturing process of the device 900.

[0036] Figure 9B shows the steps following Figure 8A. In Figure 9B, the conductive material 710 can be etched to remove portions of the conductive material 710 on the first doped region 114 and the second doped region 116, as well as portions within the trench 101. The remaining conductive material 710 forms the gate 904. In Figure 9C, an oxide layer (hereinafter referred to as "oxide film") 910 can be formed on the gate 904 by oxidation. The oxide film 910 may be, for example, SiO2. In Figure 9D, the conductive material forming the gate 902 can be deposited on the oxide 910. In Figure 9E, an additional oxide layer 802 can be added on top of the entire layered structure shown in Figure 9D to form the passivation oxide layer 108 and source 104 shown in Figure 9A.

[0037] Figure 10 is a flowchart showing a process for manufacturing a silicon carbide MOSFET including a two-stage oxide trench in one embodiment. By carrying out the process 1000 shown in Figure 10, semiconductor devices such as the apparatus 100 and / or apparatus 900 described herein can be manufactured. The exemplary process may include one or more operations, actions, or functions indicated by one or more blocks 1002, 1004, 1006, 1008, 1010, and / or 1012. Although shown in the figure as individual blocks, various blocks can be divided into additional blocks, combined into fewer blocks, omitted, executed in different orders, or executed in parallel, depending on the desired application.

[0038] Process 1000 can be started from block 1002. In block 1002, a first oxide layer having a first thickness may be formed to cover the inner surface of the trench formed in the silicon carbide (SiC) substrate. In one embodiment, a shielding region may be formed below the trench before the first oxide layer is formed. The width of the shielding region may be less than or equal to the width of the trench. The shielding region may be formed so as not to overlap with the side walls of the trench.

[0039] Process 1000 can proceed from block 1002 to block 1004. In block 1004, a layer of conductive material such as polysilicon may be formed at the bottom of a trench whose inner surface is covered with a first oxide layer.

[0040] Process 1000 can proceed from block 1004 to block 1006. In block 1006, a nitride layer may be formed above the layer of conductive material and along the side walls of the trench that are not covered by the conductive material. The nitride layer may be used as a hard mask for etching the conductive material. By etching the conductive material using the nitride layer as a hard mask, the thickness of the remaining portion of the conductive material layer becomes approximately the same as the thickness of the nitride layer 512.

[0041] Process 1000 can proceed from block 1006 to block 1008. In block 1008, a first oxidation process may be carried out to form the bottom and lower sides of the oxidation region within the trench.

[0042] Process 1000 can proceed from block 1008 to block 1010. In block 1010, after the nitride layer is removed and the exposed sidewalls of the trench are cleaned, a second oxidation process may be carried out to form the upper side of the oxidation region. In one embodiment, the oxidation region includes a bottom, a lower side, and an upper side. The thickness of the bottom is greater than the thickness of the upper side, and the thickness of the lower side is greater than the thickness of the upper side. The oxidation region is formed such that the inner surfaces of different parts of the trench have different oxide film thicknesses. The thickness of the bottom of the oxidation region is a combination of the first thickness and the thickness of the horizontal portion of the remaining layer of conductive material before oxidation. The thickness of the lower side is a combination of the first thickness and the thickness of the vertical portion of the remaining layer of conductive material before oxidation. The thickness of the upper side is determined by the duration of the second oxidation process.

[0043] Process 1000 can proceed from block 1010 to block 1012. In block 1012, the gate electrode may be formed in a trench whose inner surface is covered with an oxidation region. In one embodiment, a second oxide layer may be formed on the gate electrode. Another gate electrode may be formed on the second oxide layer. A passivation oxide layer may be formed on this other gate electrode.

[0044] [Note] Note 1: A method for forming a semiconductor device, The steps include forming a first oxide layer having a first thickness that covers the inner surface of a trench formed in a silicon carbide (SiC) substrate, The steps include forming a layer of conductive material on the bottom of a trench whose inner surface is covered with a first oxide layer, The steps include forming a nitride layer above the conductive material layer and along the side walls of the trench, • A step of etching a conductive material using a nitride layer as a hard mask, The steps include: carrying out a first oxidation process on the remaining portion of the conductive material layer to form the bottom and lower sides of the oxidation region in the trench; • The steps include removing the nitride layer and cleaning the exposed side walls of the trench, The steps include: • Performing a second oxidation process on the exposed sidewall of the trench to form the upper side of the oxidation region; The steps include forming a gate electrode in a trench whose inner surface is covered with an oxidized region, Methods that include...

[0045] Note 2: The method according to Note 1, further comprising the step of forming a shielding region below the trench before forming the first oxide layer.

[0046] Note 3: The width of the shield area is less than or equal to the width of the trench, as described in Note 2.

[0047] Note 4: The shield area does not overlap with the trench sidewall, as described in Note 2.

[0048] Note 5: The method according to Note 1, wherein by etching the conductive material using the nitride layer as a hard mask, the remaining portion of the conductive material layer has the same thickness as the nitride layer.

[0049] Note 6: The oxidized region includes the bottom, lower side, and upper side. • The thickness of the bottom is greater than the thickness of the top and sides. The thickness of the lower side is greater than the thickness of the upper side. The method described in Appendix 1.

[0050] Note 7: The thickness of the bottom is a combination of the first thickness and the thickness of the horizontal portion of the remaining layer of conductive material. The thickness of the lower side is a combination of the first thickness and the thickness of the vertical portion of the remaining layer of conductive material. The thickness of the upper side is determined by the duration of the second oxidation process. The method described in Appendix 6.

[0051] Note 8: The steps include forming a second oxide layer on the gate electrode, The steps include forming another gate electrode on a second oxide layer, The steps include forming a passivation oxide layer on another gate electrode, The method described in Appendix 1, further including the method described in Appendix 1.

[0052] Note 9: A method for forming a semiconductor device, The steps include: forming a first conductive semiconductor substrate using a silicon carbide (SiC) substrate; The steps include forming a first conductivity type drift region within a semiconductor substrate, The steps include forming a channel of a second conductivity type opposite to the first conductivity type in the drift region, The steps include forming a first conductive source region above the channel, The steps include: forming a trench adjacent to the channel that reaches the drift region, A step of forming an oxidation region within a trench so as to cover the side walls of the trench, wherein the oxidation region includes a bottom, a lower side, and an upper side, the thickness of the bottom being greater than the thickness of the upper side, and the thickness of the lower side being greater than the thickness of the upper side, The steps include forming a gate electrode in a trench whose inner surface is covered with an oxidized region, The steps include forming a second conductive shielding region that contacts the bottom of the trench, A method that includes such a method, where the width of the shield area is less than or equal to the width of the trench.

[0053] Note 10: The method according to Note 9, wherein the lower side of the oxidation region is in contact with the upper side of the oxidation region.

[0054] Note 11: The shield area does not overlap with the trench sidewall, as described in Note 9.

[0055] Note 12: The method according to Note 9, wherein the drift region is in contact with at least a portion of the upper side and at least a portion of the lower side of the oxidation region.

[0056] Note 13: The thickness of the bottom of the oxidized region is in the range of 1 nm to 500 nm, as described in Note 9.

[0057] Note 14: The thickness of the lower side of the oxidized region is in the range of 1 nm to 500 nm, as described in Note 9.

[0058] Note 15: The impurity concentration in the shielding region is lower than the impurity concentration in the channel, as described in Note 9.

[0059] Note 16: The impurity concentration in the shield area is 1 × 10⁻⁶ 15 cm -3 ~5×10 17 cm -3 The method described in Appendix 9, which is within the scope of the specified method.

[0060] Note 17: A method for forming a semiconductor device, The steps include: forming a first conductive semiconductor substrate using a silicon carbide (SiC) substrate; The steps include forming a first conductivity type drift region within a semiconductor substrate, The steps include forming a channel of a second conductivity type opposite to the first conductivity type in the drift region, The steps include forming a first conductive source region above the channel, The steps include: forming a trench adjacent to the channel that reaches the drift region, The step of forming an oxidation region within a trench so as to cover the side walls of the trench, wherein the oxidation region includes a bottom, a lower side, and an upper side, the thickness of the bottom being greater than the thickness of the upper side, and the thickness of the lower side being greater than the thickness of the upper side, The steps include forming at least one gate electrode in a trench whose inner surface is covered with an oxidized region, The step of forming a second conductive shielding region that contacts the bottom of the trench, wherein the width of the shielding region is less than or equal to the width of the trench, Methods that include...

[0061] Note 18: The method described in Note 16, wherein the lower side of the oxidation region is in contact with the upper side of the oxidation region.

[0062] Note 19: The method described in Note 16, wherein the shield area does not overlap with the side wall of the trench.

[0063] Note 20: The method according to Note 16, wherein the drift region is in contact with at least a portion of the upper side and at least a portion of the lower side of the oxidation region.

[0064] The terms used herein are used solely to describe specific embodiments and are not intended to limit the invention. Unless otherwise specified, singular terms used herein are also intended to include plural forms. Furthermore, the term “equipped with” as used herein defines the presence of the described features, integers, steps, actions, elements, and / or components, but does not exclude the presence or addition of one or more features, integers, steps, actions, elements, components, and / or groups thereof.

[0065] All means or steps and corresponding structures, materials, operations, and their equivalents described in the appended claims are intended to encompass any structures, materials, or operations for achieving a function in combination with other elements specifically described. The description of the disclosed embodiments of the present invention is provided for illustrative and explanatory purposes, but is not intended to be exhaustive or to limit oneself to the disclosed forms. It will be apparent to those skilled in the art that many modifications and variations can be applied without departing from the scope and spirit of the invention. The embodiments described above have been selected and described in order to best illustrate the principles and practical applications of the present invention, and so that those skilled in the art may understand the invention in terms of various embodiments with various modifications to suit the specific applications under consideration.

Claims

1. A semiconductor device, A first conductive semiconductor substrate formed of silicon carbide (SiC), The first conductivity type drift region formed on the semiconductor substrate, A channel of a second conductivity type opposite to the first conductivity type is formed on the drift region, The first conductive source region formed on the channel, A trench that penetrates the source region and the channel and reaches the drift region, The oxidation region covering the inner surface of the trench, The oxidized region includes the bottom, lower side, and upper side. The thickness of the bottom portion is greater than the thickness of the upper side portion. The thickness of the lower side portion is greater than the thickness of the upper side portion. Oxidation region, A gate electrode formed in the trench whose inner surface is covered by the aforementioned oxidation region, The second conductive shielding region in contact with the bottom of the trench, Equipped with, The width of the shield region is less than or equal to the width of the trench. Semiconductor equipment.

2. The semiconductor device according to claim 1, wherein the lower side of the oxidation region is in contact with the upper side of the oxidation region.

3. The semiconductor device according to claim 1, wherein the shielding region does not overlap with the side wall of the trench.

4. The semiconductor device according to claim 1, wherein the drift region is in contact with at least a portion of the upper side of the oxidation region and at least a portion of the lower side of the oxidation region.

5. The semiconductor device according to claim 1, wherein the thickness of the bottom of the oxidation region is in the range of 1 nm to 500 nm.

6. The semiconductor device according to claim 1, wherein the thickness of the lower side portion of the oxidation region is in the range of 1 nm to 500 nm.

7. The semiconductor device according to claim 1, wherein the impurity concentration in the shield region is lower than the impurity concentration in the channel.

8. The impurity concentration in the shield region is 1 × 10 １５ cm －３ ~5 x 10 １７ cm －３ A semiconductor device according to claim 1, which is within the range of

9. A semiconductor device, A first conductive semiconductor substrate formed of silicon carbide (SiC), The first conductivity type drift region formed on the semiconductor substrate, A channel of a second conductivity type opposite to the first conductivity type is formed on the drift region, The first conductive source region formed on the channel, A trench that penetrates the source region and the channel and reaches the drift region, The oxidation region covering the inner surface of the trench, The oxidized region includes the bottom, lower side, and upper side. The thickness of the bottom portion is greater than the thickness of the upper side portion. The thickness of the lower side portion is greater than the thickness of the upper side portion. Oxidation region, At least one gate electrode formed in the trench whose inner surface is covered by the oxidation region, The second conductive shielding region in contact with the bottom of the trench, Equipped with, The width of the shield region is less than or equal to the width of the trench. Semiconductor equipment.

10. The semiconductor device according to claim 9, wherein the lower side of the oxidation region is in contact with the upper side of the oxidation region.

11. The semiconductor device according to claim 9, wherein the shielding region does not overlap with the side wall of the trench.

12. The semiconductor device according to claim 9, wherein the drift region is in contact with at least a portion of the upper side of the oxidation region and at least a portion of the lower side of the oxidation region.

13. A method for forming a semiconductor device, The steps include forming a first oxide layer having a first thickness to cover the inner surface of a trench formed in a silicon carbide (SiC) substrate, The steps include forming a layer of conductive material on the bottom of the trench, which is covered on its inner surface with the first oxide layer, The steps include forming a nitride layer above the conductive material layer and along the side wall of the trench, The steps include etching the conductive material using the nitride layer as a hard mask, The steps include: performing a first oxidation process on the remaining portion of the conductive material layer to form the bottom and lower sides of the oxidation region in the trench; The steps of removing the nitride layer and The steps include cleaning the exposed side wall of the trench, The steps include: performing a second oxidation process on the exposed side wall of the trench to form the upper side of the oxidation region; The steps include forming a gate electrode in the trench whose inner surface is covered by the oxidized region, Methods that include...

14. The method according to claim 13, further comprising the step of forming a shielding region below the trench before forming the first oxide layer.

15. The method according to claim 14, wherein the width of the shield region is less than or equal to the width of the trench.

16. The method according to claim 14, wherein the shield region does not overlap with the side wall of the trench.

17. The method according to claim 13, wherein the conductive material is etched using the nitride layer as a hard mask, so that the remaining portion of the conductive material layer has the same thickness as the nitride layer.

18. The oxidized region includes the bottom, the lower side, and the upper side. The thickness of the bottom portion is greater than the thickness of the upper side portion. The thickness of the lower side portion is greater than the thickness of the upper side portion. The method according to claim 13.

19. The thickness of the bottom portion is a combination of the first thickness and the thickness of the horizontal portion of the remaining part of the conductive material layer. The thickness of the lower side portion is a combination of the first thickness and the thickness of the vertical portion of the remaining part of the conductive material layer. The thickness of the upper side portion is determined by the duration of the second oxidation process. The method according to claim 18.

20. The steps include forming a second oxide layer on the gate electrode, The steps include forming another gate electrode on the second oxide layer, The steps include forming a passivation oxide layer on the aforementioned other gate electrode, The method according to claim 13, further comprising:

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