substrate

Abstract

To provide a substrate that contributes to cost reduction and miniaturization in electronic devices. [Solution] The substrate 1 is a substrate for mounting a power semiconductor 2, which is laminated with an insulating layer i in between and has a plurality of conductors c, and includes a drain / collector connection part 8 formed by making electrical connections between conductors c, c arranged in different layers and connected to the drain terminal or collector terminal of the power semiconductor 2, and a source / emitter connection part 10 formed by making electrical connections between conductors c, c arranged in different layers and connected to the source / emitter terminal of the power semiconductor 2.

Description

Technical Field

[0001] The present invention relates to a substrate.

Background Art

[0002] In a substrate for mounting a power semiconductor such as a conventional FET (Field-effect transistor) or IGBT (Insulated Gate Bipolar Transistor), for example, it is used in an inverter or the like for driving a motor, and forms legs and arms in the inverter together with the mounted power semiconductor (see, for example, Patent Document 1).

[0003] When it is necessary to supply a large current to a motor, a plurality of power semiconductors are used for one arm, and the substrate allows mounting of a plurality of power semiconductors, and the copper foil provided inside to form wiring also allows a large current. Therefore, a thick one is used.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] As described above, when a thick copper foil is adopted to allow a large current, etching of the copper foil for mounting a microcomputer or the like with a narrow interval between terminals and pads becomes difficult. Therefore, in a substrate designed to allow a large current, it is difficult to mount a microcomputer or the like together with a power semiconductor.

[0006] Therefore, a substrate for mounting a microcomputer or the like is required separately from the substrate for mounting a power semiconductor, and there is a problem that the cost of an electronic device including these substrates and mounted products increases and the size becomes larger.

[0007] Therefore, the present invention aims to provide a substrate that contributes to cost reduction and miniaturization in electronic devices. [Means for solving the problem]

[0008] To achieve the above objective, the substrate of the present invention is a substrate for mounting power semiconductors, which is laminated with an insulating layer in between and includes a plurality of conductors, and is configured to include a drain / collector connection portion formed by electrically connecting conductors arranged in different layers and connected to the drain terminal or collector terminal of the power semiconductor, and a source / emitter connection portion formed by electrically connecting conductors arranged in different layers and connected to the source terminal or emitter terminal of the power semiconductor.

[0009] With a substrate configured in this way, even without increasing the thickness of the conductors, the cross-sectional area of ​​the current path can be secured by stacking multiple conductors that constitute the drain / collector connection and source / emitter connection. This allows for the use of thin conductors while accommodating large currents, making it possible to etch conductors for mounting not only power semiconductors but also microcontrollers and other devices with narrow terminal and pad spacing. Therefore, with the substrate of this embodiment, it is possible to mount not only power semiconductors but also microcontrollers and other devices with narrow terminal and pad spacing. This eliminates the need to mount power semiconductors and microcontrollers separately on multiple substrates, thereby reducing the cost of electronic devices including the substrate and contributing to the miniaturization of electronic devices.

[0010] Furthermore, the substrate may include a drain / collector relay section formed of multiple conductors stacked above the drain / collector connection section and the source / emitter connection section, which is connected to the drain terminal or collector terminal of multiple power semiconductors and the drain / collector connection section, and a source / emitter relay section formed of multiple conductors stacked above the drain / collector connection section and the source / emitter connection section and arranged in the same layer as the drain / collector relay section, which is connected to the source terminal or emitter terminal of multiple power semiconductors and the source / emitter connection section.

[0011] With a substrate configured in this way, regardless of the structure of the power semiconductor, it is possible to mount the power semiconductor on the substrate and allow for high current while suppressing heat generation, and to mount the power semiconductor while avoiding an increase in the size of the substrate.

[0012] Furthermore, the drain / collector connection and source / emitter connection on the substrate may have multiple trapezoidal conductors stacked on the same layer, and the conductors in the drain / collector connection and the conductors in the source / emitter connection, which are located on the same layer, may be arranged alternately with their slanted sides facing each other, with the narrow side and the wide side that connects to the outside facing opposite directions. With a substrate configured in this way, the amount of conductors used on the substrate can be reduced while avoiding current concentration, thereby reducing the cost of the substrate and suppressing heat generation.

[0013] Furthermore, the substrate may include a drain / collector wiring integration section located below the drain / collector connection and source / emitter connection, positioned in a plan view on the lower bottom side of the conductors of the drain / collector connection, facing all of the drain / collector connection and source / emitter connection, and protruding from the row on the lower bottom side of the conductors of the drain / collector connection; and a source / emitter wiring integration section located below the drain / collector connection and source / emitter connection, positioned in a plan view on the lower bottom side of the conductors of the source / emitter connection, facing all of the drain / collector connection and source / emitter connection.

[0014] With a substrate configured in this way, since the drain / collector wiring integration section and the source / emitter wiring integration section are provided below the drain / collector connection section and the source / emitter connection section, when mounting multiple power semiconductors with multiple drain / collector connection sections and source / emitter connection sections, the drain terminals or collector terminals can be connected in parallel by the drain / collector wiring integration section, and the source terminals or emitter terminals can be connected in parallel by the source / emitter wiring integration section. This allows for easy connection of the drain terminals or collector terminals and the source terminals or emitter terminals to an external power supply, ground, or electrical equipment such as a motor. Furthermore, the space below the drain / collector connection section and the source / emitter connection section can be effectively utilized to efficiently arrange the drain / collector wiring integration section and the source / emitter wiring integration section without increasing the size of the substrate.

[0015] Furthermore, the substrate may be formed of conductors laminated above the drain / collector wiring integration section and in a portion that does not overlap with the drain / collector connection section in a plan view, and may also include a drain / collector external connection section connected to the drain / collector wiring integration section, and a source / emitter external connection section formed of conductors laminated above the source / emitter wiring integration section and in a portion that does not overlap with the source / emitter connection section in a plan view, and connected to the source / emitter wiring integration section.

[0016] With a substrate configured in this way, a drain / collector external connection section formed by a conductor stacked above the drain / collector wiring integration section and a source / emitter external connection section formed by a conductor stacked above the source / emitter wiring integration section are provided. As a result, wiring for external power supplies, ground, motors, and other electrical equipment can be connected from the top surface of the substrate on which the power semiconductors are mounted, improving the usability of the substrate. Furthermore, the space above the drain / collector wiring integration section and the source / emitter wiring integration section can be effectively utilized to efficiently arrange the drain / collector external connection section and the source / emitter external connection section, thus avoiding an increase in the size of the substrate.

[0017] Furthermore, the substrate may have a metal layer for heat dissipation in the lowermost layer. According to the substrate configured in this way, heat generated by the flow of current through the power semiconductor mounted on the substrate and the conductors in the substrate can be efficiently released to the outside from the metal layer, suppressing the burnout of the power semiconductor.

Advantages of the Invention

[0018] As described above, according to the substrate of the present invention, the cost in electronic devices can be reduced and miniaturization can be contributed to.

Brief Description of the Drawings

[0019] [Figure 1] FIG. 1 is a plan view of a substrate in one embodiment. [Figure 2] FIG. 2(a) is a side view of a FET mounted on a substrate in one embodiment. FIG. 2(b) is a bottom view of a FET mounted on a substrate in one embodiment. [Figure 3] FIG. 3 is a partially enlarged plan view of a substrate in one embodiment. [Figure 4] FIG. 4(a) is a cross-sectional view showing a partial enlargement of the XX cross-section of a substrate in one embodiment. FIG. 4(b) is a cross-sectional view showing a partial enlargement of the YY cross-section of a substrate in one embodiment. [Figure 5] FIG. 5 is an arrangement diagram of copper foils from the fifth layer to the seventh layer of a substrate in one embodiment. [Figure 6] FIG. 6 is an arrangement diagram of copper foils from the third layer to the fourth layer of a substrate in one embodiment. [Figure 7] FIG. 7 is an arrangement diagram of the copper foil of the second layer of a substrate in one embodiment. [Figure 8] FIG. 8 is an arrangement diagram of the copper foil of the first layer of a substrate in one embodiment.

Embodiments for Carrying Out the Invention

[0020] The present invention will be described below based on the embodiments shown in the figures. In one embodiment, as shown in Figures 1 and 3 to 8, the substrate 1 is configured to include eight layers of copper foil c as a conductor and an insulating layer i formed of an insulator provided between the copper foils c, c, and the upper surface includes a pattern circuit section P having a mounting section A on which ten FETs 2 as power semiconductors are mounted in a row. In this embodiment, as shown in Figure 1, the substrate 1 has six pattern circuit sections P arranged in the left-right direction in Figure 1. Ten FETs 2 are mounted on the mounting section A of each pattern circuit section P on the substrate 1. In this embodiment, the conductor is copper foil c, but it may be a metal other than copper foil.

[0021] As shown in Figure 2, the FET2, as a power semiconductor, in this embodiment comprises a rectangular resin case 2a that houses the semiconductor internally, and 30 pads 2b that protrude from the lower end of the resin case 2a in an arrangement of 2 columns and 15 rows. In Figure 2(b), the top left pad 2b and the bottom right pad 2b in the FET2 are the gate terminal and the bottom right pad 2b are the insulating terminal, respectively. In addition, two adjacent pads 2b in the same row are either source terminals or drain terminals. Excluding the gate terminal and insulating terminal, the pads 2b alternately form source terminals and drain terminals in the column direction. Note that in Figure 2(b), the pads 2b in the row adjacent to the gate terminal and insulating terminal are source terminals.

[0022] On the other hand, the substrate 1 includes a drain / collector connection section 8 connected to the drain terminal of the FET 2, a source / emitter connection section 10 connected to the source terminal of the FET 2, a drain / collector relay section 17 stacked above the drain / collector connection section 8 and the source / emitter connection section 10 and connected to multiple drain terminals and the drain / collector connection section 8, a source / emitter relay section 20 stacked above the drain / collector connection section 8 and the source / emitter connection section 10 and connected to multiple source terminals and the source / emitter connection section 10, and the drain / collector connection section 8 and the source / emitter relay section 10. The substrate 1 comprises a pattern circuit section P which includes a drain / collector wiring integration section 4 and a source / emitter wiring integration section 5 located below the emitter connection section 10, a drain / collector external connection section 11 located above the drain / collector wiring integration section 4 and connected to the drain / collector wiring integration section 4, and a source / emitter external connection section 12 located above the source / emitter wiring integration section 5 and connected to the source / emitter wiring integration section 5, and a metal layer 3 for heat dissipation at the bottom layer. In this embodiment, the substrate 1 comprises six rectangular flat pattern circuit sections P, each having a mounting section A on which the FET 2 is mounted. Since the pattern circuit sections P on the substrate 1 have the same structure, only the configuration of one pattern circuit section P will be described in detail to avoid duplication of explanation.

[0023] As shown in Figure 4, the substrate 1 is formed by alternately laminating copper foil c and insulating layer i. More specifically, as shown in Figure 4, the insulating layer i is formed on the entire upper surface of the substrate 1, and a heat-dissipating metal layer 3 made of copper foil c is provided on the lower surface, and it is not connected to any of the copper foil c which are conductors of different layers. The metal layer 3 is provided so as to cover the entire lower surface of the substrate 1 and is located below the insulating layer i which is located at the bottom. The metal layer 3 is provided on the entire lower surface of the substrate 1 in order to efficiently dissipate heat, but it may also be provided on a part of the lower surface of the substrate 1, and even if it is provided on only a part, heat dissipation can be improved by providing it so as to face the area where the heat-generating copper foil c is located in a plan view.

[0024] As shown in Figure 4, the substrate 1 has a thermal conductive grease (not shown) applied to the metal layer 3, and then the metal layer 3 is in contact with the housing 100 or heat sink that houses the substrate 1. When current flows through the pattern circuit section P, the heat generated is conducted from the metal layer 3 to the housing 100 or heat sink, allowing for efficient heat dissipation to the outside of the substrate 1.

[0025] As shown in Figure 5, in the seventh layer from the top layer of copper foil c in the pattern circuit section P of substrate 1, which is laminated on top of the copper foil c that forms the metal layer 3 of substrate 1, a pair of trapezoidal copper foils c,c are installed. In Figure 5, the copper foil c on the right is a trapezoid formed by vertically dividing a single parallelogram, and they are arranged to face each other with their hypotenuses slightly separated, forming a parallelogram. In other words, the copper foil c on the right side of Figure 5 and the copper foil c on the left side of Figure 5 are the same trapezoid shape, and one copper foil c is rotated 180 degrees on the plane of the paper relative to the other copper foil c, and then they are arranged so that the top base of one copper foil c and the bottom base of the other copper foil c are in a straight line. The shape and arrangement of these copper foils c,c are the same as in the fifth and sixth layers.

[0026] Furthermore, the copper foils c from the 5th to the 7th layer, located on the right side in Figure 5, are electrically connected to each other by copper members 41 that are fully embedded in multiple via holes 40 provided in the insulating layer i between the laminated copper foils c, c, as shown in Figure 4, and also by copper members 31 that are fully embedded in a via hole 30 provided in the upper right of Figure 5. Thus, the drain / collector wiring integration section 4 is formed by the three copper foils c, which are arranged and laminated on the right side in Figure 5 from the 5th to the 7th layer. In this way, the drain / collector wiring integration section 4 is formed by three trapezoidal copper foils c that are laminated in the vertical direction, and copper members 31, 41 that connect these three copper foils c.

[0027] On the other hand, the copper foils c from the 5th to the 7th layer, located on the left side in Figure 5, are electrically connected to each other by copper members 43 that are fully embedded in multiple via holes 42 provided in the insulating layer i between the laminated copper foils c, c, as shown in Figure 4, and are also connected to each other by copper members 33 that are fully embedded in a via hole 32 provided in the lower left of Figure 4. The source / emitter wiring integration section 5 is formed by the three copper foils c, which are arranged and laminated on the left side in Figure 5 from the 5th to the 7th layer. Thus, the source / emitter wiring integration section 5 is formed by three trapezoidal copper foils c that are laminated in the vertical direction, and copper members 33, 43 that connect these three copper foils c. As shown in Figure 4, via holes 40 and 42 are also formed in the insulating layer i between the fourth layer of copper foil c and the fifth layer of copper foil c constituting the drain / collector wiring integration section 4 and source / emitter wiring integration section 5, and copper members 41 and 43 are fully embedded in these via holes 40 and 42, respectively.

[0028] As shown in Figure 6, the fourth layer of copper foil c from the top layer of substrate 1, which is stacked above the area where the copper foil c of the drain / collector wiring integration section 4 and the copper foil c of the source / emitter wiring integration section 5 face each other, is arranged in a row along the vertical direction in Figure 6, which is the longitudinal direction of the gap between the drain / collector wiring integration section 4 and the source / emitter wiring integration section 5, so as to straddle both the drain / collector wiring integration section 4 and the source / emitter wiring integration section 5 in a plan view.

[0029] As shown in Figure 6, of the 11 copper foils c arranged in the fourth layer, above the drain / collector wiring integration section 4 and the source / emitter wiring integration section 5, and arranged in a row spanning both sections, 9 of the copper foils c are isosceles trapezoids. Adjacent copper foils c are rotated 180 degrees on the paper alternately so that the narrower top side (upper base) and the wider bottom side (lower base) that connects to external equipment are in opposite directions, and are arranged in a row with a gap between the hypotenuses. Thus, in Figure 6, adjacent copper foils c, c arranged in a row in the vertical direction are arranged with their top and bottom bases reversed and their hypotenuses facing each other. Furthermore, among the copper foils c arranged in the fourth layer, the uppermost and lowermost copper foils c in Figure 6 are trapezoids obtained by cutting the other nine copper foils c in half along lines perpendicular to the top and bottom bases, and are arranged in a row with their hypotenuses facing each other.

[0030] More specifically, in Figure 6, adjacent copper foils c are arranged in a row along the vertical direction such that the upper base of one copper foil c and the lower base of the other copper foil c are aligned on the same straight line.

[0031] On the other hand, among the copper foils c arranged in the third layer, the copper foils c arranged in a row above the drain / collector wiring integration section 4 and the source / emitter wiring integration section 5, and spanning both the drain / collector wiring integration section 4 and the source / emitter wiring integration section 5, are arranged above the copper foils c of the fourth layer via an insulating layer i, so as to be the same shape and in the same position as the copper foils c arranged in a row spanning the drain / collector wiring integration section 4 and the source / emitter wiring integration section 5 of the fourth layer in a plan view of the substrate 1.

[0032] Furthermore, of the copper foils c arranged in rows, the five copper foils c of the third layer and the five copper foils c of the fourth layer, whose lower bases are positioned above the drain / collector wiring integration section 4, are positioned so as to overlap exactly in the vertical direction on the substrate 1. These 10 copper foils c are electrically connected to each other by a first copper member 7, which is fully embedded in a via hole 6 provided in the insulating layer i between the third layer and the fourth layer of copper foils c, as shown in Figure 4(a), and form a drain / collector connection section 8 that is connected to the drain terminal of the FET 2. In addition, 14 via holes 6 arranged in two rows are provided for each copper foil c that constitutes the drain / collector connection section 8, and the first copper member 7 is fully embedded in each via hole 6.

[0033] On the other hand, among the rows of copper foils c, the six copper foils c of the third layer and the six copper foils c of the fourth layer, whose lower bases are positioned above the source / emitter wiring integration section 5, are positioned to overlap exactly in the vertical direction on the substrate 1. These 12 copper foils c, as shown in Figure 4(b), are electrically connected to each other by a second copper member 9 embedded in via holes 6 provided in the insulating layer i between the third and fourth layers of copper foils c, forming a source / emitter connection section 10 that is connected to the source terminal of the FET 2. Thus, the source / emitter connection section 10 is composed of the copper foils c at both ends of the middle row in Figure 6. In addition, for each of the copper foils c constituting the source / emitter connection section 10, excluding the copper foils at both ends of the row, 14 via holes 6 are provided in two rows, and the second copper member 9 is embedded completely inside each via hole 6. Furthermore, seven via holes 6 are arranged in a row for each copper foil c at both ends of the row that constitute the source / emitter connection section 10, and the second copper member 9 is embedded completely inside each via hole 6.

[0034] The copper foil c forming the drain / collector connection 8 and the copper foil c forming the source / emitter connection 10, which are located on the same layer, are arranged alternately along the gap between the drain / collector wiring integration section 4 and the source / emitter wiring integration section 5, with their hypotenuses facing each other with a gap in between, forming a row. Viewed from the perspective of the drain / collector connection 8 and the source / emitter connection 10, the drain / collector wiring integration section 4 is located below the drain / collector connection 8 and the source / emitter connection 10, and in a plan view, it is positioned on the lower bottom side of the copper foil c of the drain / collector connection 8, rather than the center of the row of copper foil c of the drain / collector connection 8 and the copper foil c of the source / emitter connection 10. Furthermore, it is positioned opposite all of the drain / collector connection 8 and the source / emitter connection 10, extending from the row towards the lower bottom side, which is the wider side of the copper foil c of the drain / collector connection 8. Furthermore, as viewed from the drain / collector connection 8 and the source / emitter connection 10, the source / emitter wiring integration section 5 is located below the drain / collector connection 8 and the source / emitter connection 10, and in a plan view, it extends from the center of the row of copper foil c of the drain / collector connection 8 and the copper foil c of the source / emitter connection 10 towards the lower bottom side, which is the wider side of the copper foil c of the source / emitter connection 10, and is positioned to face both the drain / collector connection 8 and the source / emitter connection 10 and protrude from the row towards the lower bottom side of the copper foil c of the source / emitter connection 10. Note that the copper foil c as a conductor constituting the drain / collector connection 8 or the source / emitter connection 10 is trapezoidal, but it does not need to be a perfect trapezoid; it only needs to be roughly trapezoidal, and it may have notches or protrusions in some parts.

[0035] Furthermore, as shown in Figure 6, in the third and fourth layers, triangular copper foils c are laminated via an insulating layer i at positions that overlap above the fifth to seventh layers of the drain / collector wiring integration section 4, to the right of the aforementioned drain / collector connection section 8 and spaced apart from each copper foil c forming the drain / collector connection section 8. In a plan view, these positions overlap above the fifth to seventh layers of the drain / collector wiring integration section 4. In a plan view, the copper foils c of each layer in the drain / collector external connection section 11 have substantially the same shape as the triangular portion on the right side of the drain / collector wiring integration section 4, and are laminated so as to overlap with the drain / collector wiring integration section 4. These triangular copper foils c, positioned to the right of the third and fourth layer drain / collector connection portions 8, are electrically connected to each other by copper members 61, which are fully embedded in multiple via holes 60 provided along the vertically aligned edges in Figure 6, and copper members 31, which are provided along the upper edge in Figure 6 and fully embedded in via holes 30, thereby forming the drain / collector external connection portion 11.

[0036] Furthermore, the copper foil c of the drain / collector connection section 8 and the copper foil c of the drain / collector wiring integration section 4 are electrically connected to each other by copper members 41 that are fully embedded in multiple via holes 40 located at the same positions as the via holes 6 that connect the copper foils c constituting the drain / collector connection section 8, in a plan view of the substrate 1 from above.

[0037] Furthermore, as shown in Figure 6, in the third and fourth layers, triangular copper foils c are laminated via an insulating layer i at positions that overlap above the fifth to seventh layers of the source / emitter wiring integration section 5, to the left of the aforementioned drain / collector connection section 8 and spaced apart from each copper foil c forming the source / emitter connection section 10. In a plan view, each copper foil c in the source / emitter external connection section 12 has substantially the same shape as the triangular portion on the left side of the source / emitter wiring integration section 5, and is laminated so as to overlap with the source / emitter wiring integration section 5. These triangular copper foils c, positioned to the left of the third and fourth layer source / emitter connection portions 10, are connected to each other by copper members 63 fully embedded in multiple via holes 62 provided along the vertically aligned edges in Figure 6, and copper members 33 fully embedded in via holes 32 provided along the lower edge in Figure 6, in a position that does not interfere with the source / emitter connection portions 10 of the insulating layer i, thereby forming the source / emitter external connection portion 12.

[0038] Furthermore, the copper foil c of the source / emitter connection section 10 and the copper foil c of the source / emitter wiring integration section 5 are electrically connected to each other by copper members 43 that are fully embedded in a plurality of via holes 42 located at the same positions as the via holes 6 that connect the copper foils c constituting the source / emitter connection section 10, in a plan view of the substrate 1 from above.

[0039] As shown in Figure 7, in the second layer of substrate 1, above the copper foil c of the drain / collector connection 8 and the copper foil c of the source / emitter connection 10, and counting from the top layer of copper foil c of substrate 1, multiple strip-shaped copper foils c are installed in parallel in a plan view, straddling the rows of copper foil c of the drain / collector connection 8 and the source / emitter connection 10. Specifically, in the third layer above the drain / collector connection 8 and the source / emitter connection 10, 14 elongated strip-shaped copper foils c are provided, with their longitudinal direction aligned with the vertical direction in Figure 7 and arranged parallel to the left-right direction in Figure 7.

[0040] Ten FETs 2 will be mounted above the copper foil c of the drain / collector connection 8 and the copper foil c of the source / emitter connection 10 on the substrate 1, arranged in the same direction as the rows of these copper foils c. The fourteen strip-shaped copper foils c correspond to the positions of 14 of the 15 pads 2b that form a row on the FET 2 in a plan view, and are arranged parallel to each other in the left-right direction in Figure 7 with the same pitch as adjacent pads 2b, 2b in the row direction of the pads 2b.

[0041] The 14 copper foils c correspond to the alternately arranged drain terminal pads 2b and source terminal pads 2b of the FET2, and in the left-right direction of Figure 7, the copper foils c for the drain / collector and the copper foils c for the source / emitter are arranged alternately.

[0042] Of the copper foil c in the second layer, the copper foil c connected to the drain terminal of FET2 is electrically connected to the drain / collector connection 8 via a copper member 51 that is fully embedded in a via hole 50 formed in the insulating layer i that faces the copper foil c of the third layer's drain / collector connection 8 in a plan view. Furthermore, of the copper foil c in the second layer, the copper foil c connected to the source terminal of FET2 is electrically connected to the drain / collector connection 8 via a copper member 53 that is fully embedded in a via hole 52 formed in the insulating layer i that faces the copper foil c of the third layer's source / emitter connection 10 in a plan view.

[0043] In addition, the second layer has 14 copper foils c, as well as a triangular copper foil c provided in a position that overlaps with the triangular copper foil c forming the drain / collector external connection part 11, to the right of the aforementioned drain / collector connection part 8 in a plan view, and a triangular copper foil c provided in a position that overlaps with the triangular copper foil c forming the source / emitter external connection part 12, to the left of the aforementioned source / emitter connection part 10 in a plan view.

[0044] Furthermore, in the first uppermost layer of the substrate 1, above the copper foil c of the drain / collector connection 8 and the copper foil c of the source / emitter connection 10, as shown in Figure 8, multiple strip-shaped copper foils c are arranged in parallel in a plan view, straddling the rows of copper foil c of the drain / collector connection 8 and the source / emitter connection 10. Specifically, above the drain / collector connection 8 and the source / emitter connection 10 of the first layer, fifteen elongated strip-shaped copper foils c are arranged with their longitudinal direction aligned vertically in Figure 8 and parallel to the horizontal direction in Figure 8.

[0045] The 14 strip-shaped copper foils c of the first layer correspond to the positions of 14 of the 15 pads 2b that make up the row of 10 FETs 2 mounted on top of the substrate 1. They are arranged parallel to each other in the left-to-right direction in Figure 8, with the same pitch as adjacent pads 2b, 2b in the row direction of the pads 2b.

[0046] The 14 copper foils c of the first layer are stacked on top of the corresponding 14 copper foils c of the second layer, corresponding to the alternately arranged drain terminal pads 2b and source terminal pads 2b of the FET2, with the copper foils c for the drain / collector and the copper foils c for the source / emitter arranged alternately in the left-right direction of Figure 8.

[0047] Furthermore, to the left of these 14 copper foils c in the first layer, in Figure 8, is a gate connection section 13 made of elongated copper foil arranged parallel to these 14 copper foils c. The gate connection section 13 has a protruding piece 13a that projects to the right and faces the pad 2b of the gate terminal of each FET 2.

[0048] The 14 copper foils c of the first layer and the 14 copper foils c of the second layer, which are positioned below the 14 copper foils c of the first layer and connected to the pad 2b of the drain terminal of the FET2, are connected to each other by copper members 74 embedded in a plurality of via holes 73 that penetrate the insulating layer i between the first layer copper foils c and the second layer copper foils c, as shown in Figure 4(a). The via holes 73 are provided at positions opposite to the pad 2b of the drain terminal, and the pad 2b of the drain terminal is connected to the copper foil c directly below the pad 2b of the drain terminal via the copper members 74. The via holes 50 for connecting the copper foil c of the second layer connected to the drain terminal and the copper foil c of the third layer drain / collector connection section 8 are provided at positions that overlap with the via holes 73 in a plan view of the substrate 1 from above. Therefore, 14 via holes 73 and 14 via holes 50 are provided at the same positions for each copper foil c in the drain / collector connection section 8.

[0049] Furthermore, the 14 copper foils c of the first layer and the 14 copper foils c of the second layer, which are positioned below the 14 copper foils c of the first layer and connected to the source terminal pads 2b of the FET2, are connected to each other by copper members 76 embedded in a plurality of via holes 75 that penetrate the insulating layer i between the first layer copper foils c and the second layer copper foils c, as shown in Figure 4(b). The via holes 75 are provided at positions facing the source terminal pads 2b, and the source terminal pads 2b are connected to the copper foil c directly below the source terminal pads 2b via the copper members 76. The via holes 52 for connecting the copper foil c connected to the source terminal of the second layer and the copper foil c of the source / emitter connection section 10 of the third layer are provided in a position that overlaps with the via holes 75 when viewed from above on the substrate 1. Therefore, 13 via holes 75 and 52 are provided in the same position for each copper foil c, excluding the copper foil c at both ends of the copper foil c of the source / emitter connection section 10 which are arranged in a row. Note that since there are no copper foil c installed in the first and second layers directly below the pad 2b which is the source terminal in the row next to the gate terminal pad 2b of the FET2, if there is copper foil c in the source / emitter connection section 10 in the third layer directly below the pad 2b, the pad 2b is directly connected to the source / emitter connection section 10 through a copper member that is fully embedded in a via hole (not shown).

[0050] Thus, the copper foil c of the first layer c and the copper foil c of the second layer c connected to the pad 2b which will be the drain terminal form a drain / collector relay section 17 which is connected to the drain terminal of each of the 10 FETs 2 and the drain / collector connection section 8, and the copper foil c of the first layer c and the copper foil c of the second layer c connected to the pad 2b which will be the source terminal of the FET 2 form a source / emitter relay section 20 which is connected to the drain terminal of each of the 10 FETs 2 and the source / emitter connection section 10.

[0051] As shown in Figure 8, the area directly above the drain / collector relay section 17, the source / emitter relay section 20, and the protruding piece 13a of the gate connection section 13 in the pattern circuit section P of the substrate 1 is defined as the mounting section A of the pattern circuit section P. Ten FETs 2 are mounted on this mounting section A, arranged in a row in the vertical direction in Figure 1, as shown in Figure 1. The gate terminal pads 2b of the FETs 2 are connected to the gate connection section 13, the drain pads 2b are connected to the drain / collector relay section 17, and the source pads 2b are connected to the source / emitter relay section 20.

[0052] Furthermore, the via holes 6 that connect the copper foils c of the drain / collector connection part 8, the via holes 50 that connect the second layer copper foil c and the third layer copper foil c of the drain / collector connection part 8, the via holes 73 that connect the first and second layers of copper foil c located above the copper foil c of the drain / collector connection part 8, and the via hole 40 that connects the drain / collector connection part 8 to the drain / collector wiring integration part 4 are formed by a series of via holes that are located at the same position in a plan view of the substrate 1 and are arranged perpendicular to the substrate 1, making the processing of the substrate 1 easy. In addition, the first copper member 7 provided in via hole 6, the copper member 51 provided in via hole 50, the copper member 74 provided in via hole 73, and the copper member 41 provided in via hole 40 can be formed by embedding a single copper component in a continuous via hole, making the processing of the substrate 1 easy in this respect as well.

[0053] Furthermore, the via holes 6 that connect the copper foils c of the source / emitter connection section 10, the via holes 52 that connect the second layer copper foil c and the third layer copper foil c of the source / emitter connection section 10, the via holes 75 that connect the first and second layers of copper foil c located above the copper foil c of the source / emitter connection section 10, and the via hole 42 that connects the source / emitter connection section 10 to the source / emitter wiring integration section 5 are formed by a series of via holes that are located at the same position in a plan view of the substrate 1 and are arranged perpendicular to the substrate 1, making the processing of the substrate 1 easy. In addition, the second copper member 9 provided in via hole 6, the copper member 53 provided in via hole 52, the copper member 76 provided in via hole 75, and the copper member 43 provided in via hole 42 can be formed by embedding a single copper component in a continuous via hole, making the processing of the substrate 1 easy in this respect as well.

[0054] Furthermore, in addition to the 14 copper foils c, the first layer has a triangular copper foil c provided in a position that overlaps with the triangular copper foil c forming the drain / collector external connection part 11, to the right of the aforementioned drain / collector connection part 8 in a plan view, and a triangular copper foil c provided in a position that overlaps with the triangular copper foil c forming the source / emitter external connection part 12, to the left of the aforementioned source / emitter connection part 10 in a plan view.

[0055] Furthermore, the first and second layers are provided with triangular copper foil c in a position that overlaps with the triangular copper foil c forming the drain / collector external connection part 11, to the right of the aforementioned drain / collector connection part 8 in a plan view. The copper foil c of the first and second layers, which are positioned to the right of the drain / collector connection part 8 in a plan view, are connected to the drain / collector external connection part 11 by via holes 30, 60 and copper members 31, 61 embedded in the via holes 30, 60. The triangular copper foil c of the first and second layers, positioned in this manner, are connected opposite to the triangular copper foil c of the third and fourth layers, and together with the triangular copper foil c of the third and fourth layers, constitute the drain / collector external connection part 11. The via holes 30 are provided near the wide left-right portion of the copper foil c of the drain / collector external connection part 11 in Figures 5 to 7. The via hole 30 penetrates the copper foil c of the drain / collector wiring integration section 4, and the drain / collector external connection section 11 and the drain / collector wiring integration section 4 are electrically connected at the same point.

[0056] Furthermore, in the first and second layers, triangular copper foils c are provided in a position that overlaps with the triangular copper foil c forming the source / emitter external connection part 12, to the left of the aforementioned source / emitter connection part 10 in a plan view. These copper foils c of the first and second layers, positioned to the left of the source / emitter connection part 10 in a plan view, are connected to the source / emitter external connection part 12 by via holes 32, 62 and copper members 33, 63 fully embedded within the via holes 32, 62. The triangular copper foils c of the first and second layers, positioned in this manner, are connected opposite to the triangular copper foils c of the third and fourth layers, and together with the triangular copper foils c of the third and fourth layers, constitute the source / emitter external connection part 12. The via holes 32 are provided near the wide portion of the copper foil c of the source / emitter external connection part 12 in the left-right direction, as shown in Figure 2 and Figures 5 to 7. The via hole 32 penetrates the copper foil c of the source / emitter wiring integration section 5, and the source / emitter external connection section 12 and the source / emitter wiring integration section 5 are electrically connected at the same point.

[0057] In the substrate 1 configured in this way, the pad 2b of the drain terminal of the FET 2 is connected to the drain / collector external connection part 11, which is formed by the copper foil c of the first to fourth layers, via the drain / collector relay part 17, which is formed by the copper foil c of the first and second layers of the substrate 1, the drain / collector connection part 8, which is formed by the copper foil c of the third and fourth layers and the first copper member 7, and the drain / collector wiring integration part 4, which is formed by the copper foil c of the fifth to seventh layers. In addition, in the substrate 1 configured in this way, the pad 2b of the source terminal of the FET 2 is connected to the source / emitter external connection part 12, which is formed by the copper foil c of the first to fourth layers, via the source / emitter relay part 20, which is formed by the copper foil c of the first and second layers of the substrate 1, the source / emitter connection part 10, which is formed by the copper foil c of the third and fourth layers and the second copper member 9, and the source / emitter wiring integration part 5, which is formed by the copper foil c of the fifth to seventh layers.

[0058] In the pattern circuit section P of the board 1 configured in this way, when the FETs 2 are mounted on the mounting section A, the pads 2b of the gate terminals of each FET 2 are electrically connected to the gate connection section 13, the pads 2b of the drain terminals of each FET 2 are electrically connected to the drain / collector relay section 17, the drain / collector connection section 8, the drain / collector wiring integration section 4 and the drain / collector external connection section 11, and furthermore, the pads 2b of the source terminals of each FET 2 are connected to the source / emitter relay section 20, the source / emitter connection section 10, the source / emitter wiring integration section 5 and the source / emitter external connection section 12.

[0059] The first layer of copper foil c of the drain / collector external connection section 11 is connected to an external power supply (not shown) or a motor winding (not shown), the first layer of copper foil c of the source / emitter external connection section 12 is connected to a ground (not shown) or a motor winding (not shown), and the gate connection section 13 is connected to the signal output terminal of a microcontroller (not shown) mounted on the board 1 via wiring separately provided within the board 1.

[0060] As described above, the circuit board 1 is composed of six pattern circuit sections P on which the FET 2 is mounted in the mounting section A. The two left pattern circuit sections P each form an arm, and the two left pattern circuit sections P form a leg that is connected to the U-phase winding of a motor (not shown). The two central pattern circuit sections P each form an arm, and the two central pattern circuit sections P form a leg that is connected to the V-phase winding of a motor (not shown). The two right pattern circuit sections P each form an arm, and the two right pattern circuit sections P form a leg that is connected to the W-phase winding of a motor (not shown).

[0061] The adjacent pattern circuit sections P that form a pair are both spaced apart from the substrate 1, and have the same configuration except that the drain / collector wiring integration section 4, drain / collector external connection section 11, source / emitter wiring integration section 5, and source / emitter external connection section 12 have inverted shapes with their left and right sides swapped.

[0062] Furthermore, as shown in Figure 1, the central set of pattern circuit sections P is mounted on the substrate 1 in an inverted orientation in Figure 1 compared to the two pattern circuit sections P on the right and the two pattern circuit sections P on the left.

[0063] As shown in Figure 1, in the left-hand pattern circuit section P, the source / emitter external connection 12 is connected to a ground (not shown) and the drain / collector external connection 11 is connected to one end of the U-phase winding of a motor (not shown). In the right-hand pattern circuit section P of the left-hand set, the source / emitter external connection 12 is connected to a point on the U-phase winding of a motor (not shown) and the drain / collector external connection 11 is connected to an external power supply (not shown).

[0064] Furthermore, the source / emitter external connection 12 of the left pattern circuit section P of the central set is connected to one end of the V-phase winding of a motor (not shown), and the drain / collector external connection 11 is connected to an external power supply (not shown). The source / emitter external connection 12 of the right pattern circuit section P of the central set is connected to ground (not shown), and the drain / collector external connection 11 is connected to one end of the V-phase winding of a motor (not shown).

[0065] Furthermore, the source / emitter external connection 12 of the left pattern circuit section P of the right-hand set is connected to a ground (not shown), and the drain / collector external connection 11 is connected to one end of the W-phase winding of a motor (not shown). The source / emitter external connection 12 of the right pattern circuit section P of the right-hand set is connected to one end of the W-phase winding of a motor (not shown), and the drain / collector external connection 11 is connected to an external power supply (not shown).

[0066] Therefore, when a voltage is applied to the gate terminal pad 2b of FET2 from a microcontroller (not shown) mounted on board 1, FET2 turns on and current flows from the external power supply from the drain / collector external connection 11 to the source / emitter external connection 12. When the application of voltage to the gate terminal pad 2b of FET2 from the microcontroller (not shown) stops, FET2 turns off and prevents current from flowing from the drain / collector external connection 11 to the source / emitter external connection 12. In this way, board 1 constitutes an inverter circuit, and the motor (not shown) can be driven by the on / off operation of FET2.

[0067] In the substrate 1 configured as described above, the drain / collector connection portion 8 and the source / emitter connection portion 10 connected to each FET 2 are made of two layers of laminated copper foil c,c. Even when a large current flows through the FET 2, the cross-sectional area of ​​the copper foil c,c can be secured without increasing the thickness of the copper foil c,c which is the conductor through which the current passes in the drain / collector connection portion 8 and the source / emitter connection portion 10, thereby reducing electrical resistance and suppressing heat generation. In this way, even without increasing the thickness of the copper foil c,c, the cross-sectional area of ​​the current path can be secured by laminating multiple layers of copper foil c,c that constitute the drain / collector connection portion 8 and the source / emitter connection portion 10, thus reducing the current density. In this embodiment, the substrate 1 can use thin copper foil c while tolerating large currents, and etching of the copper foil c is possible for mounting microcontrollers and other devices with narrow terminal and pad spacing in addition to the FET 2.

[0068] Although the power semiconductor is described as FET2 above, it may also be an IGBT. If an IGBT is used as the power semiconductor, the collector terminal of the IGBT should be connected to the drain / collector connection 8, the emitter terminal to the source / emitter terminal 10, and the gate terminal to the gate connection 13, and the IGBT should be mounted on the substrate 1.

[0069] As described above, the substrate 1 of this embodiment is a substrate 1 for mounting an FET (power semiconductor) 2, which is laminated with an insulating layer i in between and includes a plurality of copper foils (conductors) c, and includes a drain / collector connection part 8 formed by electrically connecting copper foils (conductors) c, c arranged in different layers and connected to the drain terminal or collector terminal of the FET (power semiconductor) 2, and a source / emitter connection part 10 formed by electrically connecting copper foils (conductors) c, c arranged in different layers and connected to the source terminal or emitter terminal of the FET (power semiconductor) 2.

[0070] With the substrate 1 configured in this way, even without increasing the thickness of the copper foil (conductor) c,c, multiple layers of copper foil (conductor) c,c constituting the drain / collector connection 8 and source / emitter connection 10 can be stacked to secure the cross-sectional area in the current path. This allows for the use of thin copper foil (conductor) c while accommodating large currents, and enables etching of the copper foil (conductor) c for mounting microcontrollers and other devices with narrow terminal and pad spacing in addition to the FET (power semiconductor) 2. Therefore, with the substrate 1 of this embodiment, it becomes possible to mount microcontrollers and other devices with narrow terminal and pad spacing in addition to the FET (power semiconductor) 2, eliminating the need to mount the FET (power semiconductor) 2 and microcontrollers etc. separately on multiple substrates. This reduces the cost of the electronic device including the substrate 1 and contributes to the miniaturization of the electronic device.

[0071] The number of layers of copper foil (conductor) c in the drain / collector connection 8 and source / emitter connection 10 can be changed according to the amount of current that the substrate 1 should allow. If at least two layers are not sufficient to secure the cross-sectional area in the current path, three or more layers of copper foil (conductor) c may be used.

[0072] Furthermore, in the substrate 1 of this embodiment, the copper foils (conductors) c,c that form the drain / collector connection portion 8 are electrically connected to each other via a first copper member 7 embedded in a via hole 6 provided in the insulating layer i, and the copper foils (conductors) c,c that form the source / emitter connection portion 10 are electrically connected to each other via a second copper member 9 embedded in a via hole 6 provided in the insulating layer i.

[0073] With the substrate 1 configured in this way, the copper foil (conductor) c,c forming the drain / collector connection 8 and the copper foil (conductor) c,c forming the source / emitter connection 10 are electrically connected to each other by the first copper member 7 or second copper member 9 which are fully embedded in the via hole 6. As a result, the cross-sectional area of ​​the first copper member 7 and second copper member 9 that connect the copper foil (conductor) c,c can be secured, which suppresses heat generation caused by current concentration due to the first copper member 7 and second copper member 9 becoming bottlenecks, and suppresses a decrease in the allowable current amount of the substrate 1. In this embodiment, the number of first copper members 7 and second copper members 9 that connect the copper foil (conductor) c,c of the drain / collector connection 8 and the source / emitter connection 10 can be arbitrarily designed and changed according to the amount of current that should be allowed by the substrate 1, but by providing multiple members, current concentration in the first copper member 7 and second copper member 9 can be effectively suppressed.

[0074] Furthermore, the substrate 1 of this embodiment is configured to include a drain / collector relay section 17 formed of a plurality of copper foils (conductors) c stacked above the drain / collector connection section 8 and the source / emitter connection section 10, which is connected to the drain terminal or collector terminal of a plurality of FETs (power semiconductors) 2 and the drain / collector relay section 8, and a source / emitter relay section 20 formed of a plurality of copper foils (conductors) c stacked above the drain / collector connection section 8 and the source / emitter connection section 10 and arranged in the same layer as the drain / collector relay section 17, which is connected to the source terminal or emitter terminal of a plurality of FETs (power semiconductors) 2 and the source / emitter connection section 10.

[0075] With the substrate 1 configured in this way, even if the arrangement of the drain terminal or collector terminal and the source terminal or emitter terminal of the FET (power semiconductor) 2 prevents the drain terminal or collector terminal from being directly connected to the drain / collector connection section 8 and the source terminal or emitter terminal from being directly connected to the source / emitter connection section 10 when the FET (power semiconductor) 2 is mounted on the substrate 1, the drain terminal or collector terminal can be connected to the drain / collector connection section 8 and the source terminal or emitter terminal can be connected to the source / emitter connection section 10 via the drain / collector relay section 17 and the source / emitter relay section 20. Furthermore, since both the drain / collector relay section 17 and the source / emitter relay section 20 are constructed by laminating multiple copper foils (conductors) c, the current density can be reduced and heat generation can be suppressed. Therefore, with the substrate 1 of this embodiment configured as described above, regardless of the structure of the FET (power semiconductor) 2, it is possible to mount the FET (power semiconductor) 2 on the substrate 1 and allow high currents while suppressing heat generation. Furthermore, with the substrate 1 of this embodiment configured as described above, the drain / collector relay section 17 and the source / emitter relay section 20 are stacked and arranged above the drain / collector connection section 8 and the source / emitter connection section 10, so that the FET (power semiconductor) 2 can be mounted while avoiding an increase in the size of the substrate 1.

[0076] In this embodiment, the substrate 1 has 30 pads 2b arranged in two rows of 15 FETs (power semiconductors) 2. Therefore, the drain / collector relay section 17 and the source / emitter relay section 20 are constructed by arranging multiple elongated strip-shaped copper foils (conductors) c in parallel. However, depending on the shape and structure of the FETs (power semiconductors) 2, the shape and structure of the copper foils (conductors) c in the drain / collector relay section 17 and the source / emitter relay section 20 can be arbitrarily designed to allow the drain terminal of the FETs (power semiconductors) 2 to be connected to the drain / collector connection section 8 and the source terminal to be connected to the source / emitter connection section 10. Furthermore, the drain / collector relay section 17 and the source / emitter relay section 20 may be omitted as long as the drain terminal or collector terminal of the FET (power semiconductor) 2 can be made conductive to the drain / collector connection section 8 and the source terminal or emitter terminal can be made conductive to the source / emitter connection section 10 without using the drain / collector relay section 17 and the source / emitter relay section 20.

[0077] Furthermore, in the substrate 1 of this embodiment, the drain / collector connection section 8 and the source / emitter connection section 10 each have a plurality of trapezoidal copper foils (conductors) c that are laminated on the same layer, and the copper foils (conductors) c in the drain / collector connection section 8 and the copper foils (conductors) c in the source / emitter connection section 10, which are located on the same layer, are arranged alternately with their slanted sides facing each other, with the narrow side and the wide side that connects to the outside facing in opposite directions.

[0078] With the substrate 1 configured in this way, when mounting multiple FETs (power semiconductors) 2, the trapezoidal copper foil (conductor) c of the FETs (power semiconductors) 2 is mounted with the narrow side and the wide side connected to the outside facing opposite directions and arranged perpendicular to each other. As a result, in the drain / collector connection 8, current flows from the base end side, where the wider side of the trapezoidal copper foil (conductor) c is, to the tip end side, where the narrow side is, and in the source / emitter connection 10, current flows from the tip end side, where the narrow side of the trapezoidal copper foil (conductor) c is, to the base end side, where the wider side is.

[0079] In the drain / collector connection 8, current flows from the wider side to the narrower side of the trapezoidal copper foil (conductor) c, and in the source / emitter connection 10, current flows from the narrower side to the wider side of the trapezoidal copper foil (conductor) c. As a result, the FETs (power semiconductors) 2 are mounted on the copper foil (conductor) c in a direction perpendicular to the narrower side at the tip and the wider side at the base in a plan view. Therefore, the number of FETs (power semiconductors) 2 through which current attempts to pass decreases as you move from the base to the tip of the copper foil (conductor) c in the drain / collector connection 8 and the source / emitter connection 10. This reduces the current density while also reducing the area of ​​the copper foil (conductor) c in a plan view in the drain / collector connection 8 and the source / emitter connection 10. To allow the current flowing through all FETs (power semiconductors) 2 connected to the drain / collector connection 8 and the source / emitter connection 10 to be permissible at any point in the copper foil (conductor) c of the drain / collector connection 8 and the source / emitter connection 10, the copper foil (conductor) c would need to be a rectangle with a constant width matching the width of the part where the current flowing through is maximum. However, in the substrate 1 of this embodiment, the copper foil (conductor) c of the drain / collector connection 8 and the source / emitter connection 10 is trapezoidal in shape, with a narrower width at the tip where there is less current flowing through and therefore no concern about current concentration. Therefore, compared to using a rectangular conductor with a constant width, the amount of copper foil (conductor) c used in the substrate 1 can be reduced while avoiding current concentration, thereby reducing costs and suppressing heat generation in the substrate 1.

[0080] In this embodiment, the shape of the copper foil (conductor) c in the drain / collector connection section 8 and the source / emitter connection section 10 of the substrate 1 can be arbitrarily designed and modified as appropriate according to the shape and structure of the FET (power semiconductor) 2, as well as the number of FETs (power semiconductors) 2 mounted.

[0081] Furthermore, the substrate 1 of this embodiment is located below the drain / collector connection section 8 and the source / emitter connection section 10, and in a plan view, is positioned below the center of the row of drain / collector connection section 8 and source / emitter connection section 10, on the lower bottom side of the copper foil (conductor) c of the drain / collector connection section 8, and extends below the row of copper foil (conductor) c of the drain / collector connection section 8, facing all of the drain / collector connection section 8 and source / emitter connection section 10, and the drain / collector wiring line extends below the row of copper foil (conductor) c of the drain / collector connection section 8. The device includes a coupling section 4 and a source / emitter wiring integration section 5 located below the drain / collector connection section 8 and the source / emitter connection section 10, positioned in a plan view on the lower bottom side of the copper foil (conductor) c of the source / emitter connection section 10, and facing all of the drain / collector connection section 8 and the source / emitter connection section 10, extending on the lower bottom side of the copper foil (conductor) c of the source / emitter connection section 10, beyond the row.

[0082] With the substrate 1 configured in this way, since the drain / collector wiring integration section 4 and source / emitter wiring integration section 5 are provided below the drain / collector connection section 8 and source / emitter connection section 10, when mounting multiple FETs (power semiconductors) 2 with multiple drain / collector connection sections 8 and source / emitter connection sections 10, the drain terminals or collector terminals can be connected in parallel by the drain / collector wiring integration section 4, and the source terminals or emitter terminals can be connected in parallel by the source / emitter wiring integration section 5. This allows for easy connection of the drain terminals or collector terminals and the source terminals or emitter terminals to an external power supply, ground, or electrical equipment such as a motor. Furthermore, the space below the drain / collector connection section 8 and source / emitter connection section 10 can be effectively utilized to efficiently arrange the drain / collector wiring integration section 4 and source / emitter wiring integration section 5 without increasing the size of the substrate 1.

[0083] In this embodiment, since the drain / collector wiring integration section 4 and the source / emitter wiring integration section 5 are constructed by laminating multiple copper foils (conductors) c, the current density can be reduced in both the drain / collector wiring integration section 4 and the source / emitter wiring integration section 5, thereby suppressing heat generation. The number of layers of copper foils (conductors) c in the drain / collector wiring integration section 4 and the source / emitter wiring integration section 5 can be appropriately designed and changed according to the amount of current that should be allowed by the substrate 1. Furthermore, the copper foils (conductors) c in both the drain / collector wiring integration section 4 and the source / emitter wiring integration section 5 are trapezoidal. In the drain / collector wiring integration section 4, current flows from the wider base end to the narrower tip end of the trapezoidal copper foil (conductor) c, while in the source / emitter wiring integration section 5, current flows from the narrower tip end to the wider base end of the trapezoidal copper foil (conductor) c. Thus, in the substrate 1 of this embodiment, the copper foil (conductor) c of the drain / collector wiring integration section 4 and the source / emitter wiring integration section 5 is trapezoidal in shape, with a narrower width at the tip where there are fewer FETs (power semiconductors) 2 through which current is about to pass, thus preventing current concentration. Compared to using rectangular copper foil (conductor) with a constant width, this reduces the amount of copper foil (conductor) c used in the substrate 1 while avoiding current concentration, thereby reducing costs and suppressing heat generation in the substrate 1.

[0084] Furthermore, the substrate 1 of this embodiment is formed of copper foil (conductor) c laminated above the drain / collector wiring integration section 4 and in a portion that does not overlap with the drain / collector connection section 8 in a plan view, and includes a drain / collector external connection section 11 connected to the drain / collector wiring integration section 4, and a source / emitter external connection section 12 formed of copper foil (conductor) c laminated above the source / emitter wiring integration section 5 and in a portion that does not overlap with the source / emitter connection section 10 in a plan view, and connected to the source / emitter wiring integration section 5.

[0085] With the substrate 1 configured in this way, a drain / collector external connection section 11 formed of copper foil (conductor) c stacked above the drain / collector wiring integration section 4 and a source / emitter external connection section 12 formed of copper foil (conductor) c stacked above the source / emitter wiring integration section 5 are provided. As a result, wiring for external power supplies, ground, motors, and other electrical equipment can be connected from the top surface of the substrate 1 on which the FET (power semiconductor) 2 is mounted, improving the usability of the substrate 1. Furthermore, the space above the drain / collector wiring integration section 4 and the source / emitter wiring integration section 5 can be effectively utilized to efficiently arrange the drain / collector external connection section 11 and the source / emitter external connection section 12, thus avoiding an increase in the size of the substrate 1.

[0086] Furthermore, since the drain / collector external connection section 11 and the source / emitter external connection section 12 are constructed by stacking multiple copper foils (conductors) c, the current density can be reduced in both the drain / collector external connection section 11 and the source / emitter external connection section 12, thereby suppressing heat generation. The number of stacked copper foils (conductors) c in the drain / collector external connection section 11 and the source / emitter external connection section 12 can be appropriately designed and changed according to the amount of current that should be allowed by the substrate 1. In addition, the copper foils (conductors) c in both the drain / collector external connection section 11 and the source / emitter external connection section 12 are triangular in shape. In the drain / collector external connection section 11, current flows from the wider base end to the narrower tip end of the triangular copper foil (conductor) c, while in the source / emitter external connection section 12, current flows from the tip end to the wider base end of the triangular copper foil (conductor) c. Thus, in the substrate 1 of this embodiment, the copper foil (conductor) c of the drain / collector external connection part 11 and the source / emitter external connection part 12 is triangular in shape, with a narrower width at the tip where there are fewer FETs (power semiconductors) 2 through which the current is about to pass, thus preventing current concentration. Compared to using rectangular copper foil (conductor) with a constant width, the amount of copper foil (conductor) c used in the substrate 1 can be reduced while avoiding current concentration, thereby reducing the cost of the substrate 1 and suppressing heat generation.

[0087] Furthermore, since the substrate 1 of this embodiment has a heat-dissipating metal layer 3 at the bottom, the heat generated by the flow of current through the FET (power semiconductor) 2 mounted on the substrate 1 and the copper foil c in the substrate 1 can be efficiently dissipated to the outside through the metal layer 3, thereby suppressing burnout of the FET (power semiconductor) 2. Note that if there is a part where it is necessary to connect wiring of external equipment to the copper foil (conductor) c in the substrate 1 from the bottom side rather than the top side of the substrate 1, the metal layer 3 does not need to be provided in that part.

[0088] Although preferred embodiments of the present invention have been described in detail above, modifications, alterations, and changes are permitted as long as they do not deviate from the scope of the claims. [Explanation of Symbols]

[0089] 1...Substrate, 2...FET (Power Semiconductor), 3...Metal layer, 4...Drain / collector wiring integration section, 5...Source / emitter wiring integration section, 8...Drain / collector connection section, 10...Source / emitter connection section, 11...Drain / collector external connection section, 12...Source / emitter external connection section, 17...Drain / collector relay section, 20...Source / emitter relay section, c...Copper foil (conductor), i...Insulating layer

Claims

1. A substrate in which multiple conductors are stacked with insulating layers in between and power semiconductors are mounted on the upper surface, A drain / collector connection portion is formed by electrically connecting conductors arranged in different layers and is connected to the drain terminal or collector terminal of the power semiconductor, It includes a source / emitter connection portion formed by electrically connecting conductors arranged in different layers and connected to the source terminal or emitter terminal of the power semiconductor. A substrate characterized by the following features.

2. A drain / collector relay section is formed of a plurality of conductors stacked above the drain / collector connection section and the source / emitter connection section, and is connected to the drain terminal or collector terminal of a plurality of power semiconductors and the drain / collector connection section. The system comprises a source / emitter relay section, which is formed of a plurality of conductors stacked above the drain / collector connection section and the source / emitter connection section and arranged in the same layer as the drain / collector relay section, and is connected to the source terminal or emitter terminal of a plurality of power semiconductors and the source / emitter connection section. The substrate according to feature 1.

3. The drain / collector connection and the source / emitter connection each have a plurality of trapezoidal conductors stacked on the same layer, The conductors in the drain / collector connection and the conductors in the source / emitter connection, which are located on the same layer, are arranged alternately with their narrower sides facing each other and their wider sides (which connect to the outside) facing opposite directions. The substrate according to feature 1.

4. A drain / collector wiring integration section is located below the drain / collector connection and the source / emitter connection, positioned in a plan view on the lower bottom side of the conductor of the drain / collector connection, and facing all of the drain / collector connection and the source / emitter connection, extending on the wider side of the conductor of the drain / collector connection than the row, Below the drain / collector connection and the source / emitter connection, in a plan view, is a source / emitter wiring integration section which is positioned on the lower bottom side of the conductors of the source / emitter connection, facing all of the drain / collector connection and the source / emitter connection, and extending toward the wider side of the conductors of the source / emitter connection beyond the row. The substrate according to feature 3.

5. A conductor is formed which is stacked above the drain / collector wiring integration section and in a portion that does not overlap with the drain / collector connection section in a plan view, and a drain / collector external connection section is connected to the drain / collector wiring integration section, It comprises a conductor formed by stacking conductors above the source / emitter wiring integration section and in a portion that does not overlap with the source / emitter connection section in a plan view, and a source / emitter external connection section connected to the source / emitter wiring integration section. The substrate according to feature 4.

6. It has a metal layer at the bottom for heat dissipation. A substrate according to any one of claims 1 to 5.

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