substrate

Abstract

To provide a circuit board that can reduce costs and be miniaturized. [Solution] The substrate 1 has a plurality of circuit sections P arranged in a row, each having a mounting section A for mounting a plurality of power semiconductors 2. The circuit section P has a drain connection section 3 formed of a trapezoidal conductor c and connected to the drain terminal of the power semiconductor 2, and a source / emitter connection section 4 formed of a trapezoidal conductor c, facing the drain / collector connection section 3 with a gap between their hypotenuses, and connected to the source terminal 2b of the power semiconductor 2. The mounting section A is provided diagonally to the substrate 1, including the hypotenuse portion of the drain / collector connection section 3 and the hypotenuse portion of the source / emitter connection section 4.

Description

Technical Field

[0001] The present invention relates to a substrate.

Background Art

[0002] In a substrate for mounting a power semiconductor such as a conventional FET (Field-effect transistor) or IGBT (Insulated Gate Bipolar Transistor), for example, it is used for an inverter that drives a motor, etc., and includes a plurality of circuits that form legs and arms in the inverter together with the mounted power semiconductor (see, for example, Patent Document 1). In such a substrate, when it is necessary to supply a large current to the motor, a plurality of power semiconductors are used for one arm, and it is necessary to mount a plurality of power semiconductors on the substrate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] For example, when mounting a plurality of FETs on one circuit on a substrate, as shown in FIG. 4, in order to allow a large current, in order to avoid current concentration in the drain connection copper foil 101 and the source connection copper foil 102 connected to a drain terminal (not shown) provided on the lower surface of the FET 100 and the source terminal 100a and suppress heat generation, it is conceivable to use a thick and wide rectangular copper foil.

[0005] Then, the drain connection copper foil 101 and the source connection copper foil 102 are separated and arranged side by side, and a plurality of FETs 100 are mounted on the substrate 103 along the opposing portion of the drain connection copper foil 101 and the source connection copper foil 102.

[0006] When circuits 104 are provided on the substrate 103 and the FETs 100 are mounted in this manner, if multiple circuits 104 are provided on the substrate 103, each circuit 104 is large, which inevitably makes the substrate 103 larger, worsening its suitability for mounting on electrical equipment, and also increasing the amount of copper foil used, thus increasing costs.

[0007] Therefore, the present invention aims to provide a compact substrate that can reduce costs. [Means for solving the problem]

[0008] To achieve the above objective, the substrate of the present invention is a substrate having a plurality of circuit sections arranged in a row, each having a mounting section for mounting a plurality of power semiconductors, wherein each circuit section has a drain / collector connection section formed of a triangular or trapezoidal conductor and connected to the drain terminal or collector terminal of the power semiconductor, and a source connection section formed of a triangular or trapezoidal conductor and facing the drain / collector connection section with a gap between their hypotenuses, and connected to the source terminal of the power semiconductor, and the mounting section is provided along the hypotenuse, including the hypotenuse portion of the drain / collector connection section and the hypotenuse portion of the source / emitter connection section.

[0009] With a substrate configured in this way, the drain / collector and source connection sections are triangular or trapezoidal and tapered in shape. As a result, the number of power semiconductors through which current attempts to pass decreases from the wider base end to the narrower tip end. This reduces the amount of conductor used in the substrate while avoiding current concentration, compared to using a rectangular conductor of constant width. This reduces the cost of the substrate and suppresses heat generation. Furthermore, by reducing the area of ​​the drain / collector and source / emitter connection sections in a plan view, and by arranging the triangular or trapezoidal drain / collector and source / emitter connection sections with their hypotenuses facing each other, the circuit section can be made smaller and roughly rectangular. Therefore, when the circuit section is placed on the substrate, the circuit section can be densely arranged, and the substrate can be miniaturized.

[0010] Furthermore, the drain / collector connection and source / emitter connection on the substrate may be formed by multiple layers of stacked conductors. With a substrate configured in this way, even without increasing the thickness of the conductor, the cross-sectional area of ​​the current path can be secured by stacking multiple conductors that make up the drain / collector connection and source / emitter connection. This allows for the use of thin conductors while still accommodating large currents, making it possible to etch conductors for mounting not only power semiconductors but also microcontrollers and other devices with narrow terminal and pad spacing. Therefore, with this substrate, it becomes possible to mount not only power semiconductors but also microcontrollers and other devices with narrow terminal and pad spacing. This eliminates the need to mount power semiconductors and microcontrollers separately on multiple substrates, thus reducing the cost of electronic devices including the substrate and contributing to the miniaturization of electronic devices.

[0011] Furthermore, the substrate may have a metal layer for heat dissipation at its bottom layer. With a substrate configured in this way, the heat generated by the flow of current through the power semiconductor mounted on the substrate and the conductors in the substrate can be efficiently dissipated to the outside through the metal layer, thereby suppressing burnout of the power semiconductor. [Effects of the Invention]

[0012] Based on the above, the substrate of the present invention can reduce costs and be miniaturized. [Brief explanation of the drawing]

[0013] [Figure 1] Figure 1 is a plan view of a substrate in one embodiment in which an FET is mounted. [Figure 2] Figure 2 is a partially enlarged plan view of a substrate in one embodiment in which an FET is mounted. [Figure 3] Figure 3(a) is an enlarged cross-sectional view showing a portion of the XX cross-section of the substrate in one embodiment. Figure 3(b) is an enlarged cross-sectional view showing a portion of the YY cross-section of the substrate in one embodiment. [Figure 4] Figure 4 is a partially enlarged plan view of a conventional substrate. [Modes for carrying out the invention]

[0014] The present invention will be described below based on the embodiments shown in the figures. In one embodiment, as shown in Figures 1 to 3, the substrate 1 comprises copper foil c as a conductor laminated in multiple layers, and an insulating layer i formed of an insulator provided between the copper foils c, c, and has six circuit sections P arranged in a row, each having a mounting section A for mounting seven FETs 2 as power semiconductors.

[0015] As shown in Figure 2, the FET2, as a power semiconductor, in this embodiment comprises a rectangular resin case 2a that houses the semiconductor, a gate terminal 2c and a source terminal 2b protruding from one end of the resin case 2a, and a drain terminal (not shown) at the lower end of the resin case 2a.

[0016] On the other hand, the substrate 1 is composed of a circuit section P having a drain / collector connection section 3 connected to the drain terminal of the FET 2, a source / emitter connection section 4 connected to the source terminal 2b of the FET 2, and a gate connection section 5 connected to the gate terminal 2c, and a metal layer 15 for heat dissipation at the bottom layer. In this embodiment, the substrate 1 is rectangular and flat, and comprises six circuit sections P having mounting sections A on which the FET 2 are mounted. Since the circuit sections P on the substrate 1 have the same structure, only the configuration of one circuit section P will be described in detail to avoid duplication of explanation.

[0017] The drain / collector connection section 3 is composed of three stacked trapezoidal copper foils c as conductors, and copper members 8 and 9 that are fully embedded in via holes 6 and 7 provided in the insulating layer i between the copper foils c and c, and that provide electrical conductivity between the stacked copper foils c and c. Multiple via holes 6 are provided near the hypotenuse of the trapezoidal copper foil c, and multiple via holes 7 are provided along the upper base of the trapezoidal copper foil c, where the inner width of the upper base is wider.

[0018] Furthermore, the source / emitter connection section 4, like the drain / collector connection section 3, is composed of multiple stacked trapezoidal copper foils c as conductors, and copper members 12 and 13 that are fully embedded in via holes 10 and 11 provided in the insulating layer i between the copper foils c, c, and that allow the stacked copper foils c, c to conduct electricity with each other. Multiple via holes 10 are provided near the hypotenuse of the trapezoidal copper foils c, and multiple via holes 11 are provided along the lower base, which has a wider inner width than the upper and lower bases of the trapezoidal copper foils c. Of the copper foils c that constitute the source / emitter connection section 4, the first layer of copper foil c, which is placed on the upper surface of the substrate 1, has seven connection sections 4a protruding from its hypotenuse, the same number as the number of FETs 2 mounted on the mounting section A, so that it can be connected to the source terminal 2b of the FET 2. The drain / collector connection 3 or source / emitter connection 4 may be triangular or trapezoidal, but they do not need to be perfectly triangular or trapezoidal; they should be roughly triangular or trapezoidal, and may have notches or protrusions in some parts.

[0019] In this embodiment, the circuit section P on the substrate 1 is formed of three layers of copper foil c. However, if a sufficient cross-sectional area for current to pass through the copper foil c can be secured, it may be formed of one layer of copper foil c, and the number of layers of copper foil c can be arbitrarily designed to accommodate the desired current. Although the conductor is copper foil c, it may be a metal other than copper foil.

[0020] And as shown in FIGS. 1 and 2, the drain / collector connection portion 3 and the source / emitter connection portion 4 are arranged on the substrate 1 with their hypotenuses facing each other at an interval. Further, the gate connection portion 5 is formed by a copper foil c arranged along the hypotenuses of the drain / collector connection portion 3 and the source / emitter connection portion 4 in a plan view in a layer above the layer of the copper foil c of the drain / collector connection portion 3 and the source / emitter connection portion 4. The gate connection portion 5 includes a main body portion 5a formed by an elongated copper foil c and seven terminal connection portions 5b protruding laterally from the main body portion 5a. Since the current flowing through the gate connection portion 5 is small, the main body portion 5a in the gate connection portion 5 is formed by an elongated copper foil c.

[0021] The circuit portion P includes a trapezoidal drain / collector connection portion 3 and a source / emitter connection portion 4 with their hypotenuses facing each other, and a gate connection portion 5 provided in a layer different from the drain / collector connection portion 3 and the source / emitter connection portion 4, and is formed in a substantially rectangular shape on the substrate 1. In the substrate 1 of the present embodiment, since a plurality of compact circuit portions P formed in a substantially rectangular shape along the longitudinal direction of the substrate 1 are arranged in a row, the circuit portions P can be densely arranged in the substrate 1, and the substrate 1 can be miniaturized.

[0022] As shown in FIGS. 1 and 2, the mounting portion A is a region straddling the drain / collector connection portion 3 and the source / emitter connection portion 4, including portions overlapping with the hypotenuse portions of the drain / collector connection portion 3, the hypotenuse portions of the source / emitter connection portion 4, and the gate connection portion 5 in the circuit portion P in a plan view, and is provided along the hypotenuses of the drain / collector connection portion 3 and the source / emitter connection portion 4.

[0023] Furthermore, as shown in Figure 3, the substrate 1 is provided with a heat-dissipating metal layer 15 made of copper foil c on the underside of the insulating layer i, which is located below the copper foil c of the drain / collector connection 3 and the source / emitter connection 4. Thus, the metal layer 15 is located below the insulating layer i, which is at the very bottom, and is provided to cover the entire underside of the substrate 1, and is not connected to any copper foil c which are conductors of different layers. The metal layer 15 is provided on the entire underside of the substrate 1 in order to efficiently dissipate heat, but it may also be provided on only a part of the underside of the substrate 1.

[0024] As shown in Figure 3, the substrate 1 has a metal layer 15 to which thermal conductive grease (not shown) is applied, and then the metal layer 15 is in contact with the housing 50 or heat sink that houses the substrate 1. When current flows through the circuit section P, the heat generated is conducted from the metal layer 15 to the housing 50 or heat sink, allowing for efficient heat dissipation from the substrate 1.

[0025] When the FET2 is mounted on the mounting section A of the circuit section P, the source terminal 2b of the FET2 is connected by soldering or the like to the copper foil c of the connection section 4a of the source / emitter connection section 4 located within the mounting section A on the upper surface of the substrate 1, the gate terminal 2c is connected by soldering or the like to the copper foil c of the gate connection section 5 located within the mounting section A, and the drain terminal at the lower end of the resin case 2a is connected to the copper foil c of the drain / collector connection section 3. As shown in Figure 1, the seven FET2s are mounted in a row along the longitudinal direction of the mounting section A, which is provided along the slanted sides of the mounting section A, including the slanted side of the drain / collector connection section 3 and the slanted side of the source / emitter connection section 4 opposite the slanted side of the drain / collector connection section 3.

[0026] The first layer of copper foil c of the drain / collector connection section 3 is exposed on the upper surface of the substrate 1, as shown in Figure 3, and is connected to an external power supply (not shown) or a motor winding (not shown). The first layer of copper foil c of the source / emitter connection section 4 is also exposed on the upper surface of the substrate 1, as shown in Figure 3, and is connected to a ground (not shown) or a motor winding (not shown). The gate connection section 5 is connected to the signal output terminal of a microcontroller (not shown) mounted on the substrate 1 via wiring provided separately within the substrate 1.

[0027] As described above, circuit board 1 is composed of six circuit sections P on which the FET 2 is mounted in the mounting section A. The two circuit sections P on the left each form an arm, and these two circuit sections P on the left combine to form one leg connected to the U-phase winding of a motor (not shown). The two circuit sections P in the center each form an arm, and these two circuit sections P in the center combine to form one leg connected to the V-phase winding of a motor (not shown). The two circuit sections P on the right each form an arm, and these two circuit sections P on the right combine to form one leg connected to the W-phase winding of a motor (not shown).

[0028] The adjacent circuit sections P forming a pair are both spaced apart from the substrate 1, and have the same configuration except that the drain / collector connection section 3 and the source / emitter connection section 4 are inverted so that their left and right sides are swapped.

[0029] Furthermore, as shown in Figure 1, the central set of circuit sections P is mounted on the substrate 1 in an inverted orientation compared to the two circuit sections P on the right and the two circuit sections P on the left in Figure 1.

[0030] As shown in Figure 1, in the left-hand circuit section P, the source / emitter connection 4 is connected to a ground (not shown) and the drain / collector connection 3 is connected to one end of the U-phase winding of a motor (not shown). In the right-hand circuit section P of the left-hand set, the source / emitter connection 4 is connected to a point on the U-phase winding of a motor (not shown) and the drain / collector connection 3 is connected to an external power supply (not shown).

[0031] Furthermore, the source / emitter connection 4 of the left circuit section P of the central set is connected to one end of the V-phase winding of a motor (not shown), and the drain / collector connection 3 is connected to an external power supply (not shown). The source / emitter connection 4 of the right circuit section P of the central set is connected to ground (not shown), and the drain / collector connection 3 is connected to one end of the V-phase winding of a motor (not shown).

[0032] Furthermore, the source / emitter connection 4 of the left circuit section P of the right-hand set is connected to a ground (not shown), and the drain / collector connection 3 is connected to one end of the W-phase winding of a motor (not shown). The source / emitter connection 4 of the right circuit section P of the right-hand set is connected to one end of the W-phase winding of a motor (not shown), and the drain / collector connection 3 is connected to an external power supply (not shown).

[0033] Therefore, when a voltage is applied to the gate terminal 2c of FET2 via the gate connection 5 from a microcontroller (not shown) mounted on board 1, FET2 turns on and current flows from the external power supply from the drain / collector connection 3 to the source / emitter connection 4. When the application of voltage to the gate terminal 2c of FET2 from the microcontroller (not shown) stops, FET2 turns off and prevents current from flowing from the drain / collector connection 3 to the source / emitter connection 4. In this way, board 1 constitutes an inverter circuit, and the motor (not shown) can be driven by the on / off operation of FET2.

[0034] In the substrate 1 of this embodiment, when mounting the FET 2 on the mounting section A, the FET 2 is mounted in a row along the hypotenuse of the trapezoidal drain / collector connection section 3 and source / emitter connection section 4 in a plan view. As shown in Figure 2, in the drain / collector connection section 3, current flows from the wider upper bottom side to the narrower lower bottom side of the trapezoidal copper foil c, and in the source / emitter connection section 4, current flows from the narrower upper bottom side to the wider lower bottom side of the trapezoidal copper foil c.

[0035] In the drain / collector connection section 3, current flows from the wider lower end of the trapezoidal copper foil c to the narrower upper end, and in the source / emitter connection section 4, current flows from the narrower upper end of the trapezoidal copper foil c to the wider lower end. Since the FETs 2 are mounted along the hypotenuse of the trapezoidal drain / collector connection section 3 and source / emitter connection section 4, the number of FETs 2 through which current attempts to pass decreases as you move from the lower end to the upper end of the copper foil c in the drain / collector connection section 3 and source / emitter connection section 4. This allows for a reduction in current density without having to make the drain / collector connection section 3 and source / emitter connection section 4 rectangles that match the width of the area where the current density is most concentrated. Therefore, in the substrate 1 of this embodiment, the area of ​​the drain / collector connection section 3 and source / emitter connection section 4 in plan view can be reduced while reducing the current density in the drain / collector connection section 3 and source / emitter connection section 4. In other words, in the substrate 1 of this embodiment, the drain / collector connection section 3 and the source / emitter connection section 4 are trapezoidal. As the current moves from the wider bottom to the narrower bottom, the number of FETs 2 through which current attempts to pass decreases. Compared to using rectangular copper foil with a constant width, this reduces the amount of copper foil c used in the substrate 1 while avoiding current concentration, thereby reducing the cost and suppressing heat generation in the substrate 1. Furthermore, by reducing the area of ​​the drain / collector connection section 3 and the source / emitter connection section 4 in a plan view, and by arranging the trapezoidal drain / collector connection section 3 and the source / emitter connection section 4 with their hypotenuses facing each other, the circuit section P can be made smaller and more rectangular. Therefore, when the circuit section P is placed on the substrate 1, the circuit section P can be densely arranged, and the substrate 1 can be made smaller.

[0036] Furthermore, in the substrate 1 configured as described above, the drain / collector connection portion 3 and source / emitter connection portion 4 connected to each FET 2 are made of copper foil c stacked in multiple layers. Even when a large current flows through the FET 2, the cross-sectional area of ​​the copper foil c can be secured without increasing the thickness of the copper foil c, which is the conductor through which the current passes in the drain / collector connection portion 3 and source / emitter connection portion 4, thereby reducing electrical resistance and suppressing heat generation. In this way, even without increasing the thickness of the copper foil c, the cross-sectional area in the current path can be secured by stacking multiple copper foil c that make up the drain / collector connection portion 3 and source / emitter connection portion 4, thus reducing the current density. Therefore, in the substrate 1 of this embodiment, it is possible to use thin copper foil c while tolerating a large current, and etching of the copper foil c is possible for mounting microcontrollers and other devices with narrow spacing between terminals and pads, in addition to the FET 2.

[0037] As described above, the substrate 1 of this embodiment is a substrate 1 having a plurality of circuit sections P arranged in a line, each having a mounting section A for mounting a plurality of FETs (power semiconductors) 2. The circuit section P has a drain / collector connection section 3 formed of a trapezoidal copper foil (conductor) c and connected to the drain terminal of the FET (power semiconductor) 2, and a source / emitter connection section 4 formed of a trapezoidal copper foil (conductor) c and facing the drain / collector connection section 3 with a gap between their hypotenuses, and connected to the source terminal 2b of the FET (power semiconductor) 2. The mounting section A is provided along the hypotenuse, including the hypotenuse portion of the drain / collector connection section 3 and the hypotenuse portion of the source / emitter connection section 4.

[0038] With the substrate 1 configured in this way, the drain / collector connection section 3 and the source / emitter connection section 4 are trapezoidal and tapered. As a result, the number of FETs (power semiconductors) 2 through which current attempts to pass decreases from the wider base end to the narrower tip end. This allows for a reduction in the amount of copper foil (conductor) c used in the substrate 1 while avoiding current concentration, compared to using rectangular copper foil (conductor) of a constant width. This reduces the cost and suppresses heat generation in the substrate 1. Furthermore, by reducing the area of ​​the drain / collector connection section 3 and the source / emitter connection section 4 in plan view, and by arranging the trapezoidal drain / collector connection section 3 and the source / emitter connection section 4 with their hypotenuses facing each other, the circuit section P can be made smaller and approximately rectangular. Therefore, when the circuit section P is arranged on the substrate 1, the circuit section P can be densely arranged, and the substrate 1 can be miniaturized. Thus, the substrate 1 of this embodiment can reduce costs and be miniaturized.

[0039] Furthermore, the shape of the copper foil (conductor) c in the drain / collector connection section 3 and the source / emitter connection section 4 may be triangular. By arranging the drain / collector connection section 3 and the source / emitter connection section 4 with their hypotenuses facing each other, the amount of copper foil (conductor) c can be reduced, similar to the case where the copper foil (conductor) c in the drain / collector connection section 3 and the source / emitter connection section 4 is trapezoidal. This reduces the cost of the substrate 1 and suppresses heat generation. In addition, the circuit section P can be made smaller and approximately rectangular, thus allowing for a smaller substrate 1. Alternatively, one of the copper foil (conductor) c in the drain / collector connection section 3 and the other in the source / emitter connection section 4 may be trapezoidal and the other triangular.

[0040] Furthermore, the drain / collector connection portion 3 and the source / emitter connection portion 4 in the substrate 1 of this embodiment are formed by multiple layers of laminated copper foil (conductor) c. With the substrate 1 configured in this way, even without increasing the thickness of the copper foil (conductor) c, multiple layers of copper foil (conductor) c, c constituting the drain / collector connection portion 3 and the source / emitter connection portion 4 can be laminated to secure the cross-sectional area in the current path. This allows for the use of thin copper foil (conductor) c while accommodating large currents, and enables etching of the copper foil (conductor) c for mounting microcontrollers and other devices with narrow terminal and pad spacing in addition to the FET (power semiconductor) 2. Therefore, with the substrate 1 of this embodiment, it is possible to mount microcontrollers and other devices with narrow terminal and pad spacing in addition to the FET (power semiconductor) 2, eliminating the need to mount the FET (power semiconductor) 2 and microcontrollers separately on multiple substrates. This reduces the cost of the electronic device including the substrate 1 and contributes to the miniaturization of the electronic device.

[0041] Furthermore, since the substrate 1 of this embodiment is equipped with a heat-dissipating metal layer 15 at the bottom layer, the heat generated by the flow of current through the FET (power semiconductor) 2 mounted on the substrate 1 and the copper foil (conductor) c in the substrate 1 can be efficiently dissipated to the outside from the metal layer 15, thereby suppressing burnout of the FET (power semiconductor) 2.

[0042] Although the power semiconductor is described as FET2 above, it may also be an IGBT. If an IGBT is used as the power semiconductor, the collector terminal of the IGBT should be connected to the drain / collector connection 3, the emitter terminal to the source / emitter terminal 4, and the gate terminal to the gate connection 5, and the IGBT should be mounted on the substrate 1.

[0043] Although preferred embodiments of the present invention have been described in detail above, modifications, alterations, and changes are permitted as long as they do not deviate from the scope of the claims. [Explanation of Symbols]

[0044] 1...Substrate, 2...FET (Power Semiconductor), 3...Drain connection, 4...Source / emitter connection, 15...Metal layer, c...Copper foil (conductor), i...Insulating layer, A...Mounting section, P...Circuit section

Claims

1. A substrate having multiple circuit sections arranged in a row, each having a mounting section for mounting multiple power semiconductors, The aforementioned circuit section is A drain / collector connection portion formed of a triangular or trapezoidal conductor and connected to the drain terminal or collector terminal of the power semiconductor, It has a source / emitter connection portion formed of a triangular or trapezoidal conductor, with the drain / collector connection portion and the source / emitter connection portion facing each other with a gap between their hypotenuses, and connected to the source terminal or emitter terminal of the power semiconductor, The mounting portion is provided along the slanted edge, including the slanted edge portion of the drain / collector connection portion and the slanted edge portion of the source / emitter connection portion. A substrate characterized by the following features.

2. The drain / collector connection and the source / emitter connection are formed by a conductor stacked in multiple layers. The substrate according to feature 1.

3. It has a metal layer at the bottom for heat dissipation. The substrate according to feature 1 or 2.

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