Semiconductor device and method for manufacturing the same

Abstract

To improve the performance of semiconductor devices. [Solution] The semiconductor device includes a wiring board SUB1, a semiconductor chip mounted on a first upper surface of the wiring board SUB1, an electronic component mounted on the first upper surface, and a stiffener ring fixed to the first upper surface. The stiffener ring includes a first portion that is arranged to continuously surround the semiconductor chip in a plan view and is bonded to the first upper surface of the wiring board SUB1, and a second portion that is connected to the first portion in a plan view and is positioned away from the first upper surface of the wiring board SUB1. The electronic component partially overlaps with the second portion of the stiffener ring.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] In a semiconductor device in which a semiconductor chip is mounted on a wiring board, there is a technique of mounting a plate (stiffening) for reinforcing the wiring board on the wiring board (see, for example, Patent Document 1 (Japanese Patent Application Laid-Open No. 2003-51568) and Patent Document 2 (Japanese Patent Application Laid-Open No. 2014-130961)).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] The stiffening mounted on the wiring board is required to have a function of suppressing warping deformation of the wiring board. The stiffening is fixed on the wiring board via, for example, an adhesive layer. In order to suppress warping deformation of the wiring board, it is necessary to prevent deformation of the stiffening itself.

[0005] On the other hand, with the improvement in performance of semiconductor devices, electronic components such as chip capacitors may be mounted on the wiring board. When an electronic component is mounted on the wiring board, the stiffening cannot be adhered to the mounting area of the electronic component. In other words, when an electronic component is mounted on the wiring board, the adhesion area between the wiring board and the stiffening is limited. Therefore, a technique capable of preventing deformation of the stiffening itself with a limited adhesion area is required.

[0006] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment includes a wiring board, a semiconductor chip mounted on a first upper surface of the wiring board, an electronic component mounted on the first upper surface, and a stiffener ring fixed to the first upper surface. The stiffener ring is arranged to continuously surround the semiconductor chip in a plan view and includes a first portion that is bonded to the first upper surface of the wiring board, and a second portion that is connected to the first portion in a plan view and is positioned away from the first upper surface of the wiring board. The electronic component partially overlaps with the second portion of the stiffener ring.

[0008] A method for manufacturing a semiconductor device according to another embodiment includes the steps of: (a) preparing a wiring board having a first upper surface; (b) mounting a semiconductor chip on the first upper surface; (c) mounting an electronic component on the first upper surface; and (d) mounting a stiffener ring on the first upper surface after steps (b) and (c). The stiffener ring mounted in step (d) has a frame shape in plan view and includes a first portion that is bonded to the first upper surface in step (d), and a second portion that is connected to the first portion and positioned away from the first upper surface in step (d). In step (d), the electronic component partially overlaps with the second portion of the stiffener ring. [Effects of the Invention]

[0009] According to the above embodiment, the performance of the semiconductor device can be improved. [Brief explanation of the drawing]

[0010] [Figure 1] This is a top view of a semiconductor device according to one embodiment. [Figure 2]Figure 1 is a bottom view of the semiconductor device shown. [Figure 3] This is a cross-sectional view along line AA in Figure 1. [Figure 4] Figure 3 is an enlarged cross-sectional view showing a portion of the electronic components and stiffener ring. [Figure 5] Figure 4 is an enlarged cross-sectional view showing an example of a semiconductor chip with a heat dissipation component attached. [Figure 6] This is an enlarged cross-sectional view showing the periphery of a portion of the stiffening ring, which is a modified version of Figure 4. [Figure 7] Figure 6 is a schematic enlarged cross-sectional view showing the stiffening ring being formed by a partial punching process. [Figure 8] This is an enlarged cross-sectional view showing the periphery of a portion of the stiffening ring, which is another variation of Figure 4. [Figure 9] Figure 8 is a schematic enlarged cross-sectional view showing the process of forming the stiffening ring by drawing. [Figure 10] This is an explanatory diagram showing an example of the assembly process flow for a semiconductor device, which is one embodiment of the device. [Figure 11] Figure 10 is a plan view showing a modified example of a wiring board prepared in the wiring board preparation process. [Figure 12] This is an enlarged plan view showing the state after adjusting the positional relationship between the alignment mark and the stiffening ring in the alignment process shown in Figure 10. [Modes for carrying out the invention]

[0011] (Explanation of format, basic terminology, and usage in this application) In the following embodiments, when necessary for convenience, they are described by being divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not unrelated to each other, and one is related to a part or all of the other as a modification example, details, supplementary explanation, etc. Further, in the following embodiments, when referring to the number of elements, etc. (including the number, numerical value, quantity, range, etc.), unless otherwise specified or limited to a specific number in principle, it is not limited to that specific number, and it may be more than or less than the specific number. Furthermore, in the following embodiments, it goes without saying that the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the constituent elements, unless otherwise specified or considered not to be so in principle, it includes those substantially approximated or similar to the shape, etc. This also applies to the above numerical values and ranges.

[0012] Similarly, in the description of embodiments, etc., even when referring to materials, compositions, etc. as "X consisting of A", etc., unless otherwise specified or clearly not so from the context, it does not exclude those including elements other than A. For example, in terms of components, it means "X containing A as a main component", etc. For example, even when referring to a "silicon member", etc., it is not limited to pure silicon, and it includes members containing SiGe (silicon-germanium) alloys, other multi-element alloys having silicon as a main component, and other additives, etc. Needless to say, when referring to gold plating, a Cu layer, nickel plating, etc., unless otherwise specified, it includes not only pure ones but also members having gold, Cu, nickel, etc. as main components.

[0013] Also, in each figure of the embodiments, the same or similar parts are denoted by the same or similar symbols or reference numerals, and the description is not repeated in principle.

[0014] In the accompanying drawings, hatching and the like may be omitted even for cross-sections. In this regard, even a planar closed hole may have its background contour line omitted when it is clear from the description or the like. Further, hatching or dot patterns may be added even if it is not a cross-section, in order to clarify that it is not a void or to clarify the boundary of a region.

[0015] <Semiconductor device> FIG. 1 is a top view of a semiconductor device according to an embodiment. FIG. 2 is a bottom view of the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view taken along line A-A of FIG. 1. In FIG. 1, the outline of the semiconductor chip CHP1 covered by the stiffening ring 4 is shown by a dotted line. FIG. 4 is an enlarged cross-sectional view showing a part of the electronic component and the stiffening ring shown in FIG. 3. FIG. 5 is an enlarged cross-sectional view showing an example of a state in which a heat dissipation member is attached on the semiconductor chip shown in FIG. 4.

[0016] In FIGS. 1 to 3, any one of the X direction (see FIGS. 1 to 3), Y direction (see FIGS. 1 and 2), and Z direction (see FIG. 3) is described. The Y direction is a side intersecting the X direction, and in the following description, the X direction and the Y direction are orthogonal to each other. The Z direction is a direction orthogonal to each of the X direction and the Y direction. In other words, the Z direction is a normal direction to the X-Y plane including the X direction and the Y direction. In the following description, "thickness" generally means the length in the Z direction. Also, in the following description, "plan view" generally means a plan view as viewed from the X-Y plane.

[0017] The semiconductor device PKG1 of the present embodiment has a wiring board SUB1 and a semiconductor chip CHP1 (see FIG. 3) mounted on the wiring board SUB1. Further, the semiconductor device PKG1 has a stiffening ring 4 arranged so as to continuously surround the periphery of the semiconductor chip CHP1 in a plan view. Further, the semiconductor device PKG1 has an electronic component CD1 mounted on the wiring board SUB1.

[0018] The wiring board SUB1 is mainly composed of a so-called organic material, which is glass fiber impregnated with an epoxy resin. The semiconductor chip CHP1 is mainly composed of, for example, silicon. In other words, in this embodiment, the coefficient of linear expansion (coefficient of thermal expansion) of the wiring board SUB1 and the coefficient of linear expansion (coefficient of thermal expansion) of the semiconductor chip CHP1 are different from each other. In recent years, with the increasing sophistication of semiconductor devices, the planar size of the wiring board SUB1 used has become larger than before. Also, as shown in Figure 1, when the semiconductor chip CHP1 is positioned so as to overlap with the center of the wiring board SUB1 (the intersection of diagonals 2d1 and 2d2 shown in Figure 1), the warping deformation of the wiring board SUB1 due to the difference in the coefficients of linear expansion becomes larger at the periphery of the wiring board SUB1 (especially at the corners).

[0019] Therefore, in this embodiment, a stiffening ring 4 is mounted on the wiring board SUB1 in order to suppress warping deformation of the wiring board SUB1.

[0020] The following describes the details of the semiconductor device PKG1.

[0021] As shown in Figure 3, the wiring board SUB1 of the semiconductor device PKG1 has an upper surface 2t which is the chip mounting surface and a lower surface 2b opposite to the upper surface 2t. The lower surface 2b functions as the mounting surface of the semiconductor device PKG1.

[0022] As shown in Figure 1, the top surface 2t of the wiring board SUB1 includes edge 2s1, edge 2s2 opposite to edge 2s1, edge 2s3 intersecting edges 2s1 and 2s2, and edge 2s4 opposite to edge 2s3. The top surface 2t also includes corner 2c1, which is the intersection of edge 2s1 and edge 2s3; corner 2c2, which is the intersection of edge 2s1 and edge 2s4; corner 2c3, which is the intersection of edge 2s2 and edge 2s3; and corner 2c4, which is the intersection of edge 2s2 and edge 2s4.

[0023] Furthermore, although they are virtual lines and not visible, the top surface 2t is a quadrilateral, so two diagonals can be drawn. Specifically, a diagonal 2d1 can be drawn on the top surface 2t, connecting the intersection of side 2s1 and side 2s3 (angle 2c1) and the intersection of side 2s2 and side 2s4 (angle 2c4). Also, a diagonal 2d2 can be drawn on the top surface 2t, connecting the intersection of side 2s1 and side 2s4 (angle 2c2) and the intersection of side 2s2 and side 2s3 (angle 2c3). In the example shown in Figure 1, sides 2s1 and 2s2 are sides extending along the X direction, and sides 2s3 and 2s4 are sides extending along the Y direction.

[0024] The wiring board SUB1 of the semiconductor device PKG1 has internal interface terminals (pads 2PD) exposed from the insulating film SR1 on the upper surface 2t, and external interface terminals (lands 2LD) exposed from the insulating film SR2 on the lower surface 2b, which is the mounting surface.

[0025] Furthermore, the wiring board SUB1 has multiple wiring layers that electrically connect the internal interface terminals and the external interface terminals. In the example shown in Figure 3, the wiring board SUB1 is an 8-layer wiring board with wiring layers WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8. However, the number of wiring layers in the wiring board SUB1 is not limited to 8 layers, and may be 7 layers or less, or 9 layers or more.

[0026] Each wiring layer is located between the upper surface 2t and the lower surface 2b. Each wiring layer has a conductor pattern, such as wiring, which is a path for supplying electrical signals and power. Each wiring layer is electrically connected to one another via via wiring 2v, which is an interlayer conductive path that penetrates the insulating layer 2e, or through-hole wiring 2THW. An insulating layer 2e is placed between each wiring layer. The multiple insulating layers 2e placed between each wiring layer include a core insulating layer (insulating layer, core material, core insulating layer) 2CR placed between the upper surface 2t and the lower surface 2b. The core insulating layer 2CR is a core member for ensuring the rigidity of the wiring board SUB1, and is made of, for example, a prepreg made of glass fiber impregnated with resin.

[0027] Of the multiple wiring layers, the wiring layer WL1 located on the uppermost surface 2t side is covered with an insulating film SR1. The insulating film SR1 has an opening, and each of the multiple pads 2PD provided on the wiring layer WL1 is exposed from the insulating film SR1 at the opening.

[0028] Of the multiple wiring layers, the wiring layer WL8, which is located closest to the lower surface 2b of the wiring board SUB1, is provided with multiple lands 2LD. The wiring layer WL8 is covered with an insulating film SR2. Both insulating films SR1 and SR2 are solder resist films made of organic materials capable of suppressing solder wetting and spreading. The multiple pads 2PD provided on the wiring layer WL1 and the multiple lands 2LD provided on the wiring layer WL8 are electrically connected via conductor patterns (wiring 2d and large-area conductor patterns 2CP), via wiring 2v, and through-hole wiring 2THW formed on each wiring layer of the wiring board SUB1.

[0029] Each of the wirings 2d, pads 2PD, via wirings 2v, via lands (not shown), through-hole lands (not shown), through-hole wirings 2THW, lands 2LD, and conductor patterns 2CP is made of, for example, copper or a metal material primarily composed of copper.

[0030] The wiring board SUB1 is formed, for example, by laminating multiple wiring layers on the upper surface 2Ct and lower surface 2Cb of the core insulating layer (insulating layer, core material, core insulating layer) 2CR using a build-up method. Furthermore, the wiring layer WL4 on the upper surface 2Ct side of the core insulating layer 2CR and the wiring layer WL5 on the lower surface 2Cb side are electrically connected via multiple through-hole wiring 2THW embedded in multiple through-holes that penetrate from one side of the upper surface 2Ct to the other.

[0031] Furthermore, in the example shown in Figure 3, multiple solder balls (solder material, external terminals, electrodes, external electrodes) SB are formed on the lower surface 2b of the wiring board SUB1. More specifically, a solder ball SB is connected to each of the multiple lands 2LD on the wiring board SUB1. The solder balls SB are conductive components that electrically connect multiple terminals (not shown) on the motherboard side to multiple lands 2LD when mounting the semiconductor device PKG1 to a motherboard (not shown). The solder balls SB are made of solder material consisting of, for example, Sn-Pb solder material containing lead (Pb), or so-called lead-free solder that substantially does not contain Pb. Examples of lead-free solder include, for example, tin (Sn) only, tin-bismuth (Sn-Bi), tin-copper-silver (Sn-Cu-Ag), tin-copper (Sn-Cu), etc. Here, lead-free solder refers to solder with a lead (Pb) content of 0.1 wt% or less, and this content is defined as a standard under the RoHS (Restriction of Hazardous Substances) directive.

[0032] Furthermore, as shown in Figure 2, multiple solder balls SB are arranged in a matrix (array). Although not shown in Figure 2, multiple lands 2LD (see Figure 3) to which multiple solder balls SB are joined are also arranged in a matrix. A semiconductor device in which multiple external terminals (solder balls SB, lands 2LD) are arranged in a matrix on the mounting surface side of the wiring board SUB1 in this manner is called an area array type semiconductor device. Area array type semiconductor devices are preferable because they can effectively utilize the mounting surface (bottom surface 2b) side of the wiring board SUB1 as space for arranging external terminals, thus suppressing an increase in the mounting area of ​​the semiconductor device even when the number of external terminals increases. In other words, semiconductor devices with an increasing number of external terminals due to increased functionality and integration can be mounted in a space-saving manner.

[0033] The semiconductor device PKG1 has a semiconductor chip CHP1 mounted on a wiring board SUB1. As shown in Figure 3, each semiconductor chip CHP1 has a surface (main surface, top surface) 3t on which a plurality of protruding electrodes 3BP are arranged, and a back surface (main surface, bottom surface) 3b opposite to the surface 3t.

[0034] As shown in Figure 1, the semiconductor chip CHP1 has a rectangular shape with a smaller planar area than the wiring board SUB1 in a plan view. In the example shown in Figure 1, the semiconductor chip CHP1 is mounted in the center of the top surface 2t of the wiring board SUB1. Furthermore, each of the four sides of the semiconductor chip CHP1 extends along each of the four sides (sides 2s1, 2s2, 2s3, and 2s4) of the top surface 2t of the wiring board SUB1.

[0035] As shown in Figure 3, multiple electrodes (pads, electrode pads, bonding pads) 3PD are formed on the surface 3t side of the semiconductor chip CHP1. Surface 3t is the outermost surface of the semiconductor chip CHP1. Surface 3t includes the upper surface of a passivation film (not shown) and the upper surface of the electrodes 3PD exposed from the passivation film. Since multiple protruding electrodes 3BP are formed on the electrodes 3PD, it can be said that the multiple protruding electrodes 3BP are formed on surface 3t.

[0036] In the example shown in Figure 3, the semiconductor chip CHP1 is mounted on the wiring board SUB1 with its surface 3t facing the upper surface 2t of the wiring board SUB1. This mounting method is called face-down mounting or flip-chip connection.

[0037] Although not shown in the diagram, multiple semiconductor elements (circuit elements) are formed on the main surface of the semiconductor chip CHP1 (more specifically, the semiconductor element formation region provided on the element formation surface of the semiconductor substrate that is the base material of the semiconductor chip CHP1). Multiple electrodes 3PD are electrically connected to these multiple semiconductor elements via wiring (not shown) formed on a wiring layer located inside the semiconductor chip CHP1 (more specifically, between the surface 3t and the semiconductor element formation region, which is not shown).

[0038] The semiconductor chip CHP1 (more specifically, the semiconductor substrate of the semiconductor chip CHP1) is made of, for example, silicon (Si). Furthermore, an insulating film (a passivation film, not shown) is formed on the surface 3t, covering the semiconductor substrate and wiring of the semiconductor chip CHP1. A portion of each of the multiple electrodes 3PD is exposed from this passivation film through openings formed in the passivation film. Each of the multiple electrodes 3PD is made of a metal; in this embodiment, for example, aluminum (Al).

[0039] Furthermore, as shown in Figure 3, a bump electrode 3BP is connected to each of the multiple electrodes 3PD, and the multiple electrodes 3PD of the semiconductor chip CHP1 and the multiple pads 2PD of the wiring board SUB1 are electrically connected via the multiple bump electrodes 3BP. The bump electrode (bump electrode) 3BP is a metal member (conductive member) formed to protrude from the surface 3t of the semiconductor chip CHP1. In this embodiment, the bump electrode 3BP has a structure in which a columnar electrode (so-called copper pillar electrode) made of, for example, copper is formed on the electrode 3PD, and solder material is laminated at the tip of the columnar electrode. As the solder material laminated at the tip of the columnar electrode, lead-containing solder material or lead-free solder can be used, similar to the solder ball SB described above.

[0040] When mounting the semiconductor chip CHP1 onto the wiring board SUB1, a bonding material with good solder adhesion properties (e.g., a base metal film or solder paste) is pre-formed on multiple pads 2PD. By applying a heat treatment (reflow treatment) while the solder material at the tip of the columnar electrode is in contact with the bonding material on the pad 2PD, the solder integrates and a protruding electrode 3BP is formed. Furthermore, as a modification of this embodiment, a columnar electrode made of nickel (Ni), or a so-called solder bump in which micro-solder balls are formed on the electrode 3PD via a base metal film, may be used as the protruding electrode 3BP.

[0041] Furthermore, as shown in Figure 3, an underfill resin (insulating resin) UF is placed between the semiconductor chip CHP1 and the wiring substrate SUB1. The underfill resin UF is positioned to fill the space between the surface 3t of the semiconductor chip CHP1 and the upper surface 2t of the wiring substrate SUB1. Each of the multiple protruding electrodes 3BP is sealed by the underfill resin UF. The underfill resin UF is made of an insulating (non-conductive) material (e.g., a resin material) and is positioned to seal the electrical connection portion (the junction of the multiple protruding electrodes 3BP) between the semiconductor chip CHP1 and the wiring substrate SUB1. In this way, by covering the junction between the multiple protruding electrodes 3BP and the multiple pads 2PD with the underfill resin UF, the stress generated in the electrical connection portion between the semiconductor chip CHP1 and the wiring substrate SUB1 can be relieved. Furthermore, the stress generated in the junction between the multiple electrodes 3PD and the multiple protruding electrodes 3BP of the semiconductor chip CHP1 can also be relieved. In addition, the main surface on which the semiconductor elements (circuit elements) of the semiconductor chip CHP1 are formed can be protected.

[0042] As shown in Figure 3, the stiffener ring 4 is bonded and fixed to the wiring substrate SUB1 via an adhesive layer BND (see Figure 3). As shown in Figure 1, the stiffener ring 4 is an annular member arranged to continuously surround the semiconductor chip CHP1 in a plan view. The stiffener ring 4 is made of a metal such as copper (Cu). When a copper stiffener ring 4 is used, a metal film such as nickel may be formed on the surface of the stiffener ring 4 (e.g., top surface, bottom surface, and inner surface) to prevent oxidation of the surface.

[0043] One of the purposes of mounting the stiffener ring 4 on the wiring board SUB1 is to suppress warping deformation of the wiring board SUB1. Warping deformation of the wiring board SUB1 is caused by the difference between the coefficient of linear expansion (coefficient of thermal expansion) of the wiring board SUB1 and the coefficient of linear expansion (coefficient of thermal expansion) of the semiconductor chip CHP1. This warping deformation is greatest at the peripheral edges of the wiring board SUB1 (especially at the corners). Therefore, the stiffener ring 4 is positioned along the peripheral edge of the upper surface 2t.

[0044] In order for the stiffening ring 4 to suppress the warping deformation of the wiring board SUB1, high adhesive strength between the stiffening ring 4 and the wiring board SUB1 is required. Furthermore, in order for the stiffening ring 4 to suppress the warping deformation of the wiring board SUB1, high rigidity is required of the stiffening ring 4 so that it does not deform due to external forces.

[0045] Incidentally, in BGA type semiconductor devices, there is a cover component called a lid that is positioned to cover the semiconductor chip. Since the lid is positioned on the wiring substrate to cover the semiconductor chip, it is bonded not only to the wiring substrate but also to the semiconductor chip. Therefore, the adhesive strength between the lid and the wiring substrate is contributed to by the strength of the adhesive layer that bonds the lid and the wiring substrate, as well as the strength with which the lid is fixed to the wiring substrate via the semiconductor chip.

[0046] On the other hand, since the stiffener ring 4 in this embodiment is an annular member, the stiffener ring 4 and the semiconductor chip CHP1 are spaced apart from each other. That is, the stiffener ring 4 is positioned on the wiring substrate SUB1 so as not to cover the semiconductor chip CHP1. In this case, the fixing strength between the semiconductor chip CHP1 and the wiring substrate SUB1 does not contribute to the adhesive strength between the stiffener ring 4 and the wiring substrate SUB1. Also, from the viewpoint of "rigidity" as described above, the stiffener ring 4 has lower rigidity compared to the lid. This is because the stiffener ring 4 has an opening in the part that overlaps with the semiconductor chip CHP1.

[0047] As mentioned above, since the stiffener ring 4 is an annular component, the back surface 3b of the semiconductor chip CHP1 remains exposed even after the stiffener ring 4 is mounted on the wiring board SUB1. In this case, a heat sink or similar device, larger than the top surface 2t of the wiring board SUB1, can be directly brought into contact with the back surface 3b of the semiconductor chip CHP1. This is an advantage of the stiffener ring 4 compared to a lid.

[0048] As shown in Figures 1 and 3, the semiconductor device PKG1 has electronic components CD1 mounted on the upper surface 2t of the wiring board SUB1. In the example shown in Figure 1, multiple electronic components CD1 are mounted between the semiconductor chip CHP1 and the stiffening ring 4.

[0049] Each of the multiple electronic components CD1 is a surface-mount chip component, mounted on the wiring board SUB1 via solder. Each of the multiple electronic components CD1 includes, for example, a capacitor, an inductor, or a resistor. In recent years, with the increasing functionality of semiconductor devices, multiple electronic components CD1 may be mounted on the upper surface 2t of the wiring board SUB1, separately from the semiconductor chip CHP1. Each of the multiple electronic components CD1 is positioned to protrude from the upper surface 2t of the wiring board SUB1.

[0050] As shown in Figure 4, the electronic component CD1 has multiple electrodes CDe (two electrodes in Figure 4) and a main body CDb connected to each of the multiple electrodes CDe. For example, a capacitor element, an inductor element, or a resistor element is formed on the main body CDb. As described above, since the electronic component CD1 is a surface-mount chip component, both the main body CDb and the multiple electrodes CDe are arranged on the upper surface 2t of the wiring board SUB1.

[0051] When an electronic component CD1 is mounted on the wiring board SUB1, a portion of the upper surface 2t of the wiring board SUB1 is occupied by the electronic component CD1, thus limiting the bonding area between the stiffener ring 4 and the wiring board SUB1. For example, if the shape of the stiffener ring 4 is a simple frame shape (for example, only the bonding portion 4P1 shown in Figure 1), the volume of the stiffener ring 4 is constrained due to the mounting of the electronic component CD1.

[0052] To improve the rigidity of the stiffener ring 4, it is conceivable to increase its thickness. However, if the thickness of the stiffener ring 4 is made extremely thick, accessibility will decrease when mounting a heat dissipation component (heat spreader, heat sink) HS on the back surface 3b of the semiconductor chip CHP1 via a heat dissipation adhesive layer HSB, as illustrated in Figure 5. This is because the heat dissipation characteristics of the heat dissipation component HS improve in proportion to the heat dissipation area, so it is preferable that the heat dissipation component HS be provided so as to cover the stiffener ring 4. From the viewpoint of ensuring this accessibility, it is difficult to make the thickness of the stiffener ring 4 extremely thick.

[0053] Another possible method is to increase the area of ​​the upper surface 2t of the wiring board SUB1 in order to increase the width of the adhesive portion 4P1 of the stiffener ring 4. However, in this case, the size of the semiconductor device PKG1 will increase, making it impossible to meet the demand for miniaturization of the semiconductor device. Also, if the area of ​​the upper surface 2t increases, the stress generated at the periphery of the wiring board SUB1 will increase, which will exacerbate warping deformation. For this reason, in the case of a semiconductor device PKG1 in which an electronic component CD1 is mounted on the upper surface 2t of the wiring board SUB1 as in this embodiment, it is necessary to improve the rigidity of the stiffener ring 4 within the constraint of not making the thickness of the stiffener ring 4 or the area of ​​the upper surface 2t extremely large.

[0054] Based on the above, the inventors of the present invention investigated techniques to improve the rigidity of the stiffening ring 4 by modifying its shape. Details are described below.

[0055] <Details on Stiffening> As shown in Figures 1, 3, and 4, the stiffener ring 4 includes an adhesive portion 4P1 and a separation portion 4P2. In a plan view as shown in Figure 1, the adhesive portion 4P1 is arranged to continuously surround the semiconductor chip CHP1. In the example shown in Figure 1, the separation portion 4P2 is positioned between the adhesive portion 4P1 and the semiconductor chip CHP1, so as to continuously surround the semiconductor chip CHP1. As shown in Figure 3, the adhesive portion 4P1 is bonded to the upper surface 2t of the wiring board. The separation portion 4P2 is connected to the adhesive portion 4P1 and is positioned away from the upper surface 2t of the wiring board SUB1. At least a portion of the electronic component CD1 is covered by the separation portion 4P2 of the stiffener ring 4. That is, the electronic component CD1 partially overlaps with the separation portion 4P2 of the stiffener ring 4.

[0056] More specifically, as shown in Figure 4, the adhesive portion 4P1 of the stiffener ring 4 has a lower surface 4P1b facing the upper surface 2t of the wiring board, and an upper surface 4P1t located on the opposite side of the lower surface 4P1b. The separation portion 4P2 of the stiffener ring 4 has a lower surface 4P2b facing the upper surface 2t of the wiring board, and an upper surface 4P2t located on the opposite side of the lower surface 4P2b.

[0057] The bonded portion 4P1 is the portion of the stiffener ring 4 that has a lower surface 4P1b, that is, the portion that faces the upper surface 2t of the wiring board SUB1 via the adhesive layer BND. On the other hand, the separated portion 4P2 is the portion that has a lower surface 4P2b positioned higher than the lower surface 4P1b, with the upper surface 2t of the wiring board SUB1 as the reference plane. Because the lower surface 4P2b of the separated portion 4P2 is positioned higher, a space is created between the separated portion 4P2 and the wiring board SUB1. In this embodiment, at least a portion of the electronic component CD1 is placed in the space between the separated portion 4P2 and the wiring board SUB1. This prevents an increase in the area of ​​the upper surface 2t of the wiring board SUB1 even when the width (length in the X direction) of the stiffener ring 4 is increased.

[0058] In the semiconductor device PKG1 according to this embodiment, since the electronic component CD1 is mounted on the wiring board SUB1, the width of the adhesive portion 4P1 of the stiffener ring 4 is limited. On the other hand, the separation portion 4P2 of the stiffener ring 4 is positioned to overlap with the electronic component CD1. Therefore, there is no constraint on the length of the separation portion 4P2 in the width direction (X direction shown in Figure 3) due to the mounting of the electronic component CD1.

[0059] From the standpoint of the rigidity of the stiffener ring 4, the following can be said. That is, since the separated portion 4P2 is connected to the bonded portion 4P1, the bonded portion 4P1 and the separated portion 4P2 behave as rigid bodies. For this reason, the rigidity of the stiffener ring 4 can be improved by connecting the bonded portion 4P1 and the separated portion 4P2. As already explained, it is preferable to improve the rigidity of the stiffener ring 4 from the viewpoint of suppressing warping deformation of the wiring board SUB1. According to this embodiment, the rigidity of the stiffener ring 4 can be improved, so warping deformation of the wiring board SUB1 can be suppressed.

[0060] Incidentally, although not shown in the illustration, as a modification of Figure 1, the separation portion 4P2 may not be provided to continuously surround the semiconductor chip CHP1 (for example, the separation portion 4P2 may be connected to a part of the frame-shaped adhesive portion 4P1). Even in this case, the rigidity of the stiffening ring 4 can be improved. However, as shown in Figure 1, when the separation portion 4P2 is provided to continuously surround the semiconductor chip CHP1, the rigidity of the separation portion 4P2 itself is improved. Therefore, as shown in Figure 1, it is particularly preferable that the separation portion 4P2 is provided to continuously surround the semiconductor chip CHP1.

[0061] Furthermore, in the example shown in Figure 1, the separated portion 4P2 of the stiffener ring 4 is located between the semiconductor chip CHP1 and the bonded portion 4P1 of the stiffener ring 4 in a plan view. If we focus solely on increasing the rigidity of the stiffener ring 4, an embodiment in which the separated portion 4P2 is connected to the outer circumference of the bonded portion 4P1 in a plan view can be considered. However, as mentioned above, from the viewpoint of suppressing warping deformation of the wiring substrate SUB1, it is preferable that the bonded portion 4P1 of the stiffener ring 4 is arranged along the peripheral edge of the upper surface 2t to which the greatest stress is applied. Therefore, as shown in Figure 1, it is preferable that the separated portion 4P2 of the stiffener ring 4 is located between the semiconductor chip CHP1 and the bonded portion 4P1 of the stiffener ring 4 in a plan view.

[0062] As shown in Figure 1, in this embodiment, the outer edge of the stiffener ring forms an octagon in plan view. More specifically, in plan view, the outer edge of the bonded portion 4P1 of the stiffener ring 4 has four main sides 4ms and four corner sides 4cs connected to two of the four main sides 4ms. The four main sides 4ms have main sides 4ms1 and 4ms2 extending along the X direction, and main sides 4ms3 and 4ms4 extending along the Y direction intersecting the X direction. Each of the four corner sides 4cs forms a straight line extending in a direction intersecting the X and Y directions, respectively.

[0063] The shape of the stiffening ring 4 shown in Figure 1 can be described as follows: The adhesive portion 4P1 of the stiffening ring has a shape in which the corners where the four main sides 4ms intersect are chamfered. In addition to the C-chamfer shown in Figure 1, an R-chamfer can also be exemplified. Although not shown in the illustration, in the case of an R-chamfer, each of the four corner sides 4cs forms a curve that extends in a direction intersecting the X and Y directions, respectively.

[0064] As a modification of this embodiment, the outer edge of the stiffener ring 4 may be square in shape. However, from the following viewpoint, it is preferable that the corners are chamfered, as shown in Figure 1. As shown in Figure 1, an alignment mark AM is formed on the upper surface 2t of the wiring board SUB1. The alignment mark AM is located outside the stiffener ring 4 in a plan view. More specifically, the alignment mark AM is located between one of the four corner edges 4cs of the stiffener ring 4 and one of the four corners (corner 2c4 in Figure 1) of the upper surface 2t of the wiring board SUB1 in a plan view.

[0065] Alignment marks AM are used for positioning in processes such as mounting semiconductor chips on the wiring board SUB1, mounting electronic components CD1, or mounting stiffener rings 4. Alignment marks AM may also be used when mounting the heat dissipation member shown in Figure 5. For this reason, alignment marks AM must be positioned in a location with good visibility, and the accuracy of positioning based on alignment marks AM must be high. Considering these factors, it is preferable that alignment marks AM be positioned as close as possible to the outer edge of the upper surface 2t of the wiring board SUB1.

[0066] On the other hand, as mentioned above, the stress that contributes to the warping deformation of the wiring board SUB1 is strongly applied to the outer edge of the wiring board SUB1. For this reason, it is preferable that the stiffener ring 4 is positioned close to the outer edge of the upper surface 2t. As shown in Figure 1, in this embodiment, the outer edge of the stiffener ring 4 has four corner edges 4cs. Therefore, the alignment mark AM can be placed anywhere between the four corners of the upper surface 2t of the wiring board SUB1 and the four corner edges 4cs of the stiffener ring 4. In other words, both the stiffener ring 4 and the alignment mark AM can be positioned close to the outer edge of the upper surface 2t. Furthermore, since the alignment mark AM is positioned outside the stiffener ring 4, it is possible to see the alignment mark AM even when the stiffener ring 4 is mounted.

[0067] <Variation 1 of Stiffening> Next, we will describe a modified example of the semiconductor device described using Figures 1 to 5. Figure 6 is an enlarged cross-sectional view showing the periphery of a part of the stiffener ring, which is a modified example of Figure 4. Figure 7 is an enlarged cross-sectional view schematically showing the state in which the stiffener ring shown in Figure 6 is formed by a partial punching process.

[0068] In the example shown in Figure 4, the upper surface 4P1t of the bonded portion 4P1 and the upper surface 4P2t of the separated portion 4P2 are at the same height with respect to the upper surface 2t of the wiring board SUB1 as the reference plane. Such a shape can be manufactured by methods such as etching, as shown below.

[0069] First, a plate-shaped member (metal plate) of a certain thickness is prepared. Next, a mask is formed on one side of the member (metal plate) (the side corresponding to the lower surface 4P1b in Figure 4). Next, an opening is formed in a part of the mask (the part covering the separated portion 4P2 in Figure 4). Next, a half-etching process is performed to form the surface corresponding to the lower surface 4P2b shown in Figure 4. Next, a through hole is formed in the center of the stiffening ring 4. The method for forming the through hole can be either by etching or by mechanically forming it by punching.

[0070] In the above manufacturing method, the process is complicated because it requires the formation of a mask and the formation of openings in the mask. From the viewpoint of improving the manufacturing efficiency of the stiffening ring 4 (in other words, the manufacturing efficiency of semiconductor devices), it is preferable that it be formed by mechanical processing. Therefore, the following describes modified forms of the stiffening ring 4 that can be formed by mechanical processing. In the following description, the process of forming a through hole in the center of the stiffening ring 4 can be done by general punching (cutting), so a diagrammatic explanation is omitted.

[0071] The adhesive portion 4P1 of the stiffener ring 4 in the semiconductor device PKG2 shown in Figure 6 has a lower surface 4P1b facing the upper surface 2t of the wiring board, and an upper surface 4P1t located on the opposite side of the lower surface 4P1b. The separation portion 4P2 of the stiffener ring 4 has a lower surface 4P2b facing the upper surface 2t of the wiring board, and an upper surface 4P2t located on the opposite side of the lower surface 4P2b. This is the same as the semiconductor device PKG1 shown in Figure 4. In the case of the semiconductor device PKG2 shown in Figure 6, the height difference H2 between the upper surface 2t and the upper surface 4P2t is greater than the height difference H1 between the upper surface 2t and the upper surface 4P1t. In this respect, the semiconductor device PKG2 shown in Figure 6 differs from the semiconductor device PKG1 shown in Figure 4.

[0072] Furthermore, the stiffener ring 4 shown in Figure 6 is formed by mechanical processing (partial punching), and therefore differs from the stiffener ring 4 shown in Figure 4 in the following respects. Specifically, as shown in Figure 6, the thickness of the bonded portion 4P1 is equal to the thickness of the separated portion 4P2.

[0073] Furthermore, the structure shown in Figure 6 can be described as follows: The stiffening ring 4 shown in Figure 6 has side surfaces 4s1 connected to the upper surfaces 4P1t and 4P2t, respectively, and side surfaces 4s2 connected to the lower surfaces 4P1b and 4P2b, respectively. The upper surfaces 4P1t, 4P2t, 4P1b, and 4P2b are each parallel to the upper surface 2t. Side surfaces 4s1 and 4s2 are each perpendicular to the upper surfaces 4P1t, 4P2t, 4P1b, and 4P2b, respectively.

[0074] The stiffening ring 4 shown in Figure 6 is formed by performing a partial punching process using the punching machine 40 shown in Figure 7. Partial punching is a type of punching process using a punch 40P and a die 40D, in which the material (metal plate) is not completely cut, but is sheared only partway through (for example, to about half the thickness of the material (metal plate)).

[0075] As shown in Figure 7, the punching machine 40 used to form the stiffening ring 4 by partial punching has a punch 40P and a die 40D. The punch 40P selectively contacts the lower surface 4P2b of the separated portion 4P2 of the stiffening ring 4, and the die 40D selectively contacts the upper surface 4P1t of the bonded portion 4P1 of the stiffening ring 4. In this state, as shown in Figure 7, the punch 40P is pushed upward. Note that in the example shown in Figure 7, the punch 40P moves upward and the die 40D moves downward, but there are cases where either the punch 40P or the die 40D is fixed.

[0076] As shown in Figure 7, when punching is performed, a portion of the member (metal plate) is sheared partway, forming a bonded portion 4P1 and a separated portion 4P2. The side surfaces 4s1 and 4s2 formed at this time are shear surfaces. Side surface 4s1 is connected perpendicularly to the upper surfaces 4P1t and 4P2t, respectively. Side surface 4s2 is connected perpendicularly to the lower surfaces 4P1b and 4P2b, respectively.

[0077] In the case of a stiffening ring 4 formed by a partial punching process, the bonded portion 4P1 and the separated portion 4P2 are directly connected. Therefore, as shown in Figure 6, even when the electronic component CD1 is placed near the side surface 4s2, the stiffening ring 4 and the electronic component CD1 are unlikely to come into contact. In other words, the electronic component CD1 can be placed near the side surface 4s2. In this case, the width of the bonded portion 4P1 can be increased in the X direction shown in Figure 6.

[0078] However, in the example shown in Figure 6, from the viewpoint of ensuring the strength of the stiffening ring 4, it is necessary to increase the thickness of the boundary portion between the bonded portion 4P1 and the separated portion 4P2 to a certain extent. For example, in the example shown in Figure 6, the height difference H3 between the upper surface 2t and the lower surface 4P2b is less than or equal to the height difference H4 between the upper surface 4P1t and the lower surface 4P2b. Thus, in order to increase the thickness of the boundary portion between the bonded portion 4P1 and the separated portion 4P2 to a certain extent, while also securing space to place the electronic component CD1 between the separated portion 4P2 and the wiring board SUB1, it is necessary to increase the thickness of both the bonded portion 4P1 and the separated portion 4P2.

[0079] The semiconductor device PKG2 shown in Figure 6 is the same as the semiconductor device PKG1 described using Figures 1 to 5, except for the differences mentioned above. Therefore, redundant explanations are omitted.

[0080] <Triplication of Stiffening 2> Next, we will describe modifications of the semiconductor device described using Figures 1 to 5. Figure 8 is an enlarged cross-sectional view showing the periphery of a portion of a stiffening ring, which is another modification of Figure 4. Figure 9 is an enlarged cross-sectional view schematically showing the state in which the stiffening ring shown in Figure 8 is formed by drawing.

[0081] The adhesive portion 4P1 of the stiffener ring 4 in the semiconductor device PKG3 shown in Figure 8 has a lower surface 4P1b facing the upper surface 2t of the wiring board, and an upper surface 4P1t located on the opposite side of the lower surface 4P1b. The separation portion 4P2 of the stiffener ring 4 has a lower surface 4P2b facing the upper surface 2t of the wiring board, and an upper surface 4P2t located on the opposite side of the lower surface 4P2b. This is the same as the semiconductor device PKG1 shown in Figure 4 and the semiconductor device PKG2 shown in Figure 6.

[0082] In the case of semiconductor device PKG3 shown in Figure 8, the height difference H2 between the top surface 2t and the top surface 4P2t is greater than the height difference H1 between the top surface 2t and the top surface 4P1t. Also, since the stiffening ring 4 shown in Figure 8 is formed by mechanical processing (drawing), the thickness of the bonded portion 4P1 is equal to the thickness of the separated portion 4P2. These points are the same as those of semiconductor device PKG2 shown in Figure 6, but differ from semiconductor device PKG1 shown in Figure 4.

[0083] The stiffening ring 4 shown in Figure 8 is formed by deep drawing using the press machine 41 shown in Figure 9. Deep drawing is a type of press work in which a material (metal plate) is placed between a punch 41P and a die 41D, and then the material is plastically deformed by bringing the punch 41P and die 41D closer together.

[0084] As shown in Figure 9, the press machine 41 used to form the stiffening ring 4 by drawing has a punch 41P and a die 41D. The punch 41P is positioned on the lower side of the metal plate (e.g., the lower surface 4P1b), and the die 41D is positioned on the upper side of the metal plate (e.g., the upper surface 4P1t). The punch 41P and the die 41D are each molds for forming. When the pressing surface 41Pt of the punch 41P and the pressing surface 41Db of the die 41D are combined, the metal plate sandwiched between the punch 41P and the die 41D is pressed and formed into the shape of the stiffening ring 4. In the example shown in Figure 9, the punch 41P moves upward and the die 41D moves downward, but there are cases where either the punch 41P or the die 41D is fixed.

[0085] When a stiffening ring 4 is formed by drawing, the resulting stiffening ring 4 has the following characteristics. As shown in Figure 8, the stiffening ring 4 is positioned between the adhesive portion 4P1 and the separation portion 4P2, and further has connecting portions 4P3 connected to the adhesive portion 4P1 and the separation portion 4P2, respectively. The connecting portion 4P3 of the stiffening ring 4 has an upper surface 4P3t connected to the upper surface 4P1t and the upper surface 4P2t, respectively, and a lower surface 4P3b connected to the lower surface 4P1b and the lower surface 4P2b, respectively.

[0086] Unlike punching (partial punching) explained using Figure 7, deep drawing is a method of forming a metal sheet by deforming it rather than shearing it. As a result, a connecting portion 4P3 is formed between the bonded portion 4P1 and the separated portion 4P2.

[0087] By the way, using the upper surface 2t of the wiring board SUB1 as a reference plane, in order to make the height of the lower surface 4P2b of the separated portion 4P2 higher than the height of the lower surface 4P1b of the bonded portion 4P1, the connecting portion 4P3 needs to be inclined. In order to make the width of the bonded portion 4P1 in the X direction as wide as possible, it is preferable that the inclination angle of the connecting portion 4P3 be steep (an angle close to 90 degrees). However, the steeper the inclination angle of the connecting portion 4P3, the greater the strain applied to the stiffening ring 4 by the drawing process.

[0088] In the example shown in Figure 8, the upper surfaces 4P1t, 4P2t, 4P1b, and 4P2b of the stiffening ring 4 are each parallel to the upper surface 2t. The upper surface 4P3t and the lower surface 4P3b intersect the upper surfaces 4P1t, 4P2t, 4P1b, and 4P2b at angles that are not perpendicular to each other. In other words, the inclination angle of the connecting portion 4P3 is less than 90 degrees. In this case, the strain applied to the stiffening ring 4 can be reduced.

[0089] Furthermore, focusing on the thickness of the stiffening ring 4, or the height of the separated portion 4P2, when the stiffening ring 4 is formed by drawing, the following structural characteristics are observed.

[0090] In the case of the partial punching process explained using Figure 7, the metal plate is sheared, so there are constraints on the relationship between the thickness of the metal plate and the height of the separated portion 4P2. That is, it is preferable that the height difference between the lower surface 4P2b of the separated portion 4P2 and the lower surface 4P1b of the bonded portion 4P1 shown in Figure 6 be about half or less of the thickness of the metal plate. Therefore, if it is necessary to increase the value of the height difference H3 according to the height of the electronic component CD1 shown in Figure 6, it is necessary to increase the thickness of the metal plate accordingly (i.e., the thickness of the bonded portion 4P1 and the thickness of the separated portion 4P2).

[0091] On the other hand, when forming the stiffener ring 4 by drawing, there are no such constraints as described above on the relationship between the thickness of the metal plate and the height of the separated portion 4P2. Therefore, the thickness of the metal plate (i.e., the thickness of the bonded portion 4P1 and the separated portion 4P2 shown in Figure 8) can be made as thin as possible within the range in which the rigidity of the stiffener ring 4 can be obtained. In addition, the height difference H3 between the upper surface 2t and the lower surface 4P2b shown in Figure 8 can be arbitrarily set according to the height of the electronic component CD1, regardless of the thickness of the metal plate.

[0092] Therefore, for example, in the example shown in Figure 8, the height difference H3 between the upper surface 2t and the lower surface 4P2b is greater than or equal to the thickness of the bonded portion 4P1. As explained using Figure 5, when mounting a heat dissipation member HS or the like on the back surface 3b of the semiconductor chip CHP1, it is preferable for the thickness of the stiffener ring 4 to be thin in order to prevent interference with the stiffener ring 4. This modified example is preferable because it allows the thickness of the stiffener ring 4 to be reduced within a range in which the necessary rigidity can be ensured.

[0093] The semiconductor device PKG3 shown in Figure 8 is the same as the semiconductor device PKG1 described using Figures 1 to 5, or the semiconductor device PKG2 described using Figure 6, except for the differences mentioned above. Therefore, redundant explanations are omitted.

[0094] <Manufacturing method for semiconductor devices> Next, we will explain the manufacturing method of a semiconductor device. Below, we will mainly explain the manufacturing method of semiconductor device PKG1, which was described using Figures 1 to 4 as a representative example, and then, in principle, only the differences will be explained for modified examples. Figure 10 is an explanatory diagram showing an example of the assembly process flow of a semiconductor device according to one embodiment.

[0095] <Wiring board preparation process> As part of the wiring board preparation process shown in Figure 10, the wiring board SUB1 shown in Figure 3 is prepared. The wiring board SUB1 prepared in this process has all the components of the wiring board SUB1 described using Figures 1 to 3 already formed on it. However, at this stage, the wiring board SUB1 is prepared before the semiconductor chip CHP1, electronic component CD1, and stiffener ring 4 are mounted on it.

[0096] Incidentally, in the wiring board preparation process, a wiring board 20, which is a so-called multi-cavity board with multiple device regions 21, is sometimes prepared, as shown in Figure 11. The upper surface 2t of the wiring board 20 has multiple device regions 21 and dicing regions 22 surrounding each of the multiple device regions 21. Figure 11 is a plan view showing a modified example of the wiring board prepared in the wiring board preparation process shown in Figure 10. In the following description, any of Figures 1 to 3 may be referred to as wiring board SUB1. When a multi-cavity board is used, the term wiring board SUB1 can be read as referring to the device region 21 of the wiring board 20 in the following description.

[0097] Each of the multiple device regions 21 has an alignment mark AM formed on it, as explained using Figure 1. The alignment mark AM is located near one of the corners of the multiple device regions 21 (for example, the corner corresponding to corner 2c4 shown in Figure 1). In the example shown in Figure 1, the alignment mark AM is a right-angled isosceles triangle with a right-angled vertex (vertex AMc shown in Figure 12, described later) at a position that coincides with the diagonal 2d1. The diagonal 2d1 coincides with the midpoint of the base of the right-angled isosceles triangle (the side that does not include the right-angled vertex: base AMs1 shown in Figure 12, described later).

[0098] <Semiconductor chip preparation process> Furthermore, as part of the semiconductor chip preparation process shown in Figure 10, the semiconductor chip CHP1 shown in Figures 1, 3, and 4 is prepared. The structure of the semiconductor chip CHP1 has already been explained, so a redundant explanation will be omitted.

[0099] <Semiconductor chip mounting process> Next, as shown in Figure 10, the semiconductor chip CHP1 is mounted on the upper surface 2t of the wiring substrate SUB1 as shown in Figure 3. The semiconductor chip CHP1 is mounted in each of the multiple device regions 21 shown in Figure 11. In the semiconductor chip mounting process, the semiconductor chip CHP1 is mounted on the wiring substrate SUB1 such that its surface 3t faces the upper surface 2t of the wiring substrate SUB1. Each of the multiple electrodes 3PD of the semiconductor chip CHP1 is positioned to face each of the multiple pads 2PD of the wiring substrate SUB1. After the semiconductor chip CHP1 is placed on the wiring substrate SUB1, a reflow process is performed so that each of the multiple electrodes 3PD and the multiple pads 2PD are electrically connected via the protruding electrode 3BP. This type of connection method is called a flip-chip connection method, and the semiconductor chip mounting process in this embodiment is called a face-down mounting method, in which the surface 3t of the semiconductor chip CHP1 and the upper surface 2t of the wiring substrate SUB1 face each other.

[0100] <Electronic component mounting process> Next, as shown in Figure 10, the electronic component CD1 is mounted on the upper surface 2t of the wiring board SUB1 as shown in Figure 3. The electronic component CD1 is mounted in each of the multiple device regions 21 shown in Figure 11. In the electronic component mounting process, as explained using Figure 4, the electronic component CD1 has multiple electrodes CDe (two electrodes in Figure 4) and a main body CDb connected to each of the multiple electrodes CDe. In this process, solder material is placed on multiple terminals exposed from the insulating film SR1 on the upper surface 2t of the wiring board SUB1 as shown in Figure 4. Next, the electronic component CD1 is placed on the upper surface 2t such that the multiple electrodes CDe of the electronic component and the terminals of the wiring board SUB1 face each other via the solder material. After that, by performing a reflow process, the electrodes CDe and the terminals of the wiring board SUB1 are electrically connected via the solder material.

[0101] Although Figure 10 distinguishes between the semiconductor chip mounting process and the electronic component mounting process, the reflow process included in each process can be performed in a single operation.

[0102] <Sealing process> Next, as shown in Figure 10, in the sealing process, as shown in Figure 4, underfill resin UF is supplied between the semiconductor chip CHP1 and the wiring substrate SUB1, and the multiple protruding electrodes 3BP are sealed in an insulated state from each other.

[0103] <Stiffening process> Next, as shown in Figure 10, the stiffener ring mounting process involves mounting the stiffener ring 4 on the upper surface 2t of the wiring board SUB1, as shown in Figures 1 and 3. As shown in Figure 10, the stiffener ring mounting process includes an adhesive application process, a positioning process, and a stiffener ring fixing process.

[0104] In the adhesive application process shown in Figure 10, adhesive is applied to the area where the stiffening ring 4 (see Figure 1) is to be mounted, specifically the area facing the lower surface 4P1b of the bonded portion 4P1 shown in Figure 4. The adhesive is, for example, a paste containing a thermosetting resin component, and by curing it, the adhesive layer BND shown in Figure 4 is formed.

[0105] In this process, adhesive is applied to the entire area of ​​the upper surface 2t of the wiring board SUB1 that is intended to face the lower surface 4P1b of the adhesive portion 4P1 shown in Figure 4. Alternatively, in this process, adhesive may be applied to only a portion (multiple locations) of the area of ​​the upper surface 2t of the wiring board SUB1 that is intended to face the lower surface 4P1b of the adhesive portion 4P1 shown in Figure 4.

[0106] Next, in the alignment process shown in Figure 10, the position and orientation of the stiffener ring shown in Figure 1 are adjusted by referring to the position of the alignment mark AM shown in Figure 11. Figure 12 is an enlarged plan view showing the state after the positional relationship between the alignment mark and the stiffener ring has been adjusted in the alignment process shown in Figure 10.

[0107] As explained using Figures 1 to 4, when the separated portion 4P2 of the stiffener ring 4 is mounted so as to cover the electronic component CD1, the positional accuracy of the stiffener ring 4 during mounting is important. In the XY plane shown in Figure 12, if the angular deviation of the stiffener ring 4 in the θ direction (hereinafter referred to as the θ-direction deviation) is large, a part of the adhesive portion 4P1 of the stiffener ring 4 may come into contact with the electronic component CD1.

[0108] In this embodiment, as described with reference to Figure 1, the outer edge of the adhesive portion 4P1 of the stiffening ring 4 has four main sides 4ms and four corner sides 4cs connected to two of the four main sides 4ms. The four main sides 4ms have main sides 4ms1 and 4ms2 extending along the X direction and main sides 4ms3 and 4ms4 extending along the Y direction intersecting the X direction. Each of the four corner sides 4cs forms a straight line (or curve) extending in a direction intersecting the X and Y directions, respectively.

[0109] In the alignment process, the outer diameter shape of the stiffening ring 4 described above can be used to improve the alignment accuracy. For example, in this embodiment, the position of the alignment mark AM and the position of one of the four corner edges 4cs (see Figure 1) of the stiffening ring 4 are acquired by an image sensor (not shown) during the alignment process.

[0110] Next, the position of the stiffener ring 4 and the wiring board SUB1 are adjusted by referring to the position of the alignment mark AM and the position of one of the four corner edges 4cs of the stiffener ring 4. At this time, as shown in Figure 12, for example, the alignment is performed so that the bottom edge AMs1 of the alignment mark AM and the corner edge 4cs of the stiffener ring 4 are parallel. Alternatively, the alignment is performed so that the edge AMs2 of the alignment mark AM and the main edge 4ms2 of the stiffener ring 4 are aligned in a straight line, and the edge AMs3 of the alignment mark AM and the main edge 4ms4 of the stiffener ring 4 are aligned in a straight line.

[0111] In this case, the displacement of the stiffener ring 4 in the θ direction can be suppressed. As previously explained, the alignment shown in Figure 12 is achieved by placing the alignment mark AM on the outside of the stiffener ring 4.

[0112] According to this embodiment, the stiffener ring 4 can be aligned with high precision, so even if the separation distance between the electronic component CD1 and the adhesive portion 4P1 of the stiffener ring 4 shown in Figure 4 is small in the design, contact between the electronic component CD1 and the stiffener ring 4 can be prevented. If the separation distance between the electronic component CD1 and the adhesive portion 4P1 of the stiffener ring 4 shown in Figure 4 can be reduced, the width of the adhesive portion 4P1 in the X direction shown in Figure 4 can be increased. This increases the adhesive area between the adhesive portion 4P1 and the wiring board SUB1 (in other words, the area of ​​the lower surface 4P1b of the adhesive portion 4P1), thereby improving the adhesive strength between the stiffener ring 4 and the wiring board SUB1.

[0113] Next, in the stiffener ring fixing process shown in Figure 10, the aligned stiffener ring 4 is pressed toward the wiring board SUB1. The adhesive applied to the upper surface 2t is sandwiched between the lower surface of the stiffener ring 4 and the upper surface 2t of the wiring board SUB1 and spread outwards. As a result, the shape of the adhesive becomes the shape of the adhesive layer BND shown in Figure 4.

[0114] Next, the adhesive interposed between the stiffener ring 4 (see Figure 3) and the wiring board SUB1 (see Figure 3) is cured to form the adhesive layer BND (see Figure 3). Through this process, the stiffener ring 4 is fixed onto the wiring board SUB1.

[0115] <Solder ball formation process> Next, as part of the solder ball formation process shown in Figure 10, multiple solder balls SB are formed on the lower surface 2b of the wiring board SUB1, as shown in Figure 2.

[0116] In this process, multiple solder balls SB (see Figures 2 and 4) are bonded to multiple lands 2LD formed on the underside of the wiring board SUB1 shown in Figure 3. After placing solder material on each of the multiple lands 2LD exposed on the underside of the wiring board SUB1, a reflow process is performed. For example, solder balls can be used as the solder material. By heating the solder balls above their melting point and then cooling them, the solder balls are bonded to the lands 2LD. In some cases, the reflow process may be performed with the solder balls in contact with flux in order to activate the surface of the solder balls. Alternatively, as a variation of this process, a solder material containing solder and flux components, called solder paste, may be applied. In either case, the solder material is formed into a ball shape on the lands 2LD due to the surface tension of the solder component, so that multiple solder balls SB shown in Figure 2 are obtained.

[0117] Flux components used to activate the surface of the solder material may remain as residue around the solder balls (SB) after the reflow process. In this case, although not shown in Figure 10, it is preferable to add a cleaning step after the solder ball formation step to remove the flux component residue.

[0118] <Singulation process> When using the wiring board 20 described with reference to Figure 11, a fragmentation process is performed after the solder ball formation process, as shown in Figure 10. In the fragmentation process, the wiring board 20 is cut along the dicing region 22 shown in Figure 11, and multiple device regions 21 are separated into individual pieces. The cutting method is not particularly limited, but for example, a method of cutting the wiring board 20 using a dicing blade (not shown) can be exemplified. Note that when preparing the wiring board SUB1 shown in Figures 1 to 6 in the wiring board preparation process shown in Figure 10, the fragmentation process can be omitted. This is because the wiring board SUB1 shown in Figures 1 to 6 corresponds to one device region 21 shown in Figure 11.

[0119] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence.

[0120] For example, as a modification of the stiffener ring 4 shown in Figure 3, the thickness of the stiffener ring 4 may be smaller than not only the thickness T2 of the wiring substrate SUB1, but also the thickness of the core insulating layer 2CR that constitutes the wiring substrate SUB1. However, in order to more reliably prevent warping deformation of the wiring substrate SUB1, it is preferable to use a stiffener ring whose rigidity is improved by increasing its thickness in addition to arranging multiple adhesive layers BND in appropriate positions. [Explanation of Symbols]

[0121] 2b,2Cb Bottom surface 2c1,2c2,2c3,2c4 angle 2CP conductor pattern 2CR Core Insulation Layer (Insulation Layer, Core Material, Core Insulation Layer) 2Ct,2t top surface 2D wiring 2d1, 2d2 diagonal 2e insulating layer 2LD Land 2PD pads 2s1, 2s2, 2s3, 2s4 sides 2THW Through-hole wiring 2V via wiring 3b Back side (main side, bottom side) 3BP (Bump Electrode) 3PD electrodes (pads, electrode pads, bonding pads) 3t surface (main surface, top surface) 4. Stiffening 4cs corner edge 4ms,4ms1,4ms2,4ms3,4ms4 Main side 4P1 Glued part 4P1b,4P2b,4P3b Bottom surface 4P1t,4P2t,4P3t Top surface 4P2 Separation part 4P3 connection part 4s,4s1,4s2 side 20, SUB1 Wiring Board 21 Device Area 22 Dicing area 40 Punching machine 40D, 41D Die 40P, 41P Punch 41 Pressing machine 41Db, ​​41Pt pressing surface AM Alignment Mark AMc vertex AMs1 Bottom AMs2, AMs3 sides BND adhesive layer CD1 Electronic Components CDb main unit CDe electrode CHP1 semiconductor chip H1,H2,H3,H4 Height difference HS heat dissipation components (heat spreaders, heat sinks) HSB adhesive layer PKG1, PKG2, PKG3 Semiconductor Device SB Solder Balls (Solder material, external terminals, electrodes, external electrodes) SR1, SR2 insulating film UF Underfil resin (insulating resin) WL1, WL2, WL3, WL4, WL5, WL6, WL7, WL8 wiring layers

Claims

1. A wiring board having a first upper surface and a first lower surface opposite to the first upper surface, A semiconductor chip mounted on the first upper surface of the wiring board, The electronic components mounted on the first upper surface of the wiring board, A stiffening ring fixed to the first upper surface of the wiring board, Includes, The stiffening ring is A first portion is arranged to continuously surround the semiconductor chip in a plan view and is bonded to the first upper surface of the wiring substrate, A second portion connected to the first portion and positioned away from the first upper surface of the wiring board, Includes, The aforementioned electronic component partially overlaps with the second portion of the stiffening ring in a semiconductor device.

2. In the semiconductor device described in claim 1, A semiconductor device wherein the second portion of the stiffening ring is located between the semiconductor chip and the first portion of the stiffening ring in a plan view.

3. In the semiconductor device described in claim 2, The second portion of the stiffening ring is arranged to continuously surround the semiconductor chip in a plan view, in a semiconductor device.

4. In the semiconductor device described in claim 3, The first portion of the stiffening ring has a second lower surface facing the first upper surface of the wiring board, and a second upper surface located on the opposite side of the second lower surface. The second portion of the stiffening ring has a third lower surface facing the first upper surface of the wiring board, and a third upper surface located on the opposite side of the third lower surface. The height difference between the first upper surface and the third upper surface is the same as the height difference between the first upper surface and the second upper surface. A semiconductor device in which the first part and the second part are directly connected.

5. In the semiconductor device described in claim 3, The first portion of the stiffening ring has a second lower surface facing the first upper surface of the wiring board, and a second upper surface located on the opposite side of the second lower surface. The second portion of the stiffening ring has a third lower surface facing the first upper surface of the wiring board, and a third upper surface located on the opposite side of the third lower surface. A semiconductor device wherein the height difference between the first upper surface and the third upper surface is greater than the height difference between the first upper surface and the second upper surface.

6. In the semiconductor device described in claim 5, A semiconductor device in which the thickness of the first portion is equal to the thickness of the second portion.

7. In the semiconductor device described in claim 6, The first part and the second part are directly connected, A semiconductor device in which the height difference between the first upper surface and the third lower surface is less than or equal to the height difference between the second upper surface and the third lower surface.

8. In the semiconductor device described in claim 5, The stiffening ring is A first side surface connected to the second upper surface and the third upper surface, A second side surface connected to the second lower surface and the third lower surface, It has, Each of the second upper surface, the third upper surface, the second lower surface, and the third lower surface is parallel to the first upper surface. A semiconductor device wherein each of the first and second sides is perpendicular to each of the second upper surface, the third upper surface, the second lower surface, and the third lower surface.

9. In the semiconductor device described in claim 5, A semiconductor device wherein the stiffening ring is positioned between the first portion and the second portion and further has a third portion connected to each of the first and second portions.

10. In the semiconductor device described in claim 9, The third portion of the stiffening ring is A fourth upper surface connected to the second upper surface and the third upper surface, A fourth lower surface connected to the second lower surface and the third lower surface, It has, Each of the second upper surface, the third upper surface, the second lower surface, and the third lower surface is parallel to the first upper surface. A semiconductor device wherein the fourth upper surface and the fourth lower surface each intersect the second upper surface, the third upper surface, the second lower surface, and the third lower surface at angles that are not perpendicular to each other.

11. In the semiconductor device according to claim 10, A semiconductor device in which the height difference between the first upper surface and the third lower surface is greater than or equal to the thickness of the first portion.

12. In the semiconductor device described in claim 3, In plan view, the outer edge of the first portion of the stiffening ring has four main sides and four corner sides connected to two of the four main sides, The four main sides mentioned above are, The first principal side and the second principal side extend along the first direction, The third and fourth principal sides extend along the second direction intersecting the first direction, It has, A semiconductor device in which each of the four corner edges forms a straight line or curve extending in a direction intersecting the first direction and the second direction, respectively.

13. In the semiconductor device according to claim 12, The wiring board further has alignment marks formed on the first upper surface, The alignment mark is located between the outer edge of the first upper surface of the wiring board and the stiffening ring in a plan view of the semiconductor device.

14. (a) A step of preparing a wiring board having a first upper surface having a plurality of device regions and a dicing region surrounding each of the plurality of device regions, (b) A step of mounting a semiconductor chip on the first upper surface of each of the plurality of device regions, (c) A step of mounting an electronic component on the first upper surface of each of the plurality of device regions, (d) After step (b) and step (c), a step of mounting stiffening rings on the first upper surface of each of the plurality of device regions, It has, The stiffening ring installed in step (d) above is A first portion which forms a frame shape in plan view and is adhered to the first upper surface in step (d), A second portion connected to the first portion and positioned away from the first upper surface in step (d), Includes, A method for manufacturing a semiconductor device, wherein in step (d), the electronic component partially overlaps with the second portion of the stiffening ring.

15. In the method for manufacturing a semiconductor device according to claim 14, In step (d) above, the second portion of the stiffening ring is located between the semiconductor chip and the first portion of the stiffening ring in a plan view, and is arranged to continuously surround the semiconductor chip in a plan view. In plan view, the outer edge of the first portion of the stiffening ring has four main sides and four corner sides connected to two of the four main sides, The four main sides mentioned above are, The first principal side and the second principal side extend along the first direction, The third and fourth principal sides extend along the second direction intersecting the first direction, It has, A method for manufacturing a semiconductor device, wherein each of the four corner edges forms a straight line or curve extending in a direction intersecting the first direction and the second direction, respectively.

16. In the method for manufacturing a semiconductor device according to claim 15, The wiring board further has alignment marks formed in each of the plurality of device regions, A method for manufacturing a semiconductor device, wherein in step (d), the stiffening ring is mounted on the first upper surface after adjusting the mounting position of the stiffening ring by referring to the position of the alignment mark and the position of one of the four corner edges of the stiffening ring.

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