Silicon carbide semiconductor substrate, silicon carbide semiconductor device, method for inspecting a silicon carbide semiconductor substrate, and method for manufacturing a silicon carbide semiconductor device.

Abstract

This invention provides a silicon carbide semiconductor substrate, a silicon carbide semiconductor device, a silicon carbide semiconductor substrate inspection method, and a silicon carbide semiconductor device manufacturing method that can improve product yield by enabling the detection of crystal defects that do not affect device operation. [Solution] The silicon carbide semiconductor substrate inspection method is a method for inspecting a silicon carbide semiconductor substrate having an epitaxial layer. By differential interference contrast observation of the silicon carbide semiconductor substrate, it is determined whether the crystal defects of the silicon carbide semiconductor substrate are defects that have grown obliquely within the epitaxial layer. From the photoluminescence image of the silicon carbide semiconductor substrate, it is determined whether the defects are stacking faults that have grown trapezoidally within the epitaxial layer. By transmission polarization observation of the silicon carbide semiconductor substrate, it is determined whether the stacking faults are associated with through-helical dislocations.

Description

[Technical Field]

[0001] This disclosure relates to silicon carbide semiconductor substrates, silicon carbide semiconductor devices, methods for inspecting silicon carbide semiconductor substrates, and methods for manufacturing silicon carbide semiconductor devices. [Background technology]

[0002] Conventionally, methods for classifying detected defects based on photoluminescence measurements, reflection images and photoluminescence images, or differential interference images are known (see, for example, Patent Documents 1, 2, and 3 below). [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2013-162112 [Patent Document 2] Patent No. 5713419 [Patent Document 3] Japanese Patent Publication No. 2012-174896 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] However, conventional inspection methods for silicon carbide semiconductor substrates cannot perform detailed analysis of crystal defects contained in single-crystal silicon carbide semiconductor substrates. As a result, crystal defects that do not actually affect device operation are mistakenly identified as defects and excluded from the product. This disclosure aims to provide a silicon carbide semiconductor substrate, a silicon carbide semiconductor device, an inspection method for a silicon carbide semiconductor substrate, and a method for manufacturing a silicon carbide semiconductor device that can improve product yield compared to conventional inspection methods by enabling the identification of crystal defects that do not affect device operation. [Means for solving the problem]

[0005] To solve the problems described above and achieve the objectives of this disclosure, the silicon carbide semiconductor substrate relating to this disclosure has the following features. A silicon carbide semiconductor substrate having an epitaxial layer, wherein the silicon carbide semiconductor substrate is divided into a first determination point location and a second determination point location for silicon carbide semiconductor devices formed by fragmentation, the first determination point location includes stacking faults that have grown trapezoidally within the epitaxial layer with a through-helical dislocation at their origin, and stacking faults that have grown trapezoidally within the epitaxial layer with a through-helical dislocation at their origin, among stacking faults that have grown trapezoidally within the epitaxial layer without a through-helical dislocation at their origin, and the second determination point location includes stacking faults that have grown trapezoidally within the epitaxial layer with a through-helical dislocation at their origin, and stacking faults that have grown trapezoidally within the epitaxial layer without a through-helical dislocation at their origin.

[0006] According to the disclosure described above, diagonal defects with through-helical dislocations and diagonal defects without through-helical dislocations are determined by transmitted polarization observation. As a result, since diagonal defects with through-helical dislocations do not affect device operation, if only these defects are present, the product can be judged as good, thereby improving product yield. [Effects of the Invention]

[0007] The silicon carbide semiconductor substrate, silicon carbide semiconductor device, silicon carbide semiconductor substrate inspection method, and silicon carbide semiconductor device manufacturing method described herein enable the determination of stacking faults that do not affect device operation, thereby improving product yield compared to conventional inspection methods. [Brief explanation of the drawing]

[0008] [Figure 1] This is a flowchart showing a method for inspecting a silicon carbide semiconductor substrate according to an embodiment. [Figure 2]It is a flowchart showing a method for determining crystal defects in an inspection method of a silicon carbide semiconductor substrate according to an embodiment. [Figure 3] It is a schematic diagram of a transmission polarization image of diagonal defects in an inspection method of a silicon carbide semiconductor substrate according to an embodiment. [Figure 4] It is a schematic diagram of a radiation light X-ray topography image of diagonal defects in an inspection method of a silicon carbide semiconductor substrate according to an embodiment. [Figure 5] It is a schematic diagram of a differential interference image of micropipe defects included in a silicon carbide semiconductor substrate in an inspection method of a silicon carbide semiconductor substrate according to an embodiment. [Figure 6] It is a schematic diagram of a transmission polarization image of micropipe defects in an inspection method of a silicon carbide semiconductor substrate according to an embodiment. [Figure 7] It is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to an embodiment. [Figure 8] It is a flowchart showing a conventional inspection method of a silicon carbide semiconductor substrate. [Figure 9] It is a schematic diagram of a silicon carbide semiconductor substrate having epitaxial growth defects after epitaxial growth. [Figure 10] It is a schematic diagram of a differential interference image of epitaxial growth defects of a silicon carbide semiconductor substrate. [Figure 11] It is a schematic diagram showing a PL imaging image of epitaxial growth defects of a silicon carbide semiconductor substrate. [Figure 12] It is a schematic diagram showing a micropipe blocked in a conventional silicon carbide semiconductor substrate provided with an epitaxial layer.

Embodiments for Carrying Out the Invention

[0009] <Summary of Embodiments of the Present Disclosure> To solve the above-mentioned problems and achieve the objectives of this disclosure, the silicon carbide semiconductor substrate relating to this disclosure has the following features: A silicon carbide semiconductor substrate having an epitaxial layer, wherein the silicon carbide semiconductor substrate has separate locations for first judged products (good products) and second judged products (defective products) of silicon carbide semiconductor devices formed by fragmentation, and the locations of the first judged products are stacking faults that have grown trapezoidally within the epitaxial layer accompanied by a through-helical dislocation at the origin, and stacking faults that have grown trapezoidally within the epitaxial layer without a through-helical dislocation at the origin The stacking faults include those that have grown trapezoidally within the epitaxial layer with a through-helical dislocation at their origin, and the position of the second determined product includes stacking faults that have grown trapezoidally within the epitaxial layer with a through-helical dislocation at their origin, and stacking faults that have grown trapezoidally within the epitaxial layer without a through-helical dislocation at their origin.

[0010] According to the disclosure described above, diagonal defects with through-helical dislocations and diagonal defects without through-helical dislocations are determined by transmitted polarization observation. As a result, since diagonal defects with through-helical dislocations do not affect device operation, if only these defects are present, the product can be judged as good, thereby improving product yield.

[0011] To solve the above-mentioned problems and achieve the objectives of this disclosure, the silicon carbide semiconductor device according to this disclosure has the following features: A vertical silicon carbide semiconductor device having electrodes on both main surfaces of a silicon carbide semiconductor substrate having an epitaxial layer, wherein the silicon carbide semiconductor substrate has stacking faults that have grown trapezoidally within the epitaxial layer accompanied by through-helical dislocations at their origin, and stacking faults that have grown trapezoidally within the epitaxial layer without through-helical dislocations at their origin, and which have grown trapezoidally within the epitaxial layer accompanied by through-helical dislocations at their origin.

[0012] To solve the above-mentioned problems and achieve the objectives of this disclosure, the inspection method for a silicon carbide semiconductor substrate according to this disclosure has the following features: An inspection method for a silicon carbide semiconductor substrate having an epitaxial layer, comprising: first, a first step of determining whether a crystal defect in the silicon carbide semiconductor substrate is a defect that grew obliquely within the epitaxial layer by differential interference contrast observation of the silicon carbide semiconductor substrate; second, a second step of determining whether the defect is a stacking fault that grew trapezoidally within the epitaxial layer by photoluminescence image of the silicon carbide semiconductor substrate; and third, a third step of determining whether the stacking fault is associated with a through-helical dislocation by transmission polarization observation of the silicon carbide semiconductor substrate.

[0013] Furthermore, the inspection method for a silicon carbide semiconductor substrate according to this disclosure is characterized in that it further includes a fourth step of detecting a micropipe defect that is blocked by the epitaxial layer by transmission polarization observation of the silicon carbide semiconductor substrate as described above.

[0014] Furthermore, the inspection method for silicon carbide semiconductor substrates according to this disclosure is characterized in that the silicon carbide semiconductor substrate is a single-crystal 4H-SiC substrate, as described in the above disclosure.

[0015] Furthermore, the inspection method for silicon carbide semiconductor substrates according to this disclosure is characterized in that, as described above, a fifth step is further included, after the second step and before the third step, in which the back surface of the silicon carbide semiconductor substrate is polished to make the surface of the back surface of the silicon carbide semiconductor substrate have a roughness Ra (arithmetic mean roughness) of < 3 nm.

[0016] To solve the above-mentioned problems and achieve the objectives of this disclosure, the method for manufacturing a silicon carbide semiconductor device according to this disclosure has the following features. This is a method for manufacturing a vertical silicon carbide semiconductor device, wherein electrodes are provided on both main surfaces of a silicon carbide semiconductor substrate having an epitaxial layer. First, a first step is performed in which a crystal defect in the silicon carbide semiconductor substrate is determined by differential interference contrast observation of the silicon carbide semiconductor substrate to determine whether the defect is a defect that grew obliquely within the epitaxial layer. Next, a second step is performed in which a photoluminescence image of the silicon carbide semiconductor substrate is determined to determine whether the defect is a stacking fault that grew trapezoidally within the epitaxial layer. Next, a third step is performed in which a transmission polarization observation of the silicon carbide semiconductor substrate is determined to determine whether the stacking fault originates from a through-helical dislocation. Next, a formation step is performed in which a predetermined element structure is formed on the silicon carbide semiconductor substrate. Next, after the formation step, a cutting step is performed in which the silicon carbide semiconductor substrate is diced to form individual silicon carbide semiconductor devices. Next, a sorting process is performed to select a first judged silicon carbide semiconductor device based on the first to third steps.

[0017] Preferred embodiments of the silicon carbide semiconductor substrate, silicon carbide semiconductor device, inspection method for silicon carbide semiconductor substrate, and manufacturing method for silicon carbide semiconductor device according to this disclosure will be described in detail below with reference to the attached drawings. In this specification and the attached drawings, layers or regions prefixed with n or p mean that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to n and p mean that they have a higher and lower impurity concentration than layers or regions without these signs, respectively. In the following description of embodiments and attached drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted. It is preferable that the descriptions of "same" or "equivalent" include a range of ±5% to account for manufacturing variations.

[0018] (Embodiment) <Knowledge forming the basis of this disclosure> First, we will explain the conventional inspection method for silicon carbide semiconductor substrates. Figure 8 is a flowchart showing the conventional inspection method for silicon carbide semiconductor substrates. Silicon carbide (SiC) is expected to be the next-generation semiconductor material to replace silicon (Si). Semiconductor devices using silicon carbide (hereinafter referred to as silicon carbide semiconductor devices) have various advantages compared to conventional semiconductor devices using silicon, such as the ability to reduce the resistance of the device in the ON state to a fraction of that of silicon, and the ability to be used in environments with higher temperatures (above 200°C). This is due to the inherent characteristics of the material itself, such as the fact that the band gap of silicon is about three times larger than that of silicon, and the dielectric breakdown field strength is nearly an order of magnitude greater than that of silicon.

[0019] However, there are many challenges to overcome in the manufacturing methods of silicon carbide semiconductor devices. For example, improving the efficiency of the manufacturing process and improving product yield are among the challenges. Since SiC crystal growth technology and epitaxial growth technology are still under development, many crystal defects and epitaxial growth defects exist in the substrate. These defects become device killer defects that degrade the properties of SiC devices and are a major factor in reducing yield. For this reason, silicon carbide semiconductor substrates are inspected before and after the formation of the device structure on the substrate.

[0020] For example, as shown in Figure 8, first, a SiC bulk substrate is prepared (step S101). A SiC bulk substrate is obtained by slicing a single-crystal SiC ingot and then mirror-polishing both sides. A substrate on which an epitaxial layer made of SiC is grown on one surface of a SiC bulk substrate is called a SiC epitaxial substrate. The flowchart in Figure 8 shows the case where a SiC bulk substrate is prepared; if a SiC epitaxial substrate is prepared, steps S102 to S106 are unnecessary, and step S101 becomes the process of preparing the SiC epitaxial substrate.

[0021] Next, the SiC bulk substrate is subjected to CMP (Chemical Mechanical Polishing) (Step S102). For example, CMP is performed on the Si surface, which is the epitaxial growth surface. Next, the SiC bulk substrate is cleaned (Step S103). For example, the Si surface is thoroughly cleaned by pure water ultrasonic cleaning, organic solvent ultrasonic cleaning, SPM (Sulfuric Acid Peroxide Mixture) cleaning, and RCA (wet cleaning using strong acid and high base solutions).

[0022] Next, the SiC bulk substrate is inspected (step S104). For example, the Si surface is inspected by differential interference contrast observation using an optical microscope. Next, the SiC bulk substrate is cleaned (step S105). As in step S103, the Si surface is thoroughly cleaned. Note that if the substrate is commercially available and has already undergone CMP processing and final cleaning, steps S102 to S105 can be omitted.

[0023] Next, an epitaxial layer is grown on the SiC bulk substrate (step S106). For example, the SiC bulk substrate is set on a susceptor in the chamber of the epitaxial growth apparatus, and an epitaxial layer made of SiC is grown on the Si surface. Next, a surface image inspection of the SiC epitaxial substrate is performed (step S107). For example, a surface image inspection of the Si surface is performed using differential interference contrast observation or photoluminescence (PL) imaging. Next, the back surface of the SiC epitaxial substrate is polished (step S108).

[0024] Here, Figure 9 is a schematic diagram showing a silicon carbide semiconductor substrate with epitaxial growth defects after epitaxial growth. As shown in Figure 9, the silicon carbide semiconductor substrate has multiple epitaxial growth defects 160. Figure 10 is a schematic diagram showing the differential interference pattern of the silicon carbide semiconductor substrate. Figure 11 is a schematic diagram showing the PL imaging pattern of the epitaxial growth defects of the silicon carbide semiconductor substrate. Figure 10 is the surface image inspection data (differential interference pattern) of the epitaxial growth defects 160 in Figure 9, and Figure 11 is the PL imaging pattern of the epitaxial growth defects 160 in Figure 9 at a wavelength of 420 nm. In Figure 11, the region indicated by the dotted line 150 is the emission region where the epitaxial growth defects 160 emit light at a wavelength of 420 nm.

[0025] Conventionally, detailed analysis of epitaxial growth defects could not be performed using only morphological observation with differential interference contrast microscopy or PL imaging. As a result, if epitaxial growth defects 160 were present, even if they did not actually affect the device's operation, the product would be mistakenly judged as defective and excluded from the market.

[0026] Figure 12 is a schematic diagram showing a blocked micropipe in a conventional silicon carbide semiconductor substrate with an epitaxial layer. When an epitaxial layer 162 is epitaxially grown on a SiC bulk substrate 161, micropipe defects 163 are blocked by the epitaxial layer 162 and become invisible when observed from the outermost surface, or even if they are accompanied by surface defects, they may be mistaken for pits or deposits. Thus, conventionally, it has been difficult to distinguish and detect blocked micropipe defects from other defects in differential interference contrast images or PL imaging images because it is difficult to identify defects grown within the epitaxial layer 162.

[0027] (Method for inspecting a silicon carbide semiconductor substrate according to an embodiment) The following describes an inspection method for a silicon carbide semiconductor substrate according to an embodiment that solves the above-mentioned problems. Specifically, the silicon carbide semiconductor substrate is a single crystal 4H-SiC (four-layer periodic hexagonal silicon carbide) bulk substrate with a remaining thickness of 10 to 500 μm, an off-angle of 0 to 8°, and a conductivity type of n-type or p-type, with an impurity concentration of 1 × 10⁻¹⁶ on the Si plane, C plane, or any slice plane. 14 / cm 3 ~5×10 19 / cm 3 This is a single-crystal 4H-SiC epitaxial substrate in which an n-type or p-type epitaxial film with a thickness of 0.5 to 300 μm is epitaxially grown in a single layer or multi-layer configuration. Furthermore, this single-crystal 4H-SiC epitaxial substrate has an impurity concentration of 1 × 10⁻¹⁶. 14 / cm 3 ~5×10 19 / cm 3 It may include one or more n-type or p-type ion implantation layers.

[0028] Figure 1 is a flowchart illustrating a silicon carbide semiconductor substrate inspection method according to an embodiment. As with conventional methods, the flowchart in Figure 1 shows the case where a SiC bulk substrate is prepared. If a SiC epitaxial substrate is prepared, steps S2 to S6 become unnecessary, and step S1 becomes the process of preparing the SiC epitaxial substrate.

[0029] As shown in Figure 1, first, a SiC bulk substrate is prepared (Step S1). Next, CMP processing is performed on the SiC bulk substrate (Step S2). For example, CMP processing is performed on the Si surface, which is the epitaxial growth surface. Next, the SiC bulk substrate is cleaned (Step S3). For example, pure water ultrasonic cleaning, organic solvent ultrasonic cleaning, SPM cleaning, and RCA cleaning are performed to ensure the Si surface is sufficiently clean.

[0030] Next, the SiC bulk substrate is inspected (step S4). For example, the Si surface is inspected by differential interference contrast observation using an optical microscope. Next, the SiC bulk substrate is cleaned (step S5). As in step S3, the Si surface is thoroughly cleaned. Note that if the substrate is commercially available and has already undergone CMP processing and final cleaning, steps S2 to S5 can be omitted.

[0031] Next, an epitaxial layer is grown on the SiC bulk substrate (step S6). For example, the SiC bulk substrate is set on a susceptor in the chamber of the epitaxial growth apparatus, and an epitaxial layer made of SiC is grown on the Si surface. Next, a first inspection of the SiC epitaxial substrate is performed (step S7). In the first inspection, the Si surface is inspected by differential interference contrast observation and photoluminescence imaging. Next, the back surface of the SiC epitaxial substrate is polished (step S8: seventh step). For example, by polishing the SiC epitaxial substrate from the back side, the surface roughness of the back surface of the SiC epitaxial substrate is set to Ra (arithmetic mean roughness) < 3 nm. More preferably, Ra < 0.3 nm. Next, the SiC epitaxial substrate is cleaned (step S9). For example, similar to step S3, the Si surface is thoroughly cleaned by pure water ultrasonic cleaning, organic solvent ultrasonic cleaning, SPM cleaning, and RCA cleaning.

[0032] Next, a second inspection of the SiC epitaxial substrate is performed (step S10). In the second inspection, the Si surface is inspected by transmitted polarized light observation. Figure 2 is a flowchart showing the determination of crystal defects in the silicon carbide semiconductor substrate inspection method according to this embodiment. Figure 2 illustrates the details of the first and second inspections.

[0033] First, assume that a crystal defect (surface defect) is detected on the surface by differential interference contrast observation in the first inspection (Step S11). The surface defect is observed by differential interference contrast observation as in the conventional manner, as shown in Figure 10. Next, it is determined whether this defect is a diagonal defect by differential interference contrast observation in the first inspection (Step S12: First step). As shown in Figure 10, a diagonal defect is a defect that grows at an angle within the epitaxial layer and occurs at the edge of a flank-type stacking fault. If it is determined that it is not a diagonal defect (Step S12: No), then this defect is determined to be another epitaxial growth defect (epit defect) (Step S14).

[0034] Next, if it is determined to be a diagonal defect (Step S12: Yes), the photoluminescence image from the first inspection is used to determine whether this diagonal defect is accompanied by a stacking fault (SF) (Step S13: Second step). The photoluminescence image is observed as in the conventional manner, as shown in Figure 11. As shown in Figure 11, a diagonal defect accompanied by a stacking fault is a defect that grows in a trapezoidal shape within the epitaxial layer. If it is determined that there is no stacking fault (Step S13: No), then this diagonal defect is determined to be a diagonal defect without a stacking fault (Step S16).

[0035] Next, if it is determined that the defect is a diagonal defect accompanied by a stacking fault (Step S13: Yes), the second inspection, transmitted polarized light observation, is used to determine whether the diagonal defect is accompanied by a threading screw dislocation (TSD) (Step S15: Third step). Here, a threading screw dislocation is a crystal defect in which the dislocation line is parallel to the Burgers vector (b) which indicates the direction of crystal displacement, and is called a threading screw dislocation because the atomic planes are arranged spirally around the dislocation line. In the case of a hexagonal crystal, a threading screw dislocation that penetrates the c-plane is called a threading screw dislocation.

[0036] Figure 3 is a schematic diagram showing a transmitted polarization image of a diagonal defect in the silicon carbide semiconductor substrate inspection method according to the embodiment. The substrate was inverted and linearly polarized light was incident from the Si side, and the image was captured from the C side with a digital camera, so the left and right sides are reversed compared to Figure 4. In this transmitted polarization image, it can be confirmed that there is a through-helical dislocation at the starting point 62 of the diagonal defect 61 in the area indicated by the dotted circle in the figure. The area indicated by the dotted trapezoid in the figure is a stacking fault 60 that has grown in a trapezoidal shape.

[0037] Figure 4 is a schematic diagram of a synchrotron X-ray topography image of a diagonal defect in the silicon carbide semiconductor substrate inspection method according to the embodiment. As shown in Figure 4, the presence of a through-helix dislocation at the starting point 62 of the diagonal defect 61 can also be identified by the synchrotron X-ray topography image at the position of the dotted circle in Figure 4.

[0038] If it is determined here that the defect is a diagonal defect accompanied by a through-helical dislocation (Step S15: Yes), then this diagonal defect can be determined to be either (1) a flank-type SF converted from a through-helical dislocation or (2) a flank-type or Shockley-type SF that occurred simultaneously with a through-helical dislocation (Step S17). Since these defects do not affect the operation of the device, if only these defects are present, the product can be determined to be good, thereby improving the product yield.

[0039] On the other hand, if it is determined that the defect is not a diagonal defect accompanied by a through-helical dislocation (Step S15: No), then the defect can be determined to be either (3) a defect in which SF from the SiC bulk substrate has propagated into the SiC epitaxial film, or (4) a diagonal defect caused by 3C inclusions or foreign matter contamination (Step S18). Defect (4) is detrimental to device operation and should be excluded from the product. In the case of defective products due to 3C inclusions or foreign matter contamination, the defect determination may also be made after considering the nature of the electrical characteristic defects such as leakage current and withstand voltage.

[0040] In the embodiment, the location information used to identify the location of the defect does not include information about diagonal defects accompanied by through-helix dislocations, or information that can distinguish between diagonal defects accompanied by through-helix dislocations and diagonal defects without through-helix dislocations is recorded (fourth step). For example, the location of the defect may be obtained based on a location identification mark for identifying the position (coordinates) in a direction parallel to the surface of the semiconductor substrate, and the location information may be recorded on the silicon carbide semiconductor substrate by laser marking or etching. Alternatively, the location information may be recorded on a computer-readable recording medium such as a solid-state drive (SSD), hard disk drive (HDD), Blu-ray disc (BD), floppy disk, universal serial bus flash memory (USB), compact disc (CD), magneto-optical disk (MO), or digital versatile disc (DVD). This allows for an improvement in product yield by forming a semiconductor structure on a silicon carbide semiconductor substrate, then dicing the silicon carbide semiconductor substrate to create individual silicon carbide semiconductor devices (cutting process), and then determining, based on this positional information, that silicon carbide semiconductor devices containing only diagonal defects accompanied by through-helical dislocations as crystal defects and free from other device-killer defects are good products (determination process).

[0041] Figure 5 is a schematic diagram of the differential interference pattern of micropipe defects contained in a silicon carbide semiconductor substrate using a conventional inspection method for silicon carbide semiconductor substrates. Figure 5 shows a schematic diagram of a blocked micropipe defect 163, which was identified as a pit in differential interference observation, identified as having no SF in PL imaging, and classified as an epitaxial defect that does not affect device operation, as an example of misidentification.

[0042] Figure 6 is a schematic diagram showing a transmitted polarization image of a micropipe defect in the silicon carbide semiconductor substrate inspection method according to the embodiment. Since the second inspection of the embodiment is performed by observing transmitted polarization, optical distortion due to internal stress caused by the micropipe defect 63 can be detected and determined to be a blocked micropipe defect 63 (5th step), and products having this defect can be excluded from the products to be excluded. For example, the location of the blocked micropipe defect 63 is recorded in the location information that identifies the location of the defect (6th step), and after the silicon carbide semiconductor device is pieced together, the silicon carbide semiconductor device containing the blocked micropipe defect 63 is determined based on this location information. Based on this determination, the silicon carbide semiconductor device containing the blocked micropipe defect 63 may be considered a good product. Alternatively, if the leakage current increases in the blocked micropipe defect area and problems arise in long-term reliability, the silicon carbide semiconductor device containing the blocked micropipe defect 63 may be considered a defective product.

[0043] Furthermore, the silicon carbide semiconductor substrate according to the embodiment is a SiC epitaxial substrate in which epitaxial layers made of SiC are stacked, and is inspected by the above inspection method and has positional information that identifies the location of crystal defects in the epitaxial layer. This positional information does not include information on diagonal defects accompanied by through-helix dislocations, or it is possible to distinguish between diagonal defects accompanied by through-helix dislocations and diagonal defects without through-helix dislocations, and may also include information that identifies the location of blocked micropipe defects.

[0044] (Silicon carbide semiconductor device according to an embodiment) The silicon carbide semiconductor device includes a Schottky barrier diode, a PiN (P-intrinsic-N) diode, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: insulated gate field effect transistor), a SJ (Super Junction)-MOSFET, an IGBT (Insulated Gate Bipolar Transistor: insulated gate bipolar transistor), etc., using this single crystal 4H-SiC epitaxial substrate. FIG. 7 is a cross-sectional view showing the configuration of the semiconductor device according to the embodiment. Regarding the structure of the semiconductor device according to the embodiment, the trench type MOSFET 50 will be described as an example.

[0045] The trench type MOSFET 50 is a trench gate MOSFET with a breakdown voltage of 1.2 kV formed on a 4H-SiC substrate. In the trench type MOSFET 50, on the front surface of the n-type starting substrate 1 which is a 4H-SiC substrate, a first n-type silicon carbide epitaxial layer 2 is deposited. + On the surface side opposite to the n-type starting substrate side 1 of the first n-type silicon carbide epitaxial layer 2, a second n-type silicon carbide layer 6 is provided. - On the surface side opposite to the n-type starting substrate side 1 of the first n-type silicon carbide epitaxial layer 2, a second n-type silicon carbide layer 6 is provided. - On the surface side opposite to the n-type starting substrate side 1 of the first n-type silicon carbide epitaxial layer 2, a second n-type silicon carbide layer 6 is provided. + On the surface side opposite to the n-type starting substrate side 1 of the first n-type silicon carbide epitaxial layer 2, a second n-type silicon carbide layer 6 is provided. - On the surface side opposite to the n-type starting substrate side 1 of the first n-type silicon carbide epitaxial layer 2, a second n-type silicon carbide layer 6 is provided. - On the surface side opposite to the n-type starting substrate side 1 of the first n-type silicon carbide epitaxial layer 2, a second n-type silicon carbide layer 6 is provided. + On the side opposite to the n-type starting substrate side 1 of the second n-type silicon carbide layer 6, a first p-type region 4 is selectively provided. + On the side opposite to the n-type starting substrate side 1 of the second n-type silicon carbide layer 6, a first p-type region 4 is selectively provided. - On the second n-type silicon carbide layer 6, a second p-type region 5 is selectively provided so as to cover the entire bottom surface of the trench 18. + On the second n-type silicon carbide layer 6, a second p-type region 5 is selectively provided so as to cover the entire bottom surface of the trench 18.

[0046] In addition, the trench type MOSFET 50 further includes a p-type base layer 3, an n-type source region 7, a p-type contact region 8, a gate insulating film 9, a gate electrode 10, an interlayer insulating film 11, an ohmic electrode 13, a back surface electrode 14, a source electrode pad 15, and a drain electrode pad (not shown). The ohmic electrode 13 is connected to the n-type source region 7, the p-type + type source region 7, the p ++ type contact region 8, the gate insulating film 9, the gate electrode 10, the interlayer insulating film 11, the ohmic electrode 13, the back surface electrode 14, the source electrode pad 15, and a drain electrode pad (not shown). The ohmic electrode 13 is connected to the n-type source region 7, the p + type source region 7, the p ++A source electrode pad 15 is provided on the ohmic electrode 13, which is located on the contact area 8.

[0047] Furthermore, a barrier metal (not shown) is provided between the ohmic electrode 13 and the interlayer insulating film 11 and the source electrode pad 15 to prevent the diffusion of metal atoms, for example, from the ohmic electrode 13 to the gate electrode 10 side.

[0048] In the silicon carbide semiconductor device according to the embodiment, n + On the front surface of the mold starting substrate 1, the first n - The silicon carbide semiconductor substrate on which the silicon carbide epitaxial layer 2 is deposited has been inspected using the above inspection method, and is judged as good if it contains only diagonal defects accompanied by through-helical dislocations. Therefore, this silicon carbide semiconductor substrate contains diagonal defects accompanied by through-helical dislocations. Furthermore, this silicon carbide semiconductor substrate judged as good is assumed to be free from diagonal defects without through-helical dislocations and other device killer defects.

[0049] Furthermore, the silicon carbide semiconductor device according to the embodiment can be manufactured by forming a front surface structure and surface electrodes on the front surface of a silicon carbide semiconductor substrate inspected by the inspection method described above, using a general method, and forming back surface electrodes on the back surface. In the case of MOSFETs and IGBTs, the front surface structure includes a MOS structure, and in the case of IGBTs, the back surface structure is formed on the back surface of the silicon carbide semiconductor substrate.

[0050] After forming element structures such as the front surface structure and back surface structure, and electrodes such as the front electrodes and back electrodes, the silicon carbide semiconductor substrate is diced to separate it into individual silicon carbide semiconductor devices, and silicon carbide semiconductor devices containing crystal defects in the silicon carbide semiconductor substrate are deemed defective. In this case, in the silicon carbide semiconductor device manufacturing method of the embodiment, based on positional information that identifies the location of crystal defects, a silicon carbide semiconductor device that contains only diagonal defects determined to be accompanied by through-helix dislocations and does not contain other device killer defects is judged to be a good product.

[0051] For example, by recording diagonal defects determined not to involve through-helix dislocations in the location information, and not recording diagonal defects determined to involve through-helix dislocations, a silicon carbide semiconductor device that contains only diagonal defects determined to involve through-helix dislocations and does not contain other device killer defects can be judged as a good product. Furthermore, by recording in the location information in a way that distinguishes between diagonal defects determined to involve through-helix dislocations and defects determined not to involve through-helix dislocations, a silicon carbide semiconductor device that contains only diagonal defects determined to involve through-helix dislocations and does not contain other device killer defects can also be judged as a good product.

[0052] Furthermore, this positional information records the location of micropipe defects that are blocked by the epitaxial layer, allowing us to determine whether a silicon carbide semiconductor device containing these micropipe defects is a good or defective product.

[0053] As described above, according to the embodiment, diagonal defects accompanied by through-helical dislocations and diagonal defects without through-helical dislocations are determined by transmitted polarized light observation. As a result, since diagonal defects accompanied by through-helical dislocations do not affect device operation, if only these defects are present, the product can be judged as good, thereby improving product yield.

[0054] In summary, this disclosure is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit of this disclosure. Furthermore, the type of semiconductor (e.g., silicon carbide (SiC)), the surface orientation of the main surface of the substrate, etc., can be modified in various ways. Also, in this disclosure, the first conductivity type is n-type and the second conductivity type is p-type in each embodiment, but this disclosure also holds true if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial applicability]

[0055] As described above, the silicon carbide semiconductor substrate, silicon carbide semiconductor device, inspection method for silicon carbide semiconductor substrate, and manufacturing method for silicon carbide semiconductor device according to this disclosure are useful for SJ structure power semiconductor devices used in power converters, power supply devices for various industrial machines, and the like. [Explanation of Symbols]

[0056] 1 n + Mold starting substrate 2 1stn - Silicon carbide epitaxial layer 3. p-type base layer 4 1st p. + type area 5 2nd p. + type area 6 2nd n - mold silicon carbide layer 7 n + Type source area 8 p ++ Type Contact Area 9 Gate insulating film 10 Guard Station 11 Interlayer insulating film 13 Ohmic electrodes 14 Backside electrode 15 Source electrode pads 18 Trench 50 Trench-type MOSFETs 160 Epitaxial Growth Defects 61 Diagonal Defect 63,163 Micropipe Defects 161 SiC bulk substrate 162 Epitaxial layer

Claims

1. A silicon carbide semiconductor substrate having an epitaxial layer, The silicon carbide semiconductor substrate is divided into sections, with separate positions for the first and second criterion components of the silicon carbide semiconductor device formed by fractionating the components. The location of the first determined sample includes stacking faults that have grown trapezoidally within the epitaxial layer with a through-helical dislocation at their origin, and stacking faults that have grown trapezoidally within the epitaxial layer with a through-helical dislocation at their origin, among stacking faults that have grown trapezoidally within the epitaxial layer without a through-helical dislocation at their origin, The silicon carbide semiconductor substrate is characterized in that the location of the second judged product includes stacking faults that have grown in a trapezoidal shape within the epitaxial layer accompanied by a through-helical dislocation at their origin, and stacking faults that have grown in a trapezoidal shape within the epitaxial layer without a through-helical dislocation at their origin.

2. A vertical silicon carbide semiconductor device comprising electrodes on both main surfaces of a silicon carbide semiconductor substrate having an epitaxial layer, The silicon carbide semiconductor device is characterized in that the silicon carbide semiconductor substrate has stacking faults that grow in a trapezoidal shape within the epitaxial layer accompanied by through-helical dislocations at their starting points, and stacking faults that grow in a trapezoidal shape within the epitaxial layer without through-helical dislocations at their starting points, among which stacking faults grow in a trapezoidal shape within the epitaxial layer accompanied by through-helical dislocations at their starting points.

3. A method for inspecting a silicon carbide semiconductor substrate having an epitaxial layer, A first step involves determining whether the crystal defects in the silicon carbide semiconductor substrate are defects that grew obliquely within the epitaxial layer by differential interference observation of the silicon carbide semiconductor substrate. A second step involves determining from the photoluminescence image of the silicon carbide semiconductor substrate whether the defect is a stacking fault that has grown trapezoidally within the epitaxial layer, A third step involves determining whether the stacking fault originates from a through-helic dislocation by observing the transmitted polarized light of the silicon carbide semiconductor substrate. A method for inspecting a silicon carbide semiconductor substrate, characterized by including the following:

4. A fourth step involves detecting micropipe defects that are blocked by the epitaxial layer by observing the transmitted polarized light of the silicon carbide semiconductor substrate, The method for inspecting a silicon carbide semiconductor substrate according to claim 3, further comprising the above.

5. The method for inspecting a silicon carbide semiconductor substrate according to claim 3, characterized in that the silicon carbide semiconductor substrate is a single crystal 4H-SiC substrate.

6. After the second step, and before the third step, The method for inspecting a silicon carbide semiconductor substrate according to claim 3, further comprising a fifth step of polishing the back surface of the silicon carbide semiconductor substrate to make the surface of the back surface of the silicon carbide semiconductor substrate have a roughness Ra (arithmetic mean roughness) of < 3 nm.

7. A method for manufacturing a vertical silicon carbide semiconductor device, comprising electrodes on both main surfaces of a silicon carbide semiconductor substrate having an epitaxial layer, A first step involves determining whether the crystal defects in the silicon carbide semiconductor substrate are defects that grew obliquely within the epitaxial layer by differential interference observation of the silicon carbide semiconductor substrate. A second step involves determining from the photoluminescence image of the silicon carbide semiconductor substrate whether the defect is a stacking fault that has grown trapezoidally within the epitaxial layer, A third step involves determining whether the stacking fault originates from a through-helic dislocation by observing the transmitted polarized light of the silicon carbide semiconductor substrate. A forming step of forming a predetermined device structure on the silicon carbide semiconductor substrate, After the forming step, a cutting step is performed in which the silicon carbide semiconductor substrate is diced to form individual silicon carbide semiconductor devices. A sorting step for selecting a first judged silicon carbide semiconductor device based on the first to third steps, A method for manufacturing a silicon carbide semiconductor device, characterized by including the following:

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