Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor capable of suppressing electric field concentration. [Solution] The laminate 10 has a plurality of dielectric layers 20 and a plurality of internal electrode layers 30, and first and second external electrodes 40A and 40B, wherein the plurality of internal electrode layers 30 have a plurality of first and second internal electrode layers 31 and 32 that are electrically connected to the first and second external electrodes 40A and 40B respectively, and the first and second internal electrode layers 31 and 32 have a plurality of holes H with different area equivalent diameters, and the area equivalent diameter D99 is defined as the area equivalent diameter at which the cumulative value in the cumulative distribution of the area equivalent diameters of the plurality of holes H becomes 99%, and when the thickness t of the dielectric layer 20 sandwiched between the first and second internal electrode layers 31 and 32 is defined as the thickness t of the dielectric layer 20 is 0.5 μm or more, and further satisfies the following formula (1). (Area equivalent diameter D99) < 0.0879 × exp(2.86 × t) ···(1)

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor.

Background Art

[0002] Conventionally, multilayer ceramic capacitors are known. Generally, a multilayer ceramic capacitor includes a laminate in which a plurality of dielectric layers and internal electrode layers are alternately laminated. Such a multilayer ceramic capacitor is used not only for small electronic devices such as smartphones with a low rated voltage, but also for in-vehicle applications with a relatively high rated voltage. When a multilayer ceramic capacitor is used for applications with a high rated voltage, ensuring high reliability when a voltage is applied is required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] For example, in Patent Document 1, when a dielectric layer with a thin thickness is used for high voltage, there is a risk of dielectric breakdown due to electric field concentration. On the other hand, increasing the distance between the internal electrode layers and further increasing the distance between the internal electrode layer and the surface of the capacitor element can achieve higher withstand voltage. Also, Patent Document 1 shows that by providing a plurality of auxiliary electrodes, electric field concentration can be suppressed and higher withstand voltage can be achieved. However, in Patent Document 1, the influence of the holes in the internal electrode layer on the electric field concentration of the multilayer ceramic capacitor is not considered.

[0005] An object of the present invention is to provide a multilayer ceramic capacitor capable of suppressing electric field concentration.

Means for Solving the Problems

[0006] The multilayer ceramic capacitor according to the present invention comprises a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, and a laminate having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and the width direction, and a first external electrode and a second external electrode, wherein the plurality of internal electrode layers are electrically connected to the first external electrode. The dielectric material comprises a plurality of successive first internal electrode layers and a plurality of second internal electrode layers electrically connected to the second external electrode, wherein the first internal electrode layer and the second internal electrode layer have a plurality of holes with different area equivalent diameters, and the area equivalent diameter D99 is defined as the area equivalent diameter at which the cumulative value in the cumulative distribution of the area equivalent diameters of the plurality of holes becomes 99%, and when the thickness of the dielectric layer sandwiched between the first internal electrode layer and the second internal electrode layer is defined as thickness t, the thickness t of the dielectric layer is 0.5 μm or more, and further satisfies the following formula (1). (Area equivalent diameter D99) < 0.0879 × exp(2.86 × t) ···(1) [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can suppress electric field concentration. [Brief explanation of the drawing]

[0008] [Figure 1] This is an external perspective view of the multilayer ceramic capacitor of the embodiment. [Figure 2] Figure 1 is a cross-sectional view of the multilayer ceramic capacitor along the line II-II. [Figure 3] Figure 2 is a cross-sectional view of the multilayer ceramic capacitor along line III-III. [Figure 4A] Figure 2 is a cross-sectional view of a multilayer ceramic capacitor along the IVA-IVA line. [Figure 4B]Figure 2 is a cross-sectional view of the multilayer ceramic capacitor along the IVB-IVB line. [Figure 5] Figure 4A is an enlarged view of the V section of the multilayer ceramic capacitor 1 shown in Figure 4A. [Figure 6] This figure shows the area-equivalent diameter distribution data of multiple holes present in the internal electrode layer. [Figure 7A] This figure shows the model of the internal electrode layer used in the simulation. [Figure 7B] This figure shows the electric field strength distribution near the holes in the internal electrode layer. [Figure 8] This graph plots the maximum electric field strength within each simulation model, calculated by varying the value of D99, which is the equivalent area diameter of holes in the internal electrode layer. [Figure 9] This graph plots the maximum electric field strength within each simulation model, calculated by varying the thickness of the dielectric layer and the value of D99, which represents the equivalent area diameter of holes in the internal electrode layer. [Figure 10] This graph shows the region where electric field concentration can be suppressed when voltage is applied. [Figure 11] This figure illustrates a method for measuring the thickness of the internal electrode layer and dielectric layer, and shows an example of a magnified image of the exposed effective layer cross-section of a multilayer ceramic capacitor observed by SEM. [Figure 12] This is an SEM image corresponding to the magnified view of section XII of the multilayer ceramic capacitor shown in Figure 3, and it shows the burn state of the laminate at the time of dielectric breakdown during accelerated life testing. [Modes for carrying out the invention]

[0009] Hereinafter, the multilayer ceramic capacitor 1 according to an embodiment of the present disclosure will be described. FIG. 1 is an external perspective view of the multilayer ceramic capacitor 1 of the present embodiment. FIG. 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor 1 in FIG. 1. FIG. 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor 1 in FIG. 2. FIG. 4A is a cross-sectional view taken along line IVA-IVA of the multilayer ceramic capacitor 1 in FIG. 2. FIG. 4B is a cross-sectional view taken along line IVB-IVB of the multilayer ceramic capacitor 1 in FIG. 2.

[0010] The multilayer ceramic capacitor 1 includes a laminate 10 and external electrodes 40.

[0011] In FIGS. 1 to 4B, an XYZ orthogonal coordinate system is shown. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The height direction T of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross-section shown in FIG. 2 is also referred to as an LT cross-section. The cross-section shown in FIG. 3 is also referred to as a WT cross-section. The cross-sections shown in FIGS. 4A and 4B are also referred to as LW cross-sections.

[0012] As shown in FIGS. 1 to 4B, the laminate 10 includes a first main surface TS1 and a second main surface TS2 that face each other in the height direction T, a first side surface WS1 and a second side surface WS2 that face each other in the width direction W orthogonal to the height direction T, and a first end surface LS1 and a second end surface LS2 that face each other in the length direction L orthogonal to the height direction T and the width direction W.

[0013] As shown in FIG. 1, the laminate 10 has a substantially rectangular parallelepiped shape. Note that the dimension in the length direction L of the laminate 10 is not necessarily longer than the dimension in the width direction W. It is preferable that the corners and ridge lines of the laminate 10 are rounded. A corner is a portion where three surfaces of the laminate meet, and a ridge line is a portion where two surfaces of the laminate meet. Note that irregularities or the like may be formed on a part or all of the surfaces constituting the laminate 10.

[0014] The dimensions of the laminate 10 are not particularly limited. However, when the dimension in the length direction L of the laminate 10 is defined as the L dimension, the L dimension is preferably 0.2 mm or more and 6 mm or less. Further, when the dimension in the height direction T of the laminate 10 is defined as the T dimension, the T dimension is preferably 0.05 mm or more and 5 mm or less. Further, when the dimension in the width direction W of the laminate 10 is defined as the W dimension, the W dimension is preferably 0.1 mm or more and 5 mm or less.

[0015] As shown in FIGS. 2 and 3, the laminate 10 includes an inner layer portion 11, and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 disposed so as to sandwich the inner layer portion 11 in the height direction T.

[0016] The inner layer portion 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30. The inner layer portion 11 includes from the internal electrode layer 30 located closest to the first main surface TS1 side to the internal electrode layer 30 located closest to the second main surface TS2 side in the height direction T. In the inner layer portion 11, a plurality of internal electrode layers 30 are disposed to face each other via the dielectric layer 20. The inner layer portion 11 is a portion that generates capacitance and functions substantially as a capacitor.

[0017] The plurality of dielectric layers 20 are made of a dielectric material. The dielectric material may be, for example, a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Further, the dielectric material may be one in which auxiliary components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds are added to these main components. The dielectric material is particularly preferably a material containing BaTiO3 as the main component.

[0018] The thickness of the dielectric layer 20 is preferably 0.5 μm or more. For example, the thickness t of the dielectric layer 20 may be 0.5 μm or more and 1.6 μm or less. The number of dielectric layers 20 to be laminated is preferably 15 or more and 1200 or less. Note that the number of these dielectric layers 20 is the total number of the number of dielectric layers in the inner layer portion 11 and the number of dielectric layers in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0019] The multiple internal electrode layers 30 have multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The multiple first internal electrode layers 31 are arranged on multiple dielectric layers 20. The multiple second internal electrode layers 32 are arranged on multiple dielectric layers 20. The multiple first internal electrode layers 31 and the multiple second internal electrode layers 32 are arranged alternately in the height direction T of the laminate 10 via the dielectric layers 20. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the dielectric layers 20.

[0020] The first internal electrode layer 31 has a first opposing portion 31A that faces the second internal electrode layer 32, and a first leading portion 31B that is drawn out from the first opposing portion 31A to the first end face LS1. The first leading portion 31B is exposed to the first end face LS1.

[0021] The second internal electrode layer 32 has a second opposing portion 32A that faces the first internal electrode layer 31, and a second leading portion 32B that is drawn out from the second opposing portion 32A to the second end face LS2. The second leading portion 32B is exposed to the second end face LS2.

[0022] In this embodiment, capacitance is formed when the first opposing portion 31A and the second opposing portion 32A face each other via the dielectric layer 20, and the characteristics of a capacitor are exhibited.

[0023] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle. The shapes of the first pull-out portion 31B and the second pull-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle.

[0024] The widthwise dimension W of the first opposing portion 31A and the widthwise dimension W of the first drawer portion 31B may be the same, or one of them may be smaller. The widthwise dimension W of the second opposing portion 32A and the widthwise dimension W of the second drawer portion 32B may be the same, or one of them may be narrower.

[0025] As shown in Figure 4A, the first internal electrode layer 31 has a first side WE1 on the first side WS1 side and a second side WE2 on the second side WS2 side. As shown in Figure 4B, the second internal electrode layer 32 has a third side WE3 on the first side WS1 side and a fourth side WE4 on the second side WS2 side.

[0026] The first internal electrode layer 31 and the second internal electrode layer 32 are made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals. When using an alloy, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0027] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 15 or more and 1000 or less.

[0028] The first main surface-side outer layer 12 is located on the first main surface TS1 side of the laminate 10. The first main surface-side outer layer 12 is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. The dielectric layers 20 used in the first main surface-side outer layer 12 may be the same as the dielectric layers 20 used in the inner layer 11.

[0029] The second main surface-side outer layer 13 is located on the second main surface TS2 side of the laminate 10. The second main surface-side outer layer 13 is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the second main surface-side outer layer 13 may be the same as the dielectric layers 20 used in the inner layer 11.

[0030] Thus, the laminate 10 has a plurality of stacked dielectric layers 20 and a plurality of internal electrode layers 30 stacked on the dielectric layers 20. In other words, the multilayer ceramic capacitor 1 has a laminate 10 in which the dielectric layers 20 and internal electrode layers 30 are stacked alternately.

[0031] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is the portion where the first counter portion 31A of the first internal electrode layer 31 and the second counter portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as part of the inner layer portion 11. Figures 4A and 4B show the width W and length L ranges of the counter electrode portion 11E. The counter electrode portion 11E is also called the capacitor effective portion.

[0032] The laminate 10 has a side outer layer. The side outer layer has a first side outer layer WG1 and a second side outer layer WG2. The first side outer layer WG1 is the portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the first side WS1. The second side outer layer WG2 is the portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the second side WS2. Figures 3, 4A, and 4B show the widthwise range W of the first side outer layer WG1 and the second side outer layer WG2. The side outer layer is also called the W gap or side gap.

[0033] The laminate 10 has an end-face outer layer. The end-face outer layer has a first end-face outer layer LG1 and a second end-face outer layer LG2. The first end-face outer layer LG1 is the portion that includes the dielectric layer 20 located between the opposing electrode portion 11E and the first end face LS1. The second end-face outer layer LG2 is the portion that includes the dielectric layer 20 located between the opposing electrode portion 11E and the second end face LS2. Figures 2, 4A, and 4B show the range L in the longitudinal direction of the first end-face outer layer LG1 and the second end-face outer layer LG2. The end-face outer layer is also called the L gap or end gap.

[0034] The external electrode 40 includes a first external electrode 40A positioned on the first end face LS1 side and a second external electrode 40B positioned on the second end face LS2 side.

[0035] The first external electrode 40A is positioned on the first end face LS1. The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed extending from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0036] The second external electrode 40B is positioned on the second end face LS2. The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed extending from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0037] As described above, within the laminate 10, capacitance is formed by the opposition of the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 via the dielectric layer 20. Therefore, capacitor characteristics are exhibited between the first external electrode 40A to which the first internal electrode layer 31 is connected and the second external electrode 40B to which the second internal electrode layer 32 is connected.

[0038] The first external electrode 40A includes a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A.

[0039] The second external electrode 40B includes a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B.

[0040] The first base electrode layer 50A is positioned on the first end face LS1. The first base electrode layer 50A is connected to the first internal electrode layer 31. In this embodiment, the first base electrode layer 50A is formed extending from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0041] The second base electrode layer 50B is positioned on the second end face LS2. The second base electrode layer 50B is connected to the second internal electrode layer 32. In this embodiment, the second base electrode layer 50B is formed extending from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0042] The first base electrode layer 50A and the second base electrode layer 50B in this embodiment are baked layers. The baked layers preferably contain a metal component and either a glass component or a ceramic component, or both. The metal component includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The glass component includes, for example, at least one selected from B, Si, Ba, Mg, Al, Li, etc. The ceramic component may be the same type of ceramic material as the dielectric layer 20, or a different type of ceramic material may be used. The ceramic component includes, for example, at least one selected from BaTiO3, CaTiO3, (Ba,Ca)TiO3, SrTiO3, CaZrO3, etc.

[0043] The baked layer is, for example, formed by applying a conductive paste containing glass and metal to a laminate and baking it. The baked layer may be formed by simultaneously firing a laminate chip having internal electrodes and a dielectric layer and the conductive paste applied to the laminate chip, or by firing a laminate chip having internal electrodes and a dielectric layer to obtain a laminate, and then applying the conductive paste to the laminate and baking it. When firing a laminate chip having internal electrodes and a dielectric layer and the conductive paste applied to the laminate chip simultaneously, it is preferable to form the baked layer by baking a material with a ceramic component added instead of glass. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. The baked layer may consist of multiple layers.

[0044] The longitudinal thickness of the first base electrode layer 50A located at the first end face LS1 is preferably, for example, 3 μm to 200 μm at the center of the height T and width W of the first base electrode layer 50A.

[0045] The longitudinal thickness of the second base electrode layer 50B located at the second end face LS2 is preferably, for example, 3 μm to 200 μm at the center of the height T and width W of the second base electrode layer 50B.

[0046] When the first base electrode layer 50A is provided on a part of at least one of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness of the first base electrode layer 50A in the height direction in this portion is, for example, 3 μm or more and 25 μm or less in the central part of the length direction L and width direction W of the first base electrode layer 50A provided in this portion.

[0047] When the first base electrode layer 50A is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the thickness of the first base electrode layer 50A in the width direction provided in this portion is preferably, for example, 3 μm or more and 25 μm or less at the center of the length direction L and height direction T of the first base electrode layer 50A provided in this portion.

[0048] When a second base electrode layer 50B is provided on at least one of the surfaces of the first main surface TS1 or the second main surface TS2, the thickness of the second base electrode layer 50B in the height direction provided in this portion is preferably, for example, 3 μm or more and 25 μm or less at the center of the length direction L and width direction W of the second base electrode layer 50B provided in this portion.

[0049] When a second base electrode layer 50B is provided on at least one of the surfaces of the first side surface WS1 or the second side surface WS2, it is preferable that the thickness of the second base electrode layer 50B in the width direction in this portion is, for example, 3 μm or more and 25 μm or less in the central part of the length direction L and height direction T of the second base electrode layer 50B provided in this portion.

[0050] The first base electrode layer 50A and the second base electrode layer 50B are not limited to baked layers. The first base electrode layer 50A and the second base electrode layer 50B include at least one selected from baked layers, conductive resin layers, thin film layers, etc. For example, the first base electrode layer 50A and the second base electrode layer 50B may be thin film layers. The thin film layer is formed by a thin film formation method such as sputtering or vapor deposition. The thin film layer is a layer of 10 μm or less in thickness on which metal particles are deposited.

[0051] The first plating layer 60A is positioned to cover the first underlay electrode layer 50A.

[0052] The second plating layer 60B is positioned to cover the second under electrode layer 50B.

[0053] The first plating layer 60A and the second plating layer 60B may each contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed by multiple layers. Preferably, the first plating layer 60A and the second plating layer 60B have a two-layer structure in which a Sn plating layer is formed on top of a Ni plating layer.

[0054] The first plating layer 60A is arranged to cover the first underlay electrode layer 50A. In this embodiment, the first plating layer 60A has a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0055] The second plating layer 60B is arranged to cover the second under electrode layer 50B. In this embodiment, the second plating layer 60B includes a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0056] The Ni plating layer prevents the first underlay electrode layer 50A and the second underlay electrode layer 50B from being corroded by the solder used when mounting the multilayer ceramic capacitor 1. The Sn plating layer also improves the wettability of the solder used when mounting the multilayer ceramic capacitor 1. This facilitates the mounting of the multilayer ceramic capacitor 1. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B, and the second Sn plating layer 62B is preferably between 2 μm and 10 μm.

[0057] In this embodiment, the first external electrode 40A and the second external electrode 40B may have, for example, a conductive resin layer containing conductive particles and a thermosetting resin. When a conductive resin layer is provided as a base electrode layer (first base electrode layer 50A, second base electrode layer 50B), the conductive resin layer may be arranged to cover the baking layer, or it may be placed directly on the laminate 10 without providing a baking layer. When the conductive resin layer is arranged to cover the baking layer, the conductive resin layer is placed between the baking layer and the plating layer (first plating layer 60A, second plating layer 60B). The conductive resin layer may completely cover the baking layer, or it may cover a part of the baking layer.

[0058] A conductive resin layer containing a thermosetting resin is more flexible than a conductive layer made of, for example, a plated film or a fired conductive paste. Therefore, even if the multilayer ceramic capacitor 1 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer. Thus, the conductive resin layer suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0059] The metal constituting the conductive particles may be Ag, Cu, Ni, Sn, Bi, or alloys containing these. The conductive particles preferably contain Ag. For example, the conductive particles are Ag metal powder. Ag is suitable as an electrode material because it has the lowest resistivity among metals. Furthermore, since Ag is a noble metal, it is resistant to oxidation and has high weather resistance. Therefore, Ag metal powder is suitable as conductive particles.

[0060] Furthermore, the conductive particles may be metal powder with an Ag coating on its surface. When using metal powder with an Ag coating on its surface, the metal powder is preferably Cu, Ni, Sn, Bi, or an alloy of these. It is preferable to use Ag-coated metal powder in order to maintain the properties of Ag while making the base metal inexpensive.

[0061] Furthermore, the conductive particles may be Cu or Ni that have been treated to prevent oxidation. Alternatively, the conductive particles may be metal powder coated with Sn, Ni, or Cu on the surface of the metal powder. When using metal powder coated with Sn, Ni, or Cu on the surface, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy of these.

[0062] The shape of the conductive particles is not particularly limited. Conductive particles can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical metal powder and flattened metal powder.

[0063] The conductive particles contained in the conductive resin layer primarily play a role in ensuring the conductivity of the conductive resin layer. Specifically, the contact between multiple conductive particles forms an electrical pathway within the conductive resin layer.

[0064] The resin constituting the conductive resin layer may include at least one selected from various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, it is preferable that the resin in the conductive resin layer includes a curing agent together with the thermosetting resin. When epoxy resin is used as the base resin, the curing agent for the epoxy resin may be various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0065] The conductive resin layer may be formed from multiple layers. The thickness of the thickest part of the conductive resin layer is preferably 10 μm or more and 150 μm or less.

[0066] Furthermore, the first and second base electrode layers 50A and 50B may be omitted, and the first and second plating layers 60A and 50B described later may be directly placed on the laminate 10. In other words, the multilayer ceramic capacitor 1 may include a plating layer that is directly electrically connected to the first internal electrode layer 31 and the second internal electrode layer 32. In such a case, the plating layer may be formed after a catalyst is placed on the surface of the laminate 10 as a pretreatment.

[0067] In this case as well, it is preferable that the plating layer consists of multiple layers. The lower plating layer and the upper plating layer each preferably contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing these metals. The lower plating layer is more preferably formed using Ni, which has solder barrier properties. The upper plating layer is more preferably formed using Sn or Au, which has good solder wettability. For example, if the first internal electrode layer 31 and the second internal electrode layer 32 are formed using Ni, it is preferable that the lower plating layer be formed using Cu, which has good bonding properties with Ni. The upper plating layer may be formed as needed, and the external electrode 40 may consist only of the lower plating layer. Furthermore, the upper plating layer may be the outermost layer, or other plating layers may be formed on the surface of the upper plating layer.

[0068] The thickness of each plating layer, when placed without an undercoat electrode layer, is preferably 2 μm to 10 μm. Furthermore, the plating layer preferably does not contain glass. The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0069] Furthermore, when the plating layer is formed directly on the laminate 10, the thickness of the base electrode layer can be reduced. Therefore, by reducing the thickness of the base electrode layer, the height T dimension of the multilayer ceramic capacitor 1 can be reduced, thereby making the multilayer ceramic capacitor 1 lower profile. Alternatively, by reducing the thickness of the base electrode layer, the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 can be increased, thereby improving the overall thickness. In this way, by forming the plating layer directly on the laminate 10, the design flexibility of the multilayer ceramic capacitor can be improved.

[0070] Furthermore, if the lengthwise dimension of the multilayer ceramic capacitor 1, including the laminated body 10 and the external electrodes 40, is denoted as dimension L, then it is preferable that dimension L is between 0.2 mm and 6 mm. Also, if the heightwise dimension of the multilayer ceramic capacitor 1, is denoted as dimension T, then it is preferable that dimension T is between 0.05 mm and 5 mm. Furthermore, if the widthwise dimension of the multilayer ceramic capacitor 1, is denoted as dimension W, then it is preferable that dimension W is between 0.1 mm and 5 mm.

[0071] Here, through a series of studies, experiments, and simulations, the inventors of this application have found that, in order to improve the reliability of multilayer ceramic capacitors, it is desirable to ensure that the holes in the internal electrode layer are in an appropriate state. This point will be explained below.

[0072] Conventionally, various methods have been employed to improve the reliability of multilayer ceramic capacitors. For example, Patent Document 1 discloses a multilayer ceramic capacitor comprising a laminate in which dielectric layers and internal electrode layers are alternately stacked, and a plurality of auxiliary electrodes. In the multilayer ceramic capacitor of Patent Document 1, electric field concentration is suppressed by having a plurality of auxiliary electrodes, thereby improving the reliability of the product. However, Patent Document 1 did not consider the effect that holes in the internal electrode layer have on the reliability of the multilayer ceramic capacitor. Therefore, additional components such as auxiliary electrodes were required.

[0073] Considering the above, the inventors of the present invention diligently studied the configuration of an internal electrode layer that can ensure basic dielectric strength by securing the thickness of the dielectric layer, and further suppress electric field concentration to improve reliability when voltage is applied. As a result, the inventors of the present invention have found that by adopting the configuration of this embodiment, electric field concentration can be suppressed and reliability when voltage is applied can be improved.

[0074] Specifically, the inventors of this invention discovered that when dielectric breakdown occurs in a multilayer ceramic capacitor, the burnout starts at the location where holes exist in the internal electrode layer. Furthermore, the inventors found that by adjusting the size of the area equivalent diameter D99 of multiple holes in the internal electrode layer (described later), it is possible to suppress electric field concentration even when a relatively high voltage is applied.

[0075] More specifically, the inventors of the present invention have found that by ensuring the thickness of the dielectric layer 20, it is possible to secure basic dielectric strength and suppress electric field concentration when a voltage is applied, by setting the area equivalent diameter D99 to the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of a plurality of holes H present in the first internal electrode layer 31 and the second internal electrode layer 32 becomes 99%, and the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 to be thickness t, and further satisfying the following equation (1). (Area equivalent diameter D99) < 0.0879 × exp(2.86 × t) ···(1)

[0076] The dielectric layer 20 and the internal electrode layer 30 of this embodiment will be described in detail below.

[0077] Figure 5 is an enlarged view of section V of the multilayer ceramic capacitor 1 shown in Figure 4A, illustrating the state of the first internal electrode layer 31 as the internal electrode layer 30. More specifically, Figure 5 is a view of the internal electrode layer 30 in the WT cross-section of the multilayer ceramic capacitor 1 of this embodiment, as seen in the height direction T connecting the first main surface TS1 and the second main surface TS2, i.e., a plan view. Note that the covering state of the first internal electrode layer 31 on the dielectric layer 20 and the covering state of the second internal electrode layer 32 on the dielectric layer 20 are basically the same when viewed in the height direction T connecting the first main surface TS1 and the second main surface TS2. Therefore, in the following description, the first internal electrode layer 31 and the second internal electrode layer 32 will be described together as the internal electrode layer 30 as needed.

[0078] Figure 5 shows the internal electrode layer 30 near the first edge WE1, which is an edge of the internal electrode layer 30. As shown in Figure 5, the internal electrode layer 30 has multiple holes H with different area equivalent diameters. The thickness of the internal electrode layer 30 shown in Figure 5 is 0.6 μm, and the coverage of the internal electrode layer over the dielectric layer 20 is 81%. The inside of the holes H in the internal electrode layer 30 may be voids, or it may contain dielectric or glass components such as silica. If the inside of the holes H in the internal electrode layer 30 is voids, the dielectric layer 20 can be seen through the holes H. The thickness of the dielectric layer 20 sandwiched between the two internal electrode layers 30 (the first internal electrode layer 31 and the second internal electrode layer 32) is 1.4 μm.

[0079] Figure 6 shows the area-equivalent diameter distribution data for multiple holes H present in the internal electrode layer 30. Figure 6 also shows the cumulative percentage relative to the area-equivalent diameter. The horizontal axis of Figure 6 represents the area-equivalent diameter of the hole H, and the vertical axis represents the cumulative percentage obtained by dividing the number of holes H with an area-equivalent diameter or less (the cumulative number of holes H) by the total number (the number of holes H forming the population). In other words, the area-equivalent diameter distribution data shown in Figure 6 is area-equivalent diameter distribution data based on the number of holes. Note that the data in Figure 6 is area-equivalent diameter distribution data in the measurement target area near the edge of the internal electrode layer 30, and the data is based on a population of holes H present in a wider area than the area shown in Figure 5.

[0080] In the multilayer ceramic capacitor 1 of this embodiment, the area equivalent diameter D99 is defined as the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the multiple holes H present in the first internal electrode layer 31 and the second internal electrode layer 32 reaches 99%. When the thickness t of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 is defined as the thickness t of the dielectric layer 20, the thickness t of the dielectric layer 20 is 0.5 μm or more, and furthermore, the following equation (1) is satisfied. Note that the units of the area equivalent diameter D99 and the thickness t of the dielectric layer 20 are expressed in the same unit, for example, "μm". (Area equivalent diameter D99) < 0.0879 × exp(2.86 × t) ···(1)

[0081] In the example of area-equivalent diameter distribution data shown in Figure 6, the area-equivalent diameter D99 is 4.7 μm. This is smaller than the value of 4.8 μm obtained by substituting 1.4 μm for the thickness t on the right-hand side of equation (1). That is, in the example where the thickness t of the dielectric layer 20 is 1.4 μm and the area-equivalent diameter distribution data of the internal electrode layer 30 is the data shown in Figure 6, the thickness t of the dielectric layer 20 is 0.5 μm or more, and equation (1) is satisfied. With such a configuration, electric field concentration can be suppressed and reliability during voltage application can be improved.

[0082] The area equivalent diameter is the diameter of a perfect circle that has an area equal to the area of ​​hole H as defined by the contour of hole H. For example, if the area of ​​hole H as defined by the contour of hole H is 50 μm²2 In this case, the area equivalent diameter is 8.0 μm.

[0083] As mentioned above, the area equivalent diameter D99 is the area equivalent diameter at which the cumulative value in the cumulative distribution of the area equivalent diameters of multiple holes H becomes 99%. In other words, the area equivalent diameter D99 is defined as the value at which the proportion of holes H with an area equivalent diameter of 99% or less becomes 99%.

[0084] Next, we will explain how the above-mentioned effects can be obtained using simulations.

[0085] Figure 7A shows the model of the internal electrode layer 30 used in the simulation. In this model, the internal electrode layer 30 is provided on the dielectric layer 20. Also, in this model, as shown in Figure 7A, multiple holes H are arranged randomly. Furthermore, the area equivalent diameter of the multiple holes H varies. In addition, in this model, an internal electrode layer 30 with multiple holes H arranged randomly is also provided on the back side of the dielectric layer 20, similar to the front side.

[0086] Multilayer ceramic capacitors are used in small electronic devices such as smartphones with low rated voltages, as well as in automotive applications with relatively high rated voltages. When multilayer ceramic capacitors are used in applications with high rated voltages, it is necessary to ensure high reliability when relatively high voltages are applied. In order to ensure dielectric breakdown voltage with the basic configuration of a multilayer ceramic capacitor, it is preferable to ensure the thickness of the dielectric layer 20 sandwiched between the two internal electrode layers 30 (the first internal electrode layer 31 and the second internal electrode layer 32). In this simulation, the thickness t of the dielectric layer 20 was first set to 1.0 μm.

[0087] Furthermore, in automotive applications, for example, multilayer ceramic capacitors with relatively higher rated voltages than those used in smartphones, etc., such as multilayer ceramic capacitors with a rated voltage of around 25V, are often used. Therefore, in this simulation, the applied voltage was set to 25V. In the simulation, a voltage is applied between the internal electrode layer 30 on the front side and the internal electrode layer 30 on the back side, sandwiching the dielectric layer 20.

[0088] Furthermore, in this simulation, the thickness of the internal electrode layer 30 was set to 0.6 μm, and the coverage of the internal electrode layer 30 over the dielectric layer 20 was set to 88%. In addition, in this simulation, first, multiple holes H were set in the internal electrode layer 30 so that the area equivalent diameter D99 was 2.0 μm.

[0089] When simulations were performed under these settings, a tendency for the electric field to concentrate around the contour of hole H was observed. Figure 7B shows the distribution of electric field strength near hole H. In Figure 7B, the electric field strength is shown in grayscale, with lighter colors indicating areas with higher electric field strength. From Figure 7B, it can be seen that the electric field is concentrated around the contour of hole H. Furthermore, a tendency for the electric field to concentrate around the contour of a relatively large hole H, as shown on the left side of Figure 7B, is observed compared to the contour of a relatively small hole H, as shown on the right side of Figure 7B.

[0090] Next, the electric field strength generated in each model was calculated using models with varying values ​​for the area-equivalent diameter D99. Specifically, additional models were created with the area-equivalent diameter D99 set to 1.0 μm, 1.5 μm, and 4.0 μm, and the electric field strength generated within each model was calculated. The thickness of the internal electrode layer 30, the coverage of the internal electrode layer 30 over the dielectric layer 20, the thickness of the dielectric layer 20, and the applied voltage were set to constant values ​​for the simulation. Figure 8 is a graph showing the results. The horizontal axis (x-axis) in Figure 8 represents the value of the area-equivalent diameter D99 in the model, and the vertical axis (y-axis) represents the maximum electric field strength within the model. Figure 8 also shows the approximate curve obtained by fitting the plotted points.

[0091] Figure 8 confirms that the smaller the area-equivalent diameter D99, the more the electric field concentration tends to be suppressed. Furthermore, the approximation curve in Figure 8 shows that when the thickness t of the dielectric layer 20 is 1.0 μm, if the area-equivalent diameter D99 of the multiple holes H in the internal electrode layer 30 is less than approximately 1.6 μm, the maximum electric field strength generated within the model falls below 72 MV / m, confirming that electric field concentration is suppressed. This maximum electric field strength value is acceptable for ensuring the reliability of the multilayer ceramic capacitor.

[0092] Next, simulations were performed to calculate the electric field strength by varying the thickness t of the dielectric layer 20. Specifically, the electric field strength was calculated in models where the equivalent area diameter D99 was set to 1.0 μm, 1.5 μm, and 2.0 μm when the thickness t of the dielectric layer 20 was 0.75 μm. In addition, the electric field strength was calculated in models where the equivalent area diameter D99 was set to 1.0 μm, 2.0 μm, and 4.0 μm when the thickness t of the dielectric layer 20 was 1.25 μm and 1.4 μm, respectively. The simulations were performed with the thickness of the internal electrode layer 30, the coverage of the internal electrode layer 30 over the dielectric layer 20, the thickness of the dielectric layer 20, and the applied voltage set to constant values.

[0093] Figure 9 is a graph showing the results. The horizontal axis (x-axis) in Figure 9 represents the value of the area equivalent diameter D99 in the model, and the vertical axis (y-axis) represents the maximum electric field strength within the model. Figure 9 also shows the approximate curve obtained by fitting the plotted points.

[0094] As shown in Figure 9, it was confirmed that, similar to the case of 1.0 μm, when the thickness t of the dielectric layer 20 is 0.75 μm, 1.25 μm, and 1.4 μm, the smaller the value of the area equivalent diameter D99, the more the electric field concentration tends to be suppressed. Furthermore, from the approximation curve in Figure 9, it was confirmed that when the thickness t of the dielectric layer 20 is 0.75 μm, if the area equivalent diameter D99 of the multiple holes H in the internal electrode layer 30 is less than approximately 0.7 μm, the maximum electric field strength generated in the model falls below 72 MV / m, and electric field concentration is suppressed. Also, when the thickness t of the dielectric layer 20 is 1.25 μm, it was confirmed that when the area equivalent diameter D99 of the multiple holes H in the internal electrode layer 30 is less than approximately 3 μm, the maximum electric field strength generated in the model falls below 72 MV / m, and electric field concentration is suppressed. Furthermore, when the thickness t of the dielectric layer 20 is 1.4 μm, it was confirmed that when the area equivalent diameter D99 of the multiple holes H present in the internal electrode layer 30 falls below approximately 5 μm, the maximum electric field strength value generated within the model falls below 72 MV / m, and electric field concentration is suppressed.

[0095] Next, using the approximation curves shown in Figure 9, the equivalent area diameter D99 at which the maximum electric field strength generated within the model is 72 MV / m was calculated for each case where the thickness t of the dielectric layer 20 is 0.75 μm, 1 μm, 1.25 μm, and 1.4 μm, and these values ​​were plotted in Figure 10. The horizontal axis (x axis) of Figure 10 represents the thickness t of the dielectric layer 20, and the vertical axis (y axis) represents the value of the equivalent area diameter D99. Figure 10 also shows the approximation curves obtained by fitting the plotted points.

[0096] In a multilayer ceramic capacitor 1, where the thickness of the dielectric layer 20 sandwiched between multiple internal electrode layers is predetermined, the reliability during voltage application can be improved by setting the area equivalent diameter D99 of the multiple holes H present in the internal electrode layer 30 to a region below the approximation curve in Figure 10. For example, if the area equivalent diameter D99 is defined as the area equivalent diameter at which the cumulative value in the cumulative distribution of the area equivalent diameters of the multiple holes H present in the first internal electrode layer 31 and the second internal electrode layer 32 becomes 99%, and the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 is defined as thickness t, then by setting the thickness t of the dielectric layer 20 to 0.5 μm or more and satisfying the following equation (1), the basic dielectric breakdown voltage can be secured by ensuring the thickness of the dielectric layer 20, and electric field concentration during voltage application can be suppressed. In this case, the area equivalent diameter D99 of the multiple holes present in the internal electrode layer may be 0.37 μm or more. (Area equivalent diameter D99) < 0.0879 × exp(2.86 × t) ···(1)

[0097] Furthermore, the thickness t of the dielectric layer may be set to 0.75 μm or more, and the configuration may satisfy the above equation (1). This ensures the basic dielectric breakdown voltage by securing the thickness of the dielectric layer, and further suppresses electric field concentration when voltage is applied. The area equivalent diameter D99 of the multiple holes H present in the internal electrode layer 30 may be 0.75 μm or more.

[0098] Furthermore, the thickness t of the dielectric layer 20 may be set to 1.4 μm or less, satisfying equation (1) above. By setting the thickness of the dielectric layer in this way, it is possible to suppress the decrease in capacitance while further suppressing electric field concentration when a voltage is applied. In addition, by setting the thickness of the dielectric layer 20 in this way, it is possible to miniaturize the multilayer ceramic capacitor 1 while further suppressing electric field concentration when a voltage is applied. The area equivalent diameter D99 of the multiple holes H present in the internal electrode layer 30 may be 4.8 μm or less.

[0099] Furthermore, the thickness t of the dielectric layer 20 may be set to 1.0 μm or less, satisfying equation (1) above. By setting the thickness of the dielectric layer 20 in this way, it is possible to suppress the decrease in capacitance while further suppressing electric field concentration when a voltage is applied. In addition, by setting the thickness of the dielectric layer 20 in this way, it is possible to miniaturize the multilayer ceramic capacitor 1 while further suppressing electric field concentration when a voltage is applied. The area equivalent diameter D99 of the multiple holes H present in the internal electrode layer 30 may be 1.5 μm or less.

[0100] The thickness t of the dielectric layer 20 may be 0.5 μm or more and 1.4 μm or less. Alternatively, the thickness t of the dielectric layer 20 may be 0.5 μm or more and 1.0 μm or less. Furthermore, the thickness t of the dielectric layer 20 may be 0.75 μm or more and 1.4 μm or less. Furthermore, the thickness t of the dielectric layer 20 may be 0.75 μm or more and 1.0 μm or less.

[0101] Furthermore, in this simulation model, even when the coverage, which is the coverage rate of the internal electrode layer 30 over the dielectric layer 20, is changed, the value of the maximum electric field strength remains almost unchanged. To ensure capacitance, a higher coverage is preferable. For example, even when the coverage is 70% to 99%, by adopting the configuration of this embodiment, it is possible to suppress electric field concentration when voltage is applied while suppressing a decrease in capacitance. Also, even when the coverage is high, such as 86% to 93%, and productivity is good, by adopting the configuration of this embodiment, it is possible to suppress electric field concentration when voltage is applied while suppressing a decrease in capacitance. The coverage may also be 81% to 93%.

[0102] Furthermore, in this simulation model, the value of the maximum electric field strength remains almost unchanged even when the thickness of the internal electrode layer 30 is changed. By reducing the thickness of the internal electrode layer 30, the number of layers can be increased even for the same size laminate 10, thereby ensuring sufficient capacitance. For example, even when the thickness of the internal electrode layer 30 is 0.2 μm or more and 2.0 μm or less, by adopting the configuration of this embodiment, it is possible to suppress electric field concentration when voltage is applied while suppressing a decrease in capacitance. Similarly, even when the thickness of the internal electrode layer 30 is 0.2 μm or more and 0.6 μm or less, by adopting the configuration of this embodiment, it is possible to suppress electric field concentration when voltage is applied while suppressing a decrease in capacitance. Furthermore, even when the thickness of the internal electrode layer 30 is 0.2 μm or more and 0.4 μm or less, by adopting the configuration of this embodiment, it is possible to suppress electric field concentration when voltage is applied while suppressing a decrease in capacitance.

[0103] Furthermore, the thicknesses of the first internal electrode layer 31 and the second internal electrode layer 32 may be greater than the thickness t of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32. This makes it easier to increase the coverage of the internal electrode layer 30 and reduce the area equivalent diameter D99 of the multiple holes H present in the internal electrode layer 30, thereby improving the reliability of the product.

[0104] Furthermore, in this simulation model, even when the area equivalent diameter D99 of multiple holes H in the internal electrode layer 30 is fixed and the average diameter is changed, the value of the maximum electric field strength hardly changes. Therefore, the dependence of the maximum electric field strength on the average hole diameter is low, and it can be said that changes in the state of holes H with larger area equivalent diameters contribute more to the suppression of the maximum electric field strength.

[0105] The configuration of this embodiment is particularly suitable for use with multilayer ceramic capacitors with a rated voltage of 10V or more, such as multilayer ceramic capacitors used in automobiles with a relatively higher rated voltage than multilayer ceramic capacitors for portable electronic devices, for example, multilayer ceramic capacitors used with a rated voltage of around 25V. For example, it is preferable that the multilayer ceramic capacitor 1 of this embodiment has a maximum electric field strength of 72MV / m or less when a rated voltage is applied between the first internal electrode layer 31 and the second internal electrode layer 32 sandwiching the dielectric layer 20. The rated voltage is, for example, 25V. It is preferable that the multilayer ceramic capacitor 1 of this embodiment has a maximum electric field strength of 72MV / m or less when 25V is applied between the first internal electrode layer 31 and the second internal electrode layer 32 sandwiching the dielectric layer 20. The multilayer ceramic capacitor 1 of this embodiment can also be practically used with multilayer ceramic capacitors with a rated voltage of about 6.3V to 50V, for example, multilayer ceramic capacitors with a rated voltage of 10V to 25V. However, the applications of multilayer ceramic capacitors are not limited to these.

[0106] The following describes the measurement methods for various parameters. These parameters can be verified using the following methods.

[0107] <Method for measuring the thickness of the internal electrode layer and dielectric layer> This document describes a method for measuring the thickness of the dielectric layer 20 and the internal electrode layer 30 of a multilayer ceramic capacitor 1.

[0108] First, the outer layer on the side is removed by polishing from either the first side WS1 or the second side WS2 to expose the internal electrode layer 30. Further polishing is performed toward the center in the width direction W to a depth of approximately 10 μm to expose the LT cross section where multiple internal electrode layers 30 are exposed. If necessary, the exposed cross section at the observation position is etched to remove the internal electrode layer 30 that has been stretched by polishing.

[0109] Of the exposed cross-section, three locations—the center in the length direction L and the upper, middle, and lower parts in the stacking direction (height direction T)—are observed using a scanning electron microscope (SEM). The magnification used for observation is such that the five dielectric layers 20 and the six internal electrode layers 30 can be observed, and the dielectric layers 20 and the internal electrode layers 30 can be clearly distinguished. Figure 11 shows an example of a magnified image of the cross-section of the multilayer ceramic capacitor 1 observed with an SEM.

[0110] When measuring the thickness of the internal electrode layer 30 of the multilayer ceramic capacitor 1, first, as shown in Figure 11, five straight lines La to Le are drawn at equal intervals (pitch S) in the stacking direction of the laminate 10 in an enlarged cross-sectional image of the multilayer ceramic capacitor 1. The pitch S should be set to approximately 5 to 10 times the thickness of the internal electrode layer 30 to be measured. For example, when measuring an internal electrode layer 30 with a thickness of approximately 0.5 μm, the pitch S = 2.5 μm. Next, the thickness of the internal electrode layer 30 is measured along each of the lines La to Le. However, if the internal electrode layer 30 is missing along each of the lines La to Le, and the dielectric layers 20 sandwiching this internal electrode layer 30 are connected, or if the enlarged image of the measurement position is unclear, a new line is drawn and the thickness of the internal electrode layer 30 is measured.

[0111] For example, when measuring the thickness of the internal electrode layer 30, as shown in Figure 11, the thickness d1 on the line La, the thickness d2 on the line Lb, the thickness d3 on the line Lc, the thickness d4 on the line Ld, and the thickness d5 on the line Le are measured. Then, for the upper, middle, and lower parts of the cross-section of the laminate 10, the thickness of each of the five internal electrode layers 30 is measured using the method described above, and the average value is taken as the thickness of the internal electrode layer 30 in this embodiment.

[0112] The thickness of the dielectric layer 20 is measured using the same method as the internal electrode layer 30. When measuring the thickness of the dielectric layer 20, as shown in Figure 11, the thickness D1 on the line La, the thickness D2 on the line Lb, the thickness D3 on the line Lc, the thickness D4 on the line Ld, and the thickness D5 on the line Le are measured. Then, for the upper, middle, and lower parts of the cross-section of the laminate 10, the thickness of each of the five dielectric layers 20 is measured using the method described above, and the average value is taken as the thickness of the dielectric layer 20 in this embodiment.

[0113] <Measurement target area such as area equivalent diameter D99> Next, we will explain the measurement area when measuring parameters such as the area equivalent diameter D99.

[0114] Through repeated studies, experiments, and simulations, the inventors have found that, in order to improve the reliability of multilayer ceramic capacitors, it is particularly desirable to ensure that the holes in a specific area of ​​the internal electrode layer are in an appropriate state. Specifically, through repeated analyses after accelerated life tests of multilayer ceramic capacitors, the inventors have found that the burnout location at the time of dielectric breakdown of the laminate of a multilayer ceramic capacitor is often near the outer layer on the side, and in an area slightly away from the edge (end) of the internal electrode layer, and that it is desirable to ensure that the holes in this area are in an appropriate state.

[0115] Figure 12 is an SEM image corresponding to an enlarged view of section XII of the WT cross-section of the multilayer ceramic capacitor 1 shown in Figure 3, and shows the burn state of the laminate 10 at the time of dielectric breakdown during accelerated life testing. Thus, in the multilayer ceramic capacitor 1, burn location D of the laminate 10 is likely to occur in the vicinity of the outer layer WG on the side and slightly away from the edge of the internal electrode layer 30.

[0116] Therefore, it is preferable to bring the multiple holes H in the internal electrode layer 30 of this region into an appropriate state, and it is preferable that the measurement target region described above is set to be in the vicinity of the side outer layer WG and slightly away from the edge of the internal electrode layer 30.

[0117] Specifically, when the region of the first internal electrode layer 31 from a position 10 μm away from the first edge WE1 to a position 50 μm away from the first edge WE1 is designated as the first region A1, the region of the second edge WE2 from a position 10 μm away from the second edge WE2 to a position 50 μm away from the second edge WE2 is designated as the second region A2, the region of the second internal electrode layer 32 from a position 10 μm away from the third edge to a position 50 μm away from the third edge is designated as the third region A3, and the region of the fourth edge from a position 10 μm away from the fourth edge to a position 50 μm away from the fourth edge is designated as the fourth region A4, it is preferable to use these first region A1, second region A2, third region A3, and fourth region A4 as the measurement target regions. If the linearity of the first side WE1 to the fourth side WE4 is low, each side is defined as a straight line by linear regression or other methods, and then the first region A1 to the fourth region A4 are defined.

[0118] Figure 4A schematically shows the first region A1 and the second region A2 as measurement target areas. Figure 4B schematically shows the third region A3 and the fourth region A4 as measurement target areas.

[0119] In the first region A1, the second region A2, the third region A3, and the fourth region A4, which are the measurement target areas, the measurement range for actually measuring parameters based on SEM observations is set.

[0120] In SEM observation, the observation area within a single field of view is set to approximately 40 μm × 40 μm to 80 μm × 80 μm. The area to be analyzed is then set to a 40 μm × 40 μm area within that field of view. Based on the combination of 12 areas to be analyzed, parameters such as the area equivalent diameter are measured.

[0121] Specifically, in each of the first region A1, second region A2, third region A3, and fourth region A4, three analysis target areas a are set. The three analysis target areas a are set within the range of the counter electrode portion 11E. Of the three analysis target areas a, the one set closest to the first end face LS1 is set 10 μm away from the outer layer portion LG1 on the first end face side. Of the three analysis target areas a, the one set closest to the second end face LS2 is set 10 μm away from the outer layer portion LG2 on the second end face side. Of the three analysis target areas a, the one set in the middle is set at the center of the length L of the laminate 10. The three analysis target areas a are set at positions that are equally spaced along the length L of the multilayer ceramic capacitor. Figure 4A shows, as an example, three analysis target areas a set in the second region A2. Then, the set of 12 analysis target areas a (4 regions × 3 locations) is used to define the measurement target area where parameters such as area equivalent diameter D99 are measured.

[0122] If the chip size of the multilayer ceramic capacitor 1 is small, the first region A1 to the fourth region A4 may be set in overlapping positions. Similarly, each analysis target range a may also be set in overlapping positions. In this case, each region should be set in different positions while overlapping, so as to cover as wide an area of ​​the internal electrode layer 30 as possible.

[0123] <Measurement method for area equivalent diameter D99> This section describes a method for measuring the area equivalent diameter D99 of holes present in the internal electrode layer 30.

[0124] First, the internal electrode layer 30 located in the central part of the stacked body 10 in the height direction is peeled off from the dielectric layer 20 by field delamination to expose the internal electrode layer 30. Next, a portion of the first region A1 to the fourth region A4 of the internal electrode layer 30, which are the measurement target areas, is set as the above-mentioned analysis target range a, and SEM observation is performed. If the first internal electrode layer 31 is exposed, first, a portion of the first region A1 and the second region A2 of the first internal electrode layer 31 is set as the above-mentioned analysis target range a, and SEM observation is performed. After that, the second internal electrode layer 32 is exposed by FIB (focused ion beam) processing. Then, a portion of the third region A3 and the fourth region A4 of the second internal electrode layer 32 is set as the above-mentioned analysis target range a, and SEM observation is performed. Alternatively, SEM observation of the first internal electrode layer 31 may be performed after SEM observation of the second internal electrode layer 32.

[0125] In SEM observation, the SEM image is analyzed to identify the contours of individual holes H formed in the internal electrode layer 30. Subsequently, for each hole H formed in the internal electrode layer 30, the area equivalent diameter of the hole H is calculated based on the area of ​​the hole H defined by its contour. The area equivalent diameter (area circle equivalent diameter) is the diameter of a perfect circle with an area equal to the area of ​​the hole H defined by its contour.

[0126] For the 12 analysis target areas a that make up the measurement target area, the area equivalent diameter of each hole H described above is calculated.

[0127] The set of all holes H identified within the measurement range, i.e., the 12 analysis ranges, is set as the population of holes H.

[0128] The area equivalent diameter D99 is calculated based on the area equivalent diameter data of the population of holes H within the measurement range. The area equivalent diameter D99 is calculated as the area equivalent diameter where the cumulative value in the cumulative distribution of the number of area equivalent diameters of multiple holes H present within the measurement area reaches 99%.

[0129] <Method for measuring coverage> A method for measuring the coverage of the internal electrode layer 30 as the covering rate of the dielectric layer 20 will be described.

[0130] First, the internal electrode layer 30 located in the central part of the stacked body 10 in the height direction is peeled off from the dielectric layer 20 by field delamination to expose the internal electrode layer 30. Next, a portion of the first region A1 to the fourth region A4 of the internal electrode layer 30, which are the measurement target areas, is set as the analysis target range a described above, and SEM observation is performed. If the first internal electrode layer 31 is exposed, first, a portion of the first region A1 and the second region A2 of the first internal electrode layer 31 is set as the analysis target range a described above, and SEM observation is performed. After that, the second internal electrode layer 32 is exposed by FIB (focused ion beam) processing. Then, a portion of the third region A3 and the fourth region A4 of the second internal electrode layer 32 is set as the analysis target range a described above, and SEM observation is performed. Alternatively, SEM observation of the first internal electrode layer 31 may be performed after SEM observation of the second internal electrode layer 32.

[0131] Subsequently, the region of the internal electrode layer 30 in the analysis target area a is identified by analysis of the SEM image. Then, based on the area of ​​the analysis target area a and the area of ​​the internal electrode layer 30 region, the coverage ratio of the internal electrode layer 30 over the dielectric layer 20 is calculated using the following equation (2). Coverage (%) = (Area of ​​internal electrode layer / Area of ​​analysis target) × 100 ... (2)

[0132] For each of the 12 analysis areas that make up the measurement area, the coverage rate of the internal electrode layer 30 over the dielectric layer 20 is calculated. The average value of these calculations is then used as the coverage rate of the internal electrode layer 30 over the dielectric layer 20 in this embodiment.

[0133] Next, the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment will be described. Note that the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment is not limited as long as it satisfies the requirements described above.

[0134] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and solvent may be known.

[0135] A conductive paste for the internal electrode layer 30 is printed on the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern for the first internal electrode layer 31 formed on it, and a dielectric sheet with the pattern for the second internal electrode layer 32 formed on it.

[0136] A predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the first main surface outer layer 12 on the first main surface TS1 side. On top of this, dielectric sheets with printed first internal electrode layer 31 patterns and dielectric sheets with printed second internal electrode layer 32 patterns are sequentially stacked to form the inner layer 11. On top of this inner layer 11, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the second main surface outer layer 13 on the second main surface TS2 side. This completes the production of the laminated sheet.

[0137] Laminated sheets are pressed in the height direction by means of hydrostatic pressing or other methods to produce laminated blocks.

[0138] The laminated block is cut to a predetermined size, thereby producing laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0139] The laminated chips are fired to produce the laminated body 10. The firing temperature depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably between 900°C and 1400°C.

[0140] Here, the above-mentioned manufacturing conditions are adjusted in order to make the area equivalent diameter D99 of the holes H in the internal electrode layer 30 less than or equal to a predetermined value, and to keep it within a predetermined range.

[0141] Specifically, the pressure, temperature, and pressurization time during lamination of dielectric sheets printed with the pattern of the internal electrode layer 30 are adjusted so that the area equivalent diameter D99 of the holes H in the internal electrode layer 30 is below a predetermined value. For example, if the internal electrode layer 30 is relatively thin, the pressure during pressing of the laminated sheets is set to a higher value.

[0142] Furthermore, the material for the conductive paste for the internal electrode layer 30 may be prepared in order to keep the area equivalent diameter D99 of the holes H present in the internal electrode layer 30 below a predetermined value. For example, if the main component of the internal electrode layer 30 is Ni, using Ni particles with a larger average particle size as the raw material for the conductive paste brings the bonding start temperature between the Ni particles closer to the sintering shrinkage start temperature of the ceramic. This suppresses the ballization of the internal electrode layer 30 and adjusts it so that the area equivalent diameter D99 is below a predetermined value. Also, if the same ceramic powder as the ceramic powder contained in the dielectric layer 20 is added as a co-material to the conductive paste for the internal electrode layer 30, using a co-material with a larger average particle size brings the bonding start temperature between the Ni particles closer to the sintering shrinkage start temperature of the ceramic. This suppresses the ballization of the internal electrode layer 30 and adjusts it so that the area equivalent diameter D99 is below a predetermined value. Furthermore, the co-material dispersibility may be improved by controlling the affinity between the Ni particles, co-material, and solvent in the conductive paste for the internal electrode layer 30. This suppresses the ballization of the internal electrode layer 30, and adjusts the area-equivalent diameter D99 of the hole H to be below a predetermined value.

[0143] Furthermore, by arranging the laminated chips closely together during firing, the uniformity of the internal temperature of the chip during firing can be improved. This suppresses the sphere formation of the internal electrode layer 30 and adjusts the area-equivalent diameter D99 to be below a predetermined value. Alternatively, by firing the laminated chips embedded in ceramic powder, the uniformity of the temperature inside and outside the chip during firing can be improved. This suppresses the sphere formation of the internal electrode layer 30 and adjusts the area-equivalent diameter D99 to be below a predetermined value. During firing, the temperature tends to rise in areas close to the first and second sides of the laminated chip, for example, the side of the internal electrode layer 30 on the first side WS1 side and the side of the internal electrode layer 30 on the second side WS2 side. Therefore, sphere formation of the internal electrode layer 30 is likely to occur in these areas. However, by the method described above, sphere formation in the first region A1 to the fourth region A4 of the internal electrode layer 30 can be suppressed, and the area-equivalent diameter D99 of the holes H in the internal electrode layer 30 can be kept below a predetermined value.

[0144] Furthermore, by forming the internal electrode layer 30 in a two-stage printing process, the internal electrode layer 30 may be formed such that the area-equivalent diameter D99 of holes H located near the first and second sides of the laminated chip, for example, in the first to fourth regions A4, is less than or equal to a predetermined value. In this case, a conductive paste containing Ni particles with a relatively large average particle size and a co-material with a relatively large average particle size is printed in at least the first to fourth regions A4. Then, a conductive paste containing Ni particles with a relatively small average particle size and a co-material with a relatively small average particle size is printed in the other regions, including the central region of the internal electrode layer 30. This makes it possible to keep the area-equivalent diameter D99 of holes H located in at least the first to fourth regions A4 below a predetermined value.

[0145] Furthermore, the method described above for setting the area-equivalent diameter D99 of the holes H in the internal electrode layer 30 to a predetermined value or less can be combined as appropriate. This allows the area-equivalent diameter D99 of the holes H in the internal electrode layer 30 to be adjusted to a predetermined value or less, or within a predetermined range. Similarly, the above method allows the area-equivalent diameter D90 of the holes H in the internal electrode layer 30 to be adjusted to a predetermined value or less, or within a predetermined range.

[0146] A conductive paste, which will form the base electrode layers (first base electrode layer 50A, second base electrode layer 50B), is applied to both end faces of the laminate 10. In this embodiment, the base electrode layers are baked layers. A conductive paste containing glass components and metal is applied to the laminate 10 by a method such as dipping. A baking process is then performed to form the base electrode layers. The temperature of this baking process is preferably 700°C to 900°C.

[0147] Furthermore, when firing the laminated chip before firing and the conductive paste applied to the laminated chip simultaneously, it is preferable to form the baked layer by baking a ceramic material added instead of the glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are fired simultaneously to form a laminated body 10 with a baked layer.

[0148] Subsequently, a plating layer is formed on the surface of the base electrode layer. In this embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. Also, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In this embodiment, a Ni plating layer and a Sn plating layer are formed as the plating layers. When performing the plating process, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of complicating the process because it requires pretreatment with a catalyst or the like to improve the plating deposition rate. Therefore, it is generally preferable to use electrolytic plating. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0149] When forming the base electrode layer as a thin film layer, masking or other methods are used to create the thin film layer as the base electrode layer in the area where the external electrode is to be formed. The thin film layer is formed by a thin film formation method such as sputtering or vapor deposition. The thin film layer is a layer of metal particles with a thickness of 1.0 μm or less.

[0150] When a conductive resin layer is provided as the base electrode layer, the conductive resin layer may be arranged to cover the baking layer, or it may be placed directly on the laminate 10 without providing a baking layer. When a conductive resin layer is provided, a conductive resin paste containing a thermosetting resin and metal components is applied to the baking layer or the laminate 10, and then heat-treated at a temperature of 250 to 550°C or higher. This causes the thermosetting resin to heat-cur, forming a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent resin scattering and oxidation of various metal components, the oxygen concentration is preferably 100 ppm or less.

[0151] Alternatively, the plating layer may be directly placed on the exposed portion of the internal electrode layer 30 of the laminate 10 without providing a base electrode layer. In this case, the first end face LS1 and the second end face LS2 of the laminate 10 are plated, and the plating layer is formed on the exposed portion of the internal electrode layer 30. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of complicating the process because it requires pretreatment with a catalyst or the like to improve the plating deposition rate. Therefore, electrolytic plating is generally preferred. Barrel plating is preferred as the plating method. In addition, if necessary, the upper plating layer formed on the surface of the lower plating layer may be formed using the same method as the lower plating layer.

[0152] Through this manufacturing process, a multilayer ceramic capacitor 1 is produced.

[0153] The multilayer ceramic capacitor 1 may be a two-terminal type with two external electrodes, or a multi-terminal type with multiple external electrodes.

[0154] The multilayer ceramic capacitor 1 of this embodiment provides the following effects.

[0155] (1) The multilayer ceramic capacitor 1 of this embodiment has a plurality of stacked dielectric layers 20 and a plurality of internal electrode layers 30 stacked on the dielectric layers 20, and a laminate 10 having a first main surface TS1 and a second main surface TS2 facing each other in the height direction, a first side surface WS1 and a second side surface WS2 facing each other in the width direction perpendicular to the height direction, and a first end surface LS1 and a second end surface LS2 facing each other in the length direction perpendicular to the height direction and width direction, and a first external electrode 40A and a second external electrode 40B, and the plurality of internal electrode layers 30 are first external The device has a plurality of first internal electrode layers 31 electrically connected to a sub-electrode 40A, and a plurality of second internal electrode layers 32 electrically connected to a second external electrode 40B, wherein the first internal electrode layer 31 and the second internal electrode layer 32 have a plurality of holes H with different area equivalent diameters, and the area equivalent diameter D99 is defined as the area equivalent diameter at which the cumulative value in the cumulative distribution of the area equivalent diameters of the plurality of holes H becomes 99%, and when the thickness t of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 is defined as the thickness t of the dielectric layer 20 is 0.5 μm or more, and further satisfies the following equation (1). (Area equivalent diameter D99) < 0.0879 × exp(2.86 × t) ···(1)

[0156] This makes it possible to provide a multilayer ceramic capacitor that can suppress electric field concentration.

[0157] (2) In the multilayer ceramic capacitor 1 of this embodiment, the thickness t of the dielectric layer 20 is 1.4 μm or less. This makes it possible to suppress electric field concentration even when the thickness t of the dielectric layer 20 is 1.4 μm or less.

[0158] (3) In the multilayer ceramic capacitor 1 of this embodiment, the thickness t of the dielectric layer 20 is 1.0 μm or less. This makes it possible to suppress electric field concentration even when the thickness t of the dielectric layer 20 is 1.0 μm or less.

[0159] (4) In the multilayer ceramic capacitor 1 of this embodiment, the thickness t of the dielectric layer 20 is 0.75 μm or more. This makes it possible to suppress electric field concentration even when the thickness of the dielectric layer 20 is 0.75 μm or more.

[0160] (5) In the multilayer ceramic capacitor 1 of this embodiment, the area equivalent diameter D99 of the multiple holes H present in the first internal electrode layer 31 and the second internal electrode layer 32 is 0.37 μm or more. In this case, 0.37 μm is the value obtained by substituting 0.5 μm as the thickness t of the dielectric layer 20 into the above formula (1).

[0161] (6) In the multilayer ceramic capacitor 1 of this embodiment, the area equivalent diameter D99 of the multiple holes H present in the first internal electrode layer 31 and the second internal electrode layer 32 is 0.75 μm or more. In this case, 0.75 μm is the value obtained by substituting 0.75 μm as the thickness t of the dielectric layer 20 into the above formula (1).

[0162] (7) In the multilayer ceramic capacitor 1 of this embodiment, the area equivalent diameter D99 of the multiple holes H present in the first internal electrode layer 31 and the second internal electrode layer 32 is 4.8 μm or less. In this case, 4.8 μm is the value obtained by substituting 1.4 μm as the thickness t of the dielectric layer 20 into the above formula (1).

[0163] (8) In the multilayer ceramic capacitor 1 of this embodiment, the coverage of the internal electrode layer 30 over the dielectric layer 20 is 70% to 99%. This suppresses the decrease in capacitance while suppressing electric field concentration when voltage is applied.

[0164] (9) In the multilayer ceramic capacitor 1 of this embodiment, the coverage of the internal electrode layer 30 over the dielectric layer 20 may be 81% or more and 93% or less, or 86% or more and 93% or less. This makes it possible to suppress electric field concentration when voltage is applied while suppressing a decrease in capacitance.

[0165] (10) The external electrode 40 of the multilayer ceramic capacitor 1 of this embodiment has a first external electrode 40A arranged on the first end face LS1 side and a second external electrode 40B arranged on the second end face LS2 side, and the plurality of internal electrode layers 30 have a plurality of first internal electrode layers 31 electrically connected to the first external electrode 40A and a plurality of second internal electrode layers 32 electrically connected to the second external electrode 40B, the first internal electrode layer 31 has a first side WE1 on the first side surface WS1 side and a second side WE2 on the second side surface WS2 side, the second internal electrode layer 32 has a third side WE3 on the first side surface WS1 side and a fourth side WE4 on the second side surface WS2 side, and the first internal electrode layer 31 has a first side WE1 at a position 10 μm away from the first side WE1 When the region from edge WE1 to a position 50 μm away is defined as the first region A1, the region from 10 μm away from the second edge WE2 to a position 50 μm away from the second edge WE2 is defined as the second region A2, the region in the second internal electrode layer 32 from 10 μm away from the third edge WE3 to a position 50 μm away from the third edge WE3 is defined as the third region A3, and the region from 10 μm away from the fourth edge WE4 to a position 50 μm away from the fourth edge WE4 is defined as the fourth region A4, and when the set of holes H existing in the first region A1, second region A2, third region A3, and fourth region A4 is defined as the population of holes H, the area equivalent diameter D99 is the area equivalent diameter at which the cumulative value in the cumulative distribution of the area equivalent diameter of holes H in the population of holes H becomes 99%. This makes it possible to suppress electric field concentration and provide a highly reliable multilayer ceramic capacitor.

[0166] (11) The multilayer ceramic capacitor 1 of this embodiment has a plurality of stacked dielectric layers 20 and a plurality of internal electrode layers 30 stacked on the dielectric layers 20, and comprises a laminate 10 having a first main surface TS1 and a second main surface TS2 that are opposite to each other in the height direction, a first side surface WS1 and a second side surface WS2 that are opposite to each other in the width direction perpendicular to the height direction, and a first end surface LS1 and a second end surface LS2 that are opposite to each other in the length direction perpendicular to the height direction and the width direction, and an external electrode 40 connected to the internal electrode layer 30, wherein the internal electrode layer 30 has different area equivalent diameters There are multiple holes H, and the external electrode 40 has a first external electrode 40A positioned on the first end face LS1 side and a second external electrode 40B positioned on the second end face LS2 side, and the multiple internal electrode layers 30 have a multiple first internal electrode layer 31 electrically connected to the first external electrode 40A and a multiple second internal electrode layer 32 electrically connected to the second external electrode 40B, the first internal electrode layer 31 has a first side WE1 on the first side face WS1 side and a second side WE2 on the second side face WS2 side, and the second internal electrode layer 32 has a first side face WS1 The first internal electrode layer 31 has a third side WE3 and a fourth side WE4 on the second side WS2. The region from 10 μm away from the first side WE1 to 50 μm away from the first side WE1 is defined as the first region A1, the region from 10 μm away from the second side WE2 to 50 μm away from the second side WE2 is defined as the second region A2, the region from 10 μm away from the third side WE3 to 50 μm away from the third side WE3 is defined as the third region A3, and the region from the fourth side WE4 Let the region from a distance of 10 μm to a distance of 50 μm from the fourth edge WE4 be defined as the fourth region A4, the set of holes H located in the first region A1, the second region A2, the third region A3, and the fourth region A4 be defined as the population of holes H, the area equivalent diameter D99 is defined as the area equivalent diameter at which the cumulative value in the cumulative distribution of the area equivalent diameter of holes H in the population of holes H becomes 99%, and let the thickness t be the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32. The thickness t of the dielectric layer 20 is 0.5 μm or more, and furthermore, the following equation (1) is satisfied. (Area equivalent diameter D99) < 0.0879 × exp(2.86 × t) ···(1) This makes it possible to suppress electric field concentration and provide highly reliable multilayer ceramic capacitors.

[0167] The present invention is not limited to the configuration of the above embodiments, and can be modified and applied as appropriate without altering the essence of the invention. Furthermore, a combination of two or more of the desirable configurations described in the above embodiments also constitutes the present invention. [Explanation of Symbols]

[0168] 1. Multilayer ceramic capacitor 10 Laminate 20 Dielectric layer 30 Internal electrode layer 31 First internal electrode layer 32 Second internal electrode layer 40 External electrode 40A First external electrode 40B Second external electrode H hole L (Length direction) W (width direction) T (height direction) LS1 First end face LS2 Second end face WS1 First Aspect WS2 Second Aspect TS1 First main surface TS2 Second main surface

Claims

1. A laminate comprising a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, and having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and the width direction, It comprises a first external electrode and a second external electrode, The plurality of internal electrode layers comprises a plurality of first internal electrode layers electrically connected to the first external electrode, and a plurality of second internal electrode layers electrically connected to the second external electrode. The first internal electrode layer and the second internal electrode layer have a plurality of holes with different area-equivalent diameters. A multilayer ceramic capacitor wherein the area equivalent diameter D99 is defined as the area equivalent diameter at which the cumulative value in the cumulative distribution of the area equivalent diameters of the plurality of holes becomes 99%, and the thickness t of the dielectric layer sandwiched between the first internal electrode layer and the second internal electrode layer is defined as the thickness t of the dielectric layer, the thickness t of the dielectric layer is 0.5 μm or more, and further satisfies the following formula (1). (Area equivalent diameter D99) < 0.0879 × exp(2.86 × t) ... (1)

2. The multilayer ceramic capacitor according to claim 1, wherein the thickness t of the dielectric layer is 1.4 μm or less.

3. The multilayer ceramic capacitor according to claim 2, wherein the thickness t of the dielectric layer is 1.0 μm or less.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the thickness t of the dielectric layer is 0.75 μm or more.

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