Semiconductor device and method for manufacturing a semiconductor device

Abstract

To suppress localized polishing in the manufacturing process of semiconductor devices. [Solution] A semiconductor device comprising a base substrate B including a wiring layer, and chips C1, C2, C3, C4, C5, C6 provided on the base substrate B, wherein electrodes and protective films P are provided between the chips C1, C2, C3, C4, C5, C6, and protective films P are also provided on the sides.

Description

Technical Field

[0001] This embodiment relates to a semiconductor device and a method for manufacturing a semiconductor device.

Background Art

[0002] As an example of a semiconductor device and a method for manufacturing a semiconductor device, a stacked device chip and a method for manufacturing a stacked device chip are known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Enable miniaturization of the pitch of the semiconductor device.

Means for Solving the Problems

[0005] This embodiment includes a base substrate including a wiring layer, and a plurality of chips stacked on the base substrate, and an electrode and a protective film are provided between the plurality of chips, and a protective film is also provided on the side surface of the chip. A semiconductor device.

Brief Description of the Drawings

[0006] [Figure 1] It is a figure for demonstrating the structure of the semiconductor memory device in 1st Embodiment. [Figure 2] It is a figure for demonstrating the manufacturing method of the semiconductor memory device shown in FIG. 1. [Figure 3] It is a figure for demonstrating the manufacturing method of the semiconductor memory device shown in FIG. [Figure 4] It is a figure for demonstrating the manufacturing method of the semiconductor memory device shown in FIG. 1. [Figure 5]This is a diagram illustrating the manufacturing method of the semiconductor memory device shown in Figure 1. [Figure 6] This is a diagram illustrating the manufacturing method of the semiconductor memory device shown in Figure 1. [Figure 7] This is a diagram illustrating the manufacturing method of the semiconductor memory device shown in Figure 1. [Figure 8] This is a magnified view of section XI in Figure 7. [Figure 9] This is a diagram illustrating the manufacturing method of the semiconductor memory device shown in Figure 1. [Figure 10] This is a diagram illustrating the chip included in the semiconductor memory device shown in Figure 1. [Figure 11] Figure 10 is a diagram illustrating the state in which the chip shown is bonded to the base substrate. [Figure 12] This figure illustrates a modified example of the base substrate shown in Figure 11. [Figure 13] This diagram illustrates the state in which another chip is bonded to the chip shown in Figure 11. [Figure 14] This is a diagram illustrating the process of bonding one chip to another. [Figure 15] This diagram illustrates the process of bonding a chip to a substrate. [Figure 16] This diagram illustrates the process of bonding a chip to a substrate. [Figure 17] This is a diagram illustrating the configuration of a semiconductor memory device in a modified example. [Figure 18] This is a diagram illustrating the configuration of a semiconductor memory device in the second embodiment. [Figure 19] Figure 18 is a diagram illustrating the manufacturing method of a semiconductor memory device. [Figure 20] Figure 18 is a diagram illustrating the manufacturing method of a semiconductor memory device. [Figure 21] Figure 18 is a diagram illustrating the manufacturing method of a semiconductor memory device. [Figure 22] Figure 18 is a diagram illustrating the manufacturing method of a semiconductor memory device. [Figure 23] It is a diagram for explaining a method of manufacturing a semiconductor memory device shown in FIG. 18. [Figure 24] It is a diagram for explaining a method of manufacturing a semiconductor memory device shown in FIG. 18. [Figure 25] It is a diagram for explaining a method of manufacturing a semiconductor memory device shown in FIG. 18. [Figure 26] It is a diagram for explaining a method of manufacturing a semiconductor memory device shown in FIG. 18. [Figure 27] It is a diagram for explaining a method of manufacturing a semiconductor memory device shown in FIG. 18. [Figure 28] It is a diagram for explaining a method of manufacturing a semiconductor memory device shown in FIG. 18.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, this embodiment will be described with reference to the accompanying drawings. For ease of understanding of the description, the same reference numerals are given to the same components in each drawing as much as possible, and redundant descriptions are omitted.

[0008] FIG. 1 is a cross-sectional view for explaining the structure of a semiconductor memory device E in the first embodiment. The semiconductor memory device E includes a base substrate B and chips C1, C2, C3, C4, C5, C6. A chip C1 is bonded onto the base substrate B. A plurality of metal balls BE are bonded to the surface of the base substrate B opposite to the surface where the chip C1 is bonded.

[0009] On chip C1, chip C2 is bonded to the side opposite to the side bonded to base substrate B. On chip C2, chip C3 is bonded to the side opposite to the side bonded to chip C1. On chip C3, chip C4 is bonded to the side opposite to the side bonded to chip C2. On chip C4, chip C5 is bonded to the side opposite to the side bonded to chip C3. On chip C5, chip C6 is bonded to the side opposite to the side bonded to chip C4. In this way, chips C1, C2, C3, C4, C5, and C6 are stacked on base substrate B.

[0010] A protective film P is provided to cover the sides of chips C1, C2, C3, C4, C5, and C6. The protective film P also covers at least a portion of the base substrate B. In this embodiment, as an example, the protective film P is provided to be relatively thicker on the chip C1 side and relatively thinner on the chip C6 side. The thickness of the protective film P is not limited to this and may be provided to be uniform. The protective film P may be provided to be relatively thicker on the chip C6 side and relatively thinner on the chip C1 side. The protective film P may be removed. A mold resin layer M is provided to cover the protective film P.

[0011] Next, the manufacturing method of semiconductor memory device E will be explained with reference to Figures 2 to 9. Although Figures 2 to 9 show the manufacturing of two semiconductor memory devices E, it is possible to manufacture three or more semiconductor memory devices E simultaneously.

[0012] As shown in Figure 2, a base substrate B is prepared by bonding a support substrate SB to a base substrate B. Alternatively, a wiring layer may be formed on the support substrate SB to create the base substrate B. A predetermined number of individual chips C1 are bonded to predetermined positions on the base substrate B. The silicon C1a is thick in each chip C1. The through-silicon via (TSV) T1 extending from the chip C1 is embedded in the silicon C1a.

[0013] Next, as shown in Figure 3, reactive ion etching (RIE) is performed on silicon C1a to expose the head of the through electrode T1.

[0014] Next, as shown in Figure 4, a protective film P1 is formed to cover the chip C1, silicon C1a, and base substrate B. The protective film P1 is a resin film containing oxides, nitrides, and carbides formed by chemical vapor deposition (CVD). For example, films such as SiO2, SiOC, SiN, and SiCN may be used for the protective film P1. The protective film P1 may also consist of an insulating film that is coated. The insulating film that is coated may consist of an organic film or a polymer material. Spin coating, inkjet printing, screen printing, etc. may be used for coating. Whether coated or chemically deposited, the protective film P1 is formed conformally along the outer shape of the chip C1.

[0015] Next, as shown in Figure 5, the protective film P1 is thinned by chemical mechanical polishing (CMP). By performing CMP, the through electrode T1 and the protective film P1 form a single surface. The through electrode T1 and the protective film P1 become the bonding surface. The pitch of the through electrode T1 may be, for example, 10 μm to 50 μm. The diameter of the ferrule electrode T1 may be 5 μm to 30 μm. The through electrode T1 may protrude from the protective film P1 by 0 to several μm. After final polishing, the thickness of the tip C1 becomes several tens of μm. Approximately 20 μm to 70 μm is preferred. The thickness of the protective film P1 on the bonding surface after polishing may be approximately 3 μm to 5 μm.

[0016] Next, as shown in Figure 6, the next chip C2 is bonded to the bonding surface of chip C1. Thereafter, the procedure described with reference to Figures 2 to 5 is repeated to stack chips C3, C4, C5, and C6 to form a chip laminate. As shown in Figure 7, a protective film is formed each time a chip is stacked, so when chip C6 is stacked, the protective film P is thicker on the side of chip C1 than on the side of chip C6. An electrode is formed on the side of chip C2 facing the bonding surface of chip C1, and an insulating film is formed around the electrode. The electrode and the insulating film may be formed on the same surface. The electrode may protrude from the insulating film by about 0 to several μm. The insulating film formed on the side of chip C2 facing the bonding surface of chip C1 may be an organic film or a polymer material, or it may be an inorganic film such as an oxide film or a nitride film. The insulating films formed on the bonding surface of chip C1 and on the side of chip C2 facing the bonding surface of chip C1 may be made of the same material or different materials.

[0017] Figure 8 shows an enlarged view of section XI in Figure 7. As shown in Figure 8, protective films P1, P2, P3, P4, P5, and P6 are stacked in order. Protective film P1 is a stacked film that was stacked when chip C1 was installed, as described above. Protective film P2 is a stacked film that was stacked when chip C2 was installed on chip C1. Protective film P3 is a stacked film that was stacked when chip C3 was installed on chip C2. Protective film P4 is a stacked film that was stacked when chip C4 was installed on chip C3. Protective film P5 is a stacked film that was stacked when chip C5 was installed on chip C4. Protective film P6 is a stacked film that was stacked when chip C6 was installed on chip C5. After chips C6 have been installed, a heat treatment may be performed to strengthen the bond between the contacting electrodes by metal diffusion. The heat treatment may be performed, for example, after stacking chip C2 on chip C1, and then after stacking chip C3 on chip C2. However, in this case, chip C1 would be subjected to multiple heat treatments, so it is preferable to heat all chips once after stacking.

[0018] As shown in Figure 8, six layers of laminated protective films are provided on the side of chip C1. Similarly, six layers of laminated protective films are provided on the base substrate B.

[0019] On the side surface of chip C2, protective film P1 is not formed, and the layers are stacked starting from protective film P2, resulting in a total of five layers of stacked protective films. On the side surface of chip C3, neither protective film P1 nor protective film P2 is formed, and the layers are stacked starting from protective film P3, resulting in a total of four layers of stacked protective films.

[0020] On the side surface of chip C4, protective films P1, P2, and P3 are not formed, and protective film P4 is laminated first, resulting in three layers of laminated protective films. On the side surface of chip C5, protective films P1, P2, P3, and P4 are not formed, and protective film P5 is laminated first, resulting in two layers of laminated protective films. On the side surface of chip C6, protective films P1, P2, P3, P4, and P5 are not formed, and protective film P6 is laminated, resulting in one layer of laminated protective films.

[0021] In this case, since there is no connection to the through-electrode T1 on the uppermost chip C6, it may not be necessary to thin chip C6. In this case, no multilayer film is provided on the side surface of chip C6. Therefore, the protective film P6 shown in Figure 8 is not formed. On the side surface of chip C1, five layers of protective film are provided. In this case, five layers of protective film are provided on the base substrate B.

[0022] Next, as shown in Figure 9, a molded resin layer M is formed. After that, the support substrate SB is removed and the semiconductor memory device E shown in Figure 1 is obtained. A portion of the protective film P is exposed from the side of the molded resin M. The exposed protective film P is a laminated film in which SiN is repeated multiple times along a direction perpendicular to the surface of the base substrate B. The number of repetitions may be equal to the number of stacked chips or one less. The protective film P on the base substrate B may be removed before forming the molded resin layer M. In this case, the protective film P is not exposed from the side of the molded resin layer M.

[0023] Next, we will further explain chip C1 with reference to Figure 10. Figure 10 is a cross-sectional view of chip C1, showing the state as described with reference to Figure 2. As shown in Figure 10, chip C1 is a three-dimensional memory in which array chip 1 and circuit chip 2 are bonded together. The array chip 1 comprises a memory cell array 11, an insulating film 12, a substrate 13, and an insulating film 14. The memory cell array 11 includes a plurality of memory cells. The insulating film 12 is provided beneath the memory cell array 11. The substrate 13 is provided beneath the insulating film 12. The insulating film 14 is provided beneath the substrate 13.

[0024] The array chip 1 further comprises an interlayer insulating film 15 and an insulating film 16. The interlayer insulating film 15 is provided on the memory cell array 11. The insulating film 16 is provided on the interlayer insulating film 15. The insulating films 12, 14, and 16 are, for example, silicon oxide films or silicon nitride films. The substrate 13 is, for example, a semiconductor substrate such as a silicon substrate.

[0025] The circuit chip 2 is provided on the array chip 1. The symbol S indicates the bonding surface between the array chip 1 and the circuit chip 2. The array chip 1 and the circuit chip 2 are formed separately and then bonded together. The circuit chip 2 comprises an insulating film 17, an interlayer insulating film 18, and a semiconductor 19. The interlayer insulating film 18 is provided on the insulating film 17. The semiconductor 19 is provided on the interlayer insulating film 18. The insulating film 17 is, for example, a silicon oxide film or a silicon nitride film.

[0026] Figure 10 shows the X and Y directions, which are parallel to and perpendicular to the surfaces S1 and S2 of the substrate 13, the surface S3 of the semiconductor 19, and the surface S4 of the substrate 60, and the Z direction, which is perpendicular to the surfaces S1, S2 and S3 and S4. In this specification, the +Z direction is treated as the upward direction and the -Z direction is treated as the downward direction. For example, the memory cell array 11 is located below the substrate 60 and above the substrate 13. The -Z direction may or may not coincide with the direction of gravity.

[0027] The array chip 1 comprises multiple word lines WL, a back gate BG, and a selection gate SG as electrode layers within the memory cell array 11. Figure 10 shows the stepped structure 21 of the memory cell array 11. The array chip 1 and the circuit chip 2 are joined to each other.

[0028] As shown in Figure 10, each word line WL is electrically connected to the word wiring layer 23 via a contact plug 22. The back gate BG is electrically connected to the back gate wiring layer 25 via a contact plug 24. The selection gate SG is electrically connected to the selection gate wiring layer 27 via a contact plug 26. A columnar portion CL is provided so as to penetrate the selection gate SG. The word lines WL, back gate BG, and columnar portion CL are electrically connected to the bit line BL via a plug 28 and are also electrically connected to the substrate 13.

[0029] The circuit chip 2 comprises a plurality of transistors 31. Each transistor 31 comprises a gate electrode 32, a source diffusion layer (not shown), and a drain diffusion layer (not shown). The gate electrode 32 is provided on the semiconductor 19 via a gate insulating film (not shown). The source diffusion layer and the drain diffusion layer are provided within the semiconductor 19.

[0030] The circuit chip 2 further comprises plugs 33, wiring layers 34, and wiring layers 35. Multiple plugs 33 are provided on the source diffusion layer or drain diffusion layer of each transistor 31. Multiple wiring layers 34 are provided on these plugs 33 and contain multiple wirings. Multiple wiring layers 35 are provided on these wiring layers 34 and contain multiple wirings.

[0031] The circuit chip 2 further includes via plugs 36 and metal pads 37. Multiple via plugs 36 are provided on the wiring layer 35. Multiple metal pads 37 are provided on these via plugs 36 within the insulating film 17.

[0032] The circuit chip 2 further comprises a substrate 60 and through-electrodes 61. The substrate 60 is provided on the surface S4 of the semiconductor 19. The substrate 60 is, for example, a semiconductor substrate such as a silicon oxide film or silicon. The through-electrodes 61 are provided within the interlayer insulating film 18, the semiconductor 19, and the substrate 60, and are provided on the wiring layer 34. The substrate 60 corresponds to silicon C1a in Figure 2, etc. The through-electrode 61 corresponds to through-electrode T1 in Figure 2, etc. The through-electrode 61 is formed so as to be embedded in the substrate 60 before the wiring layer 34 is formed, for example. The circuit chip 2 includes a CMOS control circuit (logic circuit) that controls the array chip 1.

[0033] The array chip 1 comprises metal pads 41, via plugs 42, and wiring layers 43. Multiple metal pads 41 are provided on metal pads 37 within an insulating film 16. Multiple via plugs 42 are provided on the metal pads 41. Multiple wiring layers 43 are provided on these via plugs 42 and contain multiple wirings. Each word line WL and each bit line BL are electrically connected to the corresponding wiring in the wiring layer 43.

[0034] The array chip 1 further includes plugs 44 and 46, and a metal pad 47. Plug 44 is provided within the interlayer insulating film 15 or insulating film 12 and is located on the wiring layer 43. Plug 46 is provided within the substrate 13 or insulating film 14 via insulating film 45 and is located on plug 44. The metal pad 47 is provided within the insulating film 14 and is located on plug 46. The metal pad 47 is provided flush with the lower surface of the insulating film 14. The metal pad 47 is an external connection pad for chip C1.

[0035] Figure 11 is a cross-sectional view showing the chip C1 bonded to the base substrate B by bonding. The base substrate B includes external terminals 70, a wiring layer 71, a plug 72, and a metal pad 73. Multiple external terminals 70 are provided beneath the base substrate B. The external terminals 7 are metal terminals for external connection and serve a similar role to the metal ball BE described with reference to Figure 1.

[0036] The wiring layer 71 is provided inside the base board B and contains multiple wires. The plug 72 is provided inside the base board B and is located on the wiring layer 71. The metal pad 73 is located on the plug 72. The metal pad 73 is provided inside the base board B and is located flush with the upper surface of the base board B.

[0037] The metal pad 47 of chip C1 and the metal pad 73 of base substrate B are positioned opposite each other at corresponding locations and are joined together by bonding.

[0038] A controller may be provided inside the base board. Figure 12 shows an example of a base board Ba in which a controller 74 is provided inside. The controller 74 is a controller for controlling chip C1, etc. The controller 74 and the metal pad 73 are connected by a plug 72.

[0039] Figure 13 is a cross-sectional view showing the state in which chip C2 is further bonded to chip C1 shown in Figure 11 by bonding. From the state shown in Figure 11, the through electrode 61 of chip C1 is exposed by the method described with reference to Figures 3 to 6, and chip C2 is placed on chip C1. The through electrode 61 of chip C1 and the metal pad 47 of chip C2 are positioned opposite each other at corresponding positions and are bonded together. The surface of chip C2 facing chip C1 may be formed with an insulating film such as a silicon oxide film and may be formed flush with the pad 47. The surface of chip C1 facing chip C2 may be formed with an insulating film such as a silicon oxide film and may be formed flush with the through electrode 61.

[0040] Let's take the example shown in Figure 14, where the through-electrode 61 of chip C1 and the metal pad 47 of chip C2 are arranged. Figure 14 shows the top surface of chip C1 and the bottom surface of chip C2. In the example shown in Figure 14, the through-electrode 61a corresponds to the metal pad 47a, and the through-electrode 61b corresponds to the metal pad 47b. Bonding is performed by placing chip C2 on chip C1 so that these corresponding parts are arranged facing each other.

[0041] Figure 15 illustrates the case of bonding chip C1 to base substrate B. Figure 15 shows the top surface of base substrate B and the bottom surface of chip C1. In the example shown in Figure 15, metal pad 73a corresponds to metal pad 47a, and metal pad 73b corresponds to metal pad 47b. Chip C1 is placed on base substrate B and bonded so that these corresponding parts are positioned opposite each other.

[0042] Figure 15 illustrates an example in which the metal pad 73 is arranged linearly along the short side of the base substrate B, and the metal pad 47 is also arranged linearly along the short side of the chip C1. However, the arrangement of the metal pads 73 and 47 is not limited to this.

[0043] As shown in Figure 16, the metal pads may be arranged in an irregular pattern. Figure 16 shows the top surface of the base substrate BD and the bottom surface of the chip C1D. In the example shown in Figure 16, metal pad 73Da corresponds to metal pad 47Da, and metal pad 73Db corresponds to metal pad 47Db. The chip C1D is placed on the base substrate BD and bonded so that these corresponding parts are arranged facing each other. Note that, as illustrated in Figure 16, the arrangement of the metal pads on chip C1 may be changed according to the arrangement of the metal pads on the base substrate BD, or the arrangement of the metal pads on chip C1 as illustrated in Figure 15 may be changed by rewiring.

[0044] Figure 17 is a diagram illustrating a semiconductor memory device E1 using a base substrate Ba, as described with reference to Figure 12. As shown in Figure 17, the base substrate Ba contains a controller 74 internally. A wiring layer 71 is provided inside the base substrate Ba. Chips C are stacked on the base substrate Ba. The chip C is not limited to a configuration in which a memory substrate and CMOS (Complementary Metal-oxide Semiconductor) are joined, as in the chip C1 described with reference to Figure 10, etc., but may consist of a memory substrate alone, for example. A protective film P is provided on the outer periphery of the stacked multiple chips C. A molded resin layer M is provided around the protective film P.

[0045] Figure 18 is a cross-sectional view illustrating the structure of a semiconductor memory device E2 in a second embodiment. The semiconductor memory device E2 includes a base substrate B and a plurality of chips C. The chips C are held on the base substrate B, supported by adhesive portions 81. The base substrate B and the chips C are electrically connected by connecting electrodes 82. On the base substrate B, a plurality of metal balls BE are bonded to the surface opposite to the surface to which the chips C are bonded.

[0046] Each of the multiple chips C is provided with a through-electrode T. A protective film P is provided to cover the sides of the multiple chips C. The protective film P may be removed. A molded resin layer M is provided to cover the protective film P.

[0047] Next, the manufacturing method of the semiconductor memory device E2 will be explained with reference to Figures 19 to 28. Figures 19 to 28 illustrate an example in which two chips C are mounted.

[0048] As shown in Figure 19, a support substrate SB is prepared. The support substrate SB is a substrate that is removed during the manufacturing process.

[0049] Next, as shown in Figure 20, the chip C is bonded to the support substrate SB using an adhesive or the like. A through electrode T is provided inside the chip C.

[0050] Next, as shown in Figure 21, a protective film P is applied to the chip C bonded to the support substrate SB, exposing the through-electrode T, and the next chip C is bonded. The through-electrodes T of the bonded chips C are bonded to each other. The bonding of the chips C is performed by bonding.

[0051] Next, as shown in Figure 22, a protective film P is applied to the tip C located above, and the tip is exposed to reveal the through electrode T.

[0052] Next, as shown in Figure 23, the control chip CT is connected to the chip C located above. The control chip CT is connected to the through electrode T of the chip C located above.

[0053] Next, a base substrate B is prepared as shown in Figure 24. The base substrate B has a wiring layer (not shown). The base substrate B has a metal pad 83 on its upper side. The support substrate SB and chip C shown in Figure 23 are inverted and bonded to the base substrate B. Bonding is performed by the adhesive portion 81. The adhesive portion 81 also serves as a support that holds the chip C to the base substrate B at a predetermined distance. The chip C and the base substrate B are electrically connected by an electrode 82. The electrode 82 is connected to a through electrode T and a metal pad 83.

[0054] Next, as shown in Figure 25, the support substrate SB is removed. Then, as shown in Figure 26, molding resin is filled to cover the chip C on the base substrate B, forming a molding resin layer M.

[0055] Next, as shown in Figure 27, a metal ball BE is bonded to the underside of the base substrate B. The metal ball BE is bonded to a metal pad 83 provided on the underside of the base substrate B. Subsequently, as shown in Figure 28, it is cut along the cut line L and fragmented to form a semiconductor memory device E2. At this time, the protective film P may be partially exposed from the side surface of the molded resin layer M. Unlike the semiconductor device E in Figure 1, the protective film P is exposed from near the edge of the chip C, which is furthest from the base substrate B. The protective film P may be removed before forming the molded resin layer M. In this case, the protective film P is not exposed from the molded resin layer M.

[0056] The semiconductor devices E, E1, and E2 according to the above embodiment include a base substrate B including a wiring layer and a plurality of chips C stacked on the base substrate B, with electrodes and protective films P provided between the plurality of chips, and protective films P also provided on the sides of the chips C.

[0057] The protective film P comprises at least one of SiO2, SiOC, SiN, and SiCN. The protective film P is an insulating film formed by coating.

[0058] The protective film P provided on the side of chip C has different thicknesses on the base substrate B side and on the upper edge side of chip C. The protective film P provided on the side of chip C consists of multiple layers.

[0059] The manufacturing method for semiconductor devices E, E1, and E2 according to the above embodiment involves preparing a base substrate B including a wiring layer, bonding a chip C including electrodes onto the base substrate B, forming a protective film P on the chip C, thinning the protective film P on the chip C, and exposing the electrode heads on the chip C.

[0060] The embodiments have been described above with reference to specific examples. However, this disclosure is not limited to these specific examples. Modifications made to these specific examples by those skilled in the art are also included within the scope of this disclosure, as long as they retain the features of this disclosure. The elements, their arrangement, conditions, shapes, etc., of each of the aforementioned specific examples are not limited to those illustrated and can be modified as appropriate. The elements of each of the aforementioned specific examples can be combined in different ways as appropriate, as long as no technical inconsistencies arise. [Explanation of Symbols]

[0061] 1: Array chip 2: Circuit chip 60: Insulating film 61:Through electrode 70: External terminals 71: Wiring layer 72: Plug 73: Metal pad B: Base board C, C1, C2, C3, C4, C5, C6: Chips C1a: Silicone E. Semiconductor memory devices M: Molded resin layer P:Protective film

Claims

1. A semiconductor device, A base substrate including a wiring layer, The system comprises a plurality of chips stacked on the base substrate, A semiconductor device in which electrodes and protective films are provided between the plurality of chips, and protective films are also provided on the sides of the chips.

2. A semiconductor device according to claim 1, The protective film is made of SiO ２ A semiconductor device comprising at least one of SiOC, SiN, and SiCN.

3. A semiconductor device according to claim 1, The protective film is an insulating film on which a coating is formed, wherein the semiconductor device is a semiconductor device.

4. A semiconductor device according to claim 1, A semiconductor device wherein the protective film provided on the side surface of the chip has a different thickness on the base substrate side and on the upper end side of the chip.

5. A semiconductor device according to claim 1, A semiconductor device having multiple layers of protective film provided on the side surface of the aforementioned chip.

6. A method for manufacturing a semiconductor device, Prepare a base substrate including a wiring layer, A chip including electrodes is bonded onto the base substrate, A protective film is formed on the aforementioned chip. The aforementioned chip is subjected to a thinning process for the protective film, A method for manufacturing a semiconductor device, comprising performing electrode head exposure processing on the aforementioned chip.

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