Semiconductor packages

Abstract

This invention provides a semiconductor package that improves thermal characteristics and optimizes signal transmission between semiconductor chips. [Solution] The semiconductor package of the present invention comprises an interposer, a first semiconductor chip stack provided on the interposer and comprising a plurality of first semiconductor chips, a second semiconductor chip stack provided on the interposer and comprising a plurality of second semiconductor chips and separated laterally from the first semiconductor chip stack, and a first bridge chip provided on the interposer, wherein the interposer includes a second wiring structure, a first wiring structure separated upward from the second wiring structure, a first embedded semiconductor chip and a second embedded semiconductor chip provided between the first wiring structure and the second wiring structure, and a plurality of first conductive posts provided between the first embedded semiconductor chip and the second embedded semiconductor chip.

Description

Technical Field

[0001] The present invention relates to a semiconductor package, and more particularly to a semiconductor package including a semiconductor chip stack.

Background Art

[0002] Recently, in the electronics product market, the demand for portable devices has been increasing rapidly, and as a result, there has been a continuous demand for miniaturization and weight reduction of electronic components mounted on these electronic products. For miniaturization and weight reduction of electronic components, the semiconductor packages mounted thereon are required to process high-capacity data while their volume is gradually decreasing. Accordingly, semiconductor packages including a plurality of semiconductor chips are required. For example, semiconductor packages are used that include embedded semiconductor chips inside an interposer or have a plurality of semiconductor chips provided on the interposer.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present invention has been made in view of the above prior art, and an object of the present invention is to provide a semiconductor package having improved thermal characteristics and optimized signal transmission between semiconductor chips.

Means for Solving the Problems

[0004] A semiconductor package according to one aspect of the present invention, made to achieve the above objective, comprises an interposer, a first semiconductor chip stack provided on the interposer and comprising a plurality of first semiconductor chips, a second semiconductor chip stack provided on the interposer and comprising a plurality of second semiconductor chips and spaced laterally apart from the first semiconductor chip stack, and a first bridge chip provided on the interposer between the first semiconductor chip stack and the second semiconductor chip stack, wherein the interposer includes a second wiring structure, a first wiring structure spaced upward from the second wiring structure, a first embedded semiconductor chip provided between the first wiring structure and the second wiring structure, a second embedded semiconductor chip provided between the first wiring structure and the second wiring structure and spaced laterally apart from the first embedded semiconductor chip, and a plurality of first conductive posts provided between the first embedded semiconductor chip and the second embedded semiconductor chip.

[0005] To achieve the above objective, another aspect of the present invention provides a semiconductor package comprising: an interposer; a plurality of semiconductor chip stacks provided on the interposer, each comprising a plurality of semiconductor chips; and one or more bridge chips provided on the interposer, wherein the interposer includes a second wiring structure; a first wiring structure separated upward from the second wiring structure; a first embedded semiconductor chip provided between the first wiring structure and the second wiring structure; a second embedded semiconductor chip provided between the first wiring structure and the second wiring structure and separated laterally from the first embedded semiconductor chip; and a plurality of first conductive posts provided between the first embedded semiconductor chip and the second embedded semiconductor chip, wherein the first embedded semiconductor chip and a portion of the plurality of semiconductor chips are superimposed vertically; the second embedded semiconductor chip and the remainder of the plurality of semiconductor chips are superimposed vertically; a portion of the bridge chip is superimposed vertically on the first embedded semiconductor chip; and a portion of the remainder of the bridge chip is superimposed vertically on the second embedded semiconductor chip.

[0006] A semiconductor package according to yet another aspect of the present invention made to achieve the above objectives includes an interposer, a first semiconductor chip stack comprising a plurality of first semiconductor chips and provided on the interposer, a second semiconductor chip stack comprising a plurality of second semiconductor chips and provided on the interposer and laterally separated from the first semiconductor chip stack, a first bridge chip provided on the interposer between the first semiconductor chip stack and the second semiconductor chip stack, a first heat dissipation block provided between the first semiconductor chip stack and the second semiconductor chip stack and provided on the first bridge chip, and a second heat dissipation block provided on the interposer, extending along the outer edge of the interposer, extending from between the first semiconductor chip stack and the second semiconductor chip stack and provided separately from the first heat dissipation block, wherein the interposer comprises a second wiring structure, a first wiring structure separated upward from the second wiring structure, a first embedded semiconductor chip provided between the first wiring structure and the second wiring structure, and the first wiring structure The first embedded semiconductor chip includes a second embedded semiconductor chip provided between the first embedded semiconductor chip and the second wiring structure and laterally separated from the first embedded semiconductor chip, a plurality of first conductive posts provided between the first embedded semiconductor chip and the second embedded semiconductor chip, and a plurality of second conductive posts, the plurality of second conductive posts provided between the first wiring structure and the second wiring structure, the plurality of second conductive posts provided between the outer edge of the interposer and the first embedded semiconductor chip, and between the outer edge of the interposer and the second embedded semiconductor chip, the first wiring structure includes one or more first insulating layers and a plurality of first via patterns, the first embedded semiconductor chip includes a plurality of first through-vias extending perpendicularly into the interior of the first embedded semiconductor chip, the second embedded semiconductor chip includes a plurality of second through-vias extending perpendicularly into the interior of the second embedded semiconductor chip, the first wiring structure is in contact with one surface of the first embedded semiconductor chip and the second embedded semiconductor chip, the second wiring structure is in contact with the other surface of the first embedded semiconductor chip and the second embedded semiconductor chip,At least a portion of the plurality of first conductive posts supplies power to the first bridge chip, at least a portion of the plurality of second conductive posts supplies power to the first semiconductor chip stack and the second semiconductor chip stack, and the first active surface of the first embedded semiconductor chip and the second active surface of the second embedded semiconductor chip are each provided adjacent to the first wiring structure more adjacent to the second wiring structure than the second wiring structure. [Effects of the Invention]

[0007] According to the semiconductor package of the present invention, an embedded semiconductor chip and a semiconductor chip stack are arranged adjacent to each other and facing each other, a plurality of conductive posts are provided around the embedded semiconductor chip, and a plurality of through-vias are provided on the embedded semiconductor chip. This enables efficient signal transmission within the semiconductor package. Furthermore, by placing the embedded semiconductor chip, which is a logic chip, within the interposer, the semiconductor package can be miniaturized, and by placing a heat dissipation block on the interposer, heat dissipation of the semiconductor package can be effectively achieved. [Brief explanation of the drawing]

[0008] [Figure 1] This is a cross-sectional view of a first example semiconductor package according to one embodiment of the present invention. [Figure 2] This is a plan view of the first example semiconductor package according to one embodiment of the present invention. [Figure 3] This is a cross-sectional view of a second example of a semiconductor package according to one embodiment of the present invention. [Figure 4] This is a plan view of a second example of a semiconductor package according to one embodiment of the present invention. [Figure 5] This is a cross-sectional view of a third example of a semiconductor package according to one embodiment of the present invention. [Figure 6] This is a plan view of a third example semiconductor package according to one embodiment of the present invention. [Figure 7] This is a cross-sectional view of a fourth example of a semiconductor package according to one embodiment of the present invention. [Figure 8]This is a plan view of the fourth example of a semiconductor package according to one embodiment of the present invention. [Figure 9] This is a cross-sectional view of a fifth example of a semiconductor package according to one embodiment of the present invention. [Figure 10] This is a plan view of the fifth example of a semiconductor package according to one embodiment of the present invention. [Figure 11A] This is a series of cross-sectional views illustrating a method for manufacturing a semiconductor package according to one embodiment of the present invention. [Figure 11B] This is a series of cross-sectional views illustrating a method for manufacturing a semiconductor package according to one embodiment of the present invention. [Figure 11C] This is a series of cross-sectional views illustrating a method for manufacturing a semiconductor package according to one embodiment of the present invention. [Figure 11D] This is a series of cross-sectional views illustrating a method for manufacturing a semiconductor package according to one embodiment of the present invention. [Figure 11E] This is a series of cross-sectional views illustrating a method for manufacturing a semiconductor package according to one embodiment of the present invention. [Figure 11F] This is a series of cross-sectional views illustrating a method for manufacturing a semiconductor package according to one embodiment of the present invention. [Modes for carrying out the invention]

[0009] Hereinafter, specific examples of embodiments for carrying out the present invention will be described in detail with reference to the drawings.

[0010] The embodiments of the present invention are provided to more fully explain the technical idea of ​​the invention to those who are ordinary skill in the art, and the embodiments described below can be modified into various other embodiments, and the scope of the technical idea of ​​the invention is not limited to the embodiments described below. Rather, these embodiments are provided to make the invention more complete and to fully communicate the technical idea of ​​the invention to those skilled in the art. Also, the thickness and size of each layer in the drawings are exaggerated for the sake of clarity and ease of explanation.

[0011] In this specification, the first direction means the X direction, and the second direction means the Y direction, with the first and second directions being orthogonal. The third direction is the Z direction, and the third direction is perpendicular to the first and second directions, respectively. A horizontal plane or plane refers to the XY plane. The top surface of a particular object means a surface located in the positive third direction relative to the particular object, and the bottom surface of a particular object means a surface located in the negative third direction relative to the particular object.

[0012] Figure 1 is a cross-sectional view of a first example semiconductor package 1 according to one embodiment of the present invention. Figure 2 is a plan view of a first example semiconductor package 1 according to one embodiment of the present invention. Specifically, Figure 1 is a cross-sectional view obtained by cutting off the A-A' portion of Figure 2.

[0013] Referring to Figures 1 and 2, the semiconductor package 1 includes an interposer 100, a first semiconductor chip stack CS1 provided on the interposer 100, a second semiconductor chip stack CS2 provided on the interposer 100 and laterally separated from the first semiconductor chip stack CS1, a first bridge chip 220 provided between the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2, a first heat dissipation block 310A provided on the first bridge chip 220 between the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2, and a second heat dissipation block 310B provided on the interposer 100 and extending along the outer edge of the interposer 100.

[0014] The interposer 100 includes a second wiring structure WL2, a first embedded semiconductor chip 140A provided on the second wiring structure WL2, a second embedded semiconductor chip 140B provided on the second wiring structure WL2 and spaced laterally from the first embedded semiconductor chip 140A, a plurality of first conductive posts CP1 provided between the first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B, a plurality of second conductive posts CP2 provided on the second wiring structure WL2 between the outer edge of the second wiring structure WL2 and the first embedded semiconductor chip 140A and between the outer edge of the second wiring structure WL2 and the second embedded semiconductor chip 140B, a first encapsulant 130 surrounding the plurality of first conductive posts CP1, the plurality of second conductive posts CP2, the first embedded semiconductor chip 140A, and the second embedded semiconductor chip 140B, and a first wiring structure WL1 provided on the first embedded semiconductor chip 140A, the second embedded semiconductor chip 140B, and the first encapsulant 130.

[0015] The second wiring structure WL2 includes one or more second insulating layers 123 and a plurality of second wiring patterns 120. The second wiring patterns 120 include a plurality of second line patterns 121 and a plurality of second via patterns 122.

[0016] The second insulating layer 123 surrounds the plurality of second wiring patterns 120. In one embodiment, the second wiring structure WL2 includes a plurality of stacked second insulating layers 123. The second insulating layer 123 is formed of, for example, PID (Photo Imageable Dielectric) or photosensitive polyimide (PSPI).

[0017] A passivation layer is provided on the lower surface of the second wiring structure WL2. The passivation layer that protects the second wiring structure WL2 is made of a polymer and covers at least a part of the side surface and the lower surface of each of the plurality of external connection pads 124.

[0018] The multiple second wiring patterns 120 consist of multiple second line patterns 121 and multiple second via patterns 122. The multiple second wiring patterns 120 are metals or alloys of metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), and ruthenium (Ru), but are not limited to these.

[0019] Multiple second line patterns 121 are arranged on at least one of the upper and lower surfaces of the second insulating layer 123. For example, if the second wiring structure WL2 includes multiple stacked second insulating layers 123, the multiple second line patterns 121 are arranged on the upper surface of the uppermost second insulating layer 123, the lower surface of the lowest second insulating layer 123, and between adjacent second insulating layers 123.

[0020] Multiple second via patterns 122 penetrate the second insulating layer 123 and are connected to a portion of the multiple second line patterns 121. In one embodiment, the multiple second via patterns 122 have a tapered shape, with their horizontal width decreasing as they approach the first sealant 130. In other words, the multiple second via patterns 122 have a tapered shape, with their horizontal width increasing as they move away from the first sealant 130.

[0021] In one embodiment, a portion of the plurality of second line patterns 121 is formed together with at least one portion of the plurality of second via patterns 122 to form an integral structure. For example, the second line pattern 121 and the second via pattern 122 that contacts the lower surface of the second line pattern 121 are formed together to form an integral structure.

[0022] A portion of the multiple second wiring patterns 120 that are positioned adjacent to the lower surface of the second wiring structure WL2 is referred to as a plurality of external connecting pads 124. Alternatively, the plurality of external connecting pads 124 are a portion of the multiple second line patterns 121 that are positioned adjacent to the lower surface of the second wiring structure WL2.

[0023] Multiple external connection terminals 125 are attached to each of the multiple external connection pads 124. The multiple external connection terminals 125 connect the semiconductor package 1 to the outside. In one embodiment, the multiple external connection terminals 125 are solder bumps or solder balls.

[0024] The first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B are arranged on the second wiring structure WL2, spaced apart from each other. The first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B are logic semiconductor chips. A logic semiconductor chip is a microprocessor, such as a Central Processing Unit (CPU), Graphics Processing Unit (GPU), Field Programmable Gate Array (FPGA), Application Processor (AP), Digital Signal Processor, Cryptographic Processor, Controller, or Application Specific Integrated Circuit (ASIC).

[0025] For example, the first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B are control semiconductor chips that control the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2 (e.g., data processing order determination, control to prevent errors and bad sectors, buffering to control loading, and FBI (Frequency Boosting Interface)), and are semiconductor chips that integrate application-specific semiconductors.

[0026] The first embedded semiconductor chip 140A includes a first embedded substrate 141, a plurality of embedded through-electrodes 142 that penetrate vertically through at least a portion of the first embedded substrate 141, a first active surface 141A provided adjacent to the upper surface of the first embedded substrate 141, and a plurality of embedded chip pads 143.

[0027] The first embedded substrate 141 contains a semiconductor material such as silicon (Si), or a semiconductor material such as germanium (Ge). The first embedded substrate 141 has a first active surface 141A and an inactive surface opposite to the first active surface 141A. The first embedded substrate 141 contains conductive regions, such as wells doped with impurities. The first embedded substrate 141 has various element isolation structures, such as a shallow trench isolation (STI) structure.

[0028] The first semiconductor element formed on the first active surface 141A of the first embedded substrate 141 includes a plurality of individual devices of various types. The plurality of individual devices include a variety of microelectronic devices, such as MOSFETs (metal-oxide-semiconductor field effect transistors) like CMOS transistors (complementary metal-oxide-semiconductor transistors), system LSIs (large-scale integrations), image sensors such as CIS (CMOS imaging sensors), MEMS (micro-electro-mechanical systems), active elements, passive elements, etc. The plurality of individual devices are electrically connected to the conductive region of the first embedded substrate 141. The first semiconductor element further includes at least two of the plurality of individual devices, or conductive wiring or conductive plugs that electrically connect the plurality of individual devices to the conductive region of the first embedded substrate 141. In addition, each of the plurality of individual devices is electrically isolated from other adjacent individual devices by an insulating film.

[0029] Adjacent to the first active surface 141A, the first embedded substrate 141 includes a first wiring structure layer. The first wiring structure layer electrically connects the first semiconductor element provided on the first active surface 141A to a plurality of first through electrodes 142 and a plurality of embedded chip pads 143. In Figure 1, the first wiring structure layer is schematically shown by solid lines connecting the plurality of first through electrodes 142 and the plurality of embedded chip pads 143. The first active surface 141A is provided adjacent to the upper surface of the first embedded semiconductor chip 140A rather than the lower surface of the first embedded semiconductor chip 140A. In other words, the first embedded semiconductor chip 140A is positioned such that its first active surface 141A is closer to the first wiring structure WL1 than to the second wiring structure WL2. The same applies to the second embedded semiconductor chip 140B. In other words, the second embedded semiconductor chip 140B is positioned such that its second active surface is closer to the first wiring structure WL1 than to the second wiring structure WL2.

[0030] Multiple first conductive posts CP1 are provided between the first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B. The second conductive posts CP2 are provided on the second wiring structure WL2 along the outer edge of the second wiring structure WL2 or the outer edge of the interposer 100. In other words, multiple second conductive posts CP2 are provided between the first embedded semiconductor chip 140A and the outer edge of the second wiring structure WL2, and between the second embedded semiconductor chip 140B and the outer edge of the second wiring structure WL2. The first conductive posts CP1 and the second conductive posts CP2 are each formed of metal or other conductive material. The first conductive posts CP1 and the second conductive posts CP2 are each columnar, cylindrical, or the like.

[0031] As shown in Figures 1 and 2, the multiple second conductive posts CP2 are arranged in two rows between the outer edge of the second wiring structure WL2 and the first embedded semiconductor chip 140A, and between the outer edge of the second wiring structure WL2 and the second embedded semiconductor chip 140B, and the multiple first conductive posts CP1 are arranged in two rows between the first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B. However, the present invention is not limited by such arrangement of multiple first conductive posts CP1 and multiple second conductive posts CP2.

[0032] At least some of the multiple second conductive posts CP2 supply power to the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2. Alternatively, at least some of the multiple second conductive posts CP2 transmit electrical signals to the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2. Alternatively, at least some of the multiple first conductive posts CP1 supply power to the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2. Alternatively, at least some of the multiple first conductive posts CP1 transmit electrical signals to the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2.

[0033] The first encapsulant 130 surrounds a plurality of first conductive posts CP1, a plurality of second conductive posts CP2, a first embedded semiconductor chip 140A, and a second embedded semiconductor chip 140B on the second wiring structure WL2. The first encapsulant 130 contains an epoxy mold compound (EMC) and further contains a filler.

[0034] The vertical thickness of the first encapsulant 130 is substantially the same as the vertical thickness of the first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B. The vertical level of the upper ends of the plurality of first conductive posts CP1 and the plurality of second conductive posts CP2 from the upper surface of the second wiring structure WL2 is substantially the same as the vertical thickness of the first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B. That is, the upper ends of the plurality of first conductive posts CP1, the upper ends of the plurality of second conductive posts CP2, the upper surface of the first embedded semiconductor chip 140A, the upper surface of the second embedded semiconductor chip 140B, and the upper surface of the first encapsulant 130 are coplanar.

[0035] A first wiring structure WL1 is provided on the upper surface of the first encapsulant 130. The first wiring structure WL1 includes a plurality of first insulating layers 113 and a plurality of first wiring patterns 110. The first wiring patterns 110 include a plurality of first line patterns 111 and a plurality of first via patterns 112. The sides of the first wiring structure WL1, the first encapsulant 130, and the second wiring structure WL2 are aligned vertically.

[0036] The first insulating layer 113 surrounds a plurality of first wiring patterns 110. In one embodiment, the first wiring structure WL1 includes a plurality of laminated first insulating layers 113. The first insulating layer 113 is formed of, for example, PID (Photo Imageable Dielectric) or photosensitive polyimide (PSPI).

[0037] The plurality of first wiring patterns 110 consist of a plurality of first line patterns 111 and a plurality of first via patterns 112. The plurality of first wiring patterns 110 are metals or alloys of metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), and ruthenium (Ru), but are not limited to these.

[0038] Multiple first line patterns 111 are arranged on at least one of the upper and lower surfaces of the first insulating layer 113. Multiple first via patterns 112 penetrate the first insulating layer 113 and are connected to some of the multiple first line patterns 111. In one embodiment, the multiple first via patterns 112 have a tapered shape, with their horizontal width decreasing as they approach the first sealing material 130. In other words, the multiple first via patterns 112 have a tapered shape, with their horizontal width increasing as they approach the second sealing material 330, which will be described later.

[0039] In one embodiment, a portion of the plurality of first line patterns 111 is formed together with a portion of the plurality of first via patterns 112 to form an integral structure. For example, the first line pattern 111 and the first via pattern 112 that contacts the lower surface of the first line pattern 111 are formed together to form an integral structure.

[0040] A portion of the multiple first wiring patterns 110 that are arranged adjacent to the upper surface of the first wiring structure WL1 is referred to as a plurality of first upper connecting pads 114A and a plurality of second upper connecting pads 114B. Alternatively, the plurality of first upper connecting pads 114A and a plurality of second upper connecting pads 114B are a portion of the plurality of first line patterns 111 that are arranged adjacent to the upper surface of the first wiring structure WL1.

[0041] Multiple first upper connecting pads 114A are electrically connected to multiple first chip pads 213 provided on the underside of the lowest first semiconductor chip 210B (described later) by multiple first chip connecting terminals 115A. Similarly, multiple first upper connecting pads 114A are electrically connected to multiple first chip pads 213 provided on the underside of the lowest first semiconductor chip 210B (described later) on the second semiconductor chip stack CS2 (described later) by multiple first chip connecting terminals 115A. Multiple second upper connecting pads 114B are electrically connected to multiple second chip pads 222 (described later) on the first bridge chip 220 by multiple second chip connecting terminals 115B.

[0042] A first semiconductor chip stack CS1 and a second semiconductor chip stack CS2 are provided on the interposer 100. The first semiconductor chip stack CS1 and the second semiconductor chip stack CS2 are spaced apart from each other, and a first bridge chip 220 is provided between the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2 on the interposer 100. The specific description of the second semiconductor chip stack CS2 is substantially similar to that of the first semiconductor chip stack CS1.

[0043] The first semiconductor chip stack CS1 includes a plurality of first semiconductor chips 210. For example, as shown in Figure 1, the first semiconductor chip stack CS1 includes eight first semiconductor chips 210, but the present invention is not limited thereto. The first semiconductor chip 210 includes a first substrate 211, a plurality of first through-electrodes 212 penetrating at least a portion of the first substrate 211, a plurality of first chip pads 213 provided on the upper and / or lower surfaces of the first substrate 211, and first chip connecting terminals 214 provided between the plurality of first chip pads 213 provided on the upper and lower surfaces, respectively, of adjacent and different first semiconductor chips 210.

[0044] The first semiconductor chip 210 includes a first semiconductor substrate having an active surface and an inactive surface opposite to each other, a first semiconductor element provided on the active surface of the first semiconductor chip 210, and a first wiring structure provided adjacent to the active surface of the first semiconductor chip 210. The active surfaces provided on each of the multiple first semiconductor chips 210 are provided more adjacent to the lower surfaces of each of the multiple first semiconductor chips 210 than to the upper surfaces of each of the multiple first semiconductor chips 210.

[0045] Each of the multiple first semiconductor chips 210 includes a plurality of first through-electrodes 212 connected to a first wiring structure and penetrating at least a portion of the first semiconductor chip 210. The uppermost first semiconductor chip 210T, which is one of the first semiconductor chips 210 located furthest from the interposer 100 and at the uppermost end of the semiconductor package 1, does not include the plurality of first through-electrodes 212. The first through-electrodes 212 are formed from TSVs (Through Silicon Vias).

[0046] The vertical thickness of the uppermost first semiconductor chip 210T is the same as or greater than the vertical thickness of each of the other first semiconductor chips 210 among the multiple first semiconductor chips 210, excluding the uppermost first semiconductor chip 210T.

[0047] The first substrate 211 contains a semiconductor material such as silicon (Si). The first semiconductor device includes multiple individual devices of various types. The multiple first semiconductor chips 210 are memory chips that include memory cells, and the multiple first semiconductor chips 210 do not include buffer chips. The multiple first semiconductor chips 210 are High Bandwidth Memory (HBM) without buffer chips. The multiple first semiconductor chips 210 are referred to as DRAM dies. For example, the first semiconductor chip 210 communicates directly with the first embedded semiconductor chip 140 without buffer chips used for temporary storage and arrangement of data, in order to provide a communication interface between the logic chip and the memory chip or between the first semiconductor chip 210 and the first embedded semiconductor chip 140.

[0048] The first bridge chip 220 is provided on the interposer 100 between the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2. The first bridge chip 220 has a plurality of second chip pads 222 on its lower surface and is electrically connected to a plurality of second upper connecting pads 114B by a plurality of second chip connecting terminals 115B. Adjacent to the lower surface of the first bridge chip 220 is a first bridge wiring region 221A. The first bridge wiring region 221A is a wiring structure for transmitting electrical signals between the first semiconductor chip stack CS1, the second semiconductor chip stack CS2, the first embedded semiconductor chip 140A, and the second embedded semiconductor chip 140B, which are connected via the first wiring structure WL1. The first bridge chip 220 is made of a semiconductor substrate such as silicon (Si).

[0049] According to one embodiment, the first bridge chip 220 of the semiconductor package 1 is an active bridge chip. That is, the first bridge chip 220 is not a bridge chip that is not supplied with power, but rather transmits signals when power is supplied from an external source. For example, the first bridge chip 220 is supplied with power via at least some of the multiple first conductive posts CP1 provided in the interposer 100. As a result, the first bridge chip 220 performs functions such as signal amplification, regeneration, or switching together with the transmission of electrical signals from the first semiconductor chip stack CS1, the second semiconductor chip stack CS2, the first embedded semiconductor chip 140A, and the second embedded semiconductor chip 140B. However, the first bridge chip 220 of the semiconductor package 1 may be a passive bridge chip that is not supplied with power separately.

[0050] The first heat dissipation block 310A is provided on the first bridge chip 220 between the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2. For example, the planar shape of the first heat dissipation block 310A matches the planar shape of the first bridge chip 220. A first heat transfer film 320A is interposed between the first heat dissipation block 310A and the first bridge chip 220. The planar shape of the first heat transfer film 320A is substantially identical to the planar shape of the first heat dissipation block 310A or the planar shape of the first bridge chip 220. However, the present invention is not limited by the planar shape of the first heat transfer film 320A.

[0051] The second heat dissipation block 310B is provided on the interposer 100 and along the outer edge of the interposer 100. Alternatively, it is provided between the outer edge of the interposer 100 and the first semiconductor chip stack CS1, and between the outer edge of the interposer 100 and the second semiconductor chip stack CS2. Furthermore, as shown in Figure 2, it has a shape that protrudes from the outer edge of the interposer 100 toward the first bridge chip 220 between the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2. The second heat dissipation block 310B is separated from the first heat dissipation block 310A.

[0052] The first heat dissipation block 310A and / or the second heat dissipation block 310B are provided in the semiconductor package 1 as needed, and this is the same in other embodiments as well. That is, neither the first heat dissipation block 310A nor the second heat dissipation block 310B is necessarily provided in the semiconductor package according to this embodiment.

[0053] The planar shape of the second heat dissipation block 310B is provided to surround at least a portion of the sides of the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2. However, in one embodiment, at least a portion of the sides of the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2 may not be surrounded by the second heat dissipation block 310B.

[0054] The vertical heights of the first heat dissipation block 310A and the second heat dissipation block 310B from the top surface of the interposer 100 are substantially the same as the vertical heights of the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2.

[0055] The first heat dissipation block 310A and the second heat dissipation block 310B are made of a metal containing silicon, or at least one of the following: aluminum (Al), copper (Cu), titanium (Ti), nickel (Ni), iron (Fe), cobalt (Co), palladium (Pd), platinum (Pt), gold (Au), lead (Pb), platinum (Pt), silver (Ag), carbon (C), tin (Sn), tungsten (W), chromium (Cr), or an alloy thereof.

[0056] The first heat transfer film 320A and the second heat transfer film 320B include a thermal interface material (TIM). The first heat transfer film 320A and the second heat transfer film 320B have a higher heat transfer coefficient than general adhesive materials. The first heat transfer film 320A and the second heat transfer film 320B are attached to the upper surfaces of the first bridge chip 220 and the interposer 100, respectively, and transfer heat generated inside the semiconductor package 1 to the first heat transfer block 310A and the second heat transfer block 310B. In particular, for example, the first heat transfer film 320A and the second heat transfer film 320B transfer heat generated in the first embedded semiconductor chip 140A, the second embedded semiconductor chip 140B, and the first bridge chip 220 to the first heat transfer block 310A and the second heat transfer block 310B.

[0057] The first heat transfer film 320A and the second heat transfer film 320B have a structure in which fillers such as metal particles are dispersed in a polymeric material. The heat dissipation interface material includes, for example, grease or particle-filled epoxy.

[0058] The second encapsulant 330 is provided on the interposer 100 so as to surround the first semiconductor chip stack CS1, the second semiconductor chip stack CS2, the first heat dissipation block 310A, the second heat dissipation block 310B, and the first bridge chip 220. The second encapsulant 330 comprises an epoxy mold compound (EMC) and further comprises a filler. The upper surface of the second encapsulant 330 is coplane with the upper surface of the first semiconductor chip stack CS1, the upper surface of the second semiconductor chip stack CS2, the upper surface of the first heat dissipation block 310A, and the upper surface of the second heat dissipation block 310B. As shown in Figure 1, the second encapsulant 330 is interposed between the multiple first semiconductor chips 210. Alternatively, in one embodiment, a non-conductive film (NCF) or non-conductive paste (NCP) may be interposed between the multiple first semiconductor chips 210.

[0059] The description of the second sealing material 330 applies substantially the same to each embodiment.

[0060] As shown in Figure 2, in a plan view, the planar shape of the first embedded semiconductor chip 140A is larger than the planar shape of the first semiconductor chip stack CS1. Similarly, the planar shape of the second embedded semiconductor chip 140B is larger than the planar shape of the second semiconductor chip stack CS2. For example, the first embedded semiconductor chip 140A is superimposed perpendicularly on the first semiconductor chip stack CS1, and the second embedded semiconductor chip 140B is superimposed perpendicularly on the second semiconductor chip stack CS2.

[0061] As shown in Figure 2, in a plan view, a portion of the first bridge chip 220 and a portion of the first embedded semiconductor chip 140A overlap vertically. Also, in a plan view, the remaining portion of the first bridge chip 220 and a portion of the second embedded semiconductor chip 140B overlap vertically.

[0062] In this embodiment, the semiconductor package 1 has a first semiconductor chip stack CS1 positioned very close to a first embedded semiconductor chip 140A, which is a logic semiconductor chip, with a first wiring structure WL1 in between. Therefore, the efficiency of electrical signal transmission between the first semiconductor chip stack CS1 and the first embedded semiconductor chip 140A is improved. Similarly, the efficiency of electrical signal transmission between the second semiconductor chip stack CS2 and the second embedded semiconductor chip 140B is improved. In other words, the signal transmission characteristics of the semiconductor package 1 can be improved.

[0063] Simultaneously, the first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B transmit and receive electrical signals via the first bridge chip 220. Since the first wiring structure WL1 is placed between the first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B and the first bridge chip 220, the efficiency of electrical signal transmission between the first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B and the first bridge chip 220 is improved. In other words, the above-described structure of the semiconductor package 1 according to this embodiment improves the efficiency of signal transmission between the numerous semiconductor chips contained in the semiconductor package 1, thereby improving the signal transmission characteristics of the semiconductor package 1. The improvement in the signal transmission characteristics of the semiconductor package 1 described above is an effect achievable in all semiconductor packages of this specification, and a person of ordinary skill will understand that the same effect is present in all semiconductor packages disclosed in this invention without further explanation.

[0064] A second heat dissipation block 310B is provided above the first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B, which are logic chips provided inside the interposer 100, with the first wiring structure WL1 in between, and the first heat dissipation block 310A is provided on the first bridge chip 220. Therefore, heat dissipation from the first embedded semiconductor chip 140A, the second embedded semiconductor chip 140B, and the first bridge chip 220 is effectively achieved. In addition, the second heat dissipation block 310B is provided so as to surround the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2. Therefore, the heat generated in the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2 is easily transferred to the second heat dissipation block 310B, and the heat is effectively dissipated to the outside by the second heat dissipation block 310B. Therefore, the heat dissipation characteristics of the semiconductor package 1 according to this embodiment can be improved. The improvement in the heat dissipation characteristics of semiconductor package 1 described above is an effect achievable with all semiconductor packages in this specification, and an ordinary engineer will understand that the same effect is present with all semiconductor packages in this specification without further explanation below.

[0065] Figure 3 is a cross-sectional view of a second example semiconductor package 1A according to one embodiment of the present invention. Figure 4 is a plan view of a second example semiconductor package 1A according to one embodiment of the present invention. Specifically, Figure 3 is a cross-sectional view obtained by cutting off the B-B' portion of Figure 4. The following information, unless specifically described, is substantially the same as the information described above.

[0066] Referring to Figures 3 and 4, the semiconductor package 1A includes an interposer 100A, a first semiconductor chip stack CS1 provided on the interposer 100A, a second semiconductor chip stack CS2 provided on the interposer 100A and laterally separated from the first semiconductor chip stack CS1, a first bridge chip 220 provided between the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2, a first heat dissipation block 310A provided on the first bridge chip 220 between the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2, and a second heat dissipation block 310B provided on the interposer 100A and extending along the outer edge of the interposer 100A.

[0067] The interposer 100A includes a second wiring structure WL2A, a first embedded semiconductor chip 140A provided on the second wiring structure WL2A, a second embedded semiconductor chip 140B provided on the second wiring structure WL2A, spaced laterally apart from the first embedded semiconductor chip 140A, a plurality of first conductive posts CP1 provided between the first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B, and the outer edge of the second wiring structure WL2A and the first embedded semiconductor The device includes a plurality of second conductive posts CP2A provided between the body chip 140A and the outer edge of the second wiring structure WL2A and the second embedded semiconductor chip 140B, a first encapsulating material 130 surrounding a plurality of first conductive posts CP1, a plurality of second conductive posts CP2A, the first embedded semiconductor chip 140A, and the second embedded semiconductor chip 140B, and a first wiring structure WL1A provided on the first embedded semiconductor chip 140A, the second embedded semiconductor chip 140B, and the first encapsulating material 130.

[0068] For example, the second wiring structure WL2A includes one second insulating layer 123 and a plurality of second via patterns 122. Alternatively, as in the semiconductor package 1 of Figures 1 and 2, the second wiring structure may have a plurality of second insulating layers 123 and a plurality of second wiring patterns.

[0069] The first wiring structure WL1A includes one first insulating layer 113 and a plurality of first via patterns 112. The plurality of first via patterns 112 correspond to a plurality of first upper connecting pads 114A and a plurality of second upper connecting pads 114B provided on the first wiring structure WL1A. The plurality of first via patterns 112 are also connected to a plurality of embedded chip pads 143 provided on a first embedded semiconductor chip 140A and a second embedded semiconductor chip 140B, respectively. Furthermore, the plurality of first via patterns 112 are also connected to a plurality of first conductive posts CP1, respectively.

[0070] Specifically, the multiple first via patterns 112 correspond to the multiple first upper connecting pads 114A and the multiple second upper connecting pads 114B on the upper surface of the first wiring structure WL1A, and the multiple first via patterns 112 are connected to the multiple embedded chip pads 143 of the first embedded semiconductor chip 140A, the multiple embedded chip pads 143 provided on the second embedded semiconductor chip 140B, and the multiple first conductive posts CP1 on the lower surface of the first wiring structure WL1A.

[0071] Unlike the multiple first conductive posts CP1, the multiple second conductive posts CP2A are not electrically connected to the multiple first via patterns 112. The multiple second conductive posts CP2A are not electrically connected to the first wiring structure WL1A. Therefore, the multiple second conductive posts CP2A are not electrically connected to the semiconductor chip provided in the semiconductor package 1A.

[0072] Multiple second conductive posts CP2A are provided on the second wiring structure WL2A along the outer edge of the second wiring structure WL2A or along the outer edge of the interposer 100A. In other words, multiple second conductive posts CP2 are provided between the first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B and the outer edge of the second wiring structure WL2A.

[0073] The plurality of second conductive posts CP2A provided in the semiconductor package 1A according to this embodiment are made of metal and are arranged adjacent to the sides of the first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B. The plurality of second conductive posts CP2A effectively dissipate heat generated in the first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B to the outside, and the plurality of second conductive posts CP2A quickly transfer heat to the second heat dissipation block 310B provided above the plurality of second conductive posts CP2A, thereby effectively dissipating heat from the first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B.

[0074] Figure 5 is a cross-sectional view of a third example semiconductor package 1B according to one embodiment of the present invention. Figure 6 is a plan view of a third example semiconductor package 1B according to one embodiment of the present invention. Specifically, Figure 5 is a cross-sectional view obtained by cutting off the C-C' portion of Figure 6. The following information, unless specifically described, is substantially the same as the information described above.

[0075] Referring to Figures 5 and 6, the semiconductor package 1B includes an interposer 100B, a first semiconductor chip stack CS1 provided on the interposer 100B, a second semiconductor chip stack CS2 provided on the interposer 100B and laterally separated from the first semiconductor chip stack CS1, a first bridge chip 220 provided between the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2, and a first heat dissipation block 310A provided on the first bridge chip 220 between the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2. The semiconductor package 1B further includes a third heat dissipation block 310C provided on the interposer 110B between the first semiconductor chip stack CS1, the second semiconductor chip stack CS2, and the first bridge chip 220.

[0076] The interposer 100B includes a second wiring structure WL2, a first embedded semiconductor chip 140A provided on the second wiring structure WL2, a second embedded semiconductor chip 140B provided on the second wiring structure WL2, spaced laterally from the first embedded semiconductor chip 140A, a plurality of first conductive posts CP1 provided between the first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B, and the outer edge of the second wiring structure WL2A and the first embedded semiconductor chip The device includes a plurality of second conductive posts CP2B provided between the chip 140A and the outer edge of the second wiring structure WL2A and the second embedded semiconductor chip 140B, a first encapsulating material 130 surrounding a plurality of first conductive posts CP1, a plurality of second conductive posts CP2B, the first embedded semiconductor chip 140A, and the second embedded semiconductor chip 140B, and a first wiring structure WL1A provided on the first embedded semiconductor chip 140A, the second embedded semiconductor chip 140B, and the first encapsulating material 130.

[0077] The second wiring structure WL2 includes one or more second insulating layers 123 and a plurality of second wiring patterns 120. The second wiring patterns 120 include a plurality of second line patterns 121 and a plurality of second via patterns 122.

[0078] The first wiring structure WL1A includes one first insulating layer 113 and a plurality of first via patterns 112. The plurality of first via patterns 112 correspond to a plurality of first upper connecting pads 114A and a plurality of second upper connecting pads 114B provided on the first wiring structure WL1A, respectively.

[0079] Multiple first via patterns 112 are connected to multiple embedded chip pads 143 provided on the first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B, respectively. Multiple first via patterns 112 are also connected to multiple first conductive posts CP1 and multiple second conductive posts CP2B, respectively.

[0080] Specifically, the multiple first via patterns 112 correspond to the multiple first upper connecting pads 114A and the multiple second upper connecting pads 114B on the upper surface of the first wiring structure WL1A, and the multiple first via patterns 112 are connected to the multiple embedded chip pads 143 of the first embedded semiconductor chip 140A, the multiple embedded chip pads 143 provided on the second embedded semiconductor chip 140B, the multiple first conductive posts CP1, and the multiple second conductive posts CP2B on the lower surface of the first wiring structure WL1A.

[0081] At least some of the multiple second conductive posts CP2B supply power to the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2. Alternatively, at least some of the multiple second conductive posts CP2B transmit electrical signals to the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2. At least some of the multiple first conductive posts CP1 supply power to the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2. Alternatively, at least some of the multiple first conductive posts CP1 transmit electrical signals to the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2.

[0082] As shown in Figure 6, in a plan view, for example, a portion of the first embedded semiconductor chip 140A is superimposed perpendicularly on a portion of the first semiconductor chip stack CS1, and a portion of the second embedded semiconductor chip 140B is superimposed perpendicularly on a portion of the second semiconductor chip stack CS2.

[0083] As described above, the third heat dissipation block 310C is provided on the interposer 110B between the first semiconductor chip stack CS1, the second semiconductor chip stack CS2, and the first bridge chip 220. The third heat dissipation block 310C transfers heat generated by the first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B, which are provided within the interposer 110B, and dissipates it to the outside. In addition, the third heat dissipation block 310C transfers heat generated by the first semiconductor chip stack CS1, the second semiconductor chip stack CS2, and the first bridge chip 220 and dissipates it to the outside.

[0084] Figure 7 is a cross-sectional view of the fourth example semiconductor package 1C according to one embodiment of the present invention. Figure 8 is a plan view of the fourth example semiconductor package 1C according to one embodiment of the present invention. Specifically, Figure 7 is a cross-sectional view obtained by cutting off the D-D' portion of Figure 8. The following content, unless specifically described, is substantially the same as the content described above.

[0085] Referring to Figures 7 and 8, the semiconductor package 1C includes an interposer 100C, a first semiconductor chip stack CS1, a second semiconductor chip stack CS2, a third semiconductor chip stack CS3, and a fourth semiconductor chip stack CS4, which are provided on the interposer 100C and arranged spaced apart from each other, and a fourth heat dissipation block 310D that surrounds the first to fourth semiconductor chip stacks (CS1, CS2, CS3, CS4) and extends along the outer edge of the interposer 100C.

[0086] Since the third semiconductor chip stack CS3 and the fourth semiconductor chip stack CS4 are substantially identical to the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2, differing only in their placement, a detailed explanation of the third semiconductor chip stack CS3 and the fourth semiconductor chip stack CS4 will be omitted.

[0087] The interposer 100C includes a second wiring structure WL2, a third embedded semiconductor chip 140C provided on the second wiring structure WL2, a plurality of second conductive posts CP2 provided on the second wiring structure WL2 between the outer edge of the second wiring structure WL2 and the third embedded semiconductor chip 140C, a first encapsulating material 130 surrounding the third embedded semiconductor chip 140C, and a first wiring structure WL1 provided on the third embedded semiconductor chip 140C and the first encapsulating material 130.

[0088] As shown in Figure 8, in a planar view, the planar shape of the third embedded semiconductor chip 140C is larger than the planar shapes of the first to fourth semiconductor chip stacks (CS1, CS2, CS3, CS4). For example, the size of the planar shape of the third embedded semiconductor chip 140C is more than twice as large as the size of the planar shapes of the first to fourth semiconductor chip stacks (CS1, CS2, CS3, CS4).

[0089] At least a portion of the planar shapes of the first to fourth semiconductor chip stacks (CS1, CS2, CS3, CS4) overlaps the planar shape of the third embedded semiconductor chip 140C in the vertical direction. For example, as shown in Figure 8, the entire planar shape of the first to fourth semiconductor chip stacks (CS1, CS2, CS3, CS4) overlaps the planar shape of the third embedded semiconductor chip 140C in the vertical direction.

[0090] The third embedded semiconductor chip 140C includes a first embedded substrate 141, a plurality of embedded through-electrodes 142 that penetrate vertically through at least a portion of the first embedded substrate 141, a first active surface 141A provided adjacent to the upper surface of the first embedded substrate 141, and a plurality of embedded chip pads 143. The first embedded substrate 141 has a first active surface 141A and an inactive surface opposite to the first active surface 141A. The first active surface 141A of the third embedded semiconductor chip 140C is provided adjacent to the upper surface of the third embedded semiconductor chip 140C more adjacent to the lower surface of the third embedded semiconductor chip 140C. In other words, the third embedded semiconductor chip 140C is positioned such that the first active surface 141A of the third embedded semiconductor chip 140C is closer to the first wiring structure WL1 than to the second wiring structure WL2.

[0091] The third embedded semiconductor chip 140C is a logic semiconductor chip. A logic semiconductor chip is a microprocessor, such as a Central Processing Unit (CPU), Graphics Processing Unit (GPU), Field Programmable Gate Array (FPGA), Application Processor (AP), Digital Signal Processor, Cryptographic Processor, Controller, or Application Specific Integrated Circuit (ASIC).

[0092] In this embodiment, the semiconductor package 1C has the first to fourth semiconductor chip stacks (CS1, CS2, CS3, CS4) arranged very close to the third embedded semiconductor chip 140C, which is a logic semiconductor chip, with the first wiring structure WL1 in between. Therefore, the efficiency of electrical signal transmission between the first to fourth semiconductor chip stacks (CS1, CS2, CS3, CS4) and the third embedded semiconductor chip 140C is improved. In other words, the signal transmission characteristics of the semiconductor package 1C can be improved.

[0093] Furthermore, the semiconductor package 1C according to this embodiment is equipped with a fourth heat dissipation block 310D adjacent to the third embedded semiconductor chip 140C, which is a logic semiconductor chip. The heat generated by the third embedded semiconductor chip 140C is easily transferred to the fourth heat dissipation block 310D, which effectively dissipates the heat to the outside. Therefore, the heat dissipation characteristics of the semiconductor package 1C according to this embodiment can be improved.

[0094] Figure 9 is a cross-sectional view of the fifth example semiconductor package 1D according to one embodiment of the present invention. Figure 10 is a plan view of the fifth example semiconductor package 1D according to one embodiment of the present invention. Specifically, Figure 9 is a cross-sectional view obtained by cutting off the E-E' portion of Figure 10. The following content, unless specifically described, is substantially the same as the content described above.

[0095] Referring to Figures 9 and 10, the semiconductor package 1D includes an interposer 100D, first to fourth semiconductor chip stacks (CS1, CS2, CS3, CS4) provided on the interposer 100D, a first bridge chip 220A provided between the first semiconductor chip stack CS1 and the second semiconductor chip stack CS2, a second bridge chip 220B provided between the third semiconductor chip stack CS3 and the fourth semiconductor chip stack CS4, a first heat dissipation block 310A provided on the first bridge chip 220A and the second bridge chip 220B respectively, and a second heat dissipation block 310E extending between the outer edge of the interposer 110C and the first to fourth semiconductor chip stacks (CS1, CS2, CS3, CS4) and between the first to fourth semiconductor chip stacks (CS1, CS2, CS3, CS4).

[0096] The interposer 100D includes a second wiring structure WL2, a first embedded semiconductor chip 140A provided on the second wiring structure WL2, a second embedded semiconductor chip 140B provided on the second wiring structure WL2, spaced laterally from the first embedded semiconductor chip 140A, a plurality of first conductive posts CP1 provided between the first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B, a plurality of second conductive posts CP2 provided on the second wiring structure WL2 around the first embedded semiconductor chip 140A and around the second embedded semiconductor chip 140B, a first encapsulating material 130 surrounding the plurality of first conductive posts CP1, the plurality of second conductive posts CP2, the first embedded semiconductor chip 140A, and the second embedded semiconductor chip 140B, and a first wiring structure WL1 provided on the first embedded semiconductor chip 140A, the second embedded semiconductor chip 140B, and the first encapsulating material 130.

[0097] As shown in Figure 10, in a plan view, the planar shape of the first embedded semiconductor chip 140A is larger than the planar shapes of the first semiconductor chip stack CS1 and the third semiconductor chip stack CS3. The planar shape of the second embedded semiconductor chip 140B is larger than the planar shapes of the second semiconductor chip stack CS2 and the fourth semiconductor chip stack CS4. The planar shape of the first embedded semiconductor chip 140A superimposes perpendicularly onto at least a portion of the planar shape of the first semiconductor chip stack CS1 and at least a portion of the planar shape of the third semiconductor chip stack CS3, respectively. The planar shape of the second embedded semiconductor chip 140B superimposes perpendicularly onto at least a portion of the planar shape of the second semiconductor chip stack CS2 and at least a portion of the planar shape of the fourth semiconductor chip stack CS4, respectively.

[0098] As shown in Figure 10, a portion of the first bridge chip 220A is superimposed perpendicularly on a portion of the first embedded semiconductor chip 140A, and the remaining portion of the first bridge chip 220A is superimposed perpendicularly on a portion of the second embedded semiconductor chip 140B. Similarly, a portion of the second bridge chip 220B is superimposed perpendicularly on a portion of the first embedded semiconductor chip 140A, and the remaining portion of the second bridge chip 220B is superimposed perpendicularly on a portion of the second embedded semiconductor chip 140B.

[0099] In other embodiments, instead of having multiple bridge chips such as the first bridge chip 220A and the second bridge chip 220B, only one bridge chip may be provided on the interposer 100D. That is, instead of having bridge chips only between multiple semiconductor chip stacks, one or more bridge chips may be provided between the first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B in a plan view. That is, bridge chips may be provided in adjacent central portions between the first to fourth semiconductor chip stacks (CS1, CS2, CS3, CS4) on the upper surface of the interposer 100D.

[0100] The second heat dissipation block 310E is provided on the interposer 100D, extending between the first to fourth semiconductor chip stacks (CS1, CS2, CS3, CS4) and the outer edge of the interposer 100D, and between the first to fourth semiconductor chip stacks (CS1, CS2, CS3, CS4). Therefore, the second heat dissipation block 310E extends between the first to fourth semiconductor chip stacks (CS1, CS2, CS3, CS4) where the first bridge chip 220A and the second bridge chip 220B are not provided.

[0101] In Figure 10, the portion of the second heat dissipation block 310E provided between the first to fourth semiconductor chip stacks (CS1, CS2, CS3, CS4) and the outer edge of the interposer 100D, and the portion of the second heat dissipation block 310E extending between the first to fourth semiconductor chip stacks (CS1, CS2, CS3, CS4) are shown as a single unit. However, in one embodiment, the portion of the second heat dissipation block 310E provided between the first to fourth semiconductor chip stacks (CS1, CS2, CS3, CS4) and the outer edge of the interposer 100D, and the respective portions of the second heat dissipation block 310E extending between the first to fourth semiconductor chip stacks (CS1, CS2, CS3, CS4) can be separately separated and mounted on the interposer 100D. That is, the second heat dissipation block 310E can be manufactured as multiple components that are not a single unit as a whole and mounted on the interposer 100D.

[0102] Figures 11A to 11F are cross-sectional views sequentially illustrating a method for manufacturing a semiconductor package 1 according to one embodiment of the present invention. Any information not described below is substantially the same as that described above.

[0103] Referring to Figure 11A, a first embedded semiconductor chip 140A, a second embedded semiconductor chip 140B, a plurality of first conductive posts CP1, and a plurality of second conductive posts CP2 are arranged on the carrier CR to form the first encapsulating material 130. Although not specifically shown, the process result in Figure 11A is formed in an inverted state relative to Figure 11A, and then placed on the carrier CR.

[0104] Specifically, after the multiple embedded chip pads 143 provided on the first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B are positioned on the carrier CR so that they face downwards, multiple first conductive posts CP1 are formed between the first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B, and second conductive posts CP2 are formed around the first embedded semiconductor chip 140A and the second embedded semiconductor chip 140B. Subsequently, a first encapsulating material 130 is formed so as to surround the multiple first conductive posts CP1, the second conductive posts CP2, the first embedded semiconductor chip 140A, and the second embedded semiconductor chip 140B. The first encapsulating material 130, the multiple first conductive posts CP1, the second conductive posts CP2, the first embedded semiconductor chip 140A, and the second embedded semiconductor chip 140B are planarized by chemical mechanical polishing (CMP) to form the process result shown in Figure 11A.

[0105] As a result of the above-described process, the upper surfaces of the first encapsulant 130, the multiple first conductive posts CP1, the second conductive posts CP2, the first embedded semiconductor chip 140A, and the second embedded semiconductor chip 140B are all on the same plane, and the lower surfaces of the first encapsulant 130, the multiple first conductive posts CP1, the second conductive posts CP2, the first embedded semiconductor chip 140A, and the second embedded semiconductor chip 140B are all on the same plane.

[0106] Referring to Figure 11B, a first wiring structure WL1 is formed on the process result of Figure 11A. The first wiring structure WL1 includes a plurality of first insulating layers 113. The first wiring structure WL1 is formed by a rewiring process. The first wiring structure WL1 includes a plurality of first insulating layers 113 and a plurality of first wiring patterns 110. The first wiring patterns 110 include a plurality of first line patterns 111 and a plurality of first via patterns 112. The rewiring process means a series of steps in which the first insulating layer 113 is formed, the first wiring patterns 110 are formed on the formed first insulating layer 113, and then the first insulating layer 113 is formed again on top of them.

[0107] Referring to Figure 11C, a first semiconductor chip stack CS1, a second semiconductor chip stack CS2, and a first bridge chip 220 are mounted on the first wiring structure WL1 of the process result in Figure 11B. As shown in the drawings herein, the first semiconductor chip stack CS1 is a stack of multiple first semiconductor chips 210 that are stacked and connected by multiple first chip pads 213 and first chip connector terminals 214. For example, the first semiconductor chip stack CS1 is formed by a thermocompression bonding process.

[0108] In one embodiment, two adjacent chips among a plurality of first semiconductor chips 210 are directly bonded to each other. Direct bonding of any two chips includes direct bonding of conductive components at opposing positions on the two chips, and direct bonding of insulating components at opposing positions on the two chips. Direct bonding of insulating components includes the formation of chemical bonds between insulating components. Direct bonding of any two chips includes hybrid bonding.

[0109] For example, a lower pad located on the underside of a first semiconductor chip 210 and an upper pad located on the upperside of another adjacent first semiconductor chip 210 are directly bonded. During the direct bonding process, metal atoms in the lower pad and metal atoms in the upper pad diffuse to each other. Therefore, the upper pad and lower pad are joined without any separation at the interface. The lower pad and upper pad thus integrated by the direct bonding process are collectively referred to as a bonded pad. For example, the bonded pad is made of a material containing Cu.

[0110] Referring to Figure 11D, the first heat dissipation block 310A is placed on the first bridge chip 220 of the process result in Figure 11C, and the second heat dissipation block 310B is placed on the first wiring structure WL1. The first heat transfer film 320A and the second heat transfer film 320B are interposed on the lower surfaces of the first heat dissipation block 310A and the second heat transfer film 320B, respectively.

[0111] Referring to Figures 11E and 11F, the second sealing material 330 is interposed on the first wiring structure WL1 of the process result in Figure 11D. Subsequently, the carrier CR is removed, and the rewiring process is carried out to form the second wiring structure WL2.

[0112] Although embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the embodiments described above, and can be modified and implemented in various ways without departing from the technical spirit of the present invention. [Explanation of Symbols]

[0113] 1, 1A, 1B, 1C, 1D semiconductor packages 100, 100A, 100B, 100C, 100D Interposer 110, 120 First and Second Wiring Patterns 111, 121 First and second line patterns 112, 122 First and Second Via Patterns 113, 123 First and second insulating layers 114A, 114B First and second upper connecting pads 115A, 115B First and second chip connection terminals 124 External connection pad 125 External connection terminal 130, 330 First and second sealing materials 140A, 140B, 140C First to Third Embedded Semiconductor Chips 141 First embedded substrate 141A 1st active surface 142 Embedded through-electrode 143 Embedded tip pad 210 First Semiconductor Chip 210B Bottommost first semiconductor chip 210T Topmost first semiconductor chip 211 First board 212 1st through electrode 213, 222 First and second chip pads 214 First chip connection terminal 220 First Bridge Chip 221A First Bridge Wiring Area 310A First heat dissipation block 310B, 310E Second heat dissipation block 310C, 310D Third and fourth heat dissipation blocks 320A, 320B First and second heat transfer films CP1 First conductive post CP2, CP2B Second conductive post CR Career CS1, CS2, CS3, CS4 1st to 4th semiconductor chip stacks WL1, WL1A First Wiring Structure WL2 2nd wiring structure

Claims

1. Interposer and, A first semiconductor chip stack provided on the interposer, comprising a plurality of first semiconductor chips, A second semiconductor chip stack comprising a plurality of second semiconductor chips is provided on the interposer and is spaced laterally away from the first semiconductor chip stack, The interposer includes a first bridge chip provided between the first semiconductor chip stack and the second semiconductor chip stack, The semiconductor package is characterized in that the interposer includes a second wiring structure, a first wiring structure separated upward from the second wiring structure, a first embedded semiconductor chip provided between the first wiring structure and the second wiring structure, a second embedded semiconductor chip provided between the first wiring structure and the second wiring structure and separated laterally from the first embedded semiconductor chip, and a plurality of first conductive posts provided between the first embedded semiconductor chip and the second embedded semiconductor chip.

2. The semiconductor package according to claim 1, further comprising a first heat dissipation block provided between the first semiconductor chip stack and the second semiconductor chip stack and provided on the first bridge chip.

3. The semiconductor package according to claim 1, further comprising a second heat dissipation block provided on the interposer along the outer edge of the interposer, spaced apart from the first semiconductor chip stack and the second semiconductor chip stack, and located outside the first semiconductor chip stack and the second semiconductor chip stack.

4. The first embedded semiconductor chip and the second embedded semiconductor chip are each logic chips. The semiconductor package according to claim 3, characterized in that the first active surface of the first embedded semiconductor chip and the second active surface of the second embedded semiconductor chip are each provided adjacent to the first wiring structure more adjacent to the second wiring structure than the second wiring structure.

5. The first wiring structure includes a single first insulating layer and a plurality of first via patterns, The first embedded semiconductor chip and the second embedded semiconductor chip include a plurality of embedded chip pads provided on the upper surface of the first embedded semiconductor chip and the upper surface of the second embedded semiconductor chip, The semiconductor package according to claim 1, characterized in that the plurality of first via patterns correspond to the plurality of embedded chip pads and the plurality of first conductive posts, respectively.

6. The interposer includes a plurality of second conductive posts, The plurality of second conductive posts are provided between the first wiring structure and the second wiring structure, The semiconductor package according to claim 1, characterized in that the plurality of second conductive posts are provided between the outer edge of the interposer and the first embedded semiconductor chip, and between the outer edge of the interposer and the second embedded semiconductor chip.

7. The interposer includes a plurality of second conductive posts, The first wiring structure includes a single first insulating layer and a plurality of first via patterns, The plurality of second conductive posts are provided between the first wiring structure and the second wiring structure, The plurality of second conductive posts are provided between the outer edge of the interposer and the first embedded semiconductor chip, and between the outer edge of the interposer and the second embedded semiconductor chip. The first embedded semiconductor chip and the second embedded semiconductor chip include a plurality of embedded chip pads provided on the upper surface of the first embedded semiconductor chip and the upper surface of the second embedded semiconductor chip, The semiconductor package according to claim 1, characterized in that the plurality of first via patterns correspond to the plurality of embedded chip pads, the plurality of first conductive posts, and the plurality of second conductive posts, respectively.

8. The interposer includes a plurality of second conductive posts, The plurality of second conductive posts are provided between the first wiring structure and the second wiring structure, The plurality of second conductive posts are provided between the outer edge of the interposer and the first embedded semiconductor chip, and between the outer edge of the interposer and the second embedded semiconductor chip. At least some of the plurality of first conductive posts supply power to the first bridge chip. The semiconductor package according to claim 7, characterized in that at least a portion of the plurality of second conductive posts supplies power to the first semiconductor chip stack and the second semiconductor chip stack.

9. Interposer and, Multiple semiconductor chip stacks, each containing multiple semiconductor chips, are provided on the interposer, The interposer has one or more bridge chips provided on it, The interposer includes a second wiring structure, a first wiring structure separated upward from the second wiring structure, a first embedded semiconductor chip provided between the first wiring structure and the second wiring structure, a second embedded semiconductor chip provided between the first wiring structure and the second wiring structure and separated laterally from the first embedded semiconductor chip, and a plurality of first conductive posts provided between the first embedded semiconductor chip and the second embedded semiconductor chip. The first embedded semiconductor chip and a portion of the plurality of semiconductor chips are superimposed in the vertical direction. The second embedded semiconductor chip and the remaining semiconductor chips are superimposed in the vertical direction. A portion of the bridge chip is superimposed perpendicularly on the first embedded semiconductor chip, A semiconductor package characterized in that the remaining portion of the bridge chip is superimposed perpendicularly on the second embedded semiconductor chip.

10. Interposer and, A first semiconductor chip stack provided on the interposer, comprising a plurality of first semiconductor chips, A second semiconductor chip stack comprising a plurality of second semiconductor chips is provided on the interposer and is spaced laterally away from the first semiconductor chip stack, A first bridge chip is provided on the interposer between the first semiconductor chip stack and the second semiconductor chip stack, A first heat dissipation block is provided between the first semiconductor chip stack and the second semiconductor chip stack and is provided on the first bridge chip, The interposer includes a second heat dissipation block that extends along the outer edge of the interposer, extends from between the first semiconductor chip stack and the second semiconductor chip stack, and is positioned away from the first heat dissipation block. The interposer includes a second wiring structure, a first wiring structure separated upward from the second wiring structure, a first embedded semiconductor chip provided between the first wiring structure and the second wiring structure, a second embedded semiconductor chip provided between the first wiring structure and the second wiring structure and separated laterally from the first embedded semiconductor chip, a plurality of first conductive posts provided between the first embedded semiconductor chip and the second embedded semiconductor chip, and a plurality of second conductive posts. The plurality of second conductive posts are provided between the first wiring structure and the second wiring structure, The plurality of second conductive posts are provided between the outer edge of the interposer and the first embedded semiconductor chip, and between the outer edge of the interposer and the second embedded semiconductor chip. The first wiring structure includes one or more first insulating layers and a plurality of first via patterns, The first embedded semiconductor chip includes a plurality of first through-vias extending perpendicularly into the interior of the first embedded semiconductor chip. The second embedded semiconductor chip includes a plurality of second through-vias extending perpendicularly into the interior of the second embedded semiconductor chip. The first wiring structure is in contact with one surface of the first embedded semiconductor chip and the second embedded semiconductor chip, The second wiring structure is in contact with the other side of the first embedded semiconductor chip and the second embedded semiconductor chip, At least some of the plurality of first conductive posts supply power to the first bridge chip. At least a portion of the plurality of second conductive posts supplies power to the first semiconductor chip stack and the second semiconductor chip stack. A semiconductor package characterized in that the first active surface of the first embedded semiconductor chip and the second active surface of the second embedded semiconductor chip are each provided adjacent to the first wiring structure more adjacent to the second wiring structure.

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