Power supply unit and control method for power supply unit

Abstract

The voltage on the first side is detected based on the voltage on the second side. [Solution] The transformer includes a first winding connected to a bridge circuit and a second winding magnetically coupled to the first winding; an inductor connected between the center tap of the second winding and a third terminal; a fifth switching element connected between one end of the second winding and a fourth terminal; a sixth switching element electrically connected between the other end of the second winding and a fourth terminal; a first switch connected between one end of the fifth switching element and a third terminal; a second switch connected between one end of the sixth switching element and a third terminal; a voltage detection unit that detects the voltage between one end or the other end of the second winding and the center tap based on at least one of the terminal voltages of the fifth switching element and the terminal voltages of the sixth switching element; and a control unit that calculates the voltage between the first terminal and the second terminal based on the voltage detected by the voltage detection unit.

Description

[Technical Field]

[0001] This disclosure relates to a power supply and a method for controlling a power supply. [Background technology]

[0002] For example, in electric vehicles, a DC-DC converter is used that steps down the voltage from the first side (high voltage side, e.g., the traction battery) to the second side (low voltage side, e.g., the auxiliary battery) and outputs the voltage, and then steps up the voltage from the second side to the first side and outputs the voltage. Phase-shifted full-bridge circuits are the mainstream for these DC-DC converters.

[0003] Patent Document 1 describes a voltage detection device for a phase-shift full-bridge circuit that detects the voltage on the first side based on the voltage on the second side. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2021-114845 [Overview of the project] [Problems that the invention aims to solve]

[0005] When transmitting power from the second side to the first side in a phase-shift full-bridge circuit, a choke input method is used. Furthermore, if the transformer turns ratio is first turns:second turns = N:1, when outputting a voltage higher than ((second side battery voltage) × N) to the first side, it is necessary to boost the voltage not only with the transformer but also with the output inductor. This generates a surge voltage in the output inductor, and this surge voltage is applied to the switching elements on the second side. In other words, the switching elements on the second side may be subjected to stress. Therefore, a power supply device that can suppress the possibility of stress on the switching elements on the second side is required.

[0006] Furthermore, in a power supply device that can suppress the possibility of stress on the second switching element, if the voltage on the first side is to be detected directly, an isolation amplifier is required because the first side has a high voltage. Therefore, in a power supply device that can suppress the possibility of stress on the second switching element, there is also a need to detect the voltage on the first side based on the voltage on the second side.

[0007] This disclosure aims to suppress the possibility of the second switching element being subjected to stress, and further to detect the voltage on the first side based on the voltage on the second side. [Means for solving the problem]

[0008] A power supply device in one aspect of this disclosure is: A power supply device that steps down a first voltage input between a first terminal and a second terminal and outputs it from between a third terminal and a fourth terminal, and steps up a second voltage input between the third terminal and the fourth terminal and outputs it from between the first terminal and the second terminal, A bridge circuit comprising: a first switching element with one end electrically connected to the first terminal; a second switching element with one end electrically connected to the other end of the first switching element and the other end electrically connected to the second terminal; a third switching element with one end electrically connected to the first terminal; and a fourth switching element with one end electrically connected to the other end of the third switching element and the other end electrically connected to the second terminal; A transformer comprising: a first winding, one end of which is electrically connected to the other end of the first switching element and one end of the second switching element, and the other end of which is electrically connected to the other end of the third switching element and one end of the fourth switching element; and a second winding that is magnetically coupled to the first winding; An inductor having one end electrically connected to the center tap of the second winding and the other end electrically connected to the third terminal, A fifth switching element, one end of which is electrically connected to one end of the second winding and the other end of which is electrically connected to the fourth terminal, A sixth switching element, one end of which is electrically connected to the other end of the second winding and the other end of which is electrically connected to the fourth terminal, A first switch, one end of which is electrically connected to one end of the fifth switching element and one end of the second winding, and the other end of which is electrically connected to the other end of the inductor and the third terminal, A second switch, one end of which is electrically connected to one end of the sixth switching element and the other end of the second winding, and the other end of which is electrically connected to the other end of the inductor and the third terminal, A voltage detection unit that detects the voltage between one or the other end of the second winding and the center tap based on at least one of the terminal voltages of the fifth switching element and the terminal voltages of the sixth switching element, A control unit that calculates the voltage between the first terminal and the second terminal based on the voltage detected by the voltage detection unit, including, It is characterized by the following:

[0009] In the aforementioned power supply device, The control unit, When the second voltage is boosted and output between the first terminal and the second terminal, During the first period, the fifth switching element and the first switch are turned on, and the sixth switching element and the second switch are turned off. In the second period following the first period, the first switch is turned on, and the fifth switching element, the sixth switching element, and the second switch are turned off. In the third period following the second period, the sixth switching element and the second switch are turned on, and the fifth switching element and the first switch are turned off. In the fourth period following the third period, the second switch is turned on, and the fifth switching element, the sixth switching element, and the first switch are turned off. It is characterized by the following:

[0010] In the aforementioned power supply device, The voltage detection unit is During the second or fourth period, the voltage between one end or the other end of the second winding and the center tap is detected based on the difference between the terminal voltage of the fifth switching element and the terminal voltage of the sixth switching element. It is characterized by the following:

[0011] In the aforementioned power supply device, The voltage detection unit is During the fourth period, the voltage between one or the other end of the second winding and the center tap is detected by subtracting the sum of the inductor voltage and the second voltage from the terminal voltage of the fifth switching element. It is characterized by the following:

[0012] In the aforementioned power supply device, The voltage detection unit is During the second period, the voltage between one or the other end of the second winding and the center tap is detected by subtracting the terminal voltage of the fifth switching element from the sum of the voltage of the inductor and the second voltage. It is characterized by the following:

[0013] In the aforementioned power supply device, The control unit, When the voltage between the first terminal and the second terminal reaches the target voltage, the first switching element through the sixth switching element are turned off, and at least one of the first switch and the second switch is turned on. It is characterized by the following:

[0014] In the aforementioned power supply device, The control unit, At least one of the first switch and the second switch is turned on with a predetermined duty cycle. It is characterized by the following:

[0015] A control method for a power supply device according to one aspect of this disclosure is: A bridge circuit including a first switching element with one end electrically connected to a first terminal, a second switching element with one end electrically connected to the other end of the first switching element and the other end electrically connected to a second terminal, a third switching element with one end electrically connected to the first terminal, and a fourth switching element with one end electrically connected to the other end of the third switching element and the other end electrically connected to a second terminal; a transformer including a first winding with one end electrically connected to the other end of the first switching element and one end of the second switching element, and the other end electrically connected to the other end of the third switching element and one end of the fourth switching element, and a second winding that is magnetically coupled to the first winding; an inductor with one end electrically connected to the center tap of the second winding and the other end electrically connected to the third terminal; and one end of the front A control method for a power supply device, comprising: a fifth switching element electrically connected to one end of the second winding and the other end electrically connected to the fourth terminal; a sixth switching element electrically connected to the other end of the second winding and the other end electrically connected to the fourth terminal; a first switch electrically connected to one end of the fifth switching element and one end of the second winding and the other end electrically connected to the other end of the inductor and the third terminal; a second switch electrically connected to one end of the sixth switching element and the other end of the second winding and the other end electrically connected to the other end of the inductor and the third terminal; and a voltage detection unit that detects the voltage between one end or the other end of the second winding and the center tap based on at least one of the terminal voltage of the fifth switching element and the terminal voltage of the sixth switching element, When the second voltage input between the third terminal and the fourth terminal is boosted and output from between the first terminal and the second terminal, During the first period, the fifth switching element and the first switch are turned on, and the sixth switching element and the second switch are turned off. In the second period following the first period, the first switch is turned on, and the fifth switching element, the sixth switching element, and the second switch are turned off. In the third period following the second period, the sixth switching element and the second switch are turned on, and the fifth switching element and the first switch are turned off. In the fourth period following the third period, the second switch is turned on, and the fifth switching element, the sixth switching element, and the first switch are turned off. Based on the voltage detected by the voltage detection unit, the voltage between the first terminal and the second terminal is calculated. It is characterized by the following: [Effects of the Invention]

[0016] According to this disclosure, the possibility of the second switching element being subjected to stress can be suppressed, and furthermore, the voltage on the first side can be detected based on the voltage on the second side. [Brief explanation of the drawing]

[0017] [Figure 1] Figure 1 shows an example of the configuration of the power system of an electric vehicle. [Figure 2] Figure 2 shows the configuration of a conventional DC-DC converter. [Figure 3] Figure 3 shows the configuration of the DC-DC converter according to the first embodiment. [Figure 4] Figure 4 shows the configuration of the voltage detection unit of the DC-DC converter according to the first embodiment. [Figure 5] Figure 5 is a timing diagram of the boost operation of the DC-DC converter in the first embodiment. [Figure 6] Figure 6 shows the current flow path during the boost operation of the DC-DC converter in the first embodiment. [Figure 7] Figure 7 shows the current flow path during the boost operation of the DC-DC converter in the first embodiment. [Figure 8] Figure 8 shows the current flow path during the boost operation of the DC-DC converter in the first embodiment. [Figure 9]Figure 9 shows the current flow path during the boost operation of the DC-DC converter in the first embodiment. [Figure 10] Figure 10 shows the configuration of the DC-DC converter in the second embodiment. [Figure 11] Figure 11 shows the configuration of the voltage detection unit of the DC-DC converter according to the second embodiment. [Figure 12] Figure 12 shows the configuration of the DC-DC converter according to the third embodiment. [Figure 13] Figure 13 shows the configuration of the voltage detection unit of the DC-DC converter according to the third embodiment. [Figure 14] Figure 14 is a timing diagram of the DC-DC converter according to the fourth embodiment. [Figure 15] Figure 15 is a timing diagram of the DC-DC converter according to the fourth embodiment. [Figure 16] Figure 16 is a timing diagram of the DC-DC converter according to the fifth embodiment. [Figure 17] Figure 17 is a timing diagram of the DC-DC converter according to the sixth embodiment. [Figure 18] Figure 18 is a timing diagram of the DC-DC converter according to the seventh embodiment. [Modes for carrying out the invention]

[0018] Embodiments relating to this disclosure will be described in detail below with reference to the attached drawings. However, this embodiment does not limit the disclosure, and in the following embodiments, the same parts are denoted by the same reference numerals to avoid redundant explanations.

[0019] <First Embodiment> (Example of power system configuration for electric vehicles) Figure 1 shows an example of the configuration of the power system of an electric vehicle.

[0020] Power system 1 includes a high-voltage battery 2, a resistor 3, contactors 4, 5, and 6, an inverter 7, a motor 9, a DC-DC converter 10, and a low-voltage battery 11. The inverter 7 includes a smoothing capacitor 8 on the input side.

[0021] The DC-DC converter 10 corresponds to an example of a "power supply device" in this disclosure.

[0022] The high-voltage battery 2 is exemplified by a traction battery, but the disclosure is not limited thereto. The voltage of the high-voltage battery 2 is arbitrary. The low-voltage battery 11 is exemplified by an auxiliary battery, but the disclosure is not limited thereto. The voltage of the low-voltage battery 11 is arbitrary.

[0023] Initially (for example, when starting an electric vehicle), there may be no power (charge) stored in capacitor 8. In this case, contactors 5 and 6 are turned on, and capacitor 8 is pre-charged (pre-charged) from the high-voltage battery 2 via resistor 3. After pre-charging is complete, contactor 5 is turned off and contactor 4 is turned on.

[0024] When charging the low-voltage battery 11, the DC-DC converter 10 steps down the DC voltage across the capacitor 8 and outputs it to the low-voltage battery 11. The low-voltage battery 11 is charged by the DC voltage output from the DC-DC converter 10.

[0025] Furthermore, it is desirable that the DC-DC converter 10 can boost the voltage of the low-voltage battery 11 to precharge the capacitor 8. This would eliminate the need for the resistor 3 and contactor 5 in the power system 1.

[0026] (Conventional configuration) Figure 2 shows the configuration of a conventional DC-DC converter. The DC-DC converter 200 is a phase-shifted full-bridge circuit. Currently, phase-shifted full-bridge circuits are the mainstream for power conversion from high-voltage battery 2 to low-voltage battery 11.

[0027] The DC-DC converter 200 has a first terminal 21, a second terminal 22, a third terminal 23, and a fourth terminal 24.

[0028] The first terminal 21 is electrically connected to one end (high potential side) of the capacitor 8. The second terminal 22 is electrically connected to the other end (low potential side) of the capacitor 8. The third terminal 23 is electrically connected to one end (high potential side) of the low-voltage battery 11. The fourth terminal 24 is electrically connected to the other end (low potential side) of the low-voltage battery 11.

[0029] The DC-DC converter 200 receives the voltage V input between the first terminal 21 and the second terminal 22. H The voltage is reduced, L The output is generated between the third terminal 23 and the fourth terminal 24.

[0030] The DC-DC converter 200 includes a bridge circuit 31, an inductor Lr, a transformer T, a choke Lo, a transistor Q5, a transistor Q6, a capacitor 51, and a control unit 61.

[0031] The bridge circuit 31 includes transistors Q1 through Q4.

[0032] Transistor Q1 corresponds to an example of the “first switching element” in this disclosure. Transistor Q2 corresponds to an example of the “second switching element” in this disclosure. Transistor Q3 corresponds to an example of the “third switching element” in this disclosure. Transistor Q4 corresponds to an example of the “fourth switching element” in this disclosure.

[0033] Transistor Q5 corresponds to an example of the “fifth switching element” in this disclosure. Transistor Q6 corresponds to an example of the “sixth switching element” in this disclosure.

[0034] In the embodiments, each transistor is a MOSFET, but the disclosure is not limited to this. Each transistor may be a silicon power device, a GaN power device, a SiC power device (e.g., an IGBT (Insulated Gate Bipolar Transistor)), or the like.

[0035] Each transistor has a parasitic diode (body diode) that can actively conduct current, or a diode connected in antiparallel. A parasitic diode is the pn junction between the back gate and the source and drain of a MOSFET.

[0036] The source of transistor Q1 is electrically connected to the drain of transistor Q2. The drain of transistor Q1 is electrically connected to the drain of transistor Q3. The source of transistor Q3 is electrically connected to the drain of transistor Q4. The source of transistor Q2 is electrically connected to the source of transistor Q4.

[0037] The drains of transistor Q1 and Q3 are electrically connected to the first terminal 21. The sources of transistor Q2 and Q4 are electrically connected to the second terminal 22.

[0038] The transformer T includes a first winding 41, a second winding 42, and a core 43. The first winding 41 and the second winding 42 are wound around the core 43.

[0039] The source of transistor Q1 and the drain of transistor Q2 are electrically connected to one end of inductor Lr. The other end of inductor Lr is electrically connected to one end of the first winding 41. The other end of the first winding 41 is electrically connected to the source of transistor Q3 and the drain of transistor Q4.

[0040] The inductor Lr may be a wound component, or it may be the leakage inductance of the first winding 41.

[0041] The second winding 42 is divided into a first part 42a and a second part 42b at the intermediate tap 42c.

[0042] Let the turns ratio between the first winding 41 and the first part 42a of the second winding 42 be n1:n2. Similarly, let the turns ratio between the first winding 41 and the second part 42b of the second winding 42 be n1:n2. n1 and n2 can be arbitrary values.

[0043] The voltage across the first winding 41 is, voltage V n1 Let the voltage of the first part 42a of the second winding 42 be the voltage V. n2 Let the voltage of the second part 42b of the second winding 42 be the voltage V. n2 Let's assume that. V n1 =n1 / n2·V n2 That is the case.

[0044] The center tap 42c is electrically connected to one end of the choke Lo. The other end of the choke Lo is electrically connected to one end (high potential side) of the capacitor 51 and to the third terminal 23.

[0045] One end of the first section 42a is electrically connected to the center tap 42c. The other end of the first section 42a is electrically connected to the drain of transistor Q5.

[0046] One end of the second section 42b is electrically connected to the center tap 42c. The other end of the second section 42b is electrically connected to the drain of transistor Q6.

[0047] The sources of transistor Q5 and transistor Q6 are electrically connected to the other end (low-potential side) and fourth terminal 24 of capacitor 51.

[0048] The control unit 61 outputs a drive control signal P1 to the bridge circuit 31, a drive control signal P2 to transistor Q5, and a drive control signal P3 to transistor Q6.

[0049] When the DC-DC converter 200 outputs a step-down voltage from the first side (the capacitor 8 side) to the second side (the low-voltage battery 11 side) (when charging the low-voltage battery 11), since the capacitor 8 is connected in parallel with the high-voltage battery 2, the DC-DC converter 200 adopts a capacitor input method.

[0050] When the DC-DC converter 200 outputs a step-up voltage from the second side (the low-voltage battery 11 side) to the first side (the capacitor 8 side) (when pre-charging the capacitor 8), since the choke Lo is connected in series with the low-voltage battery 11, the DC-DC converter 200 adopts a choke input method.

[0051] When the DC-DC converter 200 outputs a step-up voltage from the second side (the low-voltage battery 11 side) to the first side (the capacitor 8 side) (when pre-charging the capacitor 8), the target voltage V H is L less than or equal to n1 / n2 times of the voltage V, then the step-up by the turns ratio of the transformer T is sufficient.

[0052] However, when the target voltage V H is higher than n1 / n2 times of the voltage V L , in addition to the transformer T, a step-up by the choke Lo is required. In that case, when the choke Lo discharges energy, a surge voltage is generated by the choke Lo, and a large surge voltage is applied to the transistor Q5 and the transistor Q6, and the transistor Q5 and the transistor Q6 may be stressed.

[0053] Also, when the voltage V H reaches the desired voltage, it is desirable to stop the pre-charging. If the DC-DC converter 200 does not stop the pre-charging, the voltage V H may continue to rise, and components such as the inverter 7 may be damaged. Therefore, it is desirable for the DC-DC converter 200 to be able to detect the voltage V H .

[0054] If the voltage V H If we were to attempt to detect it directly, since capacitor 8 is a component on the first side (high voltage side), the DC-DC converter 200 would require an isolation amplifier. As a result, the DC-DC converter 200 would be larger in size and more expensive.

[0055] Therefore, the DC-DC converter 200 does not require an isolation amplifier, that is, it uses the voltage of the second side (low voltage side) to determine the voltage V H It is desirable to be able to detect it.

[0056] (Configuration of the first embodiment) Figure 3 shows the configuration of the DC-DC converter according to the first embodiment.

[0057] Compared to the conventional DC-DC converter 200 (see Figure 2), the DC-DC converter 10 further includes a first switch 71 and a second switch 72, a voltage detection unit 81, and an AD converter 91.

[0058] The first switch 71 includes a diode D7 and a transistor Q7. The anode of diode D7 is electrically connected to the other end of the first portion 42a of the second winding 42 and to the drain of transistor Q5. The cathode of diode D7 is electrically connected to the drain of transistor Q7. The source of transistor Q7 is electrically connected to the other end of choke Lo, one end of capacitor 51 and the third terminal 23. Diode D7 is a reverse current protection diode. The first switch 71 may also be a mechanical switch.

[0059] The second switch 72 includes a diode D8 and a transistor Q8. The anode of diode D8 is electrically connected to the other end of the second portion 42b of the second winding 42 and to the drain of transistor Q6. The cathode of diode D8 is electrically connected to the drain of transistor Q8. The source of transistor Q8 is electrically connected to the other end of choke Lo, one end of capacitor 51 and to the third terminal 23. Diode D8 is a reverse current protection diode. The second switch 72 may be a mechanical switch.

[0060] The control unit 61 outputs a drive control signal P4 to the gate of transistor Q7 and a drive control signal P5 to the gate of transistor Q8.

[0061] In this embodiment, diode D7 is placed on the second winding 42 side and transistor Q7 is placed on the capacitor 51 side, but the disclosure is not limited thereto. Transistor Q7 may be placed on the second winding 42 side and diode D7 may be placed on the capacitor 51 side. That is, the drain of transistor Q7 may be electrically connected to the other end of the first portion 42a of the second winding 42 and the drain of transistor Q5, the source of transistor Q7 may be electrically connected to the anode of diode D7, and the cathode of diode D7 may be electrically connected to the other end of choke Lo, one end of capacitor 51 and the third terminal 23. The same applies to diode D8 and transistor Q8.

[0062] When the DC-DC converter 10 steps down the voltage output from the first side (capacitor 8 side) to the second side (low-voltage battery 11 side) (to charge the low-voltage battery 11), the control unit 61 controls transistors Q7 and Q8 to the off state. In this case, the DC-DC converter 10 becomes the equivalent circuit of the DC-DC converter 200. In this case, since capacitor 8 is connected in parallel with the high-voltage battery 2, the DC-DC converter 10 uses a capacitor input method.

[0063] When the DC-DC converter 10 outputs a boosted voltage from the second side (low-voltage battery 11 side) to the first side (capacitor 8 side) (pre-charging capacitor 8), the choke Lo is connected in series with the low-voltage battery 11, resulting in a choke input configuration. In this case, the DC-DC converter 10, like the DC-DC converter 200, may generate a surge voltage due to the choke Lo. However, the control unit 61 controls transistor Q7 or transistor Q8 to the ON state. As a result, the DC-DC converter 10 regenerates the surge voltage to capacitor 51 via the first switch 71 or the second switch 72. This will be explained in more detail later.

[0064] Therefore, the DC-DC converter 10 can suppress the application of surge voltage to transistor Q5 or transistor Q6, and can suppress stress on transistor Q5 or transistor Q6.

[0065] Terminal 81a of the voltage detection unit 81 is electrically connected to the drain of transistor Q5, and the drain-source voltage V of transistor Q5 is detected. dsQ5 The following is input. Terminal 81b of the voltage detection unit 81 is electrically connected to the drain of transistor Q6, and the drain-source voltage V of transistor Q6 is input. dsQ6 The following is input. The voltage detection unit 81 detects the drain-source voltage V of transistor Q5. dsQ5 and the drain-source voltage V of transistor Q6 dsQ6 Voltage V corresponding to the difference DET This is output from terminal 81c to the AD converter 91.

[0066] The AD converter 91, at the timing when it receives the conversion instruction signal S1 from the control unit 61, outputs voltage V DET The signal is sampled and digitally converted, and the voltage V DET The digital signal S2 obtained by digitally converting the signal is output to the control unit 61.

[0067] Based on the digital signal S2, the control unit 61 controls the voltage V of the first portion 42a or the second portion 42b of the second winding 42.n2 The control unit 61 then detects the voltage V n2 Based on this, the voltage V of the first winding 41 n1 That is, the voltage V across capacitor 8 H It detects.

[0068] Figure 4 shows the configuration of the voltage detection unit of the DC-DC converter according to the first embodiment.

[0069] The voltage detection unit 81 includes diodes D11 and D12, resistors R11 to R16, and a differential amplifier circuit 101.

[0070] The anode of diode D11 is electrically connected to terminal 81a. The cathode of diode D11 is electrically connected to one end of resistor R11. The other end of resistor R11 is electrically connected to node N11. One end of resistor R12 is electrically connected to node N11. The other end of resistor R12 is electrically connected to the reference potential.

[0071] The voltage V11 at node N11 is equal to the drain-source voltage V of transistor Q5. dsQ5 This voltage is obtained by dividing the voltage between resistors R11 and R12.

[0072] The anode of diode D12 is electrically connected to terminal 81b. The cathode of diode D12 is electrically connected to one end of resistor R13. The other end of resistor R13 is electrically connected to node N12. One end of resistor R14 is electrically connected to node N12. The other end of resistor R14 is electrically connected to the reference potential.

[0073] The voltage V12 at node N12 is equal to the drain-source voltage V of transistor Q6. dsQ6 This voltage is obtained by dividing the voltage between resistors R13 and R14.

[0074] While it is exemplified that the ratio of the resistance value of resistor R11 to the resistance value of resistor R12 is the same as the ratio of the resistance value of resistor R13 to the resistance value of resistor R14, the disclosure is not limited thereto.

[0075] The differential amplifier circuit 101 outputs a voltage V13, which is the amplified difference between voltage V11 and voltage V12, to one end of resistor R15.

[0076] In this embodiment, the differential amplifier circuit 101 outputs a voltage V13 which is an amplified difference between voltage V11 and voltage V12, but the disclosure is not limited thereto. The differential amplifier circuit 101 may also output a voltage V13 which is an amplified difference between voltage V12 and voltage V11.

[0077] The other end of resistor R15 is electrically connected to node N13. One end of resistor R16 is electrically connected to node N13. The other end of resistor R16 is electrically connected to the reference potential.

[0078] Voltage V at node N13 DET This is the voltage obtained by dividing the voltage V13 by resistors R15 and R16.

[0079] (Boost operation in the first embodiment) The boost operation of the DC-DC converter 10 of the first embodiment will now be described.

[0080] Figure 5 is a timing diagram of the boost operation of the DC-DC converter in the first embodiment. Figures 6 to 9 are diagrams showing the current flow path during the boost operation of the DC-DC converter in the first embodiment.

[0081] Referring to Figure 5, one cycle of the boost operation includes the first period Mode1, the second period Mode2, the third period Mode3, and the fourth period Mode4.

[0082] The period from timing t0 to timing t1 is the first period, Mode 1. The period from timing t1 to timing t2 is the second period, Mode 2. The period from timing t2 to timing t3 is the third period, Mode 3. The period from timing t3 to timing t4 is the fourth period, Mode 4.

[0083] [Phase 1 Mode 1] At timing t0, the first period Mode1 starts. The control unit 61 controls transistors Q2, Q5, and Q7 to the ON state. As a result, transistor Q5 conducts on the second side, and transistor Q2 conducts on the first side.

[0084] As a variation, the control unit 61 may control transistor Q3 to be ON instead of transistor Q2.

[0085] During the first period, Mode 1, the choke Lo is charged.

[0086] Referring to Figure 6, the current on the second side flows through the path shown by line 301: high-potential end of low-voltage battery 11 → choke Lo → center tap 42c of second winding 42 → first part 42a of second winding 42 → transistor Q5 → low-potential end of low-voltage battery 11.

[0087] The current on the first side due to the induced voltage generated in the first winding 41 flows through the path shown by line 302: one end of the first winding 41 → inductor Lr → transistor Q2 → parasitic diode D4 of transistor Q4 → the other end of the first winding 41.

[0088] During the first period, Mode 1, the voltage V applied to the choke Lo is Lo is constant (voltage V L ) and the current I flowing through the choke Lo Lo It rises in a straight line.

[0089] In the first period, Mode 1, the drain-source voltage of transistor Q5 is V dsQ5and the drain-source voltage V of transistor Q6 dsQ6 This becomes a low level (reference potential).

[0090] [Period 2 Mode 2] At timing t1, the second period Mode 2 starts. The control unit 61 controls transistors Q2 and Q5 to the off state and keeps transistor Q7 in the on state. As a result, transistor Q7 conducts on the second side, and parasitic diodes D1 and D4 conduct on the first side.

[0091] During the second period, Mode 2, the choke Lo is discharged.

[0092] Referring to Figure 7, the current on the second side flows through the path shown by line 311: one end of choke Lo → center tap 42c of the second winding 42 → first part 42a of the second winding 42 → diode D7 → transistor Q7 → the other end of choke Lo.

[0093] In this way, the DC-DC converter 10 can form a regenerative path for the choke Lo, thereby suppressing the application of surge voltage to transistor Q5. Therefore, the DC-DC converter 10 can suppress stress on transistor Q5. Furthermore, the DC-DC converter 10 can reset the choke Lo.

[0094] The current on the first side flows through the path shown by line 312: one end of the first winding 41 → inductor Lr → parasitic diode D1 of transistor Q1 → capacitor 8 → parasitic diode D4 of transistor Q4 → the other end of the first winding 41.

[0095] This current on the first side precharges capacitor 8.

[0096] In the second period, Mode 2, the voltage V applied to the choke Lo is Lo This is constant (-n² / n¹·V H ) and the current I of the choke Lo Lo It decreases linearly.

[0097] In the second period, Mode 2, the drain-source voltage of transistor Q5 is V dsQ5 (See voltage V21 in Figure 5) is expressed by the following equation (1). V dsQ5 =V L +V Lo -V n2 ...(1)

[0098] In the second period, Mode 2, the drain-source voltage of transistor Q6 is V dsQ6 (See voltage V22 in Figure 5) is expressed by the following equation (2). V dsQ6 =V L +V Lo +V n2 ...(2)

[0099] Therefore, the drain-source voltage V of transistor Q5 dsQ5 From the drain-source voltage V of transistor Q6 dsQ6 The voltage obtained by subtracting this is expressed by the following equation (3). V dsQ5 -V dsQ6 =(V L +V Lo -V n2 )-(V L +V Lo +V n2 ) = -2·V n2 ...(3)

[0100] In other words, in the second period Mode2, V DET = -2·V n2 This is the result.

[0101] Also, voltage V H This can be expressed by the following equation (4). V H =V n1 = (n1 / n2)·V n2 ...(4)

[0102] From equations (3) and (4), the following equation (5) can be derived. VH =V n1 =n1 / n2·V n2 =-(n1 / (2·n2))·V DET ...(5)

[0103] Therefore, the control unit 61 controls the timing between timing t1 and timing t2. 10 In this process, the conversion instruction signal S1 is output to the AD converter 91. The AD converter 91 operates at timing t 10 In this case, voltage V DET The signal is sampled and digitally converted, and the digital signal S2 is output to the control unit 61.

[0104] If the AD converter 91 cannot handle negative voltages, a voltage absolute value circuit may be provided after the differential amplifier circuit 101 (see Figure 4) and before the AD converter 91.

[0105] The control unit 61 multiplies the digital signal S2 by -n1 / (2·n2) to obtain the voltage V H This can be detected. The control unit 61 may perform the multiplication of the digital signal S2 by -n1 / (2·n2) in hardware or in software.

[0106] The control unit 61 detects the voltage V H Once the desired voltage is reached, transistors Q1 through Q6 are controlled to turn off, ending the pre-charging of capacitor 8.

[0107] As a result, the DC-DC converter 10 receives the voltage V H This can prevent the voltage from continuing to rise, thus reducing the possibility of damage to inverter 7 and other components.

[0108] [Third Period Mode 3] At timing t2, the third period, Mode 3, starts. The control unit 61 controls transistor Q7 to the off state and transistors Q4, Q6, and Q8 to the on state. As a result, transistor Q6 conducts on the second side and transistor Q4 conducts on the first side.

[0109] As a variation, the control unit 61 may control transistor Q1 to be ON instead of transistor Q4.

[0110] In the third period, Mode 3, the choke Lo is charged.

[0111] Referring to Figure 8, the current on the second side flows through the path shown by line 321: high-potential end of the low-voltage battery 11 → choke Lo → center tap 42c of the second winding 42 → second part 42b of the second winding 42 → transistor Q6 → low-potential end of the low-voltage battery 11.

[0112] The current on the first side due to the induced voltage generated in the first winding 41 flows through the path shown by line 322: the other end of the first winding 41 → transistor Q4 → parasitic diode D2 of transistor Q2 → inductor Lr → one end of the first winding 41.

[0113] In the third period, Mode 3, the voltage V applied to the choke Lo is Lo is constant (voltage V L ) and the current I flowing through the choke Lo Lo It rises in a straight line.

[0114] In the third period, Mode 3, the drain-source voltage of transistor Q5 is V dsQ5 and the drain-source voltage V of transistor Q6 dsQ6 This will result in a low level.

[0115] [Period 4 Mode 4] At timing t3, the fourth period, Mode 4, starts. The control unit 61 controls transistors Q4 and Q6 to the off state and keeps transistor Q8 in the on state. As a result, transistor Q8 conducts on the second side, and parasitic diodes D2 and D3 conduct on the first side.

[0116] In the fourth period, Mode 4, the choke Lo is discharged.

[0117] Referring to Figure 9, the current on the second side flows through the path shown by line 331: one end of choke Lo → center tap 42c of the second winding 42 → second part 42b of the second winding 42 → diode D8 → transistor Q8 → the other end of choke Lo.

[0118] In this way, the DC-DC converter 10 can form a regenerative path for the choke Lo, thereby suppressing the application of surge voltage to transistor Q6. Consequently, the DC-DC converter 10 can suppress stress on transistor Q6. Furthermore, the DC-DC converter 10 allows for the resetting of the choke Lo.

[0119] The current on the first side due to the induced voltage generated in the first winding 41 flows through the path shown by line 332: the other end of the first winding 41 → parasitic diode D3 of transistor Q3 → capacitor 8 → parasitic diode D2 of transistor Q2 → inductor Lr → one end of the first winding 41.

[0120] This current on the first side precharges capacitor 8.

[0121] In the fourth period, Mode 4, the voltage V applied to the choke Lo is Lo This is constant (-n² / n¹·V H ) and the current I of the choke Lo Lo It decreases linearly.

[0122] In the fourth period, Mode 4, the drain-source voltage of transistor Q5 is V dsQ5(Refer to voltage V22 in FIG. 5) is represented by the following equation (6). V dsQ5 =V L +V Lo +V n2 ···(6)

[0123] In the fourth period Mode4, the drain-source voltage V dsQ6 (Refer to voltage V21 in FIG. 5) is represented by the following equation (7). V dsQ6 =V L +V Lo -V n2 ···(7)

[0124] Therefore, the voltage obtained by subtracting the drain-source voltage V dsQ5 of transistor Q5 from the drain-source voltage V dsQ6 of transistor Q6 is represented by the following equation (8). [[ID=三十]] V dsQ5 -V dsQ6 =(V L +V Lo +V n2 )-(V L +V Lo -V n2 ) =2·V n2 ···(8)

[0125] That is, in the fourth period Mode4, V DET =2·V n2 is obtained.

[0126] Also, the voltage V H is represented by the aforementioned equation (4).

[0127] From equations (8) and (4), the following equation (9) is derived. V H =V n1 =n1 / n2·V n2 =(n1 / (2·n2))·V DET ···(9)

[0128] Therefore, the control unit 61 controls the timing between timing t3 and timing t4. 11 In this process, the conversion instruction signal S1 is output to the AD converter 91. The AD converter 91 operates at timing t 11 In this case, voltage V DET The signal is sampled and digitally converted, and the digital signal S2 is output to the control unit 61.

[0129] The control unit 61 multiplies the digital signal S2 by n1 / (2·n2) to obtain the voltage V H This can be detected. The control unit 61 may perform the multiplication of the digital signal S2 by n1 / (2·n2) in hardware or in software.

[0130] The control unit 61 detects the voltage V H Once the desired voltage is reached, transistors Q1 through Q6 are controlled to turn off, ending the pre-charging of capacitor 8.

[0131] As a result, the DC-DC converter 10 receives the voltage V H This can prevent the voltage from continuing to rise, thus reducing the possibility of damage to inverter 7 and other components.

[0132] (summary) As explained above, when the DC-DC converter 10 outputs a boosted voltage from the second side (low-voltage battery 11 side) to the first side (capacitor 8 side) (pre-charging capacitor 8), the control unit 61 controls transistor Q7 or transistor Q8 to be turned ON.

[0133] As a result, the DC-DC converter 10 can form a regenerative path for the choke Lo, thereby suppressing the application of surge voltage to transistor Q5 or transistor Q6. Therefore, the DC-DC converter 10 can suppress stress on transistor Q5 or transistor Q6.

[0134] Furthermore, the DC-DC converter 10 allows for the resetting of the choke low.

[0135] Furthermore, since the DC-DC converter 10 can precharge the capacitor 8, the resistor 3 and contactor 5 (see Figure 1) of the power system 1 can be made unnecessary.

[0136] Furthermore, the DC-DC converter 10 uses the voltage on the second side (low voltage side), i.e., the drain-source voltage of transistor Q5 V dsQ5 and the drain-source voltage V of transistor Q6 dsQ6 Based on this, the voltage across capacitor 8 is V H It can be detected.

[0137] As a result, the DC-DC converter 10 receives the voltage V H An isolation amplifier is not required when attempting to directly detect the signal. Therefore, the DC-DC converter 10 can suppress an increase in device size and thus suppress an increase in cost.

[0138] Furthermore, the DC-DC converter 10 uses a voltage V H Once the desired voltage is reached, the pre-charging of capacitor 8 can be terminated.

[0139] As a result, the DC-DC converter 10 receives the voltage V H This can prevent the voltage from continuing to rise, thus reducing the possibility of damage to inverter 7 and other components.

[0140] <Second Embodiment> Figure 10 shows the configuration of the DC-DC converter in the second embodiment.

[0141] Compared to the DC-DC converter 10 of the first embodiment (see Figure 3), the DC-DC converter 10A includes a voltage detection unit 81A instead of the voltage detection unit 81.

[0142] As explained in the first embodiment, in the fourth period Mode 4, equation (6) above holds true. Equation (6) can be transformed into the following equation (10). V n2 =V dsQ5 -V L -V Lo ...(10)

[0143] The voltage detection unit 81A detects the voltage V according to equation (10). n2 It detects.

[0144] Terminal 81a of the voltage detection unit 81A is electrically connected to the drain of transistor Q5, and the drain-source voltage V of transistor Q5 is detected. dsQ5 The following is input. Terminal 81b of the voltage detection unit 81A is electrically connected to the third terminal 23, and the voltage V L The following is input. Terminals 81c and 81d of the voltage detection unit 81A are electrically connected to both ends of the choke Lo, respectively.

[0145] Figure 11 shows the configuration of the voltage detection unit of the DC-DC converter according to the second embodiment.

[0146] The voltage detection unit 81A includes a first detection unit 111, a second detection unit 112, a differential amplifier circuit 113, a third detection unit 114, and a calculation unit 115.

[0147] The first detection unit 111 detects the drain-source voltage V of transistor Q5, which is input to terminal 81a. dsQ5 It detects this and outputs it to the calculation unit 115.

[0148] The second detection unit 112 detects the voltage V input to terminal 81b. L It detects this and outputs it to the calculation unit 115.

[0149] The differential amplifier circuit 113 uses the voltage V across the choke Lo. Lo The signal is amplified and output to the third detection unit 114.

[0150] The third detection unit 114 detects the voltage V output from the differential amplifier circuit 113.Lo It detects this and outputs it to the calculation unit 115.

[0151] The calculation unit 115 calculates the drain-source voltage V of transistor Q5. dsQ5 From, voltage V Lo Subtract the voltage V Lo Subtracting this, the voltage V DET (Voltage V n2 (equivalent to) is output to the AD converter 91.

[0152] In other words, the arithmetic unit 115 performs the calculation of equation (10).

[0153] The control unit 61 controls the timing between timing t3 and timing t4. 11 (See Figure 5) The conversion instruction signal S1 is output to the AD converter 91. The AD converter 91 is at timing t 11 In this case, voltage V DET The signal is sampled and digitally converted, and the digital signal S2 is output to the control unit 61.

[0154] Voltage V n2 and voltage V H The relationship is expressed by equation (4) mentioned above.

[0155] The control unit 61 multiplies the digital signal S2 by n1 / n2 according to equation (4) to obtain the voltage V H This can be detected. The control unit 61 may perform the multiplication of the digital signal S2 by n1 / n2 in hardware or in software.

[0156] The control unit 61 detects the voltage V H Once the desired voltage is reached, transistors Q1 through Q6 are controlled to turn off, ending the pre-charging of capacitor 8.

[0157] As a result, the DC-DC converter 10A can achieve the same effect as the DC-DC converter 10.

[0158] (modified version) In this embodiment, the voltage detection unit 81A detects the drain-source voltage V of transistor Q5. dsQ5 Using voltage V n2 The drain-source voltage V of transistor Q5 was detected, but dsQ5 Instead, the drain-source voltage V of transistor Q6 dsQ6 Using voltage V n2 It is also possible to detect it.

[0159] In other words, in the fourth period, Mode 4, equation (7) holds true. Equation (7) can be transformed into equation (11). V n2 =V L +V Lo -V dsQ6 ...(11)

[0160] The voltage detection unit 81A detects the voltage V according to equation (11). n2 It can be detected.

[0161] <Third Embodiment> Figure 12 shows the configuration of the DC-DC converter according to the third embodiment.

[0162] Compared to the DC-DC converter 10A of the second embodiment (see Figure 10), the DC-DC converter 10B includes a voltage detection unit 81B instead of a voltage detection unit 81A.

[0163] As explained in the first embodiment, in the second period Mode2, equation (2) above holds true. Equation (2) can be transformed into the following equation (12). V n2 =V L +V Lo -V dsQ5 ...(12)

[0164] The voltage detection unit 81B detects the voltage V according to equation (12). n2 It detects.

[0165] The terminal 81a of the voltage detection unit 81B is electrically connected to the drain of the transistor Q5, and the drain-source voltage V of the transistor Q5 dsQ5 is input. The terminal 81b of the voltage detection unit 81B is electrically connected to the third terminal 23, and the voltage V L is input. The terminals 81c and 81d of the voltage detection unit 81B are electrically connected to both ends of the choke Lo respectively.

[0166] FIG. 13 is a diagram showing the configuration of the voltage detection unit of the DC-DC converter according to the third embodiment.

[0167] The voltage detection unit 81B includes an arithmetic unit 116 instead of the arithmetic unit 115 as compared with the voltage detection unit 81A (see FIG. 11).

[0168] The arithmetic unit 116 adds the voltage V Lo and the voltage V Lo , further subtracts the drain-source voltage V of the transistor Q5 dsQ5 , and outputs the voltage V DET .

[0169] That is, the arithmetic unit 116 performs the operation of equation (12).

[0170] The control unit 61 outputs a conversion instruction signal S1 to the AD converter 91 at a timing t 10 between the timing t1 and the timing t2 (see FIG. 5). The AD converter 91 samples and digitally converts the voltage V 10 at the timing t DET , and outputs a digital signal S2 to the control unit 61.

[0171] The relationship between the voltage V n2 and the voltage V H is represented by the aforementioned equation (4).

[0172] The control unit 61 multiplies the digital signal S2 by n1 / n2 according to equation (4), thereby obtaining the voltage V HThis can be detected. The control unit 61 may perform the multiplication of the digital signal S2 by n1 / n2 in hardware or in software.

[0173] The control unit 61 detects the voltage V H Once the desired voltage is reached, transistors Q1 through Q6 are controlled to turn off, ending the pre-charging of capacitor 8.

[0174] As a result, the DC-DC converter 10B can achieve the same effect as the DC-DC converter 10.

[0175] (modified version) In this embodiment, the voltage detection unit 81B detects the drain-source voltage V of transistor Q5. dsQ5 Using voltage V n2 The drain-source voltage V of transistor Q5 was detected, but dsQ5 Instead, the drain-source voltage V of transistor Q6 dsQ6 Using voltage V n2 It is also possible to detect it.

[0176] In other words, in the second period, Mode 2, equation (2) above holds true. Equation (2) can be transformed into the following equation (13). V n2 =V dsQ6 -V L -V Lo ...(13)

[0177] The voltage detection unit 81B detects the voltage V according to equation (13). n2 It can be detected.

[0178] <Other examples> In the first to third embodiments described above, the drain-source voltage V of transistor Q5 dsQ5 and the drain-source voltage V of transistor Q6 dsQ6 Based on at least one of the following, the voltage V n2 Detects voltage V n2 Based on this, voltage V HDetected.

[0179] However, the voltage V across the first portion 42a of the second winding 42 n2 , or the voltage V across the second portion 42b of the second winding 42. n2 Alternatively, this could be detected directly.

[0180] Furthermore, the voltage across the second winding 42 (a series circuit of the first part 42a and the second part 42b) is 2·V. n2 Alternatively, we could directly detect it.

[0181] However, in these cases, since both ends of the first portion 42a and the second portion 42b of the second winding 42 are floating with respect to the reference potential, an isolation amplifier is required.

[0182] <Fourth Embodiment> As described in the first to third embodiments, the control unit 61 controls the voltage V H Once the desired voltage is reached, transistors Q1 through Q6 are controlled to turn off, ending the pre-charging of capacitor 8.

[0183] In the fourth embodiment, the control unit 61 further controls transistors Q1 to Q6 to turn off, and then controls transistors Q7 and Q8 to turn on.

[0184] The configuration of the fourth embodiment is the same as that of the first to third embodiments (see Figures 3, 10, and 12), so its illustration and description are omitted.

[0185] Figures 14 and 15 are timing diagrams of the DC-DC converter according to the fourth embodiment.

[0186] In FIGS. 14 and 15, line 401 represents the drive control signal of transistor Q1. Line 402 represents the drive control signal of transistor Q2. Line 403 represents the drive control signal of transistor Q3. Line 404 represents the drive control signal of transistor Q4. Line 405 represents the drive control signal of transistor Q5. Line 406 represents the drive control signal of transistor Q6. Line 407 represents the drive control signal of transistor Q7. Line 408 represents the drive control signal of transistor Q8. Line 409 represents the duty (on-duty) of the drive control signals from transistor Q1 to transistor Q6.

[0187] Referring to FIG. 14, the period from timing t 20 to timing t 22 is the precharge period of capacitor 8.

[0188] At timing t 20 the precharge period of capacitor 8 starts.

[0189] The control unit 61 outputs a pulse signal to the gates of transistors Q2 and Q4 to Q8 at timing t 20 and pulse-drives transistors Q2 and Q4 to Q8.

[0190] The control unit 61 increases the duty of transistors Q2 and Q4 to Q6 from timing t 20 to timing t 21 as time elapses. The control unit 61 keeps the duty of transistors Q7 and Q8 constant regardless of the passage of time.

[0191] Referring to FIG. 15, the duty of transistors Q2 and Q4 to Q6 increases as time elapses. The duty of transistors Q7 and Q8 is constant regardless of the passage of time.

[0192] Referring again to Figure 14, timing t 21 In this case, the duty cycles of transistors Q2 and Q4 through Q6 are as shown by line 409, with a maximum duty cycle of D MAX It reaches.

[0193] The control unit 61 controls the timing t 21 From here on, the duty cycles of transistors Q2 and Q4 through Q6 are shown by line 409, with a maximum duty cycle of D MAX Maintain it.

[0194] The control unit 61 controls the timing t 22 In this case, voltage V H Once the desired voltage is reached, transistors Q2 and Q4 through Q6 are controlled to be turned off.

[0195] timing t 22 At this point, the pre-charge period for capacitor 8 ends.

[0196] The control unit 61 controls the timing t 22 The timing when a predetermined amount of time has elapsed from 23 This controls transistors Q7 and Q8 to be turned ON. As a result, current flows and the energy of choke Lo is discharged, as shown by lines 311 in Figure 7 and 331 in Figure 9.

[0197] Therefore, the control unit 61 can regenerate the surge voltage to the capacitor 51. In addition, the control unit 61 can reset the choke Lo.

[0198] In this embodiment, the control unit 61 controls timing t 22 The timing when a predetermined amount of time has elapsed from 23 The present disclosure describes controlling transistors Q7 and Q8 to be turned ON until the voltage across the terminals of choke Lo falls below a predetermined voltage.

[0199] <Fifth Embodiment> In the fifth embodiment, the control unit 61 controls transistors Q1 through Q6 to turn off, and then controls transistor Q7 to turn on.

[0200] The configuration of the fifth embodiment is the same as that of the first to third embodiments (see Figures 3, 10, and 12), so its illustration and description are omitted.

[0201] Figure 16 is a timing diagram of the DC-DC converter according to the fifth embodiment.

[0202] In Figure 16, line 411 represents the drive control signal for transistor Q1. Line 412 represents the drive control signal for transistor Q2. Line 413 represents the drive control signal for transistor Q3. Line 414 represents the drive control signal for transistor Q4. Line 415 represents the drive control signal for transistor Q5. Line 416 represents the drive control signal for transistor Q6. Line 417 represents the drive control signal for transistor Q7. Line 418 represents the drive control signal for transistor Q8. Line 419 represents the duty cycle (on-duty cycle) of the drive control signals from transistor Q1 to transistor Q6.

[0203] Referring to Figure 16, timing t 30 from timing t 32 The period up to that point is the pre-charge period for capacitor 8.

[0204] timing t 30 At this point, the pre-charge period for capacitor 8 begins.

[0205] The control unit 61 controls the timing t 30 In this configuration, pulse signals are output to the gates of transistors Q2 and Q4 through Q8, thereby pulse-driving transistors Q2 and Q4 through Q8.

[0206] The control unit 61 controls the timing t30 from timing t 31 Until then, the duty cycles of transistors Q2 and Q4 through Q6 are increased as time progresses. The control unit 61 keeps the duty cycles of transistors Q7 and Q8 constant regardless of the passage of time.

[0207] timing t 31 In this case, the duty cycles of transistors Q2 and Q4 through Q6 are as shown by line 419, with a maximum duty cycle of D MAX It reaches.

[0208] The control unit 61 controls the timing t 31 From here on, the duty cycles of transistors Q2 and Q4 through Q6 are shown by line 419, with a maximum duty cycle of D MAX Maintain it.

[0209] The control unit 61 controls the timing t 32 In this case, voltage V H Once the desired voltage is reached, transistors Q2 and Q4 through Q6 are controlled to be turned off.

[0210] timing t 32 At this point, the pre-charge period for capacitor 8 ends.

[0211] The control unit 61 controls the timing t 32 The timing when a predetermined amount of time has elapsed from 33 This controls transistor Q7 to be turned on. As a result, current flows and the energy of choke Lo is discharged, as shown by line 311 in Figure 7.

[0212] Therefore, the control unit 61 can regenerate the surge voltage to the capacitor 51. In addition, the control unit 61 can reset the choke Lo.

[0213] In this embodiment, the control unit 61 controls timing t 32The timing when a predetermined amount of time has elapsed from 33 The present disclosure describes controlling transistor Q7 to be turned on until the voltage across the terminals of choke Lo falls below a predetermined voltage.

[0214] <Sixth Embodiment> In the sixth embodiment, the control unit 61 controls transistors Q1 through Q6 to turn off, and then controls transistor Q8 to turn on.

[0215] The configuration of the sixth embodiment is the same as that of the first to third embodiments (see Figures 3, 10, and 12), so its illustration and description are omitted.

[0216] Figure 17 is a timing diagram of the DC-DC converter according to the sixth embodiment.

[0217] In Figure 17, line 421 represents the drive control signal for transistor Q1. Line 422 represents the drive control signal for transistor Q2. Line 423 represents the drive control signal for transistor Q3. Line 424 represents the drive control signal for transistor Q4. Line 425 represents the drive control signal for transistor Q5. Line 426 represents the drive control signal for transistor Q6. Line 427 represents the drive control signal for transistor Q7. Line 428 represents the drive control signal for transistor Q8. Line 429 represents the duty cycle (on duty cycle) of the drive control signals from transistor Q1 to transistor Q6.

[0218] Referring to Figure 17, timing t 40 from timing t 42 The period up to that point is the pre-charge period for capacitor 8.

[0219] timing t 40 At this point, the pre-charge period for capacitor 8 begins.

[0220] The control unit 61 controls the timing t 40In this configuration, pulse signals are output to the gates of transistors Q2 and Q4 through Q8, thereby pulse-driving transistors Q2 and Q4 through Q8.

[0221] The control unit 61 controls the timing t 40 from timing t 41 Until then, the duty cycles of transistors Q2 and Q4 through Q6 are increased as time progresses. The control unit 61 keeps the duty cycles of transistors Q7 and Q8 constant regardless of the passage of time.

[0222] timing t 41 In this case, the duty cycles of transistors Q2 and Q4 through Q6 are as shown by line 429, with a maximum duty cycle of D MAX It reaches.

[0223] The control unit 61 controls the timing t 41 From here on, the duty cycles of transistors Q2 and Q4 through Q6 are shown by line 429, with a maximum duty cycle of D MAX Maintain it.

[0224] The control unit 61 controls the timing t 42 In this case, voltage V H Once the desired voltage is reached, transistors Q2 and Q4 through Q6 are controlled to be turned off.

[0225] timing t 42 At this point, the pre-charge period for capacitor 8 ends.

[0226] The control unit 61 controls the timing t 42 The timing when a predetermined amount of time has elapsed from 43 This controls transistor Q8 to be turned on. As a result, current flows and the energy of choke Lo is discharged, as shown by line 331 in Figure 9.

[0227] Therefore, the control unit 61 can regenerate the surge voltage to the capacitor 51. In addition, the control unit 61 can reset the choke Lo.

[0228] In this embodiment, the control unit 61 controls timing t 42 The timing when a predetermined amount of time has elapsed from 43 The present disclosure describes controlling transistor Q8 to be turned ON until the voltage across the terminals of choke Lo falls below a predetermined voltage.

[0229] <Seventh Embodiment> In the seventh embodiment, the control unit 61 controls transistors Q1 to Q6 to be turned off, and then pulse-drives transistors Q7 and Q8.

[0230] The configuration of the seventh embodiment is the same as that of the first to third embodiments (see Figures 3, 10, and 12), so its illustration and description are omitted.

[0231] Figure 18 is a timing diagram of the DC-DC converter according to the seventh embodiment.

[0232] In Figure 18, line 431 represents the drive control signal for transistor Q1. Line 432 represents the drive control signal for transistor Q2. Line 433 represents the drive control signal for transistor Q3. Line 434 represents the drive control signal for transistor Q4. Line 435 represents the drive control signal for transistor Q5. Line 436 represents the drive control signal for transistor Q6. Line 437 represents the drive control signal for transistor Q7. Line 438 represents the drive control signal for transistor Q8. Line 439 represents the duty cycle (on duty cycle) of the drive control signals from transistor Q1 to transistor Q6.

[0233] Referring to Figure 18, timing t 50 from timing t 52The period up to that point is the pre-charge period for capacitor 8.

[0234] timing t 50 At this point, the pre-charge period for capacitor 8 begins.

[0235] The control unit 61 controls the timing t 50 In this configuration, pulse signals are output to the gates of transistors Q2 and Q4 through Q8, thereby pulse-driving transistors Q2 and Q4 through Q8.

[0236] The control unit 61 controls the timing t 50 from timing t 51 Until then, the duty cycles of transistors Q2 and Q4 through Q6 are increased as time progresses. The control unit 61 keeps the duty cycles of transistors Q7 and Q8 constant regardless of the passage of time.

[0237] timing t 51 In this case, the duty cycles of transistors Q2 and Q4 through Q6 are as shown by line 439, with a maximum duty cycle of D MAX It reaches.

[0238] The control unit 61 controls the timing t 51 From here on, the duty cycles of transistors Q2 and Q4 through Q6 are shown by line 439, with a maximum duty cycle of D MAX Maintain it.

[0239] The control unit 61 controls the timing t 52 In this case, voltage V H Once the desired voltage is reached, transistors Q2 and Q4 through Q6 are controlled to be turned off.

[0240] timing t 52 At this point, the pre-charge period for capacitor 8 ends.

[0241] The control unit 61 controls the timing t 52 The timing when a predetermined amount of time has elapsed from 53 Transistors Q7 and Q8 are pulsed until this point. As a result, current flows and the energy of choke Lo is discharged, as shown by lines 311 in Figure 7 and 331 in Figure 9.

[0242] Therefore, the control unit 61 can regenerate the surge voltage to the capacitor 51. In addition, the control unit 61 can reset the choke Lo.

[0243] In this embodiment, the control unit 61 controls timing t 52 The timing when a predetermined amount of time has elapsed from 53 Up to this point, transistors Q7 and Q8 are driven by pulses, but this disclosure is not limited thereto. The control unit 61 may also drive transistors Q7 and Q8 by pulses until the terminal voltage of choke Lo falls below a predetermined voltage.

[0244] Furthermore, in this embodiment, the control unit 61 controls the timing t 52 from timing t 53 Up to this point, transistors Q7 and Q8 are driven by pulses, but this disclosure is not limited thereto. The control unit 61 controls the timing t 52 from timing t 53 Until then, either transistor Q7 or transistor Q8 may be driven by pulses.

[0245] While embodiments of the present disclosure have been described above, the present disclosure is not limited by the content of these embodiments. Furthermore, the aforementioned components include those that are readily conceivable to those skilled in the art, those that are substantially identical, and those that fall within the so-called equivalent range. Moreover, the aforementioned components can be combined as appropriate. Furthermore, various omissions, substitutions, or modifications of the components can be made without departing from the spirit of the embodiments described above. [Explanation of symbols]

[0246] 1 Power system 2 High-voltage battery 3 resistors 4, 5, 6 Contactors 7 Inverter 8.51 Capacitor 9 Motors 10, 10A, 10B, 200 DC-DC converters 11 Low-voltage battery 31 Bridge Circuit 41. First winding 42. Second winding 43 cores 61 Control Unit 71. Switch 1 72 Second switch 81, 81A, 81B Voltage detection unit 91 AD Converters 101, 113 Differential Amplifier Circuit 111 First detection unit 112 Second detection unit 114 Third detection unit 115, 116 Arithmetic section D7, D8, D11, D12 diodes Lo Chalk Lr Inductor Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8 Transistors T Transformer

Claims

1. A power supply device that steps down a first voltage input between a first terminal and a second terminal and outputs it from between a third terminal and a fourth terminal, and steps up a second voltage input between the third terminal and the fourth terminal and outputs it from between the first terminal and the second terminal, A bridge circuit comprising: a first switching element with one end electrically connected to the first terminal; a second switching element with one end electrically connected to the other end of the first switching element and the other end electrically connected to the second terminal; a third switching element with one end electrically connected to the first terminal; and a fourth switching element with one end electrically connected to the other end of the third switching element and the other end electrically connected to the second terminal; A transformer comprising: a first winding, one end of which is electrically connected to the other end of the first switching element and one end of the second switching element, and the other end of which is electrically connected to the other end of the third switching element and one end of the fourth switching element; and a second winding that is magnetically coupled to the first winding; An inductor having one end electrically connected to the center tap of the second winding and the other end electrically connected to the third terminal, A fifth switching element, one end of which is electrically connected to one end of the second winding and the other end of which is electrically connected to the fourth terminal, A sixth switching element, one end of which is electrically connected to the other end of the second winding and the other end of which is electrically connected to the fourth terminal, A first switch, one end of which is electrically connected to one end of the fifth switching element and one end of the second winding, and the other end of which is electrically connected to the other end of the inductor and the third terminal, A second switch, one end of which is electrically connected to one end of the sixth switching element and the other end of the second winding, and the other end of which is electrically connected to the other end of the inductor and the third terminal, A voltage detection unit that detects the voltage between one or the other end of the second winding and the center tap based on at least one of the terminal voltages of the fifth switching element and the terminal voltages of the sixth switching element, A control unit that calculates the voltage between the first terminal and the second terminal based on the voltage detected by the voltage detection unit, including, A power supply device characterized by the following features.

2. The control unit, When the second voltage is boosted and output between the first terminal and the second terminal, During the first period, the fifth switching element and the first switch are turned on, and the sixth switching element and the second switch are turned off. In the second period following the first period, the first switch is turned on, and the fifth switching element, the sixth switching element, and the second switch are turned off. In the third period following the second period, the sixth switching element and the second switch are turned on, and the fifth switching element and the first switch are turned off. In the fourth period following the third period, the second switch is turned on, and the fifth switching element, the sixth switching element, and the first switch are turned off. The power supply device according to claim 1, characterized in that

3. The voltage detection unit is During the second or fourth period, the voltage between one end or the other end of the second winding and the center tap is detected based on the difference between the terminal voltage of the fifth switching element and the terminal voltage of the sixth switching element. The power supply device according to claim 2, characterized in that...

4. The voltage detection unit is During the fourth period, the voltage between one or the other end of the second winding and the center tap is detected by subtracting the sum of the inductor voltage and the second voltage from the terminal voltage of the fifth switching element. The power supply device according to claim 2, characterized in that...

5. The voltage detection unit is During the second period, the voltage between one or the other end of the second winding and the center tap is detected by subtracting the terminal voltage of the fifth switching element from the sum of the voltage of the inductor and the second voltage. The power supply device according to claim 2, characterized in that...

6. The control unit, When the voltage between the first terminal and the second terminal reaches the target voltage, the first switching element through the sixth switching element are turned off, and at least one of the first switch and the second switch is turned on. The power supply device according to claim 2, characterized in that...

7. The control unit, At least one of the first switch and the second switch is turned on with a predetermined duty cycle. The power supply device according to claim 6, characterized in that...

8. A bridge circuit including a first switching element with one end electrically connected to a first terminal, a second switching element with one end electrically connected to the other end of the first switching element and the other end electrically connected to a second terminal, a third switching element with one end electrically connected to the first terminal, and a fourth switching element with one end electrically connected to the other end of the third switching element and the other end electrically connected to the second terminal; a transformer including a first winding with one end electrically connected to the other end of the first switching element and one end of the second switching element, and the other end electrically connected to the other end of the third switching element and one end of the fourth switching element, and a second winding that is magnetically coupled to the first winding; an inductor with one end electrically connected to the center tap of the second winding and the other end electrically connected to the third terminal; and one end of the front A control method for a power supply device, comprising: a fifth switching element electrically connected to one end of the second winding and the other end electrically connected to the fourth terminal; a sixth switching element electrically connected to the other end of the second winding and the other end electrically connected to the fourth terminal; a first switch electrically connected to one end of the fifth switching element and one end of the second winding and the other end electrically connected to the other end of the inductor and the third terminal; a second switch electrically connected to one end of the sixth switching element and the other end of the second winding and the other end electrically connected to the other end of the inductor and the third terminal; and a voltage detection unit that detects the voltage between one end or the other end of the second winding and the center tap based on at least one of the terminal voltage of the fifth switching element and the terminal voltage of the sixth switching element, When the second voltage input between the third terminal and the fourth terminal is boosted and output from between the first terminal and the second terminal, During the first period, the fifth switching element and the first switch are turned on, and the sixth switching element and the second switch are turned off. In the second period following the first period, the first switch is turned on, and the fifth switching element, the sixth switching element, and the second switch are turned off. In the third period following the second period, the sixth switching element and the second switch are turned on, and the fifth switching element and the first switch are turned off. In the fourth period following the third period, the second switch is turned on, and the fifth switching element, the sixth switching element, and the first switch are turned off. Based on the voltage detected by the voltage detection unit, the voltage between the first terminal and the second terminal is calculated. A method for controlling a power supply device, characterized by the following features.

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